drivers/fpga/dfl-pci.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Driver for FPGA Device Feature List (DFL) PCIe device
   4  *
   5  * Copyright (C) 2017-2018 Intel Corporation, Inc.
   6  *
   7  * Authors:
   8  *   Zhang Yi <Yi.Z.Zhang@intel.com>
   9  *   Xiao Guangrong <guangrong.xiao@linux.intel.com>
  10  *   Joseph Grecco <joe.grecco@intel.com>
  11  *   Enno Luebbers <enno.luebbers@intel.com>
  12  *   Tim Whisonant <tim.whisonant@intel.com>
  13  *   Ananda Ravuri <ananda.ravuri@intel.com>
  14  *   Henry Mitchel <henry.mitchel@intel.com>
  15  */
  16
  17 #include <linux/pci.h>
  18 #include <linux/types.h>
  19 #include <linux/kernel.h>
  20 #include <linux/module.h>
  21 #include <linux/stddef.h>
  22 #include <linux/errno.h>
  23 #include <linux/aer.h>
  24
  25 #include "dfl.h"
  26
  27 #define DRV_VERSION     "0.8"
  28 #define DRV_NAME        "dfl-pci"
  29
  30 struct cci_drvdata {
  31         struct dfl_fpga_cdev *cdev;     /* container device */
  32 };
  33
  34 static void __iomem *cci_pci_ioremap_bar0(struct pci_dev *pcidev)
  35 {
  36         if (pcim_iomap_regions(pcidev, BIT(0), DRV_NAME))
  37                 return NULL;
  38
  39         return pcim_iomap_table(pcidev)[0];
  40 }
  41
  42 static int cci_pci_alloc_irq(struct pci_dev *pcidev)
  43 {
  44         int ret, nvec = pci_msix_vec_count(pcidev);
  45
  46         if (nvec <= 0) {
  47                 dev_dbg(&pcidev->dev, "fpga interrupt not supported\n");
  48                 return 0;
  49         }
  50
  51         ret = pci_alloc_irq_vectors(pcidev, nvec, nvec, PCI_IRQ_MSIX);
  52         if (ret < 0)
  53                 return ret;
  54
  55         return nvec;
  56 }
  57
  58 static void cci_pci_free_irq(struct pci_dev *pcidev)
  59 {
  60         pci_free_irq_vectors(pcidev);
  61 }
  62
  63 /* PCI Device ID */
  64 #define PCIE_DEVICE_ID_PF_INT_5_X       0xBCBD
  65 #define PCIE_DEVICE_ID_PF_INT_6_X       0xBCC0
  66 #define PCIE_DEVICE_ID_PF_DSC_1_X       0x09C4
  67 #define PCIE_DEVICE_ID_INTEL_PAC_N3000  0x0B30
  68 /* VF Device */
  69 #define PCIE_DEVICE_ID_VF_INT_5_X       0xBCBF
  70 #define PCIE_DEVICE_ID_VF_INT_6_X       0xBCC1
  71 #define PCIE_DEVICE_ID_VF_DSC_1_X       0x09C5
  72
  73 static struct pci_device_id cci_pcie_id_tbl[] = {
  74         {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_PF_INT_5_X),},
  75         {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_VF_INT_5_X),},
  76         {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_PF_INT_6_X),},
  77         {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_VF_INT_6_X),},
  78         {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_PF_DSC_1_X),},
  79         {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_VF_DSC_1_X),},
  80         {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_INTEL_PAC_N3000),},
  81         {0,}
  82 };
  83 MODULE_DEVICE_TABLE(pci, cci_pcie_id_tbl);
  84
  85 static int cci_init_drvdata(struct pci_dev *pcidev)
  86 {
  87         struct cci_drvdata *drvdata;
  88
  89         drvdata = devm_kzalloc(&pcidev->dev, sizeof(*drvdata), GFP_KERNEL);
  90         if (!drvdata)
  91                 return -ENOMEM;
  92
  93         pci_set_drvdata(pcidev, drvdata);
  94
  95         return 0;
  96 }
  97
  98 static void cci_remove_feature_devs(struct pci_dev *pcidev)
  99 {
 100         struct cci_drvdata *drvdata = pci_get_drvdata(pcidev);
 101
 102         /* remove all children feature devices */
 103         dfl_fpga_feature_devs_remove(drvdata->cdev);
 104         cci_pci_free_irq(pcidev);
 105 }
 106
 107 static int *cci_pci_create_irq_table(struct pci_dev *pcidev, unsigned int nvec)
 108 {
 109         unsigned int i;
 110         int *table;
 111
 112         table = kcalloc(nvec, sizeof(int), GFP_KERNEL);
 113         if (!table)
 114                 return table;
 115
 116         for (i = 0; i < nvec; i++)
 117                 table[i] = pci_irq_vector(pcidev, i);
 118
 119         return table;
 120 }
 121
 122 /* enumerate feature devices under pci device */
 123 static int cci_enumerate_feature_devs(struct pci_dev *pcidev)
 124 {
 125         struct cci_drvdata *drvdata = pci_get_drvdata(pcidev);
 126         int port_num, bar, i, nvec, ret = 0;
 127         struct dfl_fpga_enum_info *info;
 128         struct dfl_fpga_cdev *cdev;
 129         resource_size_t start, len;
 130         void __iomem *base;
 131         int *irq_table;
 132         u32 offset;
 133         u64 v;
 134
 135         /* allocate enumeration info via pci_dev */
 136         info = dfl_fpga_enum_info_alloc(&pcidev->dev);
 137         if (!info)
 138                 return -ENOMEM;
 139
 140         /* add irq info for enumeration if the device support irq */
 141         nvec = cci_pci_alloc_irq(pcidev);
 142         if (nvec < 0) {
 143                 dev_err(&pcidev->dev, "Fail to alloc irq %d.\n", nvec);
 144                 ret = nvec;
 145                 goto enum_info_free_exit;
 146         } else if (nvec) {
 147                 irq_table = cci_pci_create_irq_table(pcidev, nvec);
 148                 if (!irq_table) {
 149                         ret = -ENOMEM;
 150                         goto irq_free_exit;
 151                 }
 152
 153                 ret = dfl_fpga_enum_info_add_irq(info, nvec, irq_table);
 154                 kfree(irq_table);
 155                 if (ret)
 156                         goto irq_free_exit;
 157         }
 158
 159         /* start to find Device Feature List in Bar 0 */
 160         base = cci_pci_ioremap_bar0(pcidev);
 161         if (!base) {
 162                 ret = -ENOMEM;
 163                 goto irq_free_exit;
 164         }
 165
 166         /*
 167          * PF device has FME and Ports/AFUs, and VF device only has one
 168          * Port/AFU. Check them and add related "Device Feature List" info
 169          * for the next step enumeration.
 170          */
 171         if (dfl_feature_is_fme(base)) {
 172                 start = pci_resource_start(pcidev, 0);
 173                 len = pci_resource_len(pcidev, 0);
 174
 175                 dfl_fpga_enum_info_add_dfl(info, start, len);
 176
 177                 /*
 178                  * find more Device Feature Lists (e.g. Ports) per information
 179                  * indicated by FME module.
 180                  */
 181                 v = readq(base + FME_HDR_CAP);
 182                 port_num = FIELD_GET(FME_CAP_NUM_PORTS, v);
 183
 184                 WARN_ON(port_num > MAX_DFL_FPGA_PORT_NUM);
 185
 186                 for (i = 0; i < port_num; i++) {
 187                         v = readq(base + FME_HDR_PORT_OFST(i));
 188
 189                         /* skip ports which are not implemented. */
 190                         if (!(v & FME_PORT_OFST_IMP))
 191                                 continue;
 192
 193                         /*
 194                          * add Port's Device Feature List information for next
 195                          * step enumeration.
 196                          */
 197                         bar = FIELD_GET(FME_PORT_OFST_BAR_ID, v);
 198                         offset = FIELD_GET(FME_PORT_OFST_DFH_OFST, v);
 199                         start = pci_resource_start(pcidev, bar) + offset;
 200                         len = pci_resource_len(pcidev, bar) - offset;
 201
 202                         dfl_fpga_enum_info_add_dfl(info, start, len);
 203                 }
 204         } else if (dfl_feature_is_port(base)) {
 205                 start = pci_resource_start(pcidev, 0);
 206                 len = pci_resource_len(pcidev, 0);
 207
 208                 dfl_fpga_enum_info_add_dfl(info, start, len);
 209         } else {
 210                 ret = -ENODEV;
 211                 goto irq_free_exit;
 212         }
 213
 214         /* release I/O mappings for next step enumeration */
 215         pcim_iounmap_regions(pcidev, BIT(0));
 216
 217         /* start enumeration with prepared enumeration information */
 218         cdev = dfl_fpga_feature_devs_enumerate(info);
 219         if (IS_ERR(cdev)) {
 220                 dev_err(&pcidev->dev, "Enumeration failure\n");
 221                 ret = PTR_ERR(cdev);
 222                 goto irq_free_exit;
 223         }
 224
 225         drvdata->cdev = cdev;
 226
 227 irq_free_exit:
 228         if (ret)
 229                 cci_pci_free_irq(pcidev);
 230 enum_info_free_exit:
 231         dfl_fpga_enum_info_free(info);
 232
 233         return ret;
 234 }
 235
 236 static
 237 int cci_pci_probe(struct pci_dev *pcidev, const struct pci_device_id *pcidevid)
 238 {
 239         int ret;
 240
 241         ret = pcim_enable_device(pcidev);
 242         if (ret < 0) {
 243                 dev_err(&pcidev->dev, "Failed to enable device %d.\n", ret);
 244                 return ret;
 245         }
 246
 247         ret = pci_enable_pcie_error_reporting(pcidev);
 248         if (ret && ret != -EINVAL)
 249                 dev_info(&pcidev->dev, "PCIE AER unavailable %d.\n", ret);
 250
 251         pci_set_master(pcidev);
 252
 253         if (!pci_set_dma_mask(pcidev, DMA_BIT_MASK(64))) {
 254                 ret = pci_set_consistent_dma_mask(pcidev, DMA_BIT_MASK(64));
 255                 if (ret)
 256                         goto disable_error_report_exit;
 257         } else if (!pci_set_dma_mask(pcidev, DMA_BIT_MASK(32))) {
 258                 ret = pci_set_consistent_dma_mask(pcidev, DMA_BIT_MASK(32));
 259                 if (ret)
 260                         goto disable_error_report_exit;
 261         } else {
 262                 ret = -EIO;
 263                 dev_err(&pcidev->dev, "No suitable DMA support available.\n");
 264                 goto disable_error_report_exit;
 265         }
 266
 267         ret = cci_init_drvdata(pcidev);
 268         if (ret) {
 269                 dev_err(&pcidev->dev, "Fail to init drvdata %d.\n", ret);
 270                 goto disable_error_report_exit;
 271         }
 272
 273         ret = cci_enumerate_feature_devs(pcidev);
 274         if (!ret)
 275                 return ret;
 276
 277         dev_err(&pcidev->dev, "enumeration failure %d.\n", ret);
 278
 279 disable_error_report_exit:
 280         pci_disable_pcie_error_reporting(pcidev);
 281         return ret;
 282 }
 283
 284 static int cci_pci_sriov_configure(struct pci_dev *pcidev, int num_vfs)
 285 {
 286         struct cci_drvdata *drvdata = pci_get_drvdata(pcidev);
 287         struct dfl_fpga_cdev *cdev = drvdata->cdev;
 288
 289         if (!num_vfs) {
 290                 /*
 291                  * disable SRIOV and then put released ports back to default
 292                  * PF access mode.
 293                  */
 294                 pci_disable_sriov(pcidev);
 295
 296                 dfl_fpga_cdev_config_ports_pf(cdev);
 297
 298         } else {
 299                 int ret;
 300
 301                 /*
 302                  * before enable SRIOV, put released ports into VF access mode
 303                  * first of all.
 304                  */
 305                 ret = dfl_fpga_cdev_config_ports_vf(cdev, num_vfs);
 306                 if (ret)
 307                         return ret;
 308
 309                 ret = pci_enable_sriov(pcidev, num_vfs);
 310                 if (ret) {
 311                         dfl_fpga_cdev_config_ports_pf(cdev);
 312                         return ret;
 313                 }
 314         }
 315
 316         return num_vfs;
 317 }
 318
 319 static void cci_pci_remove(struct pci_dev *pcidev)
 320 {
 321         if (dev_is_pf(&pcidev->dev))
 322                 cci_pci_sriov_configure(pcidev, 0);
 323
 324         cci_remove_feature_devs(pcidev);
 325         pci_disable_pcie_error_reporting(pcidev);
 326 }
 327
 328 static struct pci_driver cci_pci_driver = {
 329         .name = DRV_NAME,
 330         .id_table = cci_pcie_id_tbl,
 331         .probe = cci_pci_probe,
 332         .remove = cci_pci_remove,
 333         .sriov_configure = cci_pci_sriov_configure,
 334 };
 335
 336 module_pci_driver(cci_pci_driver);
 337
 338 MODULE_DESCRIPTION("FPGA DFL PCIe Device Driver");
 339 MODULE_AUTHOR("Intel Corporation");
 340 MODULE_LICENSE("GPL v2");