1 // SPDX-License-Identifier: GPL-2.0-only
3 * VIA IDE driver for Linux. Supported southbridges:
5 * vt82c576, vt82c586, vt82c586a, vt82c586b, vt82c596a, vt82c596b,
6 * vt82c686, vt82c686a, vt82c686b, vt8231, vt8233, vt8233c, vt8233a,
7 * vt8235, vt8237, vt8237a
9 * Copyright (c) 2000-2002 Vojtech Pavlik
10 * Copyright (c) 2007-2010 Bartlomiej Zolnierkiewicz
12 * Based on the work of:
18 * Obsolete device documentation publicly available from via.com.tw
19 * Current device documentation available under NDA only
23 #include <linux/module.h>
24 #include <linux/kernel.h>
25 #include <linux/slab.h>
26 #include <linux/pci.h>
27 #include <linux/init.h>
28 #include <linux/ide.h>
29 #include <linux/dmi.h>
31 #ifdef CONFIG_PPC_CHRP
32 #include <asm/processor.h>
35 #define DRV_NAME "via82cxxx"
37 #define VIA_IDE_ENABLE 0x40
38 #define VIA_IDE_CONFIG 0x41
39 #define VIA_FIFO_CONFIG 0x43
40 #define VIA_MISC_1 0x44
41 #define VIA_MISC_2 0x45
42 #define VIA_MISC_3 0x46
43 #define VIA_DRIVE_TIMING 0x48
44 #define VIA_8BIT_TIMING 0x4e
45 #define VIA_ADDRESS_SETUP 0x4c
46 #define VIA_UDMA_TIMING 0x50
48 #define VIA_BAD_PREQ 0x01 /* Crashes if PREQ# till DDACK# set */
49 #define VIA_BAD_CLK66 0x02 /* 66 MHz clock doesn't work correctly */
50 #define VIA_SET_FIFO 0x04 /* Needs to have FIFO split set */
51 #define VIA_NO_UNMASK 0x08 /* Doesn't work with IRQ unmasking on */
52 #define VIA_BAD_ID 0x10 /* Has wrong vendor ID (0x1107) */
53 #define VIA_BAD_AST 0x20 /* Don't touch Address Setup Timing */
54 #define VIA_SATA_PATA 0x80 /* SATA/PATA combined configuration */
57 VIA_IDFLAG_SINGLE
= (1 << 1), /* single channel controller */
61 * VIA SouthBridge chips.
64 static struct via_isa_bridge
{
71 } via_isa_bridges
[] = {
72 { "vx855", PCI_DEVICE_ID_VIA_VX855
, 0x00, 0x2f, ATA_UDMA6
, VIA_BAD_AST
| VIA_SATA_PATA
},
73 { "vx800", PCI_DEVICE_ID_VIA_VX800
, 0x00, 0x2f, ATA_UDMA6
, VIA_BAD_AST
| VIA_SATA_PATA
},
74 { "cx700", PCI_DEVICE_ID_VIA_CX700
, 0x00, 0x2f, ATA_UDMA6
, VIA_BAD_AST
| VIA_SATA_PATA
},
75 { "vt8261", PCI_DEVICE_ID_VIA_8261
, 0x00, 0x2f, ATA_UDMA6
, VIA_BAD_AST
},
76 { "vt8237s", PCI_DEVICE_ID_VIA_8237S
, 0x00, 0x2f, ATA_UDMA6
, VIA_BAD_AST
},
77 { "vt6410", PCI_DEVICE_ID_VIA_6410
, 0x00, 0x2f, ATA_UDMA6
, VIA_BAD_AST
},
78 { "vt6415", PCI_DEVICE_ID_VIA_6415
, 0x00, 0xff, ATA_UDMA6
, VIA_BAD_AST
},
79 { "vt8251", PCI_DEVICE_ID_VIA_8251
, 0x00, 0x2f, ATA_UDMA6
, VIA_BAD_AST
},
80 { "vt8237", PCI_DEVICE_ID_VIA_8237
, 0x00, 0x2f, ATA_UDMA6
, VIA_BAD_AST
},
81 { "vt8237a", PCI_DEVICE_ID_VIA_8237A
, 0x00, 0x2f, ATA_UDMA6
, VIA_BAD_AST
},
82 { "vt8235", PCI_DEVICE_ID_VIA_8235
, 0x00, 0x2f, ATA_UDMA6
, VIA_BAD_AST
},
83 { "vt8233a", PCI_DEVICE_ID_VIA_8233A
, 0x00, 0x2f, ATA_UDMA6
, VIA_BAD_AST
},
84 { "vt8233c", PCI_DEVICE_ID_VIA_8233C_0
, 0x00, 0x2f, ATA_UDMA5
, },
85 { "vt8233", PCI_DEVICE_ID_VIA_8233_0
, 0x00, 0x2f, ATA_UDMA5
, },
86 { "vt8231", PCI_DEVICE_ID_VIA_8231
, 0x00, 0x2f, ATA_UDMA5
, },
87 { "vt82c686b", PCI_DEVICE_ID_VIA_82C686
, 0x40, 0x4f, ATA_UDMA5
, },
88 { "vt82c686a", PCI_DEVICE_ID_VIA_82C686
, 0x10, 0x2f, ATA_UDMA4
, },
89 { "vt82c686", PCI_DEVICE_ID_VIA_82C686
, 0x00, 0x0f, ATA_UDMA2
, VIA_BAD_CLK66
},
90 { "vt82c596b", PCI_DEVICE_ID_VIA_82C596
, 0x10, 0x2f, ATA_UDMA4
, },
91 { "vt82c596a", PCI_DEVICE_ID_VIA_82C596
, 0x00, 0x0f, ATA_UDMA2
, VIA_BAD_CLK66
},
92 { "vt82c586b", PCI_DEVICE_ID_VIA_82C586_0
, 0x47, 0x4f, ATA_UDMA2
, VIA_SET_FIFO
},
93 { "vt82c586b", PCI_DEVICE_ID_VIA_82C586_0
, 0x40, 0x46, ATA_UDMA2
, VIA_SET_FIFO
| VIA_BAD_PREQ
},
94 { "vt82c586b", PCI_DEVICE_ID_VIA_82C586_0
, 0x30, 0x3f, ATA_UDMA2
, VIA_SET_FIFO
},
95 { "vt82c586a", PCI_DEVICE_ID_VIA_82C586_0
, 0x20, 0x2f, ATA_UDMA2
, VIA_SET_FIFO
},
96 { "vt82c586", PCI_DEVICE_ID_VIA_82C586_0
, 0x00, 0x0f, 0x00, VIA_SET_FIFO
},
97 { "vt82c576", PCI_DEVICE_ID_VIA_82C576
, 0x00, 0x2f, 0x00, VIA_SET_FIFO
| VIA_NO_UNMASK
},
98 { "vt82c576", PCI_DEVICE_ID_VIA_82C576
, 0x00, 0x2f, 0x00, VIA_SET_FIFO
| VIA_NO_UNMASK
| VIA_BAD_ID
},
99 { "vtxxxx", PCI_DEVICE_ID_VIA_ANON
, 0x00, 0x2f, ATA_UDMA6
, VIA_BAD_AST
},
103 static unsigned int via_clock
;
104 static char *via_dma
[] = { "16", "25", "33", "44", "66", "100", "133" };
108 struct via_isa_bridge
*via_config
;
109 unsigned int via_80w
;
113 * via_set_speed - write timing registers
116 * @timing: IDE timing data to use
118 * via_set_speed writes timing values to the chipset registers
121 static void via_set_speed(ide_hwif_t
*hwif
, u8 dn
, struct ide_timing
*timing
)
123 struct pci_dev
*dev
= to_pci_dev(hwif
->dev
);
124 struct ide_host
*host
= pci_get_drvdata(dev
);
125 struct via82cxxx_dev
*vdev
= host
->host_priv
;
128 if (~vdev
->via_config
->flags
& VIA_BAD_AST
) {
129 pci_read_config_byte(dev
, VIA_ADDRESS_SETUP
, &t
);
130 t
= (t
& ~(3 << ((3 - dn
) << 1))) | ((clamp_val(timing
->setup
, 1, 4) - 1) << ((3 - dn
) << 1));
131 pci_write_config_byte(dev
, VIA_ADDRESS_SETUP
, t
);
134 pci_write_config_byte(dev
, VIA_8BIT_TIMING
+ (1 - (dn
>> 1)),
135 ((clamp_val(timing
->act8b
, 1, 16) - 1) << 4) | (clamp_val(timing
->rec8b
, 1, 16) - 1));
137 pci_write_config_byte(dev
, VIA_DRIVE_TIMING
+ (3 - dn
),
138 ((clamp_val(timing
->active
, 1, 16) - 1) << 4) | (clamp_val(timing
->recover
, 1, 16) - 1));
140 switch (vdev
->via_config
->udma_mask
) {
141 case ATA_UDMA2
: t
= timing
->udma
? (0xe0 | (clamp_val(timing
->udma
, 2, 5) - 2)) : 0x03; break;
142 case ATA_UDMA4
: t
= timing
->udma
? (0xe8 | (clamp_val(timing
->udma
, 2, 9) - 2)) : 0x0f; break;
143 case ATA_UDMA5
: t
= timing
->udma
? (0xe0 | (clamp_val(timing
->udma
, 2, 9) - 2)) : 0x07; break;
144 case ATA_UDMA6
: t
= timing
->udma
? (0xe0 | (clamp_val(timing
->udma
, 2, 9) - 2)) : 0x07; break;
147 /* Set UDMA unless device is not UDMA capable */
148 if (vdev
->via_config
->udma_mask
) {
151 pci_read_config_byte(dev
, VIA_UDMA_TIMING
+ 3 - dn
, &udma_etc
);
153 /* clear transfer mode bit */
157 /* preserve 80-wire cable detection bit */
162 pci_write_config_byte(dev
, VIA_UDMA_TIMING
+ 3 - dn
, udma_etc
);
167 * via_set_drive - configure transfer mode
169 * @drive: Drive to set up
171 * via_set_drive() computes timing values configures the chipset to
172 * a desired transfer mode. It also can be called by upper layers.
175 static void via_set_drive(ide_hwif_t
*hwif
, ide_drive_t
*drive
)
177 ide_drive_t
*peer
= ide_get_pair_dev(drive
);
178 struct ide_host
*host
= dev_get_drvdata(hwif
->dev
);
179 struct via82cxxx_dev
*vdev
= host
->host_priv
;
180 struct ide_timing t
, p
;
182 const u8 speed
= drive
->dma_mode
;
184 T
= 1000000000 / via_clock
;
186 switch (vdev
->via_config
->udma_mask
) {
187 case ATA_UDMA2
: UT
= T
; break;
188 case ATA_UDMA4
: UT
= T
/2; break;
189 case ATA_UDMA5
: UT
= T
/3; break;
190 case ATA_UDMA6
: UT
= T
/4; break;
194 ide_timing_compute(drive
, speed
, &t
, T
, UT
);
197 ide_timing_compute(peer
, peer
->pio_mode
, &p
, T
, UT
);
198 ide_timing_merge(&p
, &t
, &t
, IDE_TIMING_8BIT
);
201 via_set_speed(hwif
, drive
->dn
, &t
);
205 * via_set_pio_mode - set host controller for PIO mode
209 * A callback from the upper layers for PIO-only tuning.
212 static void via_set_pio_mode(ide_hwif_t
*hwif
, ide_drive_t
*drive
)
214 drive
->dma_mode
= drive
->pio_mode
;
215 via_set_drive(hwif
, drive
);
218 static struct via_isa_bridge
*via_config_find(struct pci_dev
**isa
)
220 struct via_isa_bridge
*via_config
;
222 for (via_config
= via_isa_bridges
;
223 via_config
->id
!= PCI_DEVICE_ID_VIA_ANON
; via_config
++)
224 if ((*isa
= pci_get_device(PCI_VENDOR_ID_VIA
+
225 !!(via_config
->flags
& VIA_BAD_ID
),
226 via_config
->id
, NULL
))) {
228 if ((*isa
)->revision
>= via_config
->rev_min
&&
229 (*isa
)->revision
<= via_config
->rev_max
)
238 * Check and handle 80-wire cable presence
240 static void via_cable_detect(struct via82cxxx_dev
*vdev
, u32 u
)
244 switch (vdev
->via_config
->udma_mask
) {
246 for (i
= 24; i
>= 0; i
-= 8)
247 if (((u
>> (i
& 16)) & 8) &&
249 (((u
>> i
) & 7) < 2)) {
254 vdev
->via_80w
|= (1 << (1 - (i
>> 4)));
259 for (i
= 24; i
>= 0; i
-= 8)
260 if (((u
>> i
) & 0x10) ||
261 (((u
>> i
) & 0x20) &&
262 (((u
>> i
) & 7) < 4))) {
263 /* BIOS 80-wire bit or
264 * UDMA w/ < 60ns/cycle
266 vdev
->via_80w
|= (1 << (1 - (i
>> 4)));
271 for (i
= 24; i
>= 0; i
-= 8)
272 if (((u
>> i
) & 0x10) ||
273 (((u
>> i
) & 0x20) &&
274 (((u
>> i
) & 7) < 6))) {
275 /* BIOS 80-wire bit or
276 * UDMA w/ < 60ns/cycle
278 vdev
->via_80w
|= (1 << (1 - (i
>> 4)));
285 * init_chipset_via82cxxx - initialization handler
288 * The initialization callback. Here we determine the IDE chip type
289 * and initialize its drive independent registers.
292 static int init_chipset_via82cxxx(struct pci_dev
*dev
)
294 struct ide_host
*host
= pci_get_drvdata(dev
);
295 struct via82cxxx_dev
*vdev
= host
->host_priv
;
296 struct via_isa_bridge
*via_config
= vdev
->via_config
;
301 * Detect cable and configure Clk66
303 pci_read_config_dword(dev
, VIA_UDMA_TIMING
, &u
);
305 via_cable_detect(vdev
, u
);
307 if (via_config
->udma_mask
== ATA_UDMA4
) {
309 pci_write_config_dword(dev
, VIA_UDMA_TIMING
, u
|0x80008);
310 } else if (via_config
->flags
& VIA_BAD_CLK66
) {
311 /* Would cause trouble on 596a and 686 */
312 pci_write_config_dword(dev
, VIA_UDMA_TIMING
, u
& ~0x80008);
316 * Check whether interfaces are enabled.
319 pci_read_config_byte(dev
, VIA_IDE_ENABLE
, &v
);
322 * Set up FIFO sizes and thresholds.
325 pci_read_config_byte(dev
, VIA_FIFO_CONFIG
, &t
);
327 /* Disable PREQ# till DDACK# */
328 if (via_config
->flags
& VIA_BAD_PREQ
) {
329 /* Would crash on 586b rev 41 */
333 /* Fix FIFO split between channels */
334 if (via_config
->flags
& VIA_SET_FIFO
) {
337 case 2: t
|= 0x00; break; /* 16 on primary */
338 case 1: t
|= 0x60; break; /* 16 on secondary */
339 case 3: t
|= 0x20; break; /* 8 pri 8 sec */
343 pci_write_config_byte(dev
, VIA_FIFO_CONFIG
, t
);
349 * Cable special cases
352 static const struct dmi_system_id cable_dmi_table
[] = {
354 .ident
= "Acer Ferrari 3400",
356 DMI_MATCH(DMI_BOARD_VENDOR
, "Acer,Inc."),
357 DMI_MATCH(DMI_BOARD_NAME
, "Ferrari 3400"),
363 static int via_cable_override(struct pci_dev
*pdev
)
366 if (dmi_check_system(cable_dmi_table
))
369 /* Arima W730-K8/Targa Visionary 811/... */
370 if (pdev
->subsystem_vendor
== 0x161F &&
371 pdev
->subsystem_device
== 0x2032)
377 static u8
via82cxxx_cable_detect(ide_hwif_t
*hwif
)
379 struct pci_dev
*pdev
= to_pci_dev(hwif
->dev
);
380 struct ide_host
*host
= pci_get_drvdata(pdev
);
381 struct via82cxxx_dev
*vdev
= host
->host_priv
;
383 if (via_cable_override(pdev
))
384 return ATA_CBL_PATA40_SHORT
;
386 if ((vdev
->via_config
->flags
& VIA_SATA_PATA
) && hwif
->channel
== 0)
389 if ((vdev
->via_80w
>> hwif
->channel
) & 1)
390 return ATA_CBL_PATA80
;
392 return ATA_CBL_PATA40
;
395 static const struct ide_port_ops via_port_ops
= {
396 .set_pio_mode
= via_set_pio_mode
,
397 .set_dma_mode
= via_set_drive
,
398 .cable_detect
= via82cxxx_cable_detect
,
401 static const struct ide_port_info via82cxxx_chipset
= {
403 .init_chipset
= init_chipset_via82cxxx
,
404 .enablebits
= { { 0x40, 0x02, 0x02 }, { 0x40, 0x01, 0x01 } },
405 .port_ops
= &via_port_ops
,
406 .host_flags
= IDE_HFLAG_PIO_NO_BLACKLIST
|
407 IDE_HFLAG_POST_SET_MODE
|
409 .pio_mask
= ATA_PIO5
,
410 .swdma_mask
= ATA_SWDMA2
,
411 .mwdma_mask
= ATA_MWDMA2
,
414 static int via_init_one(struct pci_dev
*dev
, const struct pci_device_id
*id
)
416 struct pci_dev
*isa
= NULL
;
417 struct via_isa_bridge
*via_config
;
418 struct via82cxxx_dev
*vdev
;
420 u8 idx
= id
->driver_data
;
421 struct ide_port_info d
;
423 d
= via82cxxx_chipset
;
426 * Find the ISA bridge and check we know what it is.
428 via_config
= via_config_find(&isa
);
431 * Print the boot message.
433 printk(KERN_INFO DRV_NAME
" %s: VIA %s (rev %02x) IDE %sDMA%s\n",
434 pci_name(dev
), via_config
->name
, isa
->revision
,
435 via_config
->udma_mask
? "U" : "MW",
436 via_dma
[via_config
->udma_mask
?
437 (fls(via_config
->udma_mask
) - 1) : 0]);
442 * Determine system bus clock.
444 via_clock
= (ide_pci_clk
? ide_pci_clk
: 33) * 1000;
447 case 33000: via_clock
= 33333; break;
448 case 37000: via_clock
= 37500; break;
449 case 41000: via_clock
= 41666; break;
452 if (via_clock
< 20000 || via_clock
> 50000) {
453 printk(KERN_WARNING DRV_NAME
": User given PCI clock speed "
454 "impossible (%d), using 33 MHz instead.\n", via_clock
);
459 d
.enablebits
[1].reg
= d
.enablebits
[0].reg
= 0;
461 d
.host_flags
|= IDE_HFLAG_NO_AUTODMA
;
463 if (idx
== VIA_IDFLAG_SINGLE
)
464 d
.host_flags
|= IDE_HFLAG_SINGLE
;
466 if ((via_config
->flags
& VIA_NO_UNMASK
) == 0)
467 d
.host_flags
|= IDE_HFLAG_UNMASK_IRQS
;
469 d
.udma_mask
= via_config
->udma_mask
;
471 vdev
= kzalloc(sizeof(*vdev
), GFP_KERNEL
);
473 printk(KERN_ERR DRV_NAME
" %s: out of memory :(\n",
478 vdev
->via_config
= via_config
;
480 rc
= ide_pci_init_one(dev
, &d
, vdev
);
487 static void via_remove(struct pci_dev
*dev
)
489 struct ide_host
*host
= pci_get_drvdata(dev
);
490 struct via82cxxx_dev
*vdev
= host
->host_priv
;
496 static const struct pci_device_id via_pci_tbl
[] = {
497 { PCI_VDEVICE(VIA
, PCI_DEVICE_ID_VIA_82C576_1
), 0 },
498 { PCI_VDEVICE(VIA
, PCI_DEVICE_ID_VIA_82C586_1
), 0 },
499 { PCI_VDEVICE(VIA
, PCI_DEVICE_ID_VIA_CX700_IDE
), 0 },
500 { PCI_VDEVICE(VIA
, PCI_DEVICE_ID_VIA_VX855_IDE
), VIA_IDFLAG_SINGLE
},
501 { PCI_VDEVICE(VIA
, PCI_DEVICE_ID_VIA_6410
), 1 },
502 { PCI_VDEVICE(VIA
, PCI_DEVICE_ID_VIA_6415
), 1 },
503 { PCI_VDEVICE(VIA
, PCI_DEVICE_ID_VIA_SATA_EIDE
), 1 },
506 MODULE_DEVICE_TABLE(pci
, via_pci_tbl
);
508 static struct pci_driver via_pci_driver
= {
510 .id_table
= via_pci_tbl
,
511 .probe
= via_init_one
,
512 .remove
= via_remove
,
513 .suspend
= ide_pci_suspend
,
514 .resume
= ide_pci_resume
,
517 static int __init
via_ide_init(void)
519 return ide_pci_register_driver(&via_pci_driver
);
522 static void __exit
via_ide_exit(void)
524 pci_unregister_driver(&via_pci_driver
);
527 module_init(via_ide_init
);
528 module_exit(via_ide_exit
);
530 MODULE_AUTHOR("Vojtech Pavlik, Bartlomiej Zolnierkiewicz, Michel Aubry, Jeff Garzik, Andre Hedrick");
531 MODULE_DESCRIPTION("PCI driver module for VIA IDE");
532 MODULE_LICENSE("GPL");