drivers/nvmem/sc27xx-efuse.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 // Copyright (C) 2018 Spreadtrum Communications Inc.
   3
   4 #include <linux/hwspinlock.h>
   5 #include <linux/module.h>
   6 #include <linux/of.h>
   7 #include <linux/of_device.h>
   8 #include <linux/platform_device.h>
   9 #include <linux/regmap.h>
  10 #include <linux/nvmem-provider.h>
  11
  12 /* PMIC global registers definition */
  13 #define SC27XX_MODULE_EN                0xc08
  14 #define SC2730_MODULE_EN                0x1808
  15 #define SC27XX_EFUSE_EN                 BIT(6)
  16
  17 /* Efuse controller registers definition */
  18 #define SC27XX_EFUSE_GLB_CTRL           0x0
  19 #define SC27XX_EFUSE_DATA_RD            0x4
  20 #define SC27XX_EFUSE_DATA_WR            0x8
  21 #define SC27XX_EFUSE_BLOCK_INDEX        0xc
  22 #define SC27XX_EFUSE_MODE_CTRL          0x10
  23 #define SC27XX_EFUSE_STATUS             0x14
  24 #define SC27XX_EFUSE_WR_TIMING_CTRL     0x20
  25 #define SC27XX_EFUSE_RD_TIMING_CTRL     0x24
  26 #define SC27XX_EFUSE_EFUSE_DEB_CTRL     0x28
  27
  28 /* Mask definition for SC27XX_EFUSE_BLOCK_INDEX register */
  29 #define SC27XX_EFUSE_BLOCK_MASK         GENMASK(4, 0)
  30
  31 /* Bits definitions for SC27XX_EFUSE_MODE_CTRL register */
  32 #define SC27XX_EFUSE_PG_START           BIT(0)
  33 #define SC27XX_EFUSE_RD_START           BIT(1)
  34 #define SC27XX_EFUSE_CLR_RDDONE         BIT(2)
  35
  36 /* Bits definitions for SC27XX_EFUSE_STATUS register */
  37 #define SC27XX_EFUSE_PGM_BUSY           BIT(0)
  38 #define SC27XX_EFUSE_READ_BUSY          BIT(1)
  39 #define SC27XX_EFUSE_STANDBY            BIT(2)
  40 #define SC27XX_EFUSE_GLOBAL_PROT        BIT(3)
  41 #define SC27XX_EFUSE_RD_DONE            BIT(4)
  42
  43 /* Block number and block width (bytes) definitions */
  44 #define SC27XX_EFUSE_BLOCK_MAX          32
  45 #define SC27XX_EFUSE_BLOCK_WIDTH        2
  46
  47 /* Timeout (ms) for the trylock of hardware spinlocks */
  48 #define SC27XX_EFUSE_HWLOCK_TIMEOUT     5000
  49
  50 /* Timeout (us) of polling the status */
  51 #define SC27XX_EFUSE_POLL_TIMEOUT       3000000
  52 #define SC27XX_EFUSE_POLL_DELAY_US      10000
  53
  54 /*
  55  * Since different PMICs of SC27xx series can have different
  56  * address , we should save address in the device data structure.
  57  */
  58 struct sc27xx_efuse_variant_data {
  59         u32 module_en;
  60 };
  61
  62 struct sc27xx_efuse {
  63         struct device *dev;
  64         struct regmap *regmap;
  65         struct hwspinlock *hwlock;
  66         struct mutex mutex;
  67         u32 base;
  68         const struct sc27xx_efuse_variant_data *var_data;
  69 };
  70
  71 static const struct sc27xx_efuse_variant_data sc2731_edata = {
  72         .module_en = SC27XX_MODULE_EN,
  73 };
  74
  75 static const struct sc27xx_efuse_variant_data sc2730_edata = {
  76         .module_en = SC2730_MODULE_EN,
  77 };
  78
  79 /*
  80  * On Spreadtrum platform, we have multi-subsystems will access the unique
  81  * efuse controller, so we need one hardware spinlock to synchronize between
  82  * the multiple subsystems.
  83  */
  84 static int sc27xx_efuse_lock(struct sc27xx_efuse *efuse)
  85 {
  86         int ret;
  87
  88         mutex_lock(&efuse->mutex);
  89
  90         ret = hwspin_lock_timeout_raw(efuse->hwlock,
  91                                       SC27XX_EFUSE_HWLOCK_TIMEOUT);
  92         if (ret) {
  93                 dev_err(efuse->dev, "timeout to get the hwspinlock\n");
  94                 mutex_unlock(&efuse->mutex);
  95                 return ret;
  96         }
  97
  98         return 0;
  99 }
 100
 101 static void sc27xx_efuse_unlock(struct sc27xx_efuse *efuse)
 102 {
 103         hwspin_unlock_raw(efuse->hwlock);
 104         mutex_unlock(&efuse->mutex);
 105 }
 106
 107 static int sc27xx_efuse_poll_status(struct sc27xx_efuse *efuse, u32 bits)
 108 {
 109         int ret;
 110         u32 val;
 111
 112         ret = regmap_read_poll_timeout(efuse->regmap,
 113                                        efuse->base + SC27XX_EFUSE_STATUS,
 114                                        val, (val & bits),
 115                                        SC27XX_EFUSE_POLL_DELAY_US,
 116                                        SC27XX_EFUSE_POLL_TIMEOUT);
 117         if (ret) {
 118                 dev_err(efuse->dev, "timeout to update the efuse status\n");
 119                 return ret;
 120         }
 121
 122         return 0;
 123 }
 124
 125 static int sc27xx_efuse_read(void *context, u32 offset, void *val, size_t bytes)
 126 {
 127         struct sc27xx_efuse *efuse = context;
 128         u32 buf, blk_index = offset / SC27XX_EFUSE_BLOCK_WIDTH;
 129         u32 blk_offset = (offset % SC27XX_EFUSE_BLOCK_WIDTH) * BITS_PER_BYTE;
 130         int ret;
 131
 132         if (blk_index > SC27XX_EFUSE_BLOCK_MAX ||
 133             bytes > SC27XX_EFUSE_BLOCK_WIDTH)
 134                 return -EINVAL;
 135
 136         ret = sc27xx_efuse_lock(efuse);
 137         if (ret)
 138                 return ret;
 139
 140         /* Enable the efuse controller. */
 141         ret = regmap_update_bits(efuse->regmap, efuse->var_data->module_en,
 142                                  SC27XX_EFUSE_EN, SC27XX_EFUSE_EN);
 143         if (ret)
 144                 goto unlock_efuse;
 145
 146         /*
 147          * Before reading, we should ensure the efuse controller is in
 148          * standby state.
 149          */
 150         ret = sc27xx_efuse_poll_status(efuse, SC27XX_EFUSE_STANDBY);
 151         if (ret)
 152                 goto disable_efuse;
 153
 154         /* Set the block address to be read. */
 155         ret = regmap_write(efuse->regmap,
 156                            efuse->base + SC27XX_EFUSE_BLOCK_INDEX,
 157                            blk_index & SC27XX_EFUSE_BLOCK_MASK);
 158         if (ret)
 159                 goto disable_efuse;
 160
 161         /* Start reading process from efuse memory. */
 162         ret = regmap_update_bits(efuse->regmap,
 163                                  efuse->base + SC27XX_EFUSE_MODE_CTRL,
 164                                  SC27XX_EFUSE_RD_START,
 165                                  SC27XX_EFUSE_RD_START);
 166         if (ret)
 167                 goto disable_efuse;
 168
 169         /*
 170          * Polling the read done status to make sure the reading process
 171          * is completed, that means the data can be read out now.
 172          */
 173         ret = sc27xx_efuse_poll_status(efuse, SC27XX_EFUSE_RD_DONE);
 174         if (ret)
 175                 goto disable_efuse;
 176
 177         /* Read data from efuse memory. */
 178         ret = regmap_read(efuse->regmap, efuse->base + SC27XX_EFUSE_DATA_RD,
 179                           &buf);
 180         if (ret)
 181                 goto disable_efuse;
 182
 183         /* Clear the read done flag. */
 184         ret = regmap_update_bits(efuse->regmap,
 185                                  efuse->base + SC27XX_EFUSE_MODE_CTRL,
 186                                  SC27XX_EFUSE_CLR_RDDONE,
 187                                  SC27XX_EFUSE_CLR_RDDONE);
 188
 189 disable_efuse:
 190         /* Disable the efuse controller after reading. */
 191         regmap_update_bits(efuse->regmap, efuse->var_data->module_en, SC27XX_EFUSE_EN, 0);
 192 unlock_efuse:
 193         sc27xx_efuse_unlock(efuse);
 194
 195         if (!ret) {
 196                 buf >>= blk_offset;
 197                 memcpy(val, &buf, bytes);
 198         }
 199
 200         return ret;
 201 }
 202
 203 static int sc27xx_efuse_probe(struct platform_device *pdev)
 204 {
 205         struct device_node *np = pdev->dev.of_node;
 206         struct nvmem_config econfig = { };
 207         struct nvmem_device *nvmem;
 208         struct sc27xx_efuse *efuse;
 209         int ret;
 210
 211         efuse = devm_kzalloc(&pdev->dev, sizeof(*efuse), GFP_KERNEL);
 212         if (!efuse)
 213                 return -ENOMEM;
 214
 215         efuse->regmap = dev_get_regmap(pdev->dev.parent, NULL);
 216         if (!efuse->regmap) {
 217                 dev_err(&pdev->dev, "failed to get efuse regmap\n");
 218                 return -ENODEV;
 219         }
 220
 221         ret = of_property_read_u32(np, "reg", &efuse->base);
 222         if (ret) {
 223                 dev_err(&pdev->dev, "failed to get efuse base address\n");
 224                 return ret;
 225         }
 226
 227         ret = of_hwspin_lock_get_id(np, 0);
 228         if (ret < 0) {
 229                 dev_err(&pdev->dev, "failed to get hwspinlock id\n");
 230                 return ret;
 231         }
 232
 233         efuse->hwlock = devm_hwspin_lock_request_specific(&pdev->dev, ret);
 234         if (!efuse->hwlock) {
 235                 dev_err(&pdev->dev, "failed to request hwspinlock\n");
 236                 return -ENXIO;
 237         }
 238
 239         mutex_init(&efuse->mutex);
 240         efuse->dev = &pdev->dev;
 241         efuse->var_data = of_device_get_match_data(&pdev->dev);
 242
 243         econfig.stride = 1;
 244         econfig.word_size = 1;
 245         econfig.read_only = true;
 246         econfig.name = "sc27xx-efuse";
 247         econfig.size = SC27XX_EFUSE_BLOCK_MAX * SC27XX_EFUSE_BLOCK_WIDTH;
 248         econfig.reg_read = sc27xx_efuse_read;
 249         econfig.priv = efuse;
 250         econfig.dev = &pdev->dev;
 251         nvmem = devm_nvmem_register(&pdev->dev, &econfig);
 252         if (IS_ERR(nvmem)) {
 253                 dev_err(&pdev->dev, "failed to register nvmem config\n");
 254                 return PTR_ERR(nvmem);
 255         }
 256
 257         return 0;
 258 }
 259
 260 static const struct of_device_id sc27xx_efuse_of_match[] = {
 261         { .compatible = "sprd,sc2731-efuse", .data = &sc2731_edata},
 262         { .compatible = "sprd,sc2730-efuse", .data = &sc2730_edata},
 263         { }
 264 };
 265
 266 static struct platform_driver sc27xx_efuse_driver = {
 267         .probe = sc27xx_efuse_probe,
 268         .driver = {
 269                 .name = "sc27xx-efuse",
 270                 .of_match_table = sc27xx_efuse_of_match,
 271         },
 272 };
 273
 274 module_platform_driver(sc27xx_efuse_driver);
 275
 276 MODULE_AUTHOR("Freeman Liu <freeman.liu@spreadtrum.com>");
 277 MODULE_DESCRIPTION("Spreadtrum SC27xx efuse driver");
 278 MODULE_LICENSE("GPL v2");