1 // SPDX-License-Identifier: GPL-2.0+
3 // SLG51000 High PSRR, Multi-Output Regulators
4 // Copyright (C) 2019 Dialog Semiconductor
6 // Author: Eric Jeong <eric.jeong.opensource@diasemi.com>
9 #include <linux/gpio/consumer.h>
10 #include <linux/i2c.h>
11 #include <linux/init.h>
12 #include <linux/interrupt.h>
13 #include <linux/irq.h>
14 #include <linux/module.h>
16 #include <linux/regmap.h>
17 #include <linux/regulator/driver.h>
18 #include <linux/regulator/machine.h>
19 #include <linux/regulator/of_regulator.h>
20 #include "slg51000-regulator.h"
22 #define SLG51000_SCTL_EVT 7
23 #define SLG51000_MAX_EVT_REGISTER 8
24 #define SLG51000_LDOHP_LV_MIN 1200000
25 #define SLG51000_LDOHP_HV_MIN 2400000
27 enum slg51000_regulators
{
28 SLG51000_REGULATOR_LDO1
= 0,
29 SLG51000_REGULATOR_LDO2
,
30 SLG51000_REGULATOR_LDO3
,
31 SLG51000_REGULATOR_LDO4
,
32 SLG51000_REGULATOR_LDO5
,
33 SLG51000_REGULATOR_LDO6
,
34 SLG51000_REGULATOR_LDO7
,
35 SLG51000_MAX_REGULATORS
,
40 struct regmap
*regmap
;
41 struct regulator_desc
*rdesc
[SLG51000_MAX_REGULATORS
];
42 struct regulator_dev
*rdev
[SLG51000_MAX_REGULATORS
];
43 struct gpio_desc
*cs_gpiod
;
47 struct slg51000_evt_sta
{
52 static const struct slg51000_evt_sta es_reg
[SLG51000_MAX_EVT_REGISTER
] = {
53 {SLG51000_LDO1_EVENT
, SLG51000_LDO1_STATUS
},
54 {SLG51000_LDO2_EVENT
, SLG51000_LDO2_STATUS
},
55 {SLG51000_LDO3_EVENT
, SLG51000_LDO3_STATUS
},
56 {SLG51000_LDO4_EVENT
, SLG51000_LDO4_STATUS
},
57 {SLG51000_LDO5_EVENT
, SLG51000_LDO5_STATUS
},
58 {SLG51000_LDO6_EVENT
, SLG51000_LDO6_STATUS
},
59 {SLG51000_LDO7_EVENT
, SLG51000_LDO7_STATUS
},
60 {SLG51000_SYSCTL_EVENT
, SLG51000_SYSCTL_STATUS
},
63 static const struct regmap_range slg51000_writeable_ranges
[] = {
64 regmap_reg_range(SLG51000_SYSCTL_MATRIX_CONF_A
,
65 SLG51000_SYSCTL_MATRIX_CONF_A
),
66 regmap_reg_range(SLG51000_LDO1_VSEL
, SLG51000_LDO1_VSEL
),
67 regmap_reg_range(SLG51000_LDO1_MINV
, SLG51000_LDO1_MAXV
),
68 regmap_reg_range(SLG51000_LDO1_IRQ_MASK
, SLG51000_LDO1_IRQ_MASK
),
69 regmap_reg_range(SLG51000_LDO2_VSEL
, SLG51000_LDO2_VSEL
),
70 regmap_reg_range(SLG51000_LDO2_MINV
, SLG51000_LDO2_MAXV
),
71 regmap_reg_range(SLG51000_LDO2_IRQ_MASK
, SLG51000_LDO2_IRQ_MASK
),
72 regmap_reg_range(SLG51000_LDO3_VSEL
, SLG51000_LDO3_VSEL
),
73 regmap_reg_range(SLG51000_LDO3_MINV
, SLG51000_LDO3_MAXV
),
74 regmap_reg_range(SLG51000_LDO3_IRQ_MASK
, SLG51000_LDO3_IRQ_MASK
),
75 regmap_reg_range(SLG51000_LDO4_VSEL
, SLG51000_LDO4_VSEL
),
76 regmap_reg_range(SLG51000_LDO4_MINV
, SLG51000_LDO4_MAXV
),
77 regmap_reg_range(SLG51000_LDO4_IRQ_MASK
, SLG51000_LDO4_IRQ_MASK
),
78 regmap_reg_range(SLG51000_LDO5_VSEL
, SLG51000_LDO5_VSEL
),
79 regmap_reg_range(SLG51000_LDO5_MINV
, SLG51000_LDO5_MAXV
),
80 regmap_reg_range(SLG51000_LDO5_IRQ_MASK
, SLG51000_LDO5_IRQ_MASK
),
81 regmap_reg_range(SLG51000_LDO6_VSEL
, SLG51000_LDO6_VSEL
),
82 regmap_reg_range(SLG51000_LDO6_MINV
, SLG51000_LDO6_MAXV
),
83 regmap_reg_range(SLG51000_LDO6_IRQ_MASK
, SLG51000_LDO6_IRQ_MASK
),
84 regmap_reg_range(SLG51000_LDO7_VSEL
, SLG51000_LDO7_VSEL
),
85 regmap_reg_range(SLG51000_LDO7_MINV
, SLG51000_LDO7_MAXV
),
86 regmap_reg_range(SLG51000_LDO7_IRQ_MASK
, SLG51000_LDO7_IRQ_MASK
),
87 regmap_reg_range(SLG51000_OTP_IRQ_MASK
, SLG51000_OTP_IRQ_MASK
),
90 static const struct regmap_range slg51000_readable_ranges
[] = {
91 regmap_reg_range(SLG51000_SYSCTL_PATN_ID_B0
,
92 SLG51000_SYSCTL_PATN_ID_B2
),
93 regmap_reg_range(SLG51000_SYSCTL_SYS_CONF_A
,
94 SLG51000_SYSCTL_SYS_CONF_A
),
95 regmap_reg_range(SLG51000_SYSCTL_SYS_CONF_D
,
96 SLG51000_SYSCTL_MATRIX_CONF_B
),
97 regmap_reg_range(SLG51000_SYSCTL_REFGEN_CONF_C
,
98 SLG51000_SYSCTL_UVLO_CONF_A
),
99 regmap_reg_range(SLG51000_SYSCTL_FAULT_LOG1
, SLG51000_SYSCTL_IRQ_MASK
),
100 regmap_reg_range(SLG51000_IO_GPIO1_CONF
, SLG51000_IO_GPIO_STATUS
),
101 regmap_reg_range(SLG51000_LUTARRAY_LUT_VAL_0
,
102 SLG51000_LUTARRAY_LUT_VAL_11
),
103 regmap_reg_range(SLG51000_MUXARRAY_INPUT_SEL_0
,
104 SLG51000_MUXARRAY_INPUT_SEL_63
),
105 regmap_reg_range(SLG51000_PWRSEQ_RESOURCE_EN_0
,
106 SLG51000_PWRSEQ_INPUT_SENSE_CONF_B
),
107 regmap_reg_range(SLG51000_LDO1_VSEL
, SLG51000_LDO1_VSEL
),
108 regmap_reg_range(SLG51000_LDO1_MINV
, SLG51000_LDO1_MAXV
),
109 regmap_reg_range(SLG51000_LDO1_MISC1
, SLG51000_LDO1_VSEL_ACTUAL
),
110 regmap_reg_range(SLG51000_LDO1_EVENT
, SLG51000_LDO1_IRQ_MASK
),
111 regmap_reg_range(SLG51000_LDO2_VSEL
, SLG51000_LDO2_VSEL
),
112 regmap_reg_range(SLG51000_LDO2_MINV
, SLG51000_LDO2_MAXV
),
113 regmap_reg_range(SLG51000_LDO2_MISC1
, SLG51000_LDO2_VSEL_ACTUAL
),
114 regmap_reg_range(SLG51000_LDO2_EVENT
, SLG51000_LDO2_IRQ_MASK
),
115 regmap_reg_range(SLG51000_LDO3_VSEL
, SLG51000_LDO3_VSEL
),
116 regmap_reg_range(SLG51000_LDO3_MINV
, SLG51000_LDO3_MAXV
),
117 regmap_reg_range(SLG51000_LDO3_CONF1
, SLG51000_LDO3_VSEL_ACTUAL
),
118 regmap_reg_range(SLG51000_LDO3_EVENT
, SLG51000_LDO3_IRQ_MASK
),
119 regmap_reg_range(SLG51000_LDO4_VSEL
, SLG51000_LDO4_VSEL
),
120 regmap_reg_range(SLG51000_LDO4_MINV
, SLG51000_LDO4_MAXV
),
121 regmap_reg_range(SLG51000_LDO4_CONF1
, SLG51000_LDO4_VSEL_ACTUAL
),
122 regmap_reg_range(SLG51000_LDO4_EVENT
, SLG51000_LDO4_IRQ_MASK
),
123 regmap_reg_range(SLG51000_LDO5_VSEL
, SLG51000_LDO5_VSEL
),
124 regmap_reg_range(SLG51000_LDO5_MINV
, SLG51000_LDO5_MAXV
),
125 regmap_reg_range(SLG51000_LDO5_TRIM2
, SLG51000_LDO5_TRIM2
),
126 regmap_reg_range(SLG51000_LDO5_CONF1
, SLG51000_LDO5_VSEL_ACTUAL
),
127 regmap_reg_range(SLG51000_LDO5_EVENT
, SLG51000_LDO5_IRQ_MASK
),
128 regmap_reg_range(SLG51000_LDO6_VSEL
, SLG51000_LDO6_VSEL
),
129 regmap_reg_range(SLG51000_LDO6_MINV
, SLG51000_LDO6_MAXV
),
130 regmap_reg_range(SLG51000_LDO6_TRIM2
, SLG51000_LDO6_TRIM2
),
131 regmap_reg_range(SLG51000_LDO6_CONF1
, SLG51000_LDO6_VSEL_ACTUAL
),
132 regmap_reg_range(SLG51000_LDO6_EVENT
, SLG51000_LDO6_IRQ_MASK
),
133 regmap_reg_range(SLG51000_LDO7_VSEL
, SLG51000_LDO7_VSEL
),
134 regmap_reg_range(SLG51000_LDO7_MINV
, SLG51000_LDO7_MAXV
),
135 regmap_reg_range(SLG51000_LDO7_CONF1
, SLG51000_LDO7_VSEL_ACTUAL
),
136 regmap_reg_range(SLG51000_LDO7_EVENT
, SLG51000_LDO7_IRQ_MASK
),
137 regmap_reg_range(SLG51000_OTP_EVENT
, SLG51000_OTP_EVENT
),
138 regmap_reg_range(SLG51000_OTP_IRQ_MASK
, SLG51000_OTP_IRQ_MASK
),
139 regmap_reg_range(SLG51000_OTP_LOCK_OTP_PROG
, SLG51000_OTP_LOCK_CTRL
),
140 regmap_reg_range(SLG51000_LOCK_GLOBAL_LOCK_CTRL1
,
141 SLG51000_LOCK_GLOBAL_LOCK_CTRL1
),
144 static const struct regmap_range slg51000_volatile_ranges
[] = {
145 regmap_reg_range(SLG51000_SYSCTL_FAULT_LOG1
, SLG51000_SYSCTL_STATUS
),
146 regmap_reg_range(SLG51000_IO_GPIO_STATUS
, SLG51000_IO_GPIO_STATUS
),
147 regmap_reg_range(SLG51000_LDO1_EVENT
, SLG51000_LDO1_STATUS
),
148 regmap_reg_range(SLG51000_LDO2_EVENT
, SLG51000_LDO2_STATUS
),
149 regmap_reg_range(SLG51000_LDO3_EVENT
, SLG51000_LDO3_STATUS
),
150 regmap_reg_range(SLG51000_LDO4_EVENT
, SLG51000_LDO4_STATUS
),
151 regmap_reg_range(SLG51000_LDO5_EVENT
, SLG51000_LDO5_STATUS
),
152 regmap_reg_range(SLG51000_LDO6_EVENT
, SLG51000_LDO6_STATUS
),
153 regmap_reg_range(SLG51000_LDO7_EVENT
, SLG51000_LDO7_STATUS
),
154 regmap_reg_range(SLG51000_OTP_EVENT
, SLG51000_OTP_EVENT
),
157 static const struct regmap_access_table slg51000_writeable_table
= {
158 .yes_ranges
= slg51000_writeable_ranges
,
159 .n_yes_ranges
= ARRAY_SIZE(slg51000_writeable_ranges
),
162 static const struct regmap_access_table slg51000_readable_table
= {
163 .yes_ranges
= slg51000_readable_ranges
,
164 .n_yes_ranges
= ARRAY_SIZE(slg51000_readable_ranges
),
167 static const struct regmap_access_table slg51000_volatile_table
= {
168 .yes_ranges
= slg51000_volatile_ranges
,
169 .n_yes_ranges
= ARRAY_SIZE(slg51000_volatile_ranges
),
172 static const struct regmap_config slg51000_regmap_config
= {
175 .max_register
= 0x8000,
176 .wr_table
= &slg51000_writeable_table
,
177 .rd_table
= &slg51000_readable_table
,
178 .volatile_table
= &slg51000_volatile_table
,
181 static const struct regulator_ops slg51000_regl_ops
= {
182 .enable
= regulator_enable_regmap
,
183 .disable
= regulator_disable_regmap
,
184 .is_enabled
= regulator_is_enabled_regmap
,
185 .list_voltage
= regulator_list_voltage_linear
,
186 .map_voltage
= regulator_map_voltage_linear
,
187 .get_voltage_sel
= regulator_get_voltage_sel_regmap
,
188 .set_voltage_sel
= regulator_set_voltage_sel_regmap
,
191 static const struct regulator_ops slg51000_switch_ops
= {
192 .enable
= regulator_enable_regmap
,
193 .disable
= regulator_disable_regmap
,
194 .is_enabled
= regulator_is_enabled_regmap
,
197 static int slg51000_of_parse_cb(struct device_node
*np
,
198 const struct regulator_desc
*desc
,
199 struct regulator_config
*config
)
201 struct gpio_desc
*ena_gpiod
;
203 ena_gpiod
= fwnode_gpiod_get_index(of_fwnode_handle(np
), "enable", 0,
205 GPIOD_FLAGS_BIT_NONEXCLUSIVE
,
207 if (!IS_ERR(ena_gpiod
))
208 config
->ena_gpiod
= ena_gpiod
;
213 #define SLG51000_REGL_DESC(_id, _name, _s_name, _min, _step) \
214 [SLG51000_REGULATOR_##_id] = { \
216 .supply_name = _s_name, \
217 .id = SLG51000_REGULATOR_##_id, \
218 .of_match = of_match_ptr(#_name), \
219 .of_parse_cb = slg51000_of_parse_cb, \
220 .ops = &slg51000_regl_ops, \
221 .regulators_node = of_match_ptr("regulators"), \
225 .linear_min_sel = 0, \
226 .vsel_mask = SLG51000_VSEL_MASK, \
227 .vsel_reg = SLG51000_##_id##_VSEL, \
228 .enable_reg = SLG51000_SYSCTL_MATRIX_CONF_A, \
229 .enable_mask = BIT(SLG51000_REGULATOR_##_id), \
230 .type = REGULATOR_VOLTAGE, \
231 .owner = THIS_MODULE, \
234 static struct regulator_desc regls_desc
[SLG51000_MAX_REGULATORS
] = {
235 SLG51000_REGL_DESC(LDO1
, ldo1
, NULL
, 2400000, 5000),
236 SLG51000_REGL_DESC(LDO2
, ldo2
, NULL
, 2400000, 5000),
237 SLG51000_REGL_DESC(LDO3
, ldo3
, "vin3", 1200000, 10000),
238 SLG51000_REGL_DESC(LDO4
, ldo4
, "vin4", 1200000, 10000),
239 SLG51000_REGL_DESC(LDO5
, ldo5
, "vin5", 400000, 5000),
240 SLG51000_REGL_DESC(LDO6
, ldo6
, "vin6", 400000, 5000),
241 SLG51000_REGL_DESC(LDO7
, ldo7
, "vin7", 1200000, 10000),
244 static int slg51000_regulator_init(struct slg51000
*chip
)
246 struct regulator_config config
= { };
247 struct regulator_desc
*rdesc
;
248 unsigned int reg
, val
;
251 const unsigned int min_regs
[SLG51000_MAX_REGULATORS
] = {
252 SLG51000_LDO1_MINV
, SLG51000_LDO2_MINV
, SLG51000_LDO3_MINV
,
253 SLG51000_LDO4_MINV
, SLG51000_LDO5_MINV
, SLG51000_LDO6_MINV
,
257 for (id
= 0; id
< SLG51000_MAX_REGULATORS
; id
++) {
258 chip
->rdesc
[id
] = ®ls_desc
[id
];
259 rdesc
= chip
->rdesc
[id
];
260 config
.regmap
= chip
->regmap
;
261 config
.dev
= chip
->dev
;
262 config
.driver_data
= chip
;
264 ret
= regmap_bulk_read(chip
->regmap
, min_regs
[id
],
268 "Failed to read the MIN register\n");
273 case SLG51000_REGULATOR_LDO1
:
274 case SLG51000_REGULATOR_LDO2
:
275 if (id
== SLG51000_REGULATOR_LDO1
)
276 reg
= SLG51000_LDO1_MISC1
;
278 reg
= SLG51000_LDO2_MISC1
;
280 ret
= regmap_read(chip
->regmap
, reg
, &val
);
283 "Failed to read voltage range of ldo%d\n",
288 rdesc
->linear_min_sel
= vsel_range
[0];
289 rdesc
->n_voltages
= vsel_range
[1] + 1;
290 if (val
& SLG51000_SEL_VRANGE_MASK
)
291 rdesc
->min_uV
= SLG51000_LDOHP_HV_MIN
295 rdesc
->min_uV
= SLG51000_LDOHP_LV_MIN
300 case SLG51000_REGULATOR_LDO5
:
301 case SLG51000_REGULATOR_LDO6
:
302 if (id
== SLG51000_REGULATOR_LDO5
)
303 reg
= SLG51000_LDO5_TRIM2
;
305 reg
= SLG51000_LDO6_TRIM2
;
307 ret
= regmap_read(chip
->regmap
, reg
, &val
);
310 "Failed to read LDO mode register\n");
314 if (val
& SLG51000_SEL_BYP_MODE_MASK
) {
315 rdesc
->ops
= &slg51000_switch_ops
;
316 rdesc
->n_voltages
= 0;
319 rdesc
->linear_min_sel
= 0;
322 fallthrough
; /* to the check below */
325 rdesc
->linear_min_sel
= vsel_range
[0];
326 rdesc
->n_voltages
= vsel_range
[1] + 1;
327 rdesc
->min_uV
= rdesc
->min_uV
328 + (vsel_range
[0] * rdesc
->uV_step
);
332 chip
->rdev
[id
] = devm_regulator_register(chip
->dev
, rdesc
,
334 if (IS_ERR(chip
->rdev
[id
])) {
335 ret
= PTR_ERR(chip
->rdev
[id
]);
337 "Failed to register regulator(%s):%d\n",
338 chip
->rdesc
[id
]->name
, ret
);
346 static irqreturn_t
slg51000_irq_handler(int irq
, void *data
)
348 struct slg51000
*chip
= data
;
349 struct regmap
*regmap
= chip
->regmap
;
350 enum { R0
= 0, R1
, R2
, REG_MAX
};
351 u8 evt
[SLG51000_MAX_EVT_REGISTER
][REG_MAX
];
352 int ret
, i
, handled
= IRQ_NONE
;
353 unsigned int evt_otp
, mask_otp
;
355 /* Read event[R0], status[R1] and mask[R2] register */
356 for (i
= 0; i
< SLG51000_MAX_EVT_REGISTER
; i
++) {
357 ret
= regmap_bulk_read(regmap
, es_reg
[i
].ereg
, evt
[i
], REG_MAX
);
360 "Failed to read event registers(%d)\n", ret
);
365 ret
= regmap_read(regmap
, SLG51000_OTP_EVENT
, &evt_otp
);
368 "Failed to read otp event registers(%d)\n", ret
);
372 ret
= regmap_read(regmap
, SLG51000_OTP_IRQ_MASK
, &mask_otp
);
375 "Failed to read otp mask register(%d)\n", ret
);
379 if ((evt_otp
& SLG51000_EVT_CRC_MASK
) &&
380 !(mask_otp
& SLG51000_IRQ_CRC_MASK
)) {
382 "OTP has been read or OTP crc is not zero\n");
383 handled
= IRQ_HANDLED
;
386 for (i
= 0; i
< SLG51000_MAX_REGULATORS
; i
++) {
387 if (!(evt
[i
][R2
] & SLG51000_IRQ_ILIM_FLAG_MASK
) &&
388 (evt
[i
][R0
] & SLG51000_EVT_ILIM_FLAG_MASK
)) {
389 regulator_notifier_call_chain(chip
->rdev
[i
],
390 REGULATOR_EVENT_OVER_CURRENT
, NULL
);
392 if (evt
[i
][R1
] & SLG51000_STA_ILIM_FLAG_MASK
)
394 "Over-current limit(ldo%d)\n", i
+ 1);
395 handled
= IRQ_HANDLED
;
399 if (!(evt
[SLG51000_SCTL_EVT
][R2
] & SLG51000_IRQ_HIGH_TEMP_WARN_MASK
) &&
400 (evt
[SLG51000_SCTL_EVT
][R0
] & SLG51000_EVT_HIGH_TEMP_WARN_MASK
)) {
401 for (i
= 0; i
< SLG51000_MAX_REGULATORS
; i
++) {
402 if (!(evt
[i
][R1
] & SLG51000_STA_ILIM_FLAG_MASK
) &&
403 (evt
[i
][R1
] & SLG51000_STA_VOUT_OK_FLAG_MASK
)) {
404 regulator_notifier_call_chain(chip
->rdev
[i
],
405 REGULATOR_EVENT_OVER_TEMP
, NULL
);
408 handled
= IRQ_HANDLED
;
409 if (evt
[SLG51000_SCTL_EVT
][R1
] &
410 SLG51000_STA_HIGH_TEMP_WARN_MASK
)
411 dev_warn(chip
->dev
, "High temperature warning!\n");
417 static void slg51000_clear_fault_log(struct slg51000
*chip
)
419 unsigned int val
= 0;
422 ret
= regmap_read(chip
->regmap
, SLG51000_SYSCTL_FAULT_LOG1
, &val
);
424 dev_err(chip
->dev
, "Failed to read Fault log register\n");
428 if (val
& SLG51000_FLT_OVER_TEMP_MASK
)
429 dev_dbg(chip
->dev
, "Fault log: FLT_OVER_TEMP\n");
430 if (val
& SLG51000_FLT_POWER_SEQ_CRASH_REQ_MASK
)
431 dev_dbg(chip
->dev
, "Fault log: FLT_POWER_SEQ_CRASH_REQ\n");
432 if (val
& SLG51000_FLT_RST_MASK
)
433 dev_dbg(chip
->dev
, "Fault log: FLT_RST\n");
434 if (val
& SLG51000_FLT_POR_MASK
)
435 dev_dbg(chip
->dev
, "Fault log: FLT_POR\n");
438 static int slg51000_i2c_probe(struct i2c_client
*client
)
440 struct device
*dev
= &client
->dev
;
441 struct slg51000
*chip
;
442 struct gpio_desc
*cs_gpiod
;
445 chip
= devm_kzalloc(dev
, sizeof(struct slg51000
), GFP_KERNEL
);
449 cs_gpiod
= devm_gpiod_get_optional(dev
, "dlg,cs",
451 GPIOD_FLAGS_BIT_NONEXCLUSIVE
);
452 if (IS_ERR(cs_gpiod
))
453 return PTR_ERR(cs_gpiod
);
456 dev_info(dev
, "Found chip selector property\n");
457 chip
->cs_gpiod
= cs_gpiod
;
460 i2c_set_clientdata(client
, chip
);
461 chip
->chip_irq
= client
->irq
;
463 chip
->regmap
= devm_regmap_init_i2c(client
, &slg51000_regmap_config
);
464 if (IS_ERR(chip
->regmap
)) {
465 error
= PTR_ERR(chip
->regmap
);
466 dev_err(dev
, "Failed to allocate register map: %d\n",
471 ret
= slg51000_regulator_init(chip
);
473 dev_err(chip
->dev
, "Failed to init regulator(%d)\n", ret
);
477 slg51000_clear_fault_log(chip
);
479 if (chip
->chip_irq
) {
480 ret
= devm_request_threaded_irq(dev
, chip
->chip_irq
, NULL
,
481 slg51000_irq_handler
,
484 "slg51000-irq", chip
);
486 dev_err(dev
, "Failed to request IRQ: %d\n",
491 dev_info(dev
, "No IRQ configured\n");
497 static const struct i2c_device_id slg51000_i2c_id
[] = {
501 MODULE_DEVICE_TABLE(i2c
, slg51000_i2c_id
);
503 static struct i2c_driver slg51000_regulator_driver
= {
505 .name
= "slg51000-regulator",
507 .probe_new
= slg51000_i2c_probe
,
508 .id_table
= slg51000_i2c_id
,
511 module_i2c_driver(slg51000_regulator_driver
);
513 MODULE_AUTHOR("Eric Jeong <eric.jeong.opensource@diasemi.com>");
514 MODULE_DESCRIPTION("SLG51000 regulator driver");
515 MODULE_LICENSE("GPL");