drivers/spi/spi-txx9.c

   1 /*
   2  * TXx9 SPI controller driver.
   3  *
   4  * Based on linux/arch/mips/tx4938/toshiba_rbtx4938/spi_txx9.c
   5  * Copyright (C) 2000-2001 Toshiba Corporation
   6  *
   7  * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the
   8  * terms of the GNU General Public License version 2. This program is
   9  * licensed "as is" without any warranty of any kind, whether express
  10  * or implied.
  11  *
  12  * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com)
  13  *
  14  * Convert to generic SPI framework - Atsushi Nemoto (anemo@mba.ocn.ne.jp)
  15  */
  16 #include <linux/init.h>
  17 #include <linux/delay.h>
  18 #include <linux/errno.h>
  19 #include <linux/interrupt.h>
  20 #include <linux/platform_device.h>
  21 #include <linux/sched.h>
  22 #include <linux/spinlock.h>
  23 #include <linux/workqueue.h>
  24 #include <linux/spi/spi.h>
  25 #include <linux/err.h>
  26 #include <linux/clk.h>
  27 #include <linux/io.h>
  28 #include <linux/module.h>
  29 #include <linux/gpio/machine.h>
  30 #include <linux/gpio/consumer.h>
  31
  32
  33 #define SPI_FIFO_SIZE 4
  34 #define SPI_MAX_DIVIDER 0xff    /* Max. value for SPCR1.SER */
  35 #define SPI_MIN_DIVIDER 1       /* Min. value for SPCR1.SER */
  36
  37 #define TXx9_SPMCR              0x00
  38 #define TXx9_SPCR0              0x04
  39 #define TXx9_SPCR1              0x08
  40 #define TXx9_SPFS               0x0c
  41 #define TXx9_SPSR               0x14
  42 #define TXx9_SPDR               0x18
  43
  44 /* SPMCR : SPI Master Control */
  45 #define TXx9_SPMCR_OPMODE       0xc0
  46 #define TXx9_SPMCR_CONFIG       0x40
  47 #define TXx9_SPMCR_ACTIVE       0x80
  48 #define TXx9_SPMCR_SPSTP        0x02
  49 #define TXx9_SPMCR_BCLR         0x01
  50
  51 /* SPCR0 : SPI Control 0 */
  52 #define TXx9_SPCR0_TXIFL_MASK   0xc000
  53 #define TXx9_SPCR0_RXIFL_MASK   0x3000
  54 #define TXx9_SPCR0_SIDIE        0x0800
  55 #define TXx9_SPCR0_SOEIE        0x0400
  56 #define TXx9_SPCR0_RBSIE        0x0200
  57 #define TXx9_SPCR0_TBSIE        0x0100
  58 #define TXx9_SPCR0_IFSPSE       0x0010
  59 #define TXx9_SPCR0_SBOS         0x0004
  60 #define TXx9_SPCR0_SPHA         0x0002
  61 #define TXx9_SPCR0_SPOL         0x0001
  62
  63 /* SPSR : SPI Status */
  64 #define TXx9_SPSR_TBSI          0x8000
  65 #define TXx9_SPSR_RBSI          0x4000
  66 #define TXx9_SPSR_TBS_MASK      0x3800
  67 #define TXx9_SPSR_RBS_MASK      0x0700
  68 #define TXx9_SPSR_SPOE          0x0080
  69 #define TXx9_SPSR_IFSD          0x0008
  70 #define TXx9_SPSR_SIDLE         0x0004
  71 #define TXx9_SPSR_STRDY         0x0002
  72 #define TXx9_SPSR_SRRDY         0x0001
  73
  74
  75 struct txx9spi {
  76         struct work_struct work;
  77         spinlock_t lock;        /* protect 'queue' */
  78         struct list_head queue;
  79         wait_queue_head_t waitq;
  80         void __iomem *membase;
  81         int baseclk;
  82         struct clk *clk;
  83         struct gpio_desc *last_chipselect;
  84         int last_chipselect_val;
  85 };
  86
  87 static u32 txx9spi_rd(struct txx9spi *c, int reg)
  88 {
  89         return __raw_readl(c->membase + reg);
  90 }
  91 static void txx9spi_wr(struct txx9spi *c, u32 val, int reg)
  92 {
  93         __raw_writel(val, c->membase + reg);
  94 }
  95
  96 static void txx9spi_cs_func(struct spi_device *spi, struct txx9spi *c,
  97                 int on, unsigned int cs_delay)
  98 {
  99         /*
 100          * The GPIO descriptor will track polarity inversion inside
 101          * gpiolib.
 102          */
 103         if (on) {
 104                 /* deselect the chip with cs_change hint in last transfer */
 105                 if (c->last_chipselect)
 106                         gpiod_set_value(c->last_chipselect,
 107                                         !c->last_chipselect_val);
 108                 c->last_chipselect = spi->cs_gpiod;
 109                 c->last_chipselect_val = on;
 110         } else {
 111                 c->last_chipselect = NULL;
 112                 ndelay(cs_delay);       /* CS Hold Time */
 113         }
 114         gpiod_set_value(spi->cs_gpiod, on);
 115         ndelay(cs_delay);       /* CS Setup Time / CS Recovery Time */
 116 }
 117
 118 static int txx9spi_setup(struct spi_device *spi)
 119 {
 120         struct txx9spi *c = spi_master_get_devdata(spi->master);
 121
 122         if (!spi->max_speed_hz)
 123                 return -EINVAL;
 124
 125         /* deselect chip */
 126         spin_lock(&c->lock);
 127         txx9spi_cs_func(spi, c, 0, (NSEC_PER_SEC / 2) / spi->max_speed_hz);
 128         spin_unlock(&c->lock);
 129
 130         return 0;
 131 }
 132
 133 static irqreturn_t txx9spi_interrupt(int irq, void *dev_id)
 134 {
 135         struct txx9spi *c = dev_id;
 136
 137         /* disable rx intr */
 138         txx9spi_wr(c, txx9spi_rd(c, TXx9_SPCR0) & ~TXx9_SPCR0_RBSIE,
 139                         TXx9_SPCR0);
 140         wake_up(&c->waitq);
 141         return IRQ_HANDLED;
 142 }
 143
 144 static void txx9spi_work_one(struct txx9spi *c, struct spi_message *m)
 145 {
 146         struct spi_device *spi = m->spi;
 147         struct spi_transfer *t;
 148         unsigned int cs_delay;
 149         unsigned int cs_change = 1;
 150         int status = 0;
 151         u32 mcr;
 152         u32 prev_speed_hz = 0;
 153         u8 prev_bits_per_word = 0;
 154
 155         /* CS setup/hold/recovery time in nsec */
 156         cs_delay = 100 + (NSEC_PER_SEC / 2) / spi->max_speed_hz;
 157
 158         mcr = txx9spi_rd(c, TXx9_SPMCR);
 159         if (unlikely((mcr & TXx9_SPMCR_OPMODE) == TXx9_SPMCR_ACTIVE)) {
 160                 dev_err(&spi->dev, "Bad mode.\n");
 161                 status = -EIO;
 162                 goto exit;
 163         }
 164         mcr &= ~(TXx9_SPMCR_OPMODE | TXx9_SPMCR_SPSTP | TXx9_SPMCR_BCLR);
 165
 166         /* enter config mode */
 167         txx9spi_wr(c, mcr | TXx9_SPMCR_CONFIG | TXx9_SPMCR_BCLR, TXx9_SPMCR);
 168         txx9spi_wr(c, TXx9_SPCR0_SBOS
 169                         | ((spi->mode & SPI_CPOL) ? TXx9_SPCR0_SPOL : 0)
 170                         | ((spi->mode & SPI_CPHA) ? TXx9_SPCR0_SPHA : 0)
 171                         | 0x08,
 172                         TXx9_SPCR0);
 173
 174         list_for_each_entry(t, &m->transfers, transfer_list) {
 175                 const void *txbuf = t->tx_buf;
 176                 void *rxbuf = t->rx_buf;
 177                 u32 data;
 178                 unsigned int len = t->len;
 179                 unsigned int wsize;
 180                 u32 speed_hz = t->speed_hz;
 181                 u8 bits_per_word = t->bits_per_word;
 182
 183                 wsize = bits_per_word >> 3; /* in bytes */
 184
 185                 if (prev_speed_hz != speed_hz
 186                                 || prev_bits_per_word != bits_per_word) {
 187                         int n = DIV_ROUND_UP(c->baseclk, speed_hz) - 1;
 188
 189                         n = clamp(n, SPI_MIN_DIVIDER, SPI_MAX_DIVIDER);
 190                         /* enter config mode */
 191                         txx9spi_wr(c, mcr | TXx9_SPMCR_CONFIG | TXx9_SPMCR_BCLR,
 192                                         TXx9_SPMCR);
 193                         txx9spi_wr(c, (n << 8) | bits_per_word, TXx9_SPCR1);
 194                         /* enter active mode */
 195                         txx9spi_wr(c, mcr | TXx9_SPMCR_ACTIVE, TXx9_SPMCR);
 196
 197                         prev_speed_hz = speed_hz;
 198                         prev_bits_per_word = bits_per_word;
 199                 }
 200
 201                 if (cs_change)
 202                         txx9spi_cs_func(spi, c, 1, cs_delay);
 203                 cs_change = t->cs_change;
 204                 while (len) {
 205                         unsigned int count = SPI_FIFO_SIZE;
 206                         int i;
 207                         u32 cr0;
 208
 209                         if (len < count * wsize)
 210                                 count = len / wsize;
 211                         /* now tx must be idle... */
 212                         while (!(txx9spi_rd(c, TXx9_SPSR) & TXx9_SPSR_SIDLE))
 213                                 cpu_relax();
 214                         cr0 = txx9spi_rd(c, TXx9_SPCR0);
 215                         cr0 &= ~TXx9_SPCR0_RXIFL_MASK;
 216                         cr0 |= (count - 1) << 12;
 217                         /* enable rx intr */
 218                         cr0 |= TXx9_SPCR0_RBSIE;
 219                         txx9spi_wr(c, cr0, TXx9_SPCR0);
 220                         /* send */
 221                         for (i = 0; i < count; i++) {
 222                                 if (txbuf) {
 223                                         data = (wsize == 1)
 224                                                 ? *(const u8 *)txbuf
 225                                                 : *(const u16 *)txbuf;
 226                                         txx9spi_wr(c, data, TXx9_SPDR);
 227                                         txbuf += wsize;
 228                                 } else
 229                                         txx9spi_wr(c, 0, TXx9_SPDR);
 230                         }
 231                         /* wait all rx data */
 232                         wait_event(c->waitq,
 233                                 txx9spi_rd(c, TXx9_SPSR) & TXx9_SPSR_RBSI);
 234                         /* receive */
 235                         for (i = 0; i < count; i++) {
 236                                 data = txx9spi_rd(c, TXx9_SPDR);
 237                                 if (rxbuf) {
 238                                         if (wsize == 1)
 239                                                 *(u8 *)rxbuf = data;
 240                                         else
 241                                                 *(u16 *)rxbuf = data;
 242                                         rxbuf += wsize;
 243                                 }
 244                         }
 245                         len -= count * wsize;
 246                 }
 247                 m->actual_length += t->len;
 248                 spi_transfer_delay_exec(t);
 249
 250                 if (!cs_change)
 251                         continue;
 252                 if (t->transfer_list.next == &m->transfers)
 253                         break;
 254                 /* sometimes a short mid-message deselect of the chip
 255                  * may be needed to terminate a mode or command
 256                  */
 257                 txx9spi_cs_func(spi, c, 0, cs_delay);
 258         }
 259
 260 exit:
 261         m->status = status;
 262         if (m->complete)
 263                 m->complete(m->context);
 264
 265         /* normally deactivate chipselect ... unless no error and
 266          * cs_change has hinted that the next message will probably
 267          * be for this chip too.
 268          */
 269         if (!(status == 0 && cs_change))
 270                 txx9spi_cs_func(spi, c, 0, cs_delay);
 271
 272         /* enter config mode */
 273         txx9spi_wr(c, mcr | TXx9_SPMCR_CONFIG | TXx9_SPMCR_BCLR, TXx9_SPMCR);
 274 }
 275
 276 static void txx9spi_work(struct work_struct *work)
 277 {
 278         struct txx9spi *c = container_of(work, struct txx9spi, work);
 279         unsigned long flags;
 280
 281         spin_lock_irqsave(&c->lock, flags);
 282         while (!list_empty(&c->queue)) {
 283                 struct spi_message *m;
 284
 285                 m = container_of(c->queue.next, struct spi_message, queue);
 286                 list_del_init(&m->queue);
 287                 spin_unlock_irqrestore(&c->lock, flags);
 288
 289                 txx9spi_work_one(c, m);
 290
 291                 spin_lock_irqsave(&c->lock, flags);
 292         }
 293         spin_unlock_irqrestore(&c->lock, flags);
 294 }
 295
 296 static int txx9spi_transfer(struct spi_device *spi, struct spi_message *m)
 297 {
 298         struct spi_master *master = spi->master;
 299         struct txx9spi *c = spi_master_get_devdata(master);
 300         struct spi_transfer *t;
 301         unsigned long flags;
 302
 303         m->actual_length = 0;
 304
 305         /* check each transfer's parameters */
 306         list_for_each_entry(t, &m->transfers, transfer_list) {
 307                 if (!t->tx_buf && !t->rx_buf && t->len)
 308                         return -EINVAL;
 309         }
 310
 311         spin_lock_irqsave(&c->lock, flags);
 312         list_add_tail(&m->queue, &c->queue);
 313         schedule_work(&c->work);
 314         spin_unlock_irqrestore(&c->lock, flags);
 315
 316         return 0;
 317 }
 318
 319 /*
 320  * Chip select uses GPIO only, further the driver is using the chip select
 321  * numer (from the device tree "reg" property, and this can only come from
 322  * device tree since this i MIPS and there is no way to pass platform data) as
 323  * the GPIO number. As the platform has only one GPIO controller (the txx9 GPIO
 324  * chip) it is thus using the chip select number as an offset into that chip.
 325  * This chip has a maximum of 16 GPIOs 0..15 and this is what all platforms
 326  * register.
 327  *
 328  * We modernized this behaviour by explicitly converting that offset to an
 329  * offset on the GPIO chip using a GPIO descriptor machine table of the same
 330  * size as the txx9 GPIO chip with a 1-to-1 mapping of chip select to GPIO
 331  * offset.
 332  *
 333  * This is admittedly a hack, but it is countering the hack of using "reg" to
 334  * contain a GPIO offset when it should be using "cs-gpios" as the SPI bindings
 335  * state.
 336  */
 337 static struct gpiod_lookup_table txx9spi_cs_gpio_table = {
 338         .dev_id = "spi0",
 339         .table = {
 340                 GPIO_LOOKUP_IDX("TXx9", 0, "cs", 0, GPIO_ACTIVE_LOW),
 341                 GPIO_LOOKUP_IDX("TXx9", 1, "cs", 1, GPIO_ACTIVE_LOW),
 342                 GPIO_LOOKUP_IDX("TXx9", 2, "cs", 2, GPIO_ACTIVE_LOW),
 343                 GPIO_LOOKUP_IDX("TXx9", 3, "cs", 3, GPIO_ACTIVE_LOW),
 344                 GPIO_LOOKUP_IDX("TXx9", 4, "cs", 4, GPIO_ACTIVE_LOW),
 345                 GPIO_LOOKUP_IDX("TXx9", 5, "cs", 5, GPIO_ACTIVE_LOW),
 346                 GPIO_LOOKUP_IDX("TXx9", 6, "cs", 6, GPIO_ACTIVE_LOW),
 347                 GPIO_LOOKUP_IDX("TXx9", 7, "cs", 7, GPIO_ACTIVE_LOW),
 348                 GPIO_LOOKUP_IDX("TXx9", 8, "cs", 8, GPIO_ACTIVE_LOW),
 349                 GPIO_LOOKUP_IDX("TXx9", 9, "cs", 9, GPIO_ACTIVE_LOW),
 350                 GPIO_LOOKUP_IDX("TXx9", 10, "cs", 10, GPIO_ACTIVE_LOW),
 351                 GPIO_LOOKUP_IDX("TXx9", 11, "cs", 11, GPIO_ACTIVE_LOW),
 352                 GPIO_LOOKUP_IDX("TXx9", 12, "cs", 12, GPIO_ACTIVE_LOW),
 353                 GPIO_LOOKUP_IDX("TXx9", 13, "cs", 13, GPIO_ACTIVE_LOW),
 354                 GPIO_LOOKUP_IDX("TXx9", 14, "cs", 14, GPIO_ACTIVE_LOW),
 355                 GPIO_LOOKUP_IDX("TXx9", 15, "cs", 15, GPIO_ACTIVE_LOW),
 356                 { },
 357         },
 358 };
 359
 360 static int txx9spi_probe(struct platform_device *dev)
 361 {
 362         struct spi_master *master;
 363         struct txx9spi *c;
 364         struct resource *res;
 365         int ret = -ENODEV;
 366         u32 mcr;
 367         int irq;
 368
 369         master = spi_alloc_master(&dev->dev, sizeof(*c));
 370         if (!master)
 371                 return ret;
 372         c = spi_master_get_devdata(master);
 373         platform_set_drvdata(dev, master);
 374
 375         INIT_WORK(&c->work, txx9spi_work);
 376         spin_lock_init(&c->lock);
 377         INIT_LIST_HEAD(&c->queue);
 378         init_waitqueue_head(&c->waitq);
 379
 380         c->clk = devm_clk_get(&dev->dev, "spi-baseclk");
 381         if (IS_ERR(c->clk)) {
 382                 ret = PTR_ERR(c->clk);
 383                 c->clk = NULL;
 384                 goto exit;
 385         }
 386         ret = clk_prepare_enable(c->clk);
 387         if (ret) {
 388                 c->clk = NULL;
 389                 goto exit;
 390         }
 391         c->baseclk = clk_get_rate(c->clk);
 392         master->min_speed_hz = DIV_ROUND_UP(c->baseclk, SPI_MAX_DIVIDER + 1);
 393         master->max_speed_hz = c->baseclk / (SPI_MIN_DIVIDER + 1);
 394
 395         res = platform_get_resource(dev, IORESOURCE_MEM, 0);
 396         c->membase = devm_ioremap_resource(&dev->dev, res);
 397         if (IS_ERR(c->membase))
 398                 goto exit_busy;
 399
 400         /* enter config mode */
 401         mcr = txx9spi_rd(c, TXx9_SPMCR);
 402         mcr &= ~(TXx9_SPMCR_OPMODE | TXx9_SPMCR_SPSTP | TXx9_SPMCR_BCLR);
 403         txx9spi_wr(c, mcr | TXx9_SPMCR_CONFIG | TXx9_SPMCR_BCLR, TXx9_SPMCR);
 404
 405         irq = platform_get_irq(dev, 0);
 406         if (irq < 0)
 407                 goto exit_busy;
 408         ret = devm_request_irq(&dev->dev, irq, txx9spi_interrupt, 0,
 409                                "spi_txx9", c);
 410         if (ret)
 411                 goto exit;
 412
 413         c->last_chipselect = NULL;
 414
 415         dev_info(&dev->dev, "at %#llx, irq %d, %dMHz\n",
 416                  (unsigned long long)res->start, irq,
 417                  (c->baseclk + 500000) / 1000000);
 418
 419         gpiod_add_lookup_table(&txx9spi_cs_gpio_table);
 420
 421         /* the spi->mode bits understood by this driver: */
 422         master->mode_bits = SPI_CS_HIGH | SPI_CPOL | SPI_CPHA;
 423
 424         master->bus_num = dev->id;
 425         master->setup = txx9spi_setup;
 426         master->transfer = txx9spi_transfer;
 427         master->num_chipselect = (u16)UINT_MAX; /* any GPIO numbers */
 428         master->bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(16);
 429         master->use_gpio_descriptors = true;
 430
 431         ret = devm_spi_register_master(&dev->dev, master);
 432         if (ret)
 433                 goto exit;
 434         return 0;
 435 exit_busy:
 436         ret = -EBUSY;
 437 exit:
 438         clk_disable_unprepare(c->clk);
 439         spi_master_put(master);
 440         return ret;
 441 }
 442
 443 static int txx9spi_remove(struct platform_device *dev)
 444 {
 445         struct spi_master *master = platform_get_drvdata(dev);
 446         struct txx9spi *c = spi_master_get_devdata(master);
 447
 448         flush_work(&c->work);
 449         clk_disable_unprepare(c->clk);
 450         return 0;
 451 }
 452
 453 /* work with hotplug and coldplug */
 454 MODULE_ALIAS("platform:spi_txx9");
 455
 456 static struct platform_driver txx9spi_driver = {
 457         .probe = txx9spi_probe,
 458         .remove = txx9spi_remove,
 459         .driver = {
 460                 .name = "spi_txx9",
 461         },
 462 };
 463
 464 static int __init txx9spi_init(void)
 465 {
 466         return platform_driver_register(&txx9spi_driver);
 467 }
 468 subsys_initcall(txx9spi_init);
 469
 470 static void __exit txx9spi_exit(void)
 471 {
 472         platform_driver_unregister(&txx9spi_driver);
 473 }
 474 module_exit(txx9spi_exit);
 475
 476 MODULE_DESCRIPTION("TXx9 SPI Driver");
 477 MODULE_LICENSE("GPL");