drivers/thermal/tegra/soctherm.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /*
   3  * Copyright (c) 2014-2016, NVIDIA CORPORATION.  All rights reserved.
   4  *
   5  * This software is licensed under the terms of the GNU General Public
   6  * License version 2, as published by the Free Software Foundation, and
   7  * may be copied, distributed, and modified under those terms.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  *
  14  */
  15
  16 #ifndef __DRIVERS_THERMAL_TEGRA_SOCTHERM_H
  17 #define __DRIVERS_THERMAL_TEGRA_SOCTHERM_H
  18
  19 #define THERMCTL_LEVEL0_GROUP_CPU               0x0
  20 #define THERMCTL_LEVEL0_GROUP_GPU               0x4
  21 #define THERMCTL_LEVEL0_GROUP_MEM               0x8
  22 #define THERMCTL_LEVEL0_GROUP_TSENSE            0xc
  23
  24 #define SENSOR_CONFIG2                          8
  25 #define SENSOR_CONFIG2_THERMA_MASK              (0xffff << 16)
  26 #define SENSOR_CONFIG2_THERMA_SHIFT             16
  27 #define SENSOR_CONFIG2_THERMB_MASK              0xffff
  28 #define SENSOR_CONFIG2_THERMB_SHIFT             0
  29
  30 #define THERMCTL_THERMTRIP_CTL                  0x80
  31 /* BITs are defined in device file */
  32
  33 #define THERMCTL_INTR_ENABLE                    0x88
  34 #define THERMCTL_INTR_DISABLE                   0x8c
  35 #define TH_INTR_UP_DN_EN                        0x3
  36 #define THERM_IRQ_MEM_MASK                      (TH_INTR_UP_DN_EN << 24)
  37 #define THERM_IRQ_GPU_MASK                      (TH_INTR_UP_DN_EN << 16)
  38 #define THERM_IRQ_CPU_MASK                      (TH_INTR_UP_DN_EN << 8)
  39 #define THERM_IRQ_TSENSE_MASK                   (TH_INTR_UP_DN_EN << 0)
  40
  41 #define SENSOR_PDIV                             0x1c0
  42 #define SENSOR_PDIV_CPU_MASK                    (0xf << 12)
  43 #define SENSOR_PDIV_GPU_MASK                    (0xf << 8)
  44 #define SENSOR_PDIV_MEM_MASK                    (0xf << 4)
  45 #define SENSOR_PDIV_PLLX_MASK                   (0xf << 0)
  46
  47 #define SENSOR_HOTSPOT_OFF                      0x1c4
  48 #define SENSOR_HOTSPOT_CPU_MASK                 (0xff << 16)
  49 #define SENSOR_HOTSPOT_GPU_MASK                 (0xff << 8)
  50 #define SENSOR_HOTSPOT_MEM_MASK                 (0xff << 0)
  51
  52 #define SENSOR_TEMP1                            0x1c8
  53 #define SENSOR_TEMP1_CPU_TEMP_MASK              (0xffff << 16)
  54 #define SENSOR_TEMP1_GPU_TEMP_MASK              0xffff
  55 #define SENSOR_TEMP2                            0x1cc
  56 #define SENSOR_TEMP2_MEM_TEMP_MASK              (0xffff << 16)
  57 #define SENSOR_TEMP2_PLLX_TEMP_MASK             0xffff
  58
  59 /**
  60  * struct tegra_tsensor_group - SOC_THERM sensor group data
  61  * @name: short name of the temperature sensor group
  62  * @id: numeric ID of the temperature sensor group
  63  * @sensor_temp_offset: offset of the SENSOR_TEMP* register
  64  * @sensor_temp_mask: bit mask for this sensor group in SENSOR_TEMP* register
  65  * @pdiv: the sensor count post-divider to use during runtime
  66  * @pdiv_ate: the sensor count post-divider used during automated test
  67  * @pdiv_mask: register bitfield mask for the PDIV field for this sensor
  68  * @pllx_hotspot_diff: hotspot offset from the PLLX sensor, must be 0 for
  69     PLLX sensor group
  70  * @pllx_hotspot_mask: register bitfield mask for the HOTSPOT field
  71  */
  72 struct tegra_tsensor_group {
  73         const char *name;
  74         u8 id;
  75         u16 sensor_temp_offset;
  76         u32 sensor_temp_mask;
  77         u32 pdiv, pdiv_ate, pdiv_mask;
  78         u32 pllx_hotspot_diff, pllx_hotspot_mask;
  79         u32 thermtrip_enable_mask;
  80         u32 thermtrip_any_en_mask;
  81         u32 thermtrip_threshold_mask;
  82         u32 thermctl_isr_mask;
  83         u16 thermctl_lvl0_offset;
  84         u32 thermctl_lvl0_up_thresh_mask;
  85         u32 thermctl_lvl0_dn_thresh_mask;
  86 };
  87
  88 struct tegra_tsensor_configuration {
  89         u32 tall, tiddq_en, ten_count, pdiv, pdiv_ate, tsample, tsample_ate;
  90 };
  91
  92 struct tegra_tsensor {
  93         const char *name;
  94         const u32 base;
  95         const struct tegra_tsensor_configuration *config;
  96         const u32 calib_fuse_offset;
  97         /*
  98          * Correction values used to modify values read from
  99          * calibration fuses
 100          */
 101         const s32 fuse_corr_alpha, fuse_corr_beta;
 102         const struct tegra_tsensor_group *group;
 103 };
 104
 105 struct tsensor_group_thermtrips {
 106         u8 id;
 107         u32 temp;
 108 };
 109
 110 struct tegra_soctherm_fuse {
 111         u32 fuse_base_cp_mask, fuse_base_cp_shift;
 112         u32 fuse_base_ft_mask, fuse_base_ft_shift;
 113         u32 fuse_shift_ft_mask, fuse_shift_ft_shift;
 114         u32 fuse_spare_realignment;
 115 };
 116
 117 struct tsensor_shared_calib {
 118         u32 base_cp, base_ft;
 119         u32 actual_temp_cp, actual_temp_ft;
 120 };
 121
 122 struct tegra_soctherm_soc {
 123         const struct tegra_tsensor *tsensors;
 124         const unsigned int num_tsensors;
 125         const struct tegra_tsensor_group **ttgs;
 126         const unsigned int num_ttgs;
 127         const struct tegra_soctherm_fuse *tfuse;
 128         const int thresh_grain;
 129         const unsigned int bptt;
 130         const bool use_ccroc;
 131         struct tsensor_group_thermtrips *thermtrips;
 132 };
 133
 134 int tegra_calc_shared_calib(const struct tegra_soctherm_fuse *tfuse,
 135                             struct tsensor_shared_calib *shared);
 136 int tegra_calc_tsensor_calib(const struct tegra_tsensor *sensor,
 137                              const struct tsensor_shared_calib *shared,
 138                              u32 *calib);
 139
 140 #ifdef CONFIG_ARCH_TEGRA_124_SOC
 141 extern const struct tegra_soctherm_soc tegra124_soctherm;
 142 #endif
 143
 144 #ifdef CONFIG_ARCH_TEGRA_132_SOC
 145 extern const struct tegra_soctherm_soc tegra132_soctherm;
 146 #endif
 147
 148 #ifdef CONFIG_ARCH_TEGRA_210_SOC
 149 extern const struct tegra_soctherm_soc tegra210_soctherm;
 150 #endif
 151
 152 #endif
 153