1 /* SPDX-License-Identifier: GPL-2.0 */
3 * core.h - DesignWare USB3 DRD Core Header
5 * Copyright (C) 2010-2011 Texas Instruments Incorporated - https://www.ti.com
7 * Authors: Felipe Balbi <balbi@ti.com>,
8 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
11 #ifndef __DRIVERS_USB_DWC3_CORE_H
12 #define __DRIVERS_USB_DWC3_CORE_H
14 #include <linux/device.h>
15 #include <linux/spinlock.h>
16 #include <linux/ioport.h>
17 #include <linux/list.h>
18 #include <linux/bitops.h>
19 #include <linux/dma-mapping.h>
21 #include <linux/debugfs.h>
22 #include <linux/wait.h>
23 #include <linux/workqueue.h>
25 #include <linux/usb/ch9.h>
26 #include <linux/usb/gadget.h>
27 #include <linux/usb/otg.h>
28 #include <linux/usb/role.h>
29 #include <linux/ulpi/interface.h>
31 #include <linux/phy/phy.h>
33 #define DWC3_MSG_MAX 500
35 /* Global constants */
36 #define DWC3_PULL_UP_TIMEOUT 500 /* ms */
37 #define DWC3_BOUNCE_SIZE 1024 /* size of a superspeed bulk */
38 #define DWC3_EP0_SETUP_SIZE 512
39 #define DWC3_ENDPOINTS_NUM 32
40 #define DWC3_XHCI_RESOURCES_NUM 2
41 #define DWC3_ISOC_MAX_RETRIES 5
43 #define DWC3_SCRATCHBUF_SIZE 4096 /* each buffer is assumed to be 4KiB */
44 #define DWC3_EVENT_BUFFERS_SIZE 4096
45 #define DWC3_EVENT_TYPE_MASK 0xfe
47 #define DWC3_EVENT_TYPE_DEV 0
48 #define DWC3_EVENT_TYPE_CARKIT 3
49 #define DWC3_EVENT_TYPE_I2C 4
51 #define DWC3_DEVICE_EVENT_DISCONNECT 0
52 #define DWC3_DEVICE_EVENT_RESET 1
53 #define DWC3_DEVICE_EVENT_CONNECT_DONE 2
54 #define DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE 3
55 #define DWC3_DEVICE_EVENT_WAKEUP 4
56 #define DWC3_DEVICE_EVENT_HIBER_REQ 5
57 #define DWC3_DEVICE_EVENT_EOPF 6
58 #define DWC3_DEVICE_EVENT_SOF 7
59 #define DWC3_DEVICE_EVENT_ERRATIC_ERROR 9
60 #define DWC3_DEVICE_EVENT_CMD_CMPL 10
61 #define DWC3_DEVICE_EVENT_OVERFLOW 11
63 /* Controller's role while using the OTG block */
64 #define DWC3_OTG_ROLE_IDLE 0
65 #define DWC3_OTG_ROLE_HOST 1
66 #define DWC3_OTG_ROLE_DEVICE 2
68 #define DWC3_GEVNTCOUNT_MASK 0xfffc
69 #define DWC3_GEVNTCOUNT_EHB BIT(31)
70 #define DWC3_GSNPSID_MASK 0xffff0000
71 #define DWC3_GSNPSREV_MASK 0xffff
72 #define DWC3_GSNPS_ID(p) (((p) & DWC3_GSNPSID_MASK) >> 16)
74 /* DWC3 registers memory space boundries */
75 #define DWC3_XHCI_REGS_START 0x0
76 #define DWC3_XHCI_REGS_END 0x7fff
77 #define DWC3_GLOBALS_REGS_START 0xc100
78 #define DWC3_GLOBALS_REGS_END 0xc6ff
79 #define DWC3_DEVICE_REGS_START 0xc700
80 #define DWC3_DEVICE_REGS_END 0xcbff
81 #define DWC3_OTG_REGS_START 0xcc00
82 #define DWC3_OTG_REGS_END 0xccff
84 /* Global Registers */
85 #define DWC3_GSBUSCFG0 0xc100
86 #define DWC3_GSBUSCFG1 0xc104
87 #define DWC3_GTXTHRCFG 0xc108
88 #define DWC3_GRXTHRCFG 0xc10c
89 #define DWC3_GCTL 0xc110
90 #define DWC3_GEVTEN 0xc114
91 #define DWC3_GSTS 0xc118
92 #define DWC3_GUCTL1 0xc11c
93 #define DWC3_GSNPSID 0xc120
94 #define DWC3_GGPIO 0xc124
95 #define DWC3_GUID 0xc128
96 #define DWC3_GUCTL 0xc12c
97 #define DWC3_GBUSERRADDR0 0xc130
98 #define DWC3_GBUSERRADDR1 0xc134
99 #define DWC3_GPRTBIMAP0 0xc138
100 #define DWC3_GPRTBIMAP1 0xc13c
101 #define DWC3_GHWPARAMS0 0xc140
102 #define DWC3_GHWPARAMS1 0xc144
103 #define DWC3_GHWPARAMS2 0xc148
104 #define DWC3_GHWPARAMS3 0xc14c
105 #define DWC3_GHWPARAMS4 0xc150
106 #define DWC3_GHWPARAMS5 0xc154
107 #define DWC3_GHWPARAMS6 0xc158
108 #define DWC3_GHWPARAMS7 0xc15c
109 #define DWC3_GDBGFIFOSPACE 0xc160
110 #define DWC3_GDBGLTSSM 0xc164
111 #define DWC3_GDBGBMU 0xc16c
112 #define DWC3_GDBGLSPMUX 0xc170
113 #define DWC3_GDBGLSP 0xc174
114 #define DWC3_GDBGEPINFO0 0xc178
115 #define DWC3_GDBGEPINFO1 0xc17c
116 #define DWC3_GPRTBIMAP_HS0 0xc180
117 #define DWC3_GPRTBIMAP_HS1 0xc184
118 #define DWC3_GPRTBIMAP_FS0 0xc188
119 #define DWC3_GPRTBIMAP_FS1 0xc18c
120 #define DWC3_GUCTL2 0xc19c
122 #define DWC3_VER_NUMBER 0xc1a0
123 #define DWC3_VER_TYPE 0xc1a4
125 #define DWC3_GUSB2PHYCFG(n) (0xc200 + ((n) * 0x04))
126 #define DWC3_GUSB2I2CCTL(n) (0xc240 + ((n) * 0x04))
128 #define DWC3_GUSB2PHYACC(n) (0xc280 + ((n) * 0x04))
130 #define DWC3_GUSB3PIPECTL(n) (0xc2c0 + ((n) * 0x04))
132 #define DWC3_GTXFIFOSIZ(n) (0xc300 + ((n) * 0x04))
133 #define DWC3_GRXFIFOSIZ(n) (0xc380 + ((n) * 0x04))
135 #define DWC3_GEVNTADRLO(n) (0xc400 + ((n) * 0x10))
136 #define DWC3_GEVNTADRHI(n) (0xc404 + ((n) * 0x10))
137 #define DWC3_GEVNTSIZ(n) (0xc408 + ((n) * 0x10))
138 #define DWC3_GEVNTCOUNT(n) (0xc40c + ((n) * 0x10))
140 #define DWC3_GHWPARAMS8 0xc600
141 #define DWC3_GUCTL3 0xc60c
142 #define DWC3_GFLADJ 0xc630
144 /* Device Registers */
145 #define DWC3_DCFG 0xc700
146 #define DWC3_DCTL 0xc704
147 #define DWC3_DEVTEN 0xc708
148 #define DWC3_DSTS 0xc70c
149 #define DWC3_DGCMDPAR 0xc710
150 #define DWC3_DGCMD 0xc714
151 #define DWC3_DALEPENA 0xc720
153 #define DWC3_DEP_BASE(n) (0xc800 + ((n) * 0x10))
154 #define DWC3_DEPCMDPAR2 0x00
155 #define DWC3_DEPCMDPAR1 0x04
156 #define DWC3_DEPCMDPAR0 0x08
157 #define DWC3_DEPCMD 0x0c
159 #define DWC3_DEV_IMOD(n) (0xca00 + ((n) * 0x4))
162 #define DWC3_OCFG 0xcc00
163 #define DWC3_OCTL 0xcc04
164 #define DWC3_OEVT 0xcc08
165 #define DWC3_OEVTEN 0xcc0C
166 #define DWC3_OSTS 0xcc10
170 /* Global SoC Bus Configuration INCRx Register 0 */
171 #define DWC3_GSBUSCFG0_INCR256BRSTENA (1 << 7) /* INCR256 burst */
172 #define DWC3_GSBUSCFG0_INCR128BRSTENA (1 << 6) /* INCR128 burst */
173 #define DWC3_GSBUSCFG0_INCR64BRSTENA (1 << 5) /* INCR64 burst */
174 #define DWC3_GSBUSCFG0_INCR32BRSTENA (1 << 4) /* INCR32 burst */
175 #define DWC3_GSBUSCFG0_INCR16BRSTENA (1 << 3) /* INCR16 burst */
176 #define DWC3_GSBUSCFG0_INCR8BRSTENA (1 << 2) /* INCR8 burst */
177 #define DWC3_GSBUSCFG0_INCR4BRSTENA (1 << 1) /* INCR4 burst */
178 #define DWC3_GSBUSCFG0_INCRBRSTENA (1 << 0) /* undefined length enable */
179 #define DWC3_GSBUSCFG0_INCRBRST_MASK 0xff
181 /* Global Debug LSP MUX Select */
182 #define DWC3_GDBGLSPMUX_ENDBC BIT(15) /* Host only */
183 #define DWC3_GDBGLSPMUX_HOSTSELECT(n) ((n) & 0x3fff)
184 #define DWC3_GDBGLSPMUX_DEVSELECT(n) (((n) & 0xf) << 4)
185 #define DWC3_GDBGLSPMUX_EPSELECT(n) ((n) & 0xf)
187 /* Global Debug Queue/FIFO Space Available Register */
188 #define DWC3_GDBGFIFOSPACE_NUM(n) ((n) & 0x1f)
189 #define DWC3_GDBGFIFOSPACE_TYPE(n) (((n) << 5) & 0x1e0)
190 #define DWC3_GDBGFIFOSPACE_SPACE_AVAILABLE(n) (((n) >> 16) & 0xffff)
192 #define DWC3_TXFIFO 0
193 #define DWC3_RXFIFO 1
194 #define DWC3_TXREQQ 2
195 #define DWC3_RXREQQ 3
196 #define DWC3_RXINFOQ 4
197 #define DWC3_PSTATQ 5
198 #define DWC3_DESCFETCHQ 6
199 #define DWC3_EVENTQ 7
200 #define DWC3_AUXEVENTQ 8
202 /* Global RX Threshold Configuration Register */
203 #define DWC3_GRXTHRCFG_MAXRXBURSTSIZE(n) (((n) & 0x1f) << 19)
204 #define DWC3_GRXTHRCFG_RXPKTCNT(n) (((n) & 0xf) << 24)
205 #define DWC3_GRXTHRCFG_PKTCNTSEL BIT(29)
207 /* Global RX Threshold Configuration Register for DWC_usb31 only */
208 #define DWC31_GRXTHRCFG_MAXRXBURSTSIZE(n) (((n) & 0x1f) << 16)
209 #define DWC31_GRXTHRCFG_RXPKTCNT(n) (((n) & 0x1f) << 21)
210 #define DWC31_GRXTHRCFG_PKTCNTSEL BIT(26)
211 #define DWC31_RXTHRNUMPKTSEL_HS_PRD BIT(15)
212 #define DWC31_RXTHRNUMPKT_HS_PRD(n) (((n) & 0x3) << 13)
213 #define DWC31_RXTHRNUMPKTSEL_PRD BIT(10)
214 #define DWC31_RXTHRNUMPKT_PRD(n) (((n) & 0x1f) << 5)
215 #define DWC31_MAXRXBURSTSIZE_PRD(n) ((n) & 0x1f)
217 /* Global TX Threshold Configuration Register for DWC_usb31 only */
218 #define DWC31_GTXTHRCFG_MAXTXBURSTSIZE(n) (((n) & 0x1f) << 16)
219 #define DWC31_GTXTHRCFG_TXPKTCNT(n) (((n) & 0x1f) << 21)
220 #define DWC31_GTXTHRCFG_PKTCNTSEL BIT(26)
221 #define DWC31_TXTHRNUMPKTSEL_HS_PRD BIT(15)
222 #define DWC31_TXTHRNUMPKT_HS_PRD(n) (((n) & 0x3) << 13)
223 #define DWC31_TXTHRNUMPKTSEL_PRD BIT(10)
224 #define DWC31_TXTHRNUMPKT_PRD(n) (((n) & 0x1f) << 5)
225 #define DWC31_MAXTXBURSTSIZE_PRD(n) ((n) & 0x1f)
227 /* Global Configuration Register */
228 #define DWC3_GCTL_PWRDNSCALE(n) ((n) << 19)
229 #define DWC3_GCTL_U2RSTECN BIT(16)
230 #define DWC3_GCTL_RAMCLKSEL(x) (((x) & DWC3_GCTL_CLK_MASK) << 6)
231 #define DWC3_GCTL_CLK_BUS (0)
232 #define DWC3_GCTL_CLK_PIPE (1)
233 #define DWC3_GCTL_CLK_PIPEHALF (2)
234 #define DWC3_GCTL_CLK_MASK (3)
236 #define DWC3_GCTL_PRTCAP(n) (((n) & (3 << 12)) >> 12)
237 #define DWC3_GCTL_PRTCAPDIR(n) ((n) << 12)
238 #define DWC3_GCTL_PRTCAP_HOST 1
239 #define DWC3_GCTL_PRTCAP_DEVICE 2
240 #define DWC3_GCTL_PRTCAP_OTG 3
242 #define DWC3_GCTL_CORESOFTRESET BIT(11)
243 #define DWC3_GCTL_SOFITPSYNC BIT(10)
244 #define DWC3_GCTL_SCALEDOWN(n) ((n) << 4)
245 #define DWC3_GCTL_SCALEDOWN_MASK DWC3_GCTL_SCALEDOWN(3)
246 #define DWC3_GCTL_DISSCRAMBLE BIT(3)
247 #define DWC3_GCTL_U2EXIT_LFPS BIT(2)
248 #define DWC3_GCTL_GBLHIBERNATIONEN BIT(1)
249 #define DWC3_GCTL_DSBLCLKGTNG BIT(0)
251 /* Global User Control Register */
252 #define DWC3_GUCTL_HSTINAUTORETRY BIT(14)
254 /* Global User Control 1 Register */
255 #define DWC3_GUCTL1_PARKMODE_DISABLE_SS BIT(17)
256 #define DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS BIT(28)
257 #define DWC3_GUCTL1_DEV_L1_EXIT_BY_HW BIT(24)
259 /* Global Status Register */
260 #define DWC3_GSTS_OTG_IP BIT(10)
261 #define DWC3_GSTS_BC_IP BIT(9)
262 #define DWC3_GSTS_ADP_IP BIT(8)
263 #define DWC3_GSTS_HOST_IP BIT(7)
264 #define DWC3_GSTS_DEVICE_IP BIT(6)
265 #define DWC3_GSTS_CSR_TIMEOUT BIT(5)
266 #define DWC3_GSTS_BUS_ERR_ADDR_VLD BIT(4)
267 #define DWC3_GSTS_CURMOD(n) ((n) & 0x3)
268 #define DWC3_GSTS_CURMOD_DEVICE 0
269 #define DWC3_GSTS_CURMOD_HOST 1
271 /* Global USB2 PHY Configuration Register */
272 #define DWC3_GUSB2PHYCFG_PHYSOFTRST BIT(31)
273 #define DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS BIT(30)
274 #define DWC3_GUSB2PHYCFG_SUSPHY BIT(6)
275 #define DWC3_GUSB2PHYCFG_ULPI_UTMI BIT(4)
276 #define DWC3_GUSB2PHYCFG_ENBLSLPM BIT(8)
277 #define DWC3_GUSB2PHYCFG_PHYIF(n) (n << 3)
278 #define DWC3_GUSB2PHYCFG_PHYIF_MASK DWC3_GUSB2PHYCFG_PHYIF(1)
279 #define DWC3_GUSB2PHYCFG_USBTRDTIM(n) (n << 10)
280 #define DWC3_GUSB2PHYCFG_USBTRDTIM_MASK DWC3_GUSB2PHYCFG_USBTRDTIM(0xf)
281 #define USBTRDTIM_UTMI_8_BIT 9
282 #define USBTRDTIM_UTMI_16_BIT 5
283 #define UTMI_PHYIF_16_BIT 1
284 #define UTMI_PHYIF_8_BIT 0
286 /* Global USB2 PHY Vendor Control Register */
287 #define DWC3_GUSB2PHYACC_NEWREGREQ BIT(25)
288 #define DWC3_GUSB2PHYACC_DONE BIT(24)
289 #define DWC3_GUSB2PHYACC_BUSY BIT(23)
290 #define DWC3_GUSB2PHYACC_WRITE BIT(22)
291 #define DWC3_GUSB2PHYACC_ADDR(n) (n << 16)
292 #define DWC3_GUSB2PHYACC_EXTEND_ADDR(n) (n << 8)
293 #define DWC3_GUSB2PHYACC_DATA(n) (n & 0xff)
295 /* Global USB3 PIPE Control Register */
296 #define DWC3_GUSB3PIPECTL_PHYSOFTRST BIT(31)
297 #define DWC3_GUSB3PIPECTL_U2SSINP3OK BIT(29)
298 #define DWC3_GUSB3PIPECTL_DISRXDETINP3 BIT(28)
299 #define DWC3_GUSB3PIPECTL_UX_EXIT_PX BIT(27)
300 #define DWC3_GUSB3PIPECTL_REQP1P2P3 BIT(24)
301 #define DWC3_GUSB3PIPECTL_DEP1P2P3(n) ((n) << 19)
302 #define DWC3_GUSB3PIPECTL_DEP1P2P3_MASK DWC3_GUSB3PIPECTL_DEP1P2P3(7)
303 #define DWC3_GUSB3PIPECTL_DEP1P2P3_EN DWC3_GUSB3PIPECTL_DEP1P2P3(1)
304 #define DWC3_GUSB3PIPECTL_DEPOCHANGE BIT(18)
305 #define DWC3_GUSB3PIPECTL_SUSPHY BIT(17)
306 #define DWC3_GUSB3PIPECTL_LFPSFILT BIT(9)
307 #define DWC3_GUSB3PIPECTL_RX_DETOPOLL BIT(8)
308 #define DWC3_GUSB3PIPECTL_TX_DEEPH_MASK DWC3_GUSB3PIPECTL_TX_DEEPH(3)
309 #define DWC3_GUSB3PIPECTL_TX_DEEPH(n) ((n) << 1)
311 /* Global TX Fifo Size Register */
312 #define DWC31_GTXFIFOSIZ_TXFRAMNUM BIT(15) /* DWC_usb31 only */
313 #define DWC31_GTXFIFOSIZ_TXFDEP(n) ((n) & 0x7fff) /* DWC_usb31 only */
314 #define DWC3_GTXFIFOSIZ_TXFDEP(n) ((n) & 0xffff)
315 #define DWC3_GTXFIFOSIZ_TXFSTADDR(n) ((n) & 0xffff0000)
317 /* Global RX Fifo Size Register */
318 #define DWC31_GRXFIFOSIZ_RXFDEP(n) ((n) & 0x7fff) /* DWC_usb31 only */
319 #define DWC3_GRXFIFOSIZ_RXFDEP(n) ((n) & 0xffff)
321 /* Global Event Size Registers */
322 #define DWC3_GEVNTSIZ_INTMASK BIT(31)
323 #define DWC3_GEVNTSIZ_SIZE(n) ((n) & 0xffff)
325 /* Global HWPARAMS0 Register */
326 #define DWC3_GHWPARAMS0_MODE(n) ((n) & 0x3)
327 #define DWC3_GHWPARAMS0_MODE_GADGET 0
328 #define DWC3_GHWPARAMS0_MODE_HOST 1
329 #define DWC3_GHWPARAMS0_MODE_DRD 2
330 #define DWC3_GHWPARAMS0_MBUS_TYPE(n) (((n) >> 3) & 0x7)
331 #define DWC3_GHWPARAMS0_SBUS_TYPE(n) (((n) >> 6) & 0x3)
332 #define DWC3_GHWPARAMS0_MDWIDTH(n) (((n) >> 8) & 0xff)
333 #define DWC3_GHWPARAMS0_SDWIDTH(n) (((n) >> 16) & 0xff)
334 #define DWC3_GHWPARAMS0_AWIDTH(n) (((n) >> 24) & 0xff)
336 /* Global HWPARAMS1 Register */
337 #define DWC3_GHWPARAMS1_EN_PWROPT(n) (((n) & (3 << 24)) >> 24)
338 #define DWC3_GHWPARAMS1_EN_PWROPT_NO 0
339 #define DWC3_GHWPARAMS1_EN_PWROPT_CLK 1
340 #define DWC3_GHWPARAMS1_EN_PWROPT_HIB 2
341 #define DWC3_GHWPARAMS1_PWROPT(n) ((n) << 24)
342 #define DWC3_GHWPARAMS1_PWROPT_MASK DWC3_GHWPARAMS1_PWROPT(3)
343 #define DWC3_GHWPARAMS1_ENDBC BIT(31)
345 /* Global HWPARAMS3 Register */
346 #define DWC3_GHWPARAMS3_SSPHY_IFC(n) ((n) & 3)
347 #define DWC3_GHWPARAMS3_SSPHY_IFC_DIS 0
348 #define DWC3_GHWPARAMS3_SSPHY_IFC_GEN1 1
349 #define DWC3_GHWPARAMS3_SSPHY_IFC_GEN2 2 /* DWC_usb31 only */
350 #define DWC3_GHWPARAMS3_HSPHY_IFC(n) (((n) & (3 << 2)) >> 2)
351 #define DWC3_GHWPARAMS3_HSPHY_IFC_DIS 0
352 #define DWC3_GHWPARAMS3_HSPHY_IFC_UTMI 1
353 #define DWC3_GHWPARAMS3_HSPHY_IFC_ULPI 2
354 #define DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI 3
355 #define DWC3_GHWPARAMS3_FSPHY_IFC(n) (((n) & (3 << 4)) >> 4)
356 #define DWC3_GHWPARAMS3_FSPHY_IFC_DIS 0
357 #define DWC3_GHWPARAMS3_FSPHY_IFC_ENA 1
359 /* Global HWPARAMS4 Register */
360 #define DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(n) (((n) & (0x0f << 13)) >> 13)
361 #define DWC3_MAX_HIBER_SCRATCHBUFS 15
363 /* Global HWPARAMS6 Register */
364 #define DWC3_GHWPARAMS6_BCSUPPORT BIT(14)
365 #define DWC3_GHWPARAMS6_OTG3SUPPORT BIT(13)
366 #define DWC3_GHWPARAMS6_ADPSUPPORT BIT(12)
367 #define DWC3_GHWPARAMS6_HNPSUPPORT BIT(11)
368 #define DWC3_GHWPARAMS6_SRPSUPPORT BIT(10)
369 #define DWC3_GHWPARAMS6_EN_FPGA BIT(7)
372 #define DWC3_GHWPARAMS6_MDWIDTH(n) ((n) & (0x3 << 8))
374 /* Global HWPARAMS7 Register */
375 #define DWC3_GHWPARAMS7_RAM1_DEPTH(n) ((n) & 0xffff)
376 #define DWC3_GHWPARAMS7_RAM2_DEPTH(n) (((n) >> 16) & 0xffff)
378 /* Global Frame Length Adjustment Register */
379 #define DWC3_GFLADJ_30MHZ_SDBND_SEL BIT(7)
380 #define DWC3_GFLADJ_30MHZ_MASK 0x3f
382 /* Global User Control Register 2 */
383 #define DWC3_GUCTL2_RST_ACTBITLATER BIT(14)
385 /* Global User Control Register 3 */
386 #define DWC3_GUCTL3_SPLITDISABLE BIT(14)
388 /* Device Configuration Register */
389 #define DWC3_DCFG_DEVADDR(addr) ((addr) << 3)
390 #define DWC3_DCFG_DEVADDR_MASK DWC3_DCFG_DEVADDR(0x7f)
392 #define DWC3_DCFG_SPEED_MASK (7 << 0)
393 #define DWC3_DCFG_SUPERSPEED_PLUS (5 << 0) /* DWC_usb31 only */
394 #define DWC3_DCFG_SUPERSPEED (4 << 0)
395 #define DWC3_DCFG_HIGHSPEED (0 << 0)
396 #define DWC3_DCFG_FULLSPEED BIT(0)
397 #define DWC3_DCFG_LOWSPEED (2 << 0)
399 #define DWC3_DCFG_NUMP_SHIFT 17
400 #define DWC3_DCFG_NUMP(n) (((n) >> DWC3_DCFG_NUMP_SHIFT) & 0x1f)
401 #define DWC3_DCFG_NUMP_MASK (0x1f << DWC3_DCFG_NUMP_SHIFT)
402 #define DWC3_DCFG_LPM_CAP BIT(22)
404 /* Device Control Register */
405 #define DWC3_DCTL_RUN_STOP BIT(31)
406 #define DWC3_DCTL_CSFTRST BIT(30)
407 #define DWC3_DCTL_LSFTRST BIT(29)
409 #define DWC3_DCTL_HIRD_THRES_MASK (0x1f << 24)
410 #define DWC3_DCTL_HIRD_THRES(n) ((n) << 24)
412 #define DWC3_DCTL_APPL1RES BIT(23)
414 /* These apply for core versions 1.87a and earlier */
415 #define DWC3_DCTL_TRGTULST_MASK (0x0f << 17)
416 #define DWC3_DCTL_TRGTULST(n) ((n) << 17)
417 #define DWC3_DCTL_TRGTULST_U2 (DWC3_DCTL_TRGTULST(2))
418 #define DWC3_DCTL_TRGTULST_U3 (DWC3_DCTL_TRGTULST(3))
419 #define DWC3_DCTL_TRGTULST_SS_DIS (DWC3_DCTL_TRGTULST(4))
420 #define DWC3_DCTL_TRGTULST_RX_DET (DWC3_DCTL_TRGTULST(5))
421 #define DWC3_DCTL_TRGTULST_SS_INACT (DWC3_DCTL_TRGTULST(6))
423 /* These apply for core versions 1.94a and later */
424 #define DWC3_DCTL_NYET_THRES(n) (((n) & 0xf) << 20)
426 #define DWC3_DCTL_KEEP_CONNECT BIT(19)
427 #define DWC3_DCTL_L1_HIBER_EN BIT(18)
428 #define DWC3_DCTL_CRS BIT(17)
429 #define DWC3_DCTL_CSS BIT(16)
431 #define DWC3_DCTL_INITU2ENA BIT(12)
432 #define DWC3_DCTL_ACCEPTU2ENA BIT(11)
433 #define DWC3_DCTL_INITU1ENA BIT(10)
434 #define DWC3_DCTL_ACCEPTU1ENA BIT(9)
435 #define DWC3_DCTL_TSTCTRL_MASK (0xf << 1)
437 #define DWC3_DCTL_ULSTCHNGREQ_MASK (0x0f << 5)
438 #define DWC3_DCTL_ULSTCHNGREQ(n) (((n) << 5) & DWC3_DCTL_ULSTCHNGREQ_MASK)
440 #define DWC3_DCTL_ULSTCHNG_NO_ACTION (DWC3_DCTL_ULSTCHNGREQ(0))
441 #define DWC3_DCTL_ULSTCHNG_SS_DISABLED (DWC3_DCTL_ULSTCHNGREQ(4))
442 #define DWC3_DCTL_ULSTCHNG_RX_DETECT (DWC3_DCTL_ULSTCHNGREQ(5))
443 #define DWC3_DCTL_ULSTCHNG_SS_INACTIVE (DWC3_DCTL_ULSTCHNGREQ(6))
444 #define DWC3_DCTL_ULSTCHNG_RECOVERY (DWC3_DCTL_ULSTCHNGREQ(8))
445 #define DWC3_DCTL_ULSTCHNG_COMPLIANCE (DWC3_DCTL_ULSTCHNGREQ(10))
446 #define DWC3_DCTL_ULSTCHNG_LOOPBACK (DWC3_DCTL_ULSTCHNGREQ(11))
448 /* Device Event Enable Register */
449 #define DWC3_DEVTEN_VNDRDEVTSTRCVEDEN BIT(12)
450 #define DWC3_DEVTEN_EVNTOVERFLOWEN BIT(11)
451 #define DWC3_DEVTEN_CMDCMPLTEN BIT(10)
452 #define DWC3_DEVTEN_ERRTICERREN BIT(9)
453 #define DWC3_DEVTEN_SOFEN BIT(7)
454 #define DWC3_DEVTEN_EOPFEN BIT(6)
455 #define DWC3_DEVTEN_HIBERNATIONREQEVTEN BIT(5)
456 #define DWC3_DEVTEN_WKUPEVTEN BIT(4)
457 #define DWC3_DEVTEN_ULSTCNGEN BIT(3)
458 #define DWC3_DEVTEN_CONNECTDONEEN BIT(2)
459 #define DWC3_DEVTEN_USBRSTEN BIT(1)
460 #define DWC3_DEVTEN_DISCONNEVTEN BIT(0)
462 /* Device Status Register */
463 #define DWC3_DSTS_DCNRD BIT(29)
465 /* This applies for core versions 1.87a and earlier */
466 #define DWC3_DSTS_PWRUPREQ BIT(24)
468 /* These apply for core versions 1.94a and later */
469 #define DWC3_DSTS_RSS BIT(25)
470 #define DWC3_DSTS_SSS BIT(24)
472 #define DWC3_DSTS_COREIDLE BIT(23)
473 #define DWC3_DSTS_DEVCTRLHLT BIT(22)
475 #define DWC3_DSTS_USBLNKST_MASK (0x0f << 18)
476 #define DWC3_DSTS_USBLNKST(n) (((n) & DWC3_DSTS_USBLNKST_MASK) >> 18)
478 #define DWC3_DSTS_RXFIFOEMPTY BIT(17)
480 #define DWC3_DSTS_SOFFN_MASK (0x3fff << 3)
481 #define DWC3_DSTS_SOFFN(n) (((n) & DWC3_DSTS_SOFFN_MASK) >> 3)
483 #define DWC3_DSTS_CONNECTSPD (7 << 0)
485 #define DWC3_DSTS_SUPERSPEED_PLUS (5 << 0) /* DWC_usb31 only */
486 #define DWC3_DSTS_SUPERSPEED (4 << 0)
487 #define DWC3_DSTS_HIGHSPEED (0 << 0)
488 #define DWC3_DSTS_FULLSPEED BIT(0)
489 #define DWC3_DSTS_LOWSPEED (2 << 0)
491 /* Device Generic Command Register */
492 #define DWC3_DGCMD_SET_LMP 0x01
493 #define DWC3_DGCMD_SET_PERIODIC_PAR 0x02
494 #define DWC3_DGCMD_XMIT_FUNCTION 0x03
496 /* These apply for core versions 1.94a and later */
497 #define DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO 0x04
498 #define DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI 0x05
500 #define DWC3_DGCMD_SELECTED_FIFO_FLUSH 0x09
501 #define DWC3_DGCMD_ALL_FIFO_FLUSH 0x0a
502 #define DWC3_DGCMD_SET_ENDPOINT_NRDY 0x0c
503 #define DWC3_DGCMD_SET_ENDPOINT_PRIME 0x0d
504 #define DWC3_DGCMD_RUN_SOC_BUS_LOOPBACK 0x10
506 #define DWC3_DGCMD_STATUS(n) (((n) >> 12) & 0x0F)
507 #define DWC3_DGCMD_CMDACT BIT(10)
508 #define DWC3_DGCMD_CMDIOC BIT(8)
510 /* Device Generic Command Parameter Register */
511 #define DWC3_DGCMDPAR_FORCE_LINKPM_ACCEPT BIT(0)
512 #define DWC3_DGCMDPAR_FIFO_NUM(n) ((n) << 0)
513 #define DWC3_DGCMDPAR_RX_FIFO (0 << 5)
514 #define DWC3_DGCMDPAR_TX_FIFO BIT(5)
515 #define DWC3_DGCMDPAR_LOOPBACK_DIS (0 << 0)
516 #define DWC3_DGCMDPAR_LOOPBACK_ENA BIT(0)
518 /* Device Endpoint Command Register */
519 #define DWC3_DEPCMD_PARAM_SHIFT 16
520 #define DWC3_DEPCMD_PARAM(x) ((x) << DWC3_DEPCMD_PARAM_SHIFT)
521 #define DWC3_DEPCMD_GET_RSC_IDX(x) (((x) >> DWC3_DEPCMD_PARAM_SHIFT) & 0x7f)
522 #define DWC3_DEPCMD_STATUS(x) (((x) >> 12) & 0x0F)
523 #define DWC3_DEPCMD_HIPRI_FORCERM BIT(11)
524 #define DWC3_DEPCMD_CLEARPENDIN BIT(11)
525 #define DWC3_DEPCMD_CMDACT BIT(10)
526 #define DWC3_DEPCMD_CMDIOC BIT(8)
528 #define DWC3_DEPCMD_DEPSTARTCFG (0x09 << 0)
529 #define DWC3_DEPCMD_ENDTRANSFER (0x08 << 0)
530 #define DWC3_DEPCMD_UPDATETRANSFER (0x07 << 0)
531 #define DWC3_DEPCMD_STARTTRANSFER (0x06 << 0)
532 #define DWC3_DEPCMD_CLEARSTALL (0x05 << 0)
533 #define DWC3_DEPCMD_SETSTALL (0x04 << 0)
534 /* This applies for core versions 1.90a and earlier */
535 #define DWC3_DEPCMD_GETSEQNUMBER (0x03 << 0)
536 /* This applies for core versions 1.94a and later */
537 #define DWC3_DEPCMD_GETEPSTATE (0x03 << 0)
538 #define DWC3_DEPCMD_SETTRANSFRESOURCE (0x02 << 0)
539 #define DWC3_DEPCMD_SETEPCONFIG (0x01 << 0)
541 #define DWC3_DEPCMD_CMD(x) ((x) & 0xf)
543 /* The EP number goes 0..31 so ep0 is always out and ep1 is always in */
544 #define DWC3_DALEPENA_EP(n) BIT(n)
546 #define DWC3_DEPCMD_TYPE_CONTROL 0
547 #define DWC3_DEPCMD_TYPE_ISOC 1
548 #define DWC3_DEPCMD_TYPE_BULK 2
549 #define DWC3_DEPCMD_TYPE_INTR 3
551 #define DWC3_DEV_IMOD_COUNT_SHIFT 16
552 #define DWC3_DEV_IMOD_COUNT_MASK (0xffff << 16)
553 #define DWC3_DEV_IMOD_INTERVAL_SHIFT 0
554 #define DWC3_DEV_IMOD_INTERVAL_MASK (0xffff << 0)
556 /* OTG Configuration Register */
557 #define DWC3_OCFG_DISPWRCUTTOFF BIT(5)
558 #define DWC3_OCFG_HIBDISMASK BIT(4)
559 #define DWC3_OCFG_SFTRSTMASK BIT(3)
560 #define DWC3_OCFG_OTGVERSION BIT(2)
561 #define DWC3_OCFG_HNPCAP BIT(1)
562 #define DWC3_OCFG_SRPCAP BIT(0)
564 /* OTG CTL Register */
565 #define DWC3_OCTL_OTG3GOERR BIT(7)
566 #define DWC3_OCTL_PERIMODE BIT(6)
567 #define DWC3_OCTL_PRTPWRCTL BIT(5)
568 #define DWC3_OCTL_HNPREQ BIT(4)
569 #define DWC3_OCTL_SESREQ BIT(3)
570 #define DWC3_OCTL_TERMSELIDPULSE BIT(2)
571 #define DWC3_OCTL_DEVSETHNPEN BIT(1)
572 #define DWC3_OCTL_HSTSETHNPEN BIT(0)
574 /* OTG Event Register */
575 #define DWC3_OEVT_DEVICEMODE BIT(31)
576 #define DWC3_OEVT_XHCIRUNSTPSET BIT(27)
577 #define DWC3_OEVT_DEVRUNSTPSET BIT(26)
578 #define DWC3_OEVT_HIBENTRY BIT(25)
579 #define DWC3_OEVT_CONIDSTSCHNG BIT(24)
580 #define DWC3_OEVT_HRRCONFNOTIF BIT(23)
581 #define DWC3_OEVT_HRRINITNOTIF BIT(22)
582 #define DWC3_OEVT_ADEVIDLE BIT(21)
583 #define DWC3_OEVT_ADEVBHOSTEND BIT(20)
584 #define DWC3_OEVT_ADEVHOST BIT(19)
585 #define DWC3_OEVT_ADEVHNPCHNG BIT(18)
586 #define DWC3_OEVT_ADEVSRPDET BIT(17)
587 #define DWC3_OEVT_ADEVSESSENDDET BIT(16)
588 #define DWC3_OEVT_BDEVBHOSTEND BIT(11)
589 #define DWC3_OEVT_BDEVHNPCHNG BIT(10)
590 #define DWC3_OEVT_BDEVSESSVLDDET BIT(9)
591 #define DWC3_OEVT_BDEVVBUSCHNG BIT(8)
592 #define DWC3_OEVT_BSESSVLD BIT(3)
593 #define DWC3_OEVT_HSTNEGSTS BIT(2)
594 #define DWC3_OEVT_SESREQSTS BIT(1)
595 #define DWC3_OEVT_ERROR BIT(0)
597 /* OTG Event Enable Register */
598 #define DWC3_OEVTEN_XHCIRUNSTPSETEN BIT(27)
599 #define DWC3_OEVTEN_DEVRUNSTPSETEN BIT(26)
600 #define DWC3_OEVTEN_HIBENTRYEN BIT(25)
601 #define DWC3_OEVTEN_CONIDSTSCHNGEN BIT(24)
602 #define DWC3_OEVTEN_HRRCONFNOTIFEN BIT(23)
603 #define DWC3_OEVTEN_HRRINITNOTIFEN BIT(22)
604 #define DWC3_OEVTEN_ADEVIDLEEN BIT(21)
605 #define DWC3_OEVTEN_ADEVBHOSTENDEN BIT(20)
606 #define DWC3_OEVTEN_ADEVHOSTEN BIT(19)
607 #define DWC3_OEVTEN_ADEVHNPCHNGEN BIT(18)
608 #define DWC3_OEVTEN_ADEVSRPDETEN BIT(17)
609 #define DWC3_OEVTEN_ADEVSESSENDDETEN BIT(16)
610 #define DWC3_OEVTEN_BDEVBHOSTENDEN BIT(11)
611 #define DWC3_OEVTEN_BDEVHNPCHNGEN BIT(10)
612 #define DWC3_OEVTEN_BDEVSESSVLDDETEN BIT(9)
613 #define DWC3_OEVTEN_BDEVVBUSCHNGEN BIT(8)
615 /* OTG Status Register */
616 #define DWC3_OSTS_DEVRUNSTP BIT(13)
617 #define DWC3_OSTS_XHCIRUNSTP BIT(12)
618 #define DWC3_OSTS_PERIPHERALSTATE BIT(4)
619 #define DWC3_OSTS_XHCIPRTPOWER BIT(3)
620 #define DWC3_OSTS_BSESVLD BIT(2)
621 #define DWC3_OSTS_VBUSVLD BIT(1)
622 #define DWC3_OSTS_CONIDSTS BIT(0)
629 * struct dwc3_event_buffer - Software event buffer representation
631 * @cache: The buffer cache used in the threaded interrupt
632 * @length: size of this buffer
633 * @lpos: event offset
634 * @count: cache of last read event count register
635 * @flags: flags related to this event buffer
637 * @dwc: pointer to DWC controller
639 struct dwc3_event_buffer
{
647 #define DWC3_EVENT_PENDING BIT(0)
654 #define DWC3_EP_FLAG_STALLED BIT(0)
655 #define DWC3_EP_FLAG_WEDGED BIT(1)
657 #define DWC3_EP_DIRECTION_TX true
658 #define DWC3_EP_DIRECTION_RX false
660 #define DWC3_TRB_NUM 256
663 * struct dwc3_ep - device side endpoint representation
664 * @endpoint: usb endpoint
665 * @cancelled_list: list of cancelled requests for this endpoint
666 * @pending_list: list of pending requests for this endpoint
667 * @started_list: list of started requests on this endpoint
668 * @regs: pointer to first endpoint register
669 * @trb_pool: array of transaction buffers
670 * @trb_pool_dma: dma address of @trb_pool
671 * @trb_enqueue: enqueue 'pointer' into TRB array
672 * @trb_dequeue: dequeue 'pointer' into TRB array
673 * @dwc: pointer to DWC controller
674 * @saved_state: ep state saved during hibernation
675 * @flags: endpoint flags (wedged, stalled, ...)
676 * @number: endpoint number (1 - 15)
677 * @type: set to bmAttributes & USB_ENDPOINT_XFERTYPE_MASK
678 * @resource_index: Resource transfer index
679 * @frame_number: set to the frame number we want this transfer to start (ISOC)
680 * @interval: the interval on which the ISOC transfer is started
681 * @name: a human readable name e.g. ep1out-bulk
682 * @direction: true for TX, false for RX
683 * @stream_capable: true when streams are enabled
684 * @combo_num: the test combination BIT[15:14] of the frame number to test
685 * isochronous START TRANSFER command failure workaround
686 * @start_cmd_status: the status of testing START TRANSFER command with
690 struct usb_ep endpoint
;
691 struct list_head cancelled_list
;
692 struct list_head pending_list
;
693 struct list_head started_list
;
697 struct dwc3_trb
*trb_pool
;
698 dma_addr_t trb_pool_dma
;
703 #define DWC3_EP_ENABLED BIT(0)
704 #define DWC3_EP_STALL BIT(1)
705 #define DWC3_EP_WEDGE BIT(2)
706 #define DWC3_EP_TRANSFER_STARTED BIT(3)
707 #define DWC3_EP_END_TRANSFER_PENDING BIT(4)
708 #define DWC3_EP_PENDING_REQUEST BIT(5)
709 #define DWC3_EP_DELAY_START BIT(6)
710 #define DWC3_EP_WAIT_TRANSFER_COMPLETE BIT(7)
711 #define DWC3_EP_IGNORE_NEXT_NOSTREAM BIT(8)
712 #define DWC3_EP_FORCE_RESTART_STREAM BIT(9)
713 #define DWC3_EP_FIRST_STREAM_PRIMED BIT(10)
714 #define DWC3_EP_PENDING_CLEAR_STALL BIT(11)
716 /* This last one is specific to EP0 */
717 #define DWC3_EP0_DIR_IN BIT(31)
720 * IMPORTANT: we *know* we have 256 TRBs in our @trb_pool, so we will
721 * use a u8 type here. If anybody decides to increase number of TRBs to
722 * anything larger than 256 - I can't see why people would want to do
723 * this though - then this type needs to be changed.
725 * By using u8 types we ensure that our % operator when incrementing
726 * enqueue and dequeue get optimized away by the compiler.
739 unsigned direction
:1;
740 unsigned stream_capable
:1;
742 /* For isochronous START TRANSFER workaround only */
744 int start_cmd_status
;
748 DWC3_PHY_UNKNOWN
= 0,
754 DWC3_EP0_UNKNOWN
= 0,
757 DWC3_EP0_NRDY_STATUS
,
760 enum dwc3_ep0_state
{
767 enum dwc3_link_state
{
769 DWC3_LINK_STATE_U0
= 0x00, /* in HS, means ON */
770 DWC3_LINK_STATE_U1
= 0x01,
771 DWC3_LINK_STATE_U2
= 0x02, /* in HS, means SLEEP */
772 DWC3_LINK_STATE_U3
= 0x03, /* in HS, means SUSPEND */
773 DWC3_LINK_STATE_SS_DIS
= 0x04,
774 DWC3_LINK_STATE_RX_DET
= 0x05, /* in HS, means Early Suspend */
775 DWC3_LINK_STATE_SS_INACT
= 0x06,
776 DWC3_LINK_STATE_POLL
= 0x07,
777 DWC3_LINK_STATE_RECOV
= 0x08,
778 DWC3_LINK_STATE_HRESET
= 0x09,
779 DWC3_LINK_STATE_CMPLY
= 0x0a,
780 DWC3_LINK_STATE_LPBK
= 0x0b,
781 DWC3_LINK_STATE_RESET
= 0x0e,
782 DWC3_LINK_STATE_RESUME
= 0x0f,
783 DWC3_LINK_STATE_MASK
= 0x0f,
786 /* TRB Length, PCM and Status */
787 #define DWC3_TRB_SIZE_MASK (0x00ffffff)
788 #define DWC3_TRB_SIZE_LENGTH(n) ((n) & DWC3_TRB_SIZE_MASK)
789 #define DWC3_TRB_SIZE_PCM1(n) (((n) & 0x03) << 24)
790 #define DWC3_TRB_SIZE_TRBSTS(n) (((n) & (0x0f << 28)) >> 28)
792 #define DWC3_TRBSTS_OK 0
793 #define DWC3_TRBSTS_MISSED_ISOC 1
794 #define DWC3_TRBSTS_SETUP_PENDING 2
795 #define DWC3_TRB_STS_XFER_IN_PROG 4
798 #define DWC3_TRB_CTRL_HWO BIT(0)
799 #define DWC3_TRB_CTRL_LST BIT(1)
800 #define DWC3_TRB_CTRL_CHN BIT(2)
801 #define DWC3_TRB_CTRL_CSP BIT(3)
802 #define DWC3_TRB_CTRL_TRBCTL(n) (((n) & 0x3f) << 4)
803 #define DWC3_TRB_CTRL_ISP_IMI BIT(10)
804 #define DWC3_TRB_CTRL_IOC BIT(11)
805 #define DWC3_TRB_CTRL_SID_SOFN(n) (((n) & 0xffff) << 14)
806 #define DWC3_TRB_CTRL_GET_SID_SOFN(n) (((n) & (0xffff << 14)) >> 14)
808 #define DWC3_TRBCTL_TYPE(n) ((n) & (0x3f << 4))
809 #define DWC3_TRBCTL_NORMAL DWC3_TRB_CTRL_TRBCTL(1)
810 #define DWC3_TRBCTL_CONTROL_SETUP DWC3_TRB_CTRL_TRBCTL(2)
811 #define DWC3_TRBCTL_CONTROL_STATUS2 DWC3_TRB_CTRL_TRBCTL(3)
812 #define DWC3_TRBCTL_CONTROL_STATUS3 DWC3_TRB_CTRL_TRBCTL(4)
813 #define DWC3_TRBCTL_CONTROL_DATA DWC3_TRB_CTRL_TRBCTL(5)
814 #define DWC3_TRBCTL_ISOCHRONOUS_FIRST DWC3_TRB_CTRL_TRBCTL(6)
815 #define DWC3_TRBCTL_ISOCHRONOUS DWC3_TRB_CTRL_TRBCTL(7)
816 #define DWC3_TRBCTL_LINK_TRB DWC3_TRB_CTRL_TRBCTL(8)
819 * struct dwc3_trb - transfer request block (hw format)
833 * struct dwc3_hwparams - copy of HWPARAMS registers
834 * @hwparams0: GHWPARAMS0
835 * @hwparams1: GHWPARAMS1
836 * @hwparams2: GHWPARAMS2
837 * @hwparams3: GHWPARAMS3
838 * @hwparams4: GHWPARAMS4
839 * @hwparams5: GHWPARAMS5
840 * @hwparams6: GHWPARAMS6
841 * @hwparams7: GHWPARAMS7
842 * @hwparams8: GHWPARAMS8
844 struct dwc3_hwparams
{
857 #define DWC3_MODE(n) ((n) & 0x7)
859 #define DWC3_MDWIDTH(n) (((n) & 0xff00) >> 8)
862 #define DWC3_NUM_INT(n) (((n) & (0x3f << 15)) >> 15)
865 #define DWC3_NUM_IN_EPS_MASK (0x1f << 18)
866 #define DWC3_NUM_EPS_MASK (0x3f << 12)
867 #define DWC3_NUM_EPS(p) (((p)->hwparams3 & \
868 (DWC3_NUM_EPS_MASK)) >> 12)
869 #define DWC3_NUM_IN_EPS(p) (((p)->hwparams3 & \
870 (DWC3_NUM_IN_EPS_MASK)) >> 18)
873 #define DWC3_RAM1_DEPTH(n) ((n) & 0xffff)
876 * struct dwc3_request - representation of a transfer request
877 * @request: struct usb_request to be transferred
878 * @list: a list_head used for request queueing
879 * @dep: struct dwc3_ep owning this request
880 * @sg: pointer to first incomplete sg
881 * @start_sg: pointer to the sg which should be queued next
882 * @num_pending_sgs: counter to pending sgs
883 * @num_queued_sgs: counter to the number of sgs which already got queued
884 * @remaining: amount of data remaining
885 * @status: internal dwc3 request status tracking
886 * @epnum: endpoint number to which this request refers
887 * @trb: pointer to struct dwc3_trb
888 * @trb_dma: DMA address of @trb
889 * @num_trbs: number of TRBs used by this request
890 * @needs_extra_trb: true when request needs one extra TRB (either due to ZLP
892 * @direction: IN or OUT direction flag
893 * @mapped: true when request has been dma-mapped
895 struct dwc3_request
{
896 struct usb_request request
;
897 struct list_head list
;
899 struct scatterlist
*sg
;
900 struct scatterlist
*start_sg
;
902 unsigned int num_pending_sgs
;
903 unsigned int num_queued_sgs
;
904 unsigned int remaining
;
907 #define DWC3_REQUEST_STATUS_QUEUED 0
908 #define DWC3_REQUEST_STATUS_STARTED 1
909 #define DWC3_REQUEST_STATUS_CANCELLED 2
910 #define DWC3_REQUEST_STATUS_COMPLETED 3
911 #define DWC3_REQUEST_STATUS_UNKNOWN -1
914 struct dwc3_trb
*trb
;
917 unsigned int num_trbs
;
919 unsigned int needs_extra_trb
:1;
920 unsigned int direction
:1;
921 unsigned int mapped
:1;
925 * struct dwc3_scratchpad_array - hibernation scratchpad array
926 * (format defined by hw)
928 struct dwc3_scratchpad_array
{
929 __le64 dma_adr
[DWC3_MAX_HIBER_SCRATCHBUFS
];
933 * struct dwc3 - representation of our controller
934 * @drd_work: workqueue used for role swapping
935 * @ep0_trb: trb which is used for the ctrl_req
936 * @bounce: address of bounce buffer
937 * @scratchbuf: address of scratch buffer
938 * @setup_buf: used while precessing STD USB requests
939 * @ep0_trb_addr: dma address of @ep0_trb
940 * @bounce_addr: dma address of @bounce
941 * @ep0_usb_req: dummy req used while handling STD USB requests
942 * @scratch_addr: dma address of scratchbuf
943 * @ep0_in_setup: one control transfer is completed and enter setup phase
944 * @lock: for synchronizing
945 * @dev: pointer to our struct device
946 * @sysdev: pointer to the DMA-capable device
947 * @xhci: pointer to our xHCI child
948 * @xhci_resources: struct resources for our @xhci child
949 * @ev_buf: struct dwc3_event_buffer pointer
950 * @eps: endpoint array
951 * @gadget: device side representation of the peripheral controller
952 * @gadget_driver: pointer to the gadget driver
953 * @clks: array of clocks
954 * @num_clks: number of clocks
955 * @reset: reset control
956 * @regs: base address for our registers
957 * @regs_size: address space size
958 * @fladj: frame length adjustment
959 * @irq_gadget: peripheral controller's IRQ number
960 * @otg_irq: IRQ number for OTG IRQs
961 * @current_otg_role: current role of operation while using the OTG block
962 * @desired_otg_role: desired role of operation while using the OTG block
963 * @otg_restart_host: flag that OTG controller needs to restart host
964 * @nr_scratch: number of scratch buffers
965 * @u1u2: only used on revisions <1.83a for workaround
966 * @maximum_speed: maximum speed requested (mainly for testing purposes)
967 * @ip: controller's ID
968 * @revision: controller's version of an IP
969 * @version_type: VERSIONTYPE register contents, a sub release of a revision
970 * @dr_mode: requested mode of operation
971 * @current_dr_role: current role of operation when in dual-role mode
972 * @desired_dr_role: desired role of operation when in dual-role mode
973 * @edev: extcon handle
974 * @edev_nb: extcon notifier
975 * @hsphy_mode: UTMI phy mode, one of following:
976 * - USBPHY_INTERFACE_MODE_UTMI
977 * - USBPHY_INTERFACE_MODE_UTMIW
978 * @role_sw: usb_role_switch handle
979 * @role_switch_default_mode: default operation mode of controller while
980 * usb role is USB_ROLE_NONE.
981 * @usb2_phy: pointer to USB2 PHY
982 * @usb3_phy: pointer to USB3 PHY
983 * @usb2_generic_phy: pointer to USB2 PHY
984 * @usb3_generic_phy: pointer to USB3 PHY
985 * @phys_ready: flag to indicate that PHYs are ready
986 * @ulpi: pointer to ulpi interface
987 * @ulpi_ready: flag to indicate that ULPI is initialized
988 * @u2sel: parameter from Set SEL request.
989 * @u2pel: parameter from Set SEL request.
990 * @u1sel: parameter from Set SEL request.
991 * @u1pel: parameter from Set SEL request.
992 * @num_eps: number of endpoints
993 * @ep0_next_event: hold the next expected event
994 * @ep0state: state of endpoint zero
995 * @link_state: link state
996 * @speed: device speed (super, high, full, low)
997 * @hwparams: copy of hwparams registers
998 * @root: debugfs root folder pointer
999 * @regset: debugfs pointer to regdump file
1000 * @dbg_lsp_select: current debug lsp mux register selection
1001 * @test_mode: true when we're entering a USB test mode
1002 * @test_mode_nr: test feature selector
1003 * @lpm_nyet_threshold: LPM NYET response threshold
1004 * @hird_threshold: HIRD threshold
1005 * @rx_thr_num_pkt_prd: periodic ESS receive packet count
1006 * @rx_max_burst_prd: max periodic ESS receive burst size
1007 * @tx_thr_num_pkt_prd: periodic ESS transmit packet count
1008 * @tx_max_burst_prd: max periodic ESS transmit burst size
1009 * @hsphy_interface: "utmi" or "ulpi"
1010 * @connected: true when we're connected to a host, false otherwise
1011 * @delayed_status: true when gadget driver asks for delayed status
1012 * @ep0_bounced: true when we used bounce buffer
1013 * @ep0_expect_in: true when we expect a DATA IN transfer
1014 * @has_hibernation: true when dwc3 was configured with Hibernation
1015 * @sysdev_is_parent: true when dwc3 device has a parent driver
1016 * @has_lpm_erratum: true when core was configured with LPM Erratum. Note that
1017 * there's now way for software to detect this in runtime.
1018 * @is_utmi_l1_suspend: the core asserts output signal
1020 * 1 - utmi_l1_suspend_n
1021 * @is_fpga: true when we are using the FPGA board
1022 * @pending_events: true when we have pending IRQs to be handled
1023 * @pullups_connected: true when Run/Stop bit is set
1024 * @setup_packet_pending: true when there's a Setup Packet in FIFO. Workaround
1025 * @three_stage_setup: set if we perform a three phase setup
1026 * @dis_start_transfer_quirk: set if start_transfer failure SW workaround is
1027 * not needed for DWC_usb31 version 1.70a-ea06 and below
1028 * @usb3_lpm_capable: set if hadrware supports Link Power Management
1029 * @usb2_lpm_disable: set to disable usb2 lpm
1030 * @disable_scramble_quirk: set if we enable the disable scramble quirk
1031 * @u2exit_lfps_quirk: set if we enable u2exit lfps quirk
1032 * @u2ss_inp3_quirk: set if we enable P3 OK for U2/SS Inactive quirk
1033 * @req_p1p2p3_quirk: set if we enable request p1p2p3 quirk
1034 * @del_p1p2p3_quirk: set if we enable delay p1p2p3 quirk
1035 * @del_phy_power_chg_quirk: set if we enable delay phy power change quirk
1036 * @lfps_filter_quirk: set if we enable LFPS filter quirk
1037 * @rx_detect_poll_quirk: set if we enable rx_detect to polling lfps quirk
1038 * @dis_u3_susphy_quirk: set if we disable usb3 suspend phy
1039 * @dis_u2_susphy_quirk: set if we disable usb2 suspend phy
1040 * @dis_enblslpm_quirk: set if we clear enblslpm in GUSB2PHYCFG,
1041 * disabling the suspend signal to the PHY.
1042 * @dis_u1_entry_quirk: set if link entering into U1 state needs to be disabled.
1043 * @dis_u2_entry_quirk: set if link entering into U2 state needs to be disabled.
1044 * @dis_rxdet_inp3_quirk: set if we disable Rx.Detect in P3
1045 * @dis_u2_freeclk_exists_quirk : set if we clear u2_freeclk_exists
1046 * in GUSB2PHYCFG, specify that USB2 PHY doesn't
1047 * provide a free-running PHY clock.
1048 * @dis_del_phy_power_chg_quirk: set if we disable delay phy power
1050 * @dis_tx_ipgap_linecheck_quirk: set if we disable u2mac linestate
1051 * check during HS transmit.
1052 * @parkmode_disable_ss_quirk: set if we need to disable all SuperSpeed
1053 * instances in park mode.
1054 * @tx_de_emphasis_quirk: set if we enable Tx de-emphasis quirk
1055 * @tx_de_emphasis: Tx de-emphasis value
1056 * 0 - -6dB de-emphasis
1057 * 1 - -3.5dB de-emphasis
1058 * 2 - No de-emphasis
1060 * @dis_metastability_quirk: set to disable metastability quirk.
1061 * @dis_split_quirk: set to disable split boundary.
1062 * @imod_interval: set the interrupt moderation interval in 250ns
1063 * increments or 0 to disable.
1066 struct work_struct drd_work
;
1067 struct dwc3_trb
*ep0_trb
;
1071 dma_addr_t ep0_trb_addr
;
1072 dma_addr_t bounce_addr
;
1073 dma_addr_t scratch_addr
;
1074 struct dwc3_request ep0_usb_req
;
1075 struct completion ep0_in_setup
;
1081 struct device
*sysdev
;
1083 struct platform_device
*xhci
;
1084 struct resource xhci_resources
[DWC3_XHCI_RESOURCES_NUM
];
1086 struct dwc3_event_buffer
*ev_buf
;
1087 struct dwc3_ep
*eps
[DWC3_ENDPOINTS_NUM
];
1089 struct usb_gadget
*gadget
;
1090 struct usb_gadget_driver
*gadget_driver
;
1092 struct clk_bulk_data
*clks
;
1095 struct reset_control
*reset
;
1097 struct usb_phy
*usb2_phy
;
1098 struct usb_phy
*usb3_phy
;
1100 struct phy
*usb2_generic_phy
;
1101 struct phy
*usb3_generic_phy
;
1111 enum usb_dr_mode dr_mode
;
1112 u32 current_dr_role
;
1113 u32 desired_dr_role
;
1114 struct extcon_dev
*edev
;
1115 struct notifier_block edev_nb
;
1116 enum usb_phy_interface hsphy_mode
;
1117 struct usb_role_switch
*role_sw
;
1118 enum usb_dr_mode role_switch_default_mode
;
1123 u32 current_otg_role
;
1124 u32 desired_otg_role
;
1125 bool otg_restart_host
;
1132 #define DWC3_IP 0x5533
1133 #define DWC31_IP 0x3331
1134 #define DWC32_IP 0x3332
1138 #define DWC3_REVISION_ANY 0x0
1139 #define DWC3_REVISION_173A 0x5533173a
1140 #define DWC3_REVISION_175A 0x5533175a
1141 #define DWC3_REVISION_180A 0x5533180a
1142 #define DWC3_REVISION_183A 0x5533183a
1143 #define DWC3_REVISION_185A 0x5533185a
1144 #define DWC3_REVISION_187A 0x5533187a
1145 #define DWC3_REVISION_188A 0x5533188a
1146 #define DWC3_REVISION_190A 0x5533190a
1147 #define DWC3_REVISION_194A 0x5533194a
1148 #define DWC3_REVISION_200A 0x5533200a
1149 #define DWC3_REVISION_202A 0x5533202a
1150 #define DWC3_REVISION_210A 0x5533210a
1151 #define DWC3_REVISION_220A 0x5533220a
1152 #define DWC3_REVISION_230A 0x5533230a
1153 #define DWC3_REVISION_240A 0x5533240a
1154 #define DWC3_REVISION_250A 0x5533250a
1155 #define DWC3_REVISION_260A 0x5533260a
1156 #define DWC3_REVISION_270A 0x5533270a
1157 #define DWC3_REVISION_280A 0x5533280a
1158 #define DWC3_REVISION_290A 0x5533290a
1159 #define DWC3_REVISION_300A 0x5533300a
1160 #define DWC3_REVISION_310A 0x5533310a
1161 #define DWC3_REVISION_330A 0x5533330a
1163 #define DWC31_REVISION_ANY 0x0
1164 #define DWC31_REVISION_110A 0x3131302a
1165 #define DWC31_REVISION_120A 0x3132302a
1166 #define DWC31_REVISION_160A 0x3136302a
1167 #define DWC31_REVISION_170A 0x3137302a
1168 #define DWC31_REVISION_180A 0x3138302a
1169 #define DWC31_REVISION_190A 0x3139302a
1171 #define DWC32_REVISION_ANY 0x0
1172 #define DWC32_REVISION_100A 0x3130302a
1176 #define DWC31_VERSIONTYPE_ANY 0x0
1177 #define DWC31_VERSIONTYPE_EA01 0x65613031
1178 #define DWC31_VERSIONTYPE_EA02 0x65613032
1179 #define DWC31_VERSIONTYPE_EA03 0x65613033
1180 #define DWC31_VERSIONTYPE_EA04 0x65613034
1181 #define DWC31_VERSIONTYPE_EA05 0x65613035
1182 #define DWC31_VERSIONTYPE_EA06 0x65613036
1184 enum dwc3_ep0_next ep0_next_event
;
1185 enum dwc3_ep0_state ep0state
;
1186 enum dwc3_link_state link_state
;
1197 struct dwc3_hwparams hwparams
;
1198 struct dentry
*root
;
1199 struct debugfs_regset32
*regset
;
1205 u8 lpm_nyet_threshold
;
1207 u8 rx_thr_num_pkt_prd
;
1208 u8 rx_max_burst_prd
;
1209 u8 tx_thr_num_pkt_prd
;
1210 u8 tx_max_burst_prd
;
1212 const char *hsphy_interface
;
1214 unsigned connected
:1;
1215 unsigned delayed_status
:1;
1216 unsigned ep0_bounced
:1;
1217 unsigned ep0_expect_in
:1;
1218 unsigned has_hibernation
:1;
1219 unsigned sysdev_is_parent
:1;
1220 unsigned has_lpm_erratum
:1;
1221 unsigned is_utmi_l1_suspend
:1;
1223 unsigned pending_events
:1;
1224 unsigned pullups_connected
:1;
1225 unsigned setup_packet_pending
:1;
1226 unsigned three_stage_setup
:1;
1227 unsigned dis_start_transfer_quirk
:1;
1228 unsigned usb3_lpm_capable
:1;
1229 unsigned usb2_lpm_disable
:1;
1231 unsigned disable_scramble_quirk
:1;
1232 unsigned u2exit_lfps_quirk
:1;
1233 unsigned u2ss_inp3_quirk
:1;
1234 unsigned req_p1p2p3_quirk
:1;
1235 unsigned del_p1p2p3_quirk
:1;
1236 unsigned del_phy_power_chg_quirk
:1;
1237 unsigned lfps_filter_quirk
:1;
1238 unsigned rx_detect_poll_quirk
:1;
1239 unsigned dis_u3_susphy_quirk
:1;
1240 unsigned dis_u2_susphy_quirk
:1;
1241 unsigned dis_enblslpm_quirk
:1;
1242 unsigned dis_u1_entry_quirk
:1;
1243 unsigned dis_u2_entry_quirk
:1;
1244 unsigned dis_rxdet_inp3_quirk
:1;
1245 unsigned dis_u2_freeclk_exists_quirk
:1;
1246 unsigned dis_del_phy_power_chg_quirk
:1;
1247 unsigned dis_tx_ipgap_linecheck_quirk
:1;
1248 unsigned parkmode_disable_ss_quirk
:1;
1250 unsigned tx_de_emphasis_quirk
:1;
1251 unsigned tx_de_emphasis
:2;
1253 unsigned dis_metastability_quirk
:1;
1255 unsigned dis_split_quirk
:1;
1260 #define INCRX_BURST_MODE 0
1261 #define INCRX_UNDEF_LENGTH_BURST_MODE 1
1263 #define work_to_dwc(w) (container_of((w), struct dwc3, drd_work))
1265 /* -------------------------------------------------------------------------- */
1267 struct dwc3_event_type
{
1270 u32 reserved8_31
:24;
1273 #define DWC3_DEPEVT_XFERCOMPLETE 0x01
1274 #define DWC3_DEPEVT_XFERINPROGRESS 0x02
1275 #define DWC3_DEPEVT_XFERNOTREADY 0x03
1276 #define DWC3_DEPEVT_RXTXFIFOEVT 0x04
1277 #define DWC3_DEPEVT_STREAMEVT 0x06
1278 #define DWC3_DEPEVT_EPCMDCMPLT 0x07
1281 * struct dwc3_event_depevt - Device Endpoint Events
1282 * @one_bit: indicates this is an endpoint event (not used)
1283 * @endpoint_number: number of the endpoint
1284 * @endpoint_event: The event we have:
1286 * 0x01 - XferComplete
1287 * 0x02 - XferInProgress
1288 * 0x03 - XferNotReady
1289 * 0x04 - RxTxFifoEvt (IN->Underrun, OUT->Overrun)
1293 * @reserved11_10: Reserved, don't use.
1294 * @status: Indicates the status of the event. Refer to databook for
1296 * @parameters: Parameters of the current event. Refer to databook for
1299 struct dwc3_event_depevt
{
1301 u32 endpoint_number
:5;
1302 u32 endpoint_event
:4;
1303 u32 reserved11_10
:2;
1306 /* Within XferNotReady */
1307 #define DEPEVT_STATUS_TRANSFER_ACTIVE BIT(3)
1309 /* Within XferComplete or XferInProgress */
1310 #define DEPEVT_STATUS_BUSERR BIT(0)
1311 #define DEPEVT_STATUS_SHORT BIT(1)
1312 #define DEPEVT_STATUS_IOC BIT(2)
1313 #define DEPEVT_STATUS_LST BIT(3) /* XferComplete */
1314 #define DEPEVT_STATUS_MISSED_ISOC BIT(3) /* XferInProgress */
1316 /* Stream event only */
1317 #define DEPEVT_STREAMEVT_FOUND 1
1318 #define DEPEVT_STREAMEVT_NOTFOUND 2
1320 /* Stream event parameter */
1321 #define DEPEVT_STREAM_PRIME 0xfffe
1322 #define DEPEVT_STREAM_NOSTREAM 0x0
1324 /* Control-only Status */
1325 #define DEPEVT_STATUS_CONTROL_DATA 1
1326 #define DEPEVT_STATUS_CONTROL_STATUS 2
1327 #define DEPEVT_STATUS_CONTROL_PHASE(n) ((n) & 3)
1329 /* In response to Start Transfer */
1330 #define DEPEVT_TRANSFER_NO_RESOURCE 1
1331 #define DEPEVT_TRANSFER_BUS_EXPIRY 2
1335 /* For Command Complete Events */
1336 #define DEPEVT_PARAMETER_CMD(n) (((n) & (0xf << 8)) >> 8)
1340 * struct dwc3_event_devt - Device Events
1341 * @one_bit: indicates this is a non-endpoint event (not used)
1342 * @device_event: indicates it's a device event. Should read as 0x00
1343 * @type: indicates the type of device event.
1356 * 12 - VndrDevTstRcved
1357 * @reserved15_12: Reserved, not used
1358 * @event_info: Information about this event
1359 * @reserved31_25: Reserved, not used
1361 struct dwc3_event_devt
{
1365 u32 reserved15_12
:4;
1367 u32 reserved31_25
:7;
1371 * struct dwc3_event_gevt - Other Core Events
1372 * @one_bit: indicates this is a non-endpoint event (not used)
1373 * @device_event: indicates it's (0x03) Carkit or (0x04) I2C event.
1374 * @phy_port_number: self-explanatory
1375 * @reserved31_12: Reserved, not used.
1377 struct dwc3_event_gevt
{
1380 u32 phy_port_number
:4;
1381 u32 reserved31_12
:20;
1385 * union dwc3_event - representation of Event Buffer contents
1386 * @raw: raw 32-bit event
1387 * @type: the type of the event
1388 * @depevt: Device Endpoint Event
1389 * @devt: Device Event
1390 * @gevt: Global Event
1394 struct dwc3_event_type type
;
1395 struct dwc3_event_depevt depevt
;
1396 struct dwc3_event_devt devt
;
1397 struct dwc3_event_gevt gevt
;
1401 * struct dwc3_gadget_ep_cmd_params - representation of endpoint command
1403 * @param2: third parameter
1404 * @param1: second parameter
1405 * @param0: first parameter
1407 struct dwc3_gadget_ep_cmd_params
{
1414 * DWC3 Features to be used as Driver Data
1417 #define DWC3_HAS_PERIPHERAL BIT(0)
1418 #define DWC3_HAS_XHCI BIT(1)
1419 #define DWC3_HAS_OTG BIT(3)
1422 void dwc3_set_prtcap(struct dwc3
*dwc
, u32 mode
);
1423 void dwc3_set_mode(struct dwc3
*dwc
, u32 mode
);
1424 u32
dwc3_core_fifo_space(struct dwc3_ep
*dep
, u8 type
);
1426 #define DWC3_IP_IS(_ip) \
1427 (dwc->ip == _ip##_IP)
1429 #define DWC3_VER_IS(_ip, _ver) \
1430 (DWC3_IP_IS(_ip) && dwc->revision == _ip##_REVISION_##_ver)
1432 #define DWC3_VER_IS_PRIOR(_ip, _ver) \
1433 (DWC3_IP_IS(_ip) && dwc->revision < _ip##_REVISION_##_ver)
1435 #define DWC3_VER_IS_WITHIN(_ip, _from, _to) \
1436 (DWC3_IP_IS(_ip) && \
1437 dwc->revision >= _ip##_REVISION_##_from && \
1438 (!(_ip##_REVISION_##_to) || \
1439 dwc->revision <= _ip##_REVISION_##_to))
1441 #define DWC3_VER_TYPE_IS_WITHIN(_ip, _ver, _from, _to) \
1442 (DWC3_VER_IS(_ip, _ver) && \
1443 dwc->version_type >= _ip##_VERSIONTYPE_##_from && \
1444 (!(_ip##_VERSIONTYPE_##_to) || \
1445 dwc->version_type <= _ip##_VERSIONTYPE_##_to))
1447 bool dwc3_has_imod(struct dwc3
*dwc
);
1449 int dwc3_event_buffers_setup(struct dwc3
*dwc
);
1450 void dwc3_event_buffers_cleanup(struct dwc3
*dwc
);
1452 #if IS_ENABLED(CONFIG_USB_DWC3_HOST) || IS_ENABLED(CONFIG_USB_DWC3_DUAL_ROLE)
1453 int dwc3_host_init(struct dwc3
*dwc
);
1454 void dwc3_host_exit(struct dwc3
*dwc
);
1456 static inline int dwc3_host_init(struct dwc3
*dwc
)
1458 static inline void dwc3_host_exit(struct dwc3
*dwc
)
1462 #if IS_ENABLED(CONFIG_USB_DWC3_GADGET) || IS_ENABLED(CONFIG_USB_DWC3_DUAL_ROLE)
1463 int dwc3_gadget_init(struct dwc3
*dwc
);
1464 void dwc3_gadget_exit(struct dwc3
*dwc
);
1465 int dwc3_gadget_set_test_mode(struct dwc3
*dwc
, int mode
);
1466 int dwc3_gadget_get_link_state(struct dwc3
*dwc
);
1467 int dwc3_gadget_set_link_state(struct dwc3
*dwc
, enum dwc3_link_state state
);
1468 int dwc3_send_gadget_ep_cmd(struct dwc3_ep
*dep
, unsigned int cmd
,
1469 struct dwc3_gadget_ep_cmd_params
*params
);
1470 int dwc3_send_gadget_generic_command(struct dwc3
*dwc
, unsigned int cmd
,
1473 static inline int dwc3_gadget_init(struct dwc3
*dwc
)
1475 static inline void dwc3_gadget_exit(struct dwc3
*dwc
)
1477 static inline int dwc3_gadget_set_test_mode(struct dwc3
*dwc
, int mode
)
1479 static inline int dwc3_gadget_get_link_state(struct dwc3
*dwc
)
1481 static inline int dwc3_gadget_set_link_state(struct dwc3
*dwc
,
1482 enum dwc3_link_state state
)
1485 static inline int dwc3_send_gadget_ep_cmd(struct dwc3_ep
*dep
, unsigned int cmd
,
1486 struct dwc3_gadget_ep_cmd_params
*params
)
1488 static inline int dwc3_send_gadget_generic_command(struct dwc3
*dwc
,
1493 #if IS_ENABLED(CONFIG_USB_DWC3_DUAL_ROLE)
1494 int dwc3_drd_init(struct dwc3
*dwc
);
1495 void dwc3_drd_exit(struct dwc3
*dwc
);
1496 void dwc3_otg_init(struct dwc3
*dwc
);
1497 void dwc3_otg_exit(struct dwc3
*dwc
);
1498 void dwc3_otg_update(struct dwc3
*dwc
, bool ignore_idstatus
);
1499 void dwc3_otg_host_init(struct dwc3
*dwc
);
1501 static inline int dwc3_drd_init(struct dwc3
*dwc
)
1503 static inline void dwc3_drd_exit(struct dwc3
*dwc
)
1505 static inline void dwc3_otg_init(struct dwc3
*dwc
)
1507 static inline void dwc3_otg_exit(struct dwc3
*dwc
)
1509 static inline void dwc3_otg_update(struct dwc3
*dwc
, bool ignore_idstatus
)
1511 static inline void dwc3_otg_host_init(struct dwc3
*dwc
)
1515 /* power management interface */
1516 #if !IS_ENABLED(CONFIG_USB_DWC3_HOST)
1517 int dwc3_gadget_suspend(struct dwc3
*dwc
);
1518 int dwc3_gadget_resume(struct dwc3
*dwc
);
1519 void dwc3_gadget_process_pending_events(struct dwc3
*dwc
);
1521 static inline int dwc3_gadget_suspend(struct dwc3
*dwc
)
1526 static inline int dwc3_gadget_resume(struct dwc3
*dwc
)
1531 static inline void dwc3_gadget_process_pending_events(struct dwc3
*dwc
)
1534 #endif /* !IS_ENABLED(CONFIG_USB_DWC3_HOST) */
1536 #if IS_ENABLED(CONFIG_USB_DWC3_ULPI)
1537 int dwc3_ulpi_init(struct dwc3
*dwc
);
1538 void dwc3_ulpi_exit(struct dwc3
*dwc
);
1540 static inline int dwc3_ulpi_init(struct dwc3
*dwc
)
1542 static inline void dwc3_ulpi_exit(struct dwc3
*dwc
)
1546 #endif /* __DRIVERS_USB_DWC3_CORE_H */