drivers/usb/host/ehci-tegra.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * EHCI-compliant USB host controller driver for NVIDIA Tegra SoCs
   4  *
   5  * Copyright (C) 2010 Google, Inc.
   6  * Copyright (C) 2009 - 2013 NVIDIA Corporation
   7  */
   8
   9 #include <linux/clk.h>
  10 #include <linux/dma-mapping.h>
  11 #include <linux/err.h>
  12 #include <linux/gpio.h>
  13 #include <linux/io.h>
  14 #include <linux/irq.h>
  15 #include <linux/module.h>
  16 #include <linux/of.h>
  17 #include <linux/of_device.h>
  18 #include <linux/of_gpio.h>
  19 #include <linux/platform_device.h>
  20 #include <linux/pm_runtime.h>
  21 #include <linux/reset.h>
  22 #include <linux/slab.h>
  23 #include <linux/usb/ehci_def.h>
  24 #include <linux/usb/tegra_usb_phy.h>
  25 #include <linux/usb.h>
  26 #include <linux/usb/hcd.h>
  27 #include <linux/usb/otg.h>
  28
  29 #include "ehci.h"
  30
  31 #define PORT_WAKE_BITS (PORT_WKOC_E|PORT_WKDISC_E|PORT_WKCONN_E)
  32
  33 #define TEGRA_USB_DMA_ALIGN 32
  34
  35 #define DRIVER_DESC "Tegra EHCI driver"
  36 #define DRV_NAME "tegra-ehci"
  37
  38 static struct hc_driver __read_mostly tegra_ehci_hc_driver;
  39
  40 struct tegra_ehci_soc_config {
  41         bool has_hostpc;
  42 };
  43
  44 struct tegra_ehci_hcd {
  45         struct clk *clk;
  46         struct reset_control *rst;
  47         int port_resuming;
  48         bool needs_double_reset;
  49 };
  50
  51 static int tegra_reset_usb_controller(struct platform_device *pdev)
  52 {
  53         struct device_node *phy_np;
  54         struct usb_hcd *hcd = platform_get_drvdata(pdev);
  55         struct tegra_ehci_hcd *tegra =
  56                 (struct tegra_ehci_hcd *)hcd_to_ehci(hcd)->priv;
  57         struct reset_control *rst;
  58         int err;
  59
  60         phy_np = of_parse_phandle(pdev->dev.of_node, "nvidia,phy", 0);
  61         if (!phy_np)
  62                 return -ENOENT;
  63
  64         /*
  65          * The 1st USB controller contains some UTMI pad registers that are
  66          * global for all the controllers on the chip. Those registers are
  67          * also cleared when reset is asserted to the 1st controller.
  68          */
  69         rst = of_reset_control_get_shared(phy_np, "utmi-pads");
  70         if (IS_ERR(rst)) {
  71                 dev_warn(&pdev->dev,
  72                          "can't get utmi-pads reset from the PHY\n");
  73                 dev_warn(&pdev->dev,
  74                          "continuing, but please update your DT\n");
  75         } else {
  76                 /*
  77                  * PHY driver performs UTMI-pads reset in a case of
  78                  * non-legacy DT.
  79                  */
  80                 reset_control_put(rst);
  81         }
  82
  83         of_node_put(phy_np);
  84
  85         /* reset control is shared, hence initialize it first */
  86         err = reset_control_deassert(tegra->rst);
  87         if (err)
  88                 return err;
  89
  90         err = reset_control_assert(tegra->rst);
  91         if (err)
  92                 return err;
  93
  94         udelay(1);
  95
  96         err = reset_control_deassert(tegra->rst);
  97         if (err)
  98                 return err;
  99
 100         return 0;
 101 }
 102
 103 static int tegra_ehci_internal_port_reset(
 104         struct ehci_hcd *ehci,
 105         u32 __iomem     *portsc_reg
 106 )
 107 {
 108         u32             temp;
 109         unsigned long   flags;
 110         int             retval = 0;
 111         int             i, tries;
 112         u32             saved_usbintr;
 113
 114         spin_lock_irqsave(&ehci->lock, flags);
 115         saved_usbintr = ehci_readl(ehci, &ehci->regs->intr_enable);
 116         /* disable USB interrupt */
 117         ehci_writel(ehci, 0, &ehci->regs->intr_enable);
 118         spin_unlock_irqrestore(&ehci->lock, flags);
 119
 120         /*
 121          * Here we have to do Port Reset at most twice for
 122          * Port Enable bit to be set.
 123          */
 124         for (i = 0; i < 2; i++) {
 125                 temp = ehci_readl(ehci, portsc_reg);
 126                 temp |= PORT_RESET;
 127                 ehci_writel(ehci, temp, portsc_reg);
 128                 mdelay(10);
 129                 temp &= ~PORT_RESET;
 130                 ehci_writel(ehci, temp, portsc_reg);
 131                 mdelay(1);
 132                 tries = 100;
 133                 do {
 134                         mdelay(1);
 135                         /*
 136                          * Up to this point, Port Enable bit is
 137                          * expected to be set after 2 ms waiting.
 138                          * USB1 usually takes extra 45 ms, for safety,
 139                          * we take 100 ms as timeout.
 140                          */
 141                         temp = ehci_readl(ehci, portsc_reg);
 142                 } while (!(temp & PORT_PE) && tries--);
 143                 if (temp & PORT_PE)
 144                         break;
 145         }
 146         if (i == 2)
 147                 retval = -ETIMEDOUT;
 148
 149         /*
 150          * Clear Connect Status Change bit if it's set.
 151          * We can't clear PORT_PEC. It will also cause PORT_PE to be cleared.
 152          */
 153         if (temp & PORT_CSC)
 154                 ehci_writel(ehci, PORT_CSC, portsc_reg);
 155
 156         /*
 157          * Write to clear any interrupt status bits that might be set
 158          * during port reset.
 159          */
 160         temp = ehci_readl(ehci, &ehci->regs->status);
 161         ehci_writel(ehci, temp, &ehci->regs->status);
 162
 163         /* restore original interrupt enable bits */
 164         ehci_writel(ehci, saved_usbintr, &ehci->regs->intr_enable);
 165         return retval;
 166 }
 167
 168 static int tegra_ehci_hub_control(
 169         struct usb_hcd  *hcd,
 170         u16             typeReq,
 171         u16             wValue,
 172         u16             wIndex,
 173         char            *buf,
 174         u16             wLength
 175 )
 176 {
 177         struct ehci_hcd *ehci = hcd_to_ehci(hcd);
 178         struct tegra_ehci_hcd *tegra = (struct tegra_ehci_hcd *)ehci->priv;
 179         u32 __iomem     *status_reg;
 180         u32             temp;
 181         unsigned long   flags;
 182         int             retval = 0;
 183
 184         status_reg = &ehci->regs->port_status[(wIndex & 0xff) - 1];
 185
 186         spin_lock_irqsave(&ehci->lock, flags);
 187
 188         if (typeReq == GetPortStatus) {
 189                 temp = ehci_readl(ehci, status_reg);
 190                 if (tegra->port_resuming && !(temp & PORT_SUSPEND)) {
 191                         /* Resume completed, re-enable disconnect detection */
 192                         tegra->port_resuming = 0;
 193                         tegra_usb_phy_postresume(hcd->usb_phy);
 194                 }
 195         }
 196
 197         else if (typeReq == SetPortFeature && wValue == USB_PORT_FEAT_SUSPEND) {
 198                 temp = ehci_readl(ehci, status_reg);
 199                 if ((temp & PORT_PE) == 0 || (temp & PORT_RESET) != 0) {
 200                         retval = -EPIPE;
 201                         goto done;
 202                 }
 203
 204                 temp &= ~(PORT_RWC_BITS | PORT_WKCONN_E);
 205                 temp |= PORT_WKDISC_E | PORT_WKOC_E;
 206                 ehci_writel(ehci, temp | PORT_SUSPEND, status_reg);
 207
 208                 /*
 209                  * If a transaction is in progress, there may be a delay in
 210                  * suspending the port. Poll until the port is suspended.
 211                  */
 212                 if (ehci_handshake(ehci, status_reg, PORT_SUSPEND,
 213                                                 PORT_SUSPEND, 5000))
 214                         pr_err("%s: timeout waiting for SUSPEND\n", __func__);
 215
 216                 set_bit((wIndex & 0xff) - 1, &ehci->suspended_ports);
 217                 goto done;
 218         }
 219
 220         /* For USB1 port we need to issue Port Reset twice internally */
 221         if (tegra->needs_double_reset &&
 222            (typeReq == SetPortFeature && wValue == USB_PORT_FEAT_RESET)) {
 223                 spin_unlock_irqrestore(&ehci->lock, flags);
 224                 return tegra_ehci_internal_port_reset(ehci, status_reg);
 225         }
 226
 227         /*
 228          * Tegra host controller will time the resume operation to clear the bit
 229          * when the port control state switches to HS or FS Idle. This behavior
 230          * is different from EHCI where the host controller driver is required
 231          * to set this bit to a zero after the resume duration is timed in the
 232          * driver.
 233          */
 234         else if (typeReq == ClearPortFeature &&
 235                                         wValue == USB_PORT_FEAT_SUSPEND) {
 236                 temp = ehci_readl(ehci, status_reg);
 237                 if ((temp & PORT_RESET) || !(temp & PORT_PE)) {
 238                         retval = -EPIPE;
 239                         goto done;
 240                 }
 241
 242                 if (!(temp & PORT_SUSPEND))
 243                         goto done;
 244
 245                 /* Disable disconnect detection during port resume */
 246                 tegra_usb_phy_preresume(hcd->usb_phy);
 247
 248                 ehci->reset_done[wIndex-1] = jiffies + msecs_to_jiffies(25);
 249
 250                 temp &= ~(PORT_RWC_BITS | PORT_WAKE_BITS);
 251                 /* start resume signalling */
 252                 ehci_writel(ehci, temp | PORT_RESUME, status_reg);
 253                 set_bit(wIndex-1, &ehci->resuming_ports);
 254
 255                 spin_unlock_irqrestore(&ehci->lock, flags);
 256                 msleep(20);
 257                 spin_lock_irqsave(&ehci->lock, flags);
 258
 259                 /* Poll until the controller clears RESUME and SUSPEND */
 260                 if (ehci_handshake(ehci, status_reg, PORT_RESUME, 0, 2000))
 261                         pr_err("%s: timeout waiting for RESUME\n", __func__);
 262                 if (ehci_handshake(ehci, status_reg, PORT_SUSPEND, 0, 2000))
 263                         pr_err("%s: timeout waiting for SUSPEND\n", __func__);
 264
 265                 ehci->reset_done[wIndex-1] = 0;
 266                 clear_bit(wIndex-1, &ehci->resuming_ports);
 267
 268                 tegra->port_resuming = 1;
 269                 goto done;
 270         }
 271
 272         spin_unlock_irqrestore(&ehci->lock, flags);
 273
 274         /* Handle the hub control events here */
 275         return ehci_hub_control(hcd, typeReq, wValue, wIndex, buf, wLength);
 276
 277 done:
 278         spin_unlock_irqrestore(&ehci->lock, flags);
 279         return retval;
 280 }
 281
 282 struct dma_aligned_buffer {
 283         void *kmalloc_ptr;
 284         void *old_xfer_buffer;
 285         u8 data[];
 286 };
 287
 288 static void free_dma_aligned_buffer(struct urb *urb)
 289 {
 290         struct dma_aligned_buffer *temp;
 291         size_t length;
 292
 293         if (!(urb->transfer_flags & URB_ALIGNED_TEMP_BUFFER))
 294                 return;
 295
 296         temp = container_of(urb->transfer_buffer,
 297                 struct dma_aligned_buffer, data);
 298
 299         if (usb_urb_dir_in(urb)) {
 300                 if (usb_pipeisoc(urb->pipe))
 301                         length = urb->transfer_buffer_length;
 302                 else
 303                         length = urb->actual_length;
 304
 305                 memcpy(temp->old_xfer_buffer, temp->data, length);
 306         }
 307         urb->transfer_buffer = temp->old_xfer_buffer;
 308         kfree(temp->kmalloc_ptr);
 309
 310         urb->transfer_flags &= ~URB_ALIGNED_TEMP_BUFFER;
 311 }
 312
 313 static int alloc_dma_aligned_buffer(struct urb *urb, gfp_t mem_flags)
 314 {
 315         struct dma_aligned_buffer *temp, *kmalloc_ptr;
 316         size_t kmalloc_size;
 317
 318         if (urb->num_sgs || urb->sg ||
 319             urb->transfer_buffer_length == 0 ||
 320             !((uintptr_t)urb->transfer_buffer & (TEGRA_USB_DMA_ALIGN - 1)))
 321                 return 0;
 322
 323         /* Allocate a buffer with enough padding for alignment */
 324         kmalloc_size = urb->transfer_buffer_length +
 325                 sizeof(struct dma_aligned_buffer) + TEGRA_USB_DMA_ALIGN - 1;
 326
 327         kmalloc_ptr = kmalloc(kmalloc_size, mem_flags);
 328         if (!kmalloc_ptr)
 329                 return -ENOMEM;
 330
 331         /* Position our struct dma_aligned_buffer such that data is aligned */
 332         temp = PTR_ALIGN(kmalloc_ptr + 1, TEGRA_USB_DMA_ALIGN) - 1;
 333         temp->kmalloc_ptr = kmalloc_ptr;
 334         temp->old_xfer_buffer = urb->transfer_buffer;
 335         if (usb_urb_dir_out(urb))
 336                 memcpy(temp->data, urb->transfer_buffer,
 337                        urb->transfer_buffer_length);
 338         urb->transfer_buffer = temp->data;
 339
 340         urb->transfer_flags |= URB_ALIGNED_TEMP_BUFFER;
 341
 342         return 0;
 343 }
 344
 345 static int tegra_ehci_map_urb_for_dma(struct usb_hcd *hcd, struct urb *urb,
 346                                       gfp_t mem_flags)
 347 {
 348         int ret;
 349
 350         ret = alloc_dma_aligned_buffer(urb, mem_flags);
 351         if (ret)
 352                 return ret;
 353
 354         ret = usb_hcd_map_urb_for_dma(hcd, urb, mem_flags);
 355         if (ret)
 356                 free_dma_aligned_buffer(urb);
 357
 358         return ret;
 359 }
 360
 361 static void tegra_ehci_unmap_urb_for_dma(struct usb_hcd *hcd, struct urb *urb)
 362 {
 363         usb_hcd_unmap_urb_for_dma(hcd, urb);
 364         free_dma_aligned_buffer(urb);
 365 }
 366
 367 static const struct tegra_ehci_soc_config tegra30_soc_config = {
 368         .has_hostpc = true,
 369 };
 370
 371 static const struct tegra_ehci_soc_config tegra20_soc_config = {
 372         .has_hostpc = false,
 373 };
 374
 375 static const struct of_device_id tegra_ehci_of_match[] = {
 376         { .compatible = "nvidia,tegra30-ehci", .data = &tegra30_soc_config },
 377         { .compatible = "nvidia,tegra20-ehci", .data = &tegra20_soc_config },
 378         { },
 379 };
 380
 381 static int tegra_ehci_probe(struct platform_device *pdev)
 382 {
 383         const struct of_device_id *match;
 384         const struct tegra_ehci_soc_config *soc_config;
 385         struct resource *res;
 386         struct usb_hcd *hcd;
 387         struct ehci_hcd *ehci;
 388         struct tegra_ehci_hcd *tegra;
 389         int err = 0;
 390         int irq;
 391         struct usb_phy *u_phy;
 392
 393         match = of_match_device(tegra_ehci_of_match, &pdev->dev);
 394         if (!match) {
 395                 dev_err(&pdev->dev, "Error: No device match found\n");
 396                 return -ENODEV;
 397         }
 398         soc_config = match->data;
 399
 400         /* Right now device-tree probed devices don't get dma_mask set.
 401          * Since shared usb code relies on it, set it here for now.
 402          * Once we have dma capability bindings this can go away.
 403          */
 404         err = dma_coerce_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
 405         if (err)
 406                 return err;
 407
 408         hcd = usb_create_hcd(&tegra_ehci_hc_driver, &pdev->dev,
 409                                         dev_name(&pdev->dev));
 410         if (!hcd) {
 411                 dev_err(&pdev->dev, "Unable to create HCD\n");
 412                 return -ENOMEM;
 413         }
 414         platform_set_drvdata(pdev, hcd);
 415         ehci = hcd_to_ehci(hcd);
 416         tegra = (struct tegra_ehci_hcd *)ehci->priv;
 417
 418         hcd->has_tt = 1;
 419
 420         tegra->clk = devm_clk_get(&pdev->dev, NULL);
 421         if (IS_ERR(tegra->clk)) {
 422                 dev_err(&pdev->dev, "Can't get ehci clock\n");
 423                 err = PTR_ERR(tegra->clk);
 424                 goto cleanup_hcd_create;
 425         }
 426
 427         tegra->rst = devm_reset_control_get_shared(&pdev->dev, "usb");
 428         if (IS_ERR(tegra->rst)) {
 429                 dev_err(&pdev->dev, "Can't get ehci reset\n");
 430                 err = PTR_ERR(tegra->rst);
 431                 goto cleanup_hcd_create;
 432         }
 433
 434         err = clk_prepare_enable(tegra->clk);
 435         if (err)
 436                 goto cleanup_hcd_create;
 437
 438         err = tegra_reset_usb_controller(pdev);
 439         if (err) {
 440                 dev_err(&pdev->dev, "Failed to reset controller\n");
 441                 goto cleanup_clk_en;
 442         }
 443
 444         u_phy = devm_usb_get_phy_by_phandle(&pdev->dev, "nvidia,phy", 0);
 445         if (IS_ERR(u_phy)) {
 446                 err = -EPROBE_DEFER;
 447                 goto cleanup_clk_en;
 448         }
 449         hcd->usb_phy = u_phy;
 450         hcd->skip_phy_initialization = 1;
 451
 452         tegra->needs_double_reset = of_property_read_bool(pdev->dev.of_node,
 453                 "nvidia,needs-double-reset");
 454
 455         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 456         hcd->regs = devm_ioremap_resource(&pdev->dev, res);
 457         if (IS_ERR(hcd->regs)) {
 458                 err = PTR_ERR(hcd->regs);
 459                 goto cleanup_clk_en;
 460         }
 461         hcd->rsrc_start = res->start;
 462         hcd->rsrc_len = resource_size(res);
 463
 464         ehci->caps = hcd->regs + 0x100;
 465         ehci->has_hostpc = soc_config->has_hostpc;
 466
 467         err = usb_phy_init(hcd->usb_phy);
 468         if (err) {
 469                 dev_err(&pdev->dev, "Failed to initialize phy\n");
 470                 goto cleanup_clk_en;
 471         }
 472
 473         u_phy->otg = devm_kzalloc(&pdev->dev, sizeof(struct usb_otg),
 474                              GFP_KERNEL);
 475         if (!u_phy->otg) {
 476                 err = -ENOMEM;
 477                 goto cleanup_phy;
 478         }
 479         u_phy->otg->host = hcd_to_bus(hcd);
 480
 481         irq = platform_get_irq(pdev, 0);
 482         if (irq < 0) {
 483                 err = irq;
 484                 goto cleanup_phy;
 485         }
 486
 487         otg_set_host(u_phy->otg, &hcd->self);
 488
 489         err = usb_add_hcd(hcd, irq, IRQF_SHARED);
 490         if (err) {
 491                 dev_err(&pdev->dev, "Failed to add USB HCD\n");
 492                 goto cleanup_otg_set_host;
 493         }
 494         device_wakeup_enable(hcd->self.controller);
 495
 496         return err;
 497
 498 cleanup_otg_set_host:
 499         otg_set_host(u_phy->otg, NULL);
 500 cleanup_phy:
 501         usb_phy_shutdown(hcd->usb_phy);
 502 cleanup_clk_en:
 503         clk_disable_unprepare(tegra->clk);
 504 cleanup_hcd_create:
 505         usb_put_hcd(hcd);
 506         return err;
 507 }
 508
 509 static int tegra_ehci_remove(struct platform_device *pdev)
 510 {
 511         struct usb_hcd *hcd = platform_get_drvdata(pdev);
 512         struct tegra_ehci_hcd *tegra =
 513                 (struct tegra_ehci_hcd *)hcd_to_ehci(hcd)->priv;
 514
 515         usb_remove_hcd(hcd);
 516         otg_set_host(hcd->usb_phy->otg, NULL);
 517         usb_phy_shutdown(hcd->usb_phy);
 518         clk_disable_unprepare(tegra->clk);
 519         usb_put_hcd(hcd);
 520
 521         return 0;
 522 }
 523
 524 static void tegra_ehci_hcd_shutdown(struct platform_device *pdev)
 525 {
 526         struct usb_hcd *hcd = platform_get_drvdata(pdev);
 527
 528         if (hcd->driver->shutdown)
 529                 hcd->driver->shutdown(hcd);
 530 }
 531
 532 static struct platform_driver tegra_ehci_driver = {
 533         .probe          = tegra_ehci_probe,
 534         .remove         = tegra_ehci_remove,
 535         .shutdown       = tegra_ehci_hcd_shutdown,
 536         .driver         = {
 537                 .name   = DRV_NAME,
 538                 .of_match_table = tegra_ehci_of_match,
 539         }
 540 };
 541
 542 static int tegra_ehci_reset(struct usb_hcd *hcd)
 543 {
 544         struct ehci_hcd *ehci = hcd_to_ehci(hcd);
 545         int retval;
 546         int txfifothresh;
 547
 548         retval = ehci_setup(hcd);
 549         if (retval)
 550                 return retval;
 551
 552         /*
 553          * We should really pull this value out of tegra_ehci_soc_config, but
 554          * to avoid needing access to it, make use of the fact that Tegra20 is
 555          * the only one so far that needs a value of 10, and Tegra20 is the
 556          * only one which doesn't set has_hostpc.
 557          */
 558         txfifothresh = ehci->has_hostpc ? 0x10 : 10;
 559         ehci_writel(ehci, txfifothresh << 16, &ehci->regs->txfill_tuning);
 560
 561         return 0;
 562 }
 563
 564 static const struct ehci_driver_overrides tegra_overrides __initconst = {
 565         .extra_priv_size        = sizeof(struct tegra_ehci_hcd),
 566         .reset                  = tegra_ehci_reset,
 567 };
 568
 569 static int __init ehci_tegra_init(void)
 570 {
 571         if (usb_disabled())
 572                 return -ENODEV;
 573
 574         pr_info(DRV_NAME ": " DRIVER_DESC "\n");
 575
 576         ehci_init_driver(&tegra_ehci_hc_driver, &tegra_overrides);
 577
 578         /*
 579          * The Tegra HW has some unusual quirks, which require Tegra-specific
 580          * workarounds. We override certain hc_driver functions here to
 581          * achieve that. We explicitly do not enhance ehci_driver_overrides to
 582          * allow this more easily, since this is an unusual case, and we don't
 583          * want to encourage others to override these functions by making it
 584          * too easy.
 585          */
 586
 587         tegra_ehci_hc_driver.map_urb_for_dma = tegra_ehci_map_urb_for_dma;
 588         tegra_ehci_hc_driver.unmap_urb_for_dma = tegra_ehci_unmap_urb_for_dma;
 589         tegra_ehci_hc_driver.hub_control = tegra_ehci_hub_control;
 590
 591         return platform_driver_register(&tegra_ehci_driver);
 592 }
 593 module_init(ehci_tegra_init);
 594
 595 static void __exit ehci_tegra_cleanup(void)
 596 {
 597         platform_driver_unregister(&tegra_ehci_driver);
 598 }
 599 module_exit(ehci_tegra_cleanup);
 600
 601 MODULE_DESCRIPTION(DRIVER_DESC);
 602 MODULE_LICENSE("GPL");
 603 MODULE_ALIAS("platform:" DRV_NAME);
 604 MODULE_DEVICE_TABLE(of, tegra_ehci_of_match);