drivers/usb/host/ehci.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright (c) 2001-2002 by David Brownell
   4  */
   5
   6 #ifndef __LINUX_EHCI_HCD_H
   7 #define __LINUX_EHCI_HCD_H
   8
   9 /* definitions used for the EHCI driver */
  10
  11 /*
  12  * __hc32 and __hc16 are "Host Controller" types, they may be equivalent to
  13  * __leXX (normally) or __beXX (given EHCI_BIG_ENDIAN_DESC), depending on
  14  * the host controller implementation.
  15  *
  16  * To facilitate the strongest possible byte-order checking from "sparse"
  17  * and so on, we use __leXX unless that's not practical.
  18  */
  19 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_DESC
  20 typedef __u32 __bitwise __hc32;
  21 typedef __u16 __bitwise __hc16;
  22 #else
  23 #define __hc32  __le32
  24 #define __hc16  __le16
  25 #endif
  26
  27 /* statistics can be kept for tuning/monitoring */
  28 #ifdef CONFIG_DYNAMIC_DEBUG
  29 #define EHCI_STATS
  30 #endif
  31
  32 struct ehci_stats {
  33         /* irq usage */
  34         unsigned long           normal;
  35         unsigned long           error;
  36         unsigned long           iaa;
  37         unsigned long           lost_iaa;
  38
  39         /* termination of urbs from core */
  40         unsigned long           complete;
  41         unsigned long           unlink;
  42 };
  43
  44 /*
  45  * Scheduling and budgeting information for periodic transfers, for both
  46  * high-speed devices and full/low-speed devices lying behind a TT.
  47  */
  48 struct ehci_per_sched {
  49         struct usb_device       *udev;          /* access to the TT */
  50         struct usb_host_endpoint *ep;
  51         struct list_head        ps_list;        /* node on ehci_tt's ps_list */
  52         u16                     tt_usecs;       /* time on the FS/LS bus */
  53         u16                     cs_mask;        /* C-mask and S-mask bytes */
  54         u16                     period;         /* actual period in frames */
  55         u16                     phase;          /* actual phase, frame part */
  56         u8                      bw_phase;       /* same, for bandwidth
  57                                                    reservation */
  58         u8                      phase_uf;       /* uframe part of the phase */
  59         u8                      usecs, c_usecs; /* times on the HS bus */
  60         u8                      bw_uperiod;     /* period in microframes, for
  61                                                    bandwidth reservation */
  62         u8                      bw_period;      /* same, in frames */
  63 };
  64 #define NO_FRAME        29999                   /* frame not assigned yet */
  65
  66 /* ehci_hcd->lock guards shared data against other CPUs:
  67  *   ehci_hcd:  async, unlink, periodic (and shadow), ...
  68  *   usb_host_endpoint: hcpriv
  69  *   ehci_qh:   qh_next, qtd_list
  70  *   ehci_qtd:  qtd_list
  71  *
  72  * Also, hold this lock when talking to HC registers or
  73  * when updating hw_* fields in shared qh/qtd/... structures.
  74  */
  75
  76 #define EHCI_MAX_ROOT_PORTS     15              /* see HCS_N_PORTS */
  77
  78 /*
  79  * ehci_rh_state values of EHCI_RH_RUNNING or above mean that the
  80  * controller may be doing DMA.  Lower values mean there's no DMA.
  81  */
  82 enum ehci_rh_state {
  83         EHCI_RH_HALTED,
  84         EHCI_RH_SUSPENDED,
  85         EHCI_RH_RUNNING,
  86         EHCI_RH_STOPPING
  87 };
  88
  89 /*
  90  * Timer events, ordered by increasing delay length.
  91  * Always update event_delays_ns[] and event_handlers[] (defined in
  92  * ehci-timer.c) in parallel with this list.
  93  */
  94 enum ehci_hrtimer_event {
  95         EHCI_HRTIMER_POLL_ASS,          /* Poll for async schedule off */
  96         EHCI_HRTIMER_POLL_PSS,          /* Poll for periodic schedule off */
  97         EHCI_HRTIMER_POLL_DEAD,         /* Wait for dead controller to stop */
  98         EHCI_HRTIMER_UNLINK_INTR,       /* Wait for interrupt QH unlink */
  99         EHCI_HRTIMER_FREE_ITDS,         /* Wait for unused iTDs and siTDs */
 100         EHCI_HRTIMER_ACTIVE_UNLINK,     /* Wait while unlinking an active QH */
 101         EHCI_HRTIMER_START_UNLINK_INTR, /* Unlink empty interrupt QHs */
 102         EHCI_HRTIMER_ASYNC_UNLINKS,     /* Unlink empty async QHs */
 103         EHCI_HRTIMER_IAA_WATCHDOG,      /* Handle lost IAA interrupts */
 104         EHCI_HRTIMER_DISABLE_PERIODIC,  /* Wait to disable periodic sched */
 105         EHCI_HRTIMER_DISABLE_ASYNC,     /* Wait to disable async sched */
 106         EHCI_HRTIMER_IO_WATCHDOG,       /* Check for missing IRQs */
 107         EHCI_HRTIMER_NUM_EVENTS         /* Must come last */
 108 };
 109 #define EHCI_HRTIMER_NO_EVENT   99
 110
 111 struct ehci_hcd {                       /* one per controller */
 112         /* timing support */
 113         enum ehci_hrtimer_event next_hrtimer_event;
 114         unsigned                enabled_hrtimer_events;
 115         ktime_t                 hr_timeouts[EHCI_HRTIMER_NUM_EVENTS];
 116         struct hrtimer          hrtimer;
 117
 118         int                     PSS_poll_count;
 119         int                     ASS_poll_count;
 120         int                     died_poll_count;
 121
 122         /* glue to PCI and HCD framework */
 123         struct ehci_caps __iomem *caps;
 124         struct ehci_regs __iomem *regs;
 125         struct ehci_dbg_port __iomem *debug;
 126
 127         __u32                   hcs_params;     /* cached register copy */
 128         spinlock_t              lock;
 129         enum ehci_rh_state      rh_state;
 130
 131         /* general schedule support */
 132         bool                    scanning:1;
 133         bool                    need_rescan:1;
 134         bool                    intr_unlinking:1;
 135         bool                    iaa_in_progress:1;
 136         bool                    async_unlinking:1;
 137         bool                    shutdown:1;
 138         struct ehci_qh          *qh_scan_next;
 139
 140         /* async schedule support */
 141         struct ehci_qh          *async;
 142         struct ehci_qh          *dummy;         /* For AMD quirk use */
 143         struct list_head        async_unlink;
 144         struct list_head        async_idle;
 145         unsigned                async_unlink_cycle;
 146         unsigned                async_count;    /* async activity count */
 147         __hc32                  old_current;    /* Test for QH becoming */
 148         __hc32                  old_token;      /*  inactive during unlink */
 149
 150         /* periodic schedule support */
 151 #define DEFAULT_I_TDPS          1024            /* some HCs can do less */
 152         unsigned                periodic_size;
 153         __hc32                  *periodic;      /* hw periodic table */
 154         dma_addr_t              periodic_dma;
 155         struct list_head        intr_qh_list;
 156         unsigned                i_thresh;       /* uframes HC might cache */
 157
 158         union ehci_shadow       *pshadow;       /* mirror hw periodic table */
 159         struct list_head        intr_unlink_wait;
 160         struct list_head        intr_unlink;
 161         unsigned                intr_unlink_wait_cycle;
 162         unsigned                intr_unlink_cycle;
 163         unsigned                now_frame;      /* frame from HC hardware */
 164         unsigned                last_iso_frame; /* last frame scanned for iso */
 165         unsigned                intr_count;     /* intr activity count */
 166         unsigned                isoc_count;     /* isoc activity count */
 167         unsigned                periodic_count; /* periodic activity count */
 168         unsigned                uframe_periodic_max; /* max periodic time per uframe */
 169
 170
 171         /* list of itds & sitds completed while now_frame was still active */
 172         struct list_head        cached_itd_list;
 173         struct ehci_itd         *last_itd_to_free;
 174         struct list_head        cached_sitd_list;
 175         struct ehci_sitd        *last_sitd_to_free;
 176
 177         /* per root hub port */
 178         unsigned long           reset_done[EHCI_MAX_ROOT_PORTS];
 179
 180         /* bit vectors (one bit per port) */
 181         unsigned long           bus_suspended;          /* which ports were
 182                         already suspended at the start of a bus suspend */
 183         unsigned long           companion_ports;        /* which ports are
 184                         dedicated to the companion controller */
 185         unsigned long           owned_ports;            /* which ports are
 186                         owned by the companion during a bus suspend */
 187         unsigned long           port_c_suspend;         /* which ports have
 188                         the change-suspend feature turned on */
 189         unsigned long           suspended_ports;        /* which ports are
 190                         suspended */
 191         unsigned long           resuming_ports;         /* which ports have
 192                         started to resume */
 193
 194         /* per-HC memory pools (could be per-bus, but ...) */
 195         struct dma_pool         *qh_pool;       /* qh per active urb */
 196         struct dma_pool         *qtd_pool;      /* one or more per qh */
 197         struct dma_pool         *itd_pool;      /* itd per iso urb */
 198         struct dma_pool         *sitd_pool;     /* sitd per split iso urb */
 199
 200         unsigned                random_frame;
 201         unsigned long           next_statechange;
 202         ktime_t                 last_periodic_enable;
 203         u32                     command;
 204
 205         /* SILICON QUIRKS */
 206         unsigned                no_selective_suspend:1;
 207         unsigned                has_fsl_port_bug:1; /* FreeScale */
 208         unsigned                has_fsl_hs_errata:1;    /* Freescale HS quirk */
 209         unsigned                has_fsl_susp_errata:1;  /* NXP SUSP quirk */
 210         unsigned                big_endian_mmio:1;
 211         unsigned                big_endian_desc:1;
 212         unsigned                big_endian_capbase:1;
 213         unsigned                has_amcc_usb23:1;
 214         unsigned                need_io_watchdog:1;
 215         unsigned                amd_pll_fix:1;
 216         unsigned                use_dummy_qh:1; /* AMD Frame List table quirk*/
 217         unsigned                has_synopsys_hc_bug:1; /* Synopsys HC */
 218         unsigned                frame_index_bug:1; /* MosChip (AKA NetMos) */
 219         unsigned                need_oc_pp_cycle:1; /* MPC834X port power */
 220         unsigned                imx28_write_fix:1; /* For Freescale i.MX28 */
 221
 222         /* required for usb32 quirk */
 223         #define OHCI_CTRL_HCFS          (3 << 6)
 224         #define OHCI_USB_OPER           (2 << 6)
 225         #define OHCI_USB_SUSPEND        (3 << 6)
 226
 227         #define OHCI_HCCTRL_OFFSET      0x4
 228         #define OHCI_HCCTRL_LEN         0x4
 229         __hc32                  *ohci_hcctrl_reg;
 230         unsigned                has_hostpc:1;
 231         unsigned                has_tdi_phy_lpm:1;
 232         unsigned                has_ppcd:1; /* support per-port change bits */
 233         u8                      sbrn;           /* packed release number */
 234
 235         /* irq statistics */
 236 #ifdef EHCI_STATS
 237         struct ehci_stats       stats;
 238 #       define INCR(x) ((x)++)
 239 #else
 240 #       define INCR(x) do {} while (0)
 241 #endif
 242
 243         /* debug files */
 244 #ifdef CONFIG_DYNAMIC_DEBUG
 245         struct dentry           *debug_dir;
 246 #endif
 247
 248         /* bandwidth usage */
 249 #define EHCI_BANDWIDTH_SIZE     64
 250 #define EHCI_BANDWIDTH_FRAMES   (EHCI_BANDWIDTH_SIZE >> 3)
 251         u8                      bandwidth[EHCI_BANDWIDTH_SIZE];
 252                                                 /* us allocated per uframe */
 253         u8                      tt_budget[EHCI_BANDWIDTH_SIZE];
 254                                                 /* us budgeted per uframe */
 255         struct list_head        tt_list;
 256
 257         /* platform-specific data -- must come last */
 258         unsigned long           priv[] __aligned(sizeof(s64));
 259 };
 260
 261 /* convert between an HCD pointer and the corresponding EHCI_HCD */
 262 static inline struct ehci_hcd *hcd_to_ehci(struct usb_hcd *hcd)
 263 {
 264         return (struct ehci_hcd *) (hcd->hcd_priv);
 265 }
 266 static inline struct usb_hcd *ehci_to_hcd(struct ehci_hcd *ehci)
 267 {
 268         return container_of((void *) ehci, struct usb_hcd, hcd_priv);
 269 }
 270
 271 /*-------------------------------------------------------------------------*/
 272
 273 #include <linux/usb/ehci_def.h>
 274
 275 /*-------------------------------------------------------------------------*/
 276
 277 #define QTD_NEXT(ehci, dma)     cpu_to_hc32(ehci, (u32)dma)
 278
 279 /*
 280  * EHCI Specification 0.95 Section 3.5
 281  * QTD: describe data transfer components (buffer, direction, ...)
 282  * See Fig 3-6 "Queue Element Transfer Descriptor Block Diagram".
 283  *
 284  * These are associated only with "QH" (Queue Head) structures,
 285  * used with control, bulk, and interrupt transfers.
 286  */
 287 struct ehci_qtd {
 288         /* first part defined by EHCI spec */
 289         __hc32                  hw_next;        /* see EHCI 3.5.1 */
 290         __hc32                  hw_alt_next;    /* see EHCI 3.5.2 */
 291         __hc32                  hw_token;       /* see EHCI 3.5.3 */
 292 #define QTD_TOGGLE      (1 << 31)       /* data toggle */
 293 #define QTD_LENGTH(tok) (((tok)>>16) & 0x7fff)
 294 #define QTD_IOC         (1 << 15)       /* interrupt on complete */
 295 #define QTD_CERR(tok)   (((tok)>>10) & 0x3)
 296 #define QTD_PID(tok)    (((tok)>>8) & 0x3)
 297 #define QTD_STS_ACTIVE  (1 << 7)        /* HC may execute this */
 298 #define QTD_STS_HALT    (1 << 6)        /* halted on error */
 299 #define QTD_STS_DBE     (1 << 5)        /* data buffer error (in HC) */
 300 #define QTD_STS_BABBLE  (1 << 4)        /* device was babbling (qtd halted) */
 301 #define QTD_STS_XACT    (1 << 3)        /* device gave illegal response */
 302 #define QTD_STS_MMF     (1 << 2)        /* incomplete split transaction */
 303 #define QTD_STS_STS     (1 << 1)        /* split transaction state */
 304 #define QTD_STS_PING    (1 << 0)        /* issue PING? */
 305
 306 #define ACTIVE_BIT(ehci)        cpu_to_hc32(ehci, QTD_STS_ACTIVE)
 307 #define HALT_BIT(ehci)          cpu_to_hc32(ehci, QTD_STS_HALT)
 308 #define STATUS_BIT(ehci)        cpu_to_hc32(ehci, QTD_STS_STS)
 309
 310         __hc32                  hw_buf[5];        /* see EHCI 3.5.4 */
 311         __hc32                  hw_buf_hi[5];        /* Appendix B */
 312
 313         /* the rest is HCD-private */
 314         dma_addr_t              qtd_dma;                /* qtd address */
 315         struct list_head        qtd_list;               /* sw qtd list */
 316         struct urb              *urb;                   /* qtd's urb */
 317         size_t                  length;                 /* length of buffer */
 318 } __aligned(32);
 319
 320 /* mask NakCnt+T in qh->hw_alt_next */
 321 #define QTD_MASK(ehci)  cpu_to_hc32(ehci, ~0x1f)
 322
 323 #define IS_SHORT_READ(token) (QTD_LENGTH(token) != 0 && QTD_PID(token) == 1)
 324
 325 /*-------------------------------------------------------------------------*/
 326
 327 /* type tag from {qh,itd,sitd,fstn}->hw_next */
 328 #define Q_NEXT_TYPE(ehci, dma)  ((dma) & cpu_to_hc32(ehci, 3 << 1))
 329
 330 /*
 331  * Now the following defines are not converted using the
 332  * cpu_to_le32() macro anymore, since we have to support
 333  * "dynamic" switching between be and le support, so that the driver
 334  * can be used on one system with SoC EHCI controller using big-endian
 335  * descriptors as well as a normal little-endian PCI EHCI controller.
 336  */
 337 /* values for that type tag */
 338 #define Q_TYPE_ITD      (0 << 1)
 339 #define Q_TYPE_QH       (1 << 1)
 340 #define Q_TYPE_SITD     (2 << 1)
 341 #define Q_TYPE_FSTN     (3 << 1)
 342
 343 /* next async queue entry, or pointer to interrupt/periodic QH */
 344 #define QH_NEXT(ehci, dma) \
 345                 (cpu_to_hc32(ehci, (((u32) dma) & ~0x01f) | Q_TYPE_QH))
 346
 347 /* for periodic/async schedules and qtd lists, mark end of list */
 348 #define EHCI_LIST_END(ehci)     cpu_to_hc32(ehci, 1) /* "null pointer" to hw */
 349
 350 /*
 351  * Entries in periodic shadow table are pointers to one of four kinds
 352  * of data structure.  That's dictated by the hardware; a type tag is
 353  * encoded in the low bits of the hardware's periodic schedule.  Use
 354  * Q_NEXT_TYPE to get the tag.
 355  *
 356  * For entries in the async schedule, the type tag always says "qh".
 357  */
 358 union ehci_shadow {
 359         struct ehci_qh          *qh;            /* Q_TYPE_QH */
 360         struct ehci_itd         *itd;           /* Q_TYPE_ITD */
 361         struct ehci_sitd        *sitd;          /* Q_TYPE_SITD */
 362         struct ehci_fstn        *fstn;          /* Q_TYPE_FSTN */
 363         __hc32                  *hw_next;       /* (all types) */
 364         void                    *ptr;
 365 };
 366
 367 /*-------------------------------------------------------------------------*/
 368
 369 /*
 370  * EHCI Specification 0.95 Section 3.6
 371  * QH: describes control/bulk/interrupt endpoints
 372  * See Fig 3-7 "Queue Head Structure Layout".
 373  *
 374  * These appear in both the async and (for interrupt) periodic schedules.
 375  */
 376
 377 /* first part defined by EHCI spec */
 378 struct ehci_qh_hw {
 379         __hc32                  hw_next;        /* see EHCI 3.6.1 */
 380         __hc32                  hw_info1;       /* see EHCI 3.6.2 */
 381 #define QH_CONTROL_EP   (1 << 27)       /* FS/LS control endpoint */
 382 #define QH_HEAD         (1 << 15)       /* Head of async reclamation list */
 383 #define QH_TOGGLE_CTL   (1 << 14)       /* Data toggle control */
 384 #define QH_HIGH_SPEED   (2 << 12)       /* Endpoint speed */
 385 #define QH_LOW_SPEED    (1 << 12)
 386 #define QH_FULL_SPEED   (0 << 12)
 387 #define QH_INACTIVATE   (1 << 7)        /* Inactivate on next transaction */
 388         __hc32                  hw_info2;        /* see EHCI 3.6.2 */
 389 #define QH_SMASK        0x000000ff
 390 #define QH_CMASK        0x0000ff00
 391 #define QH_HUBADDR      0x007f0000
 392 #define QH_HUBPORT      0x3f800000
 393 #define QH_MULT         0xc0000000
 394         __hc32                  hw_current;     /* qtd list - see EHCI 3.6.4 */
 395
 396         /* qtd overlay (hardware parts of a struct ehci_qtd) */
 397         __hc32                  hw_qtd_next;
 398         __hc32                  hw_alt_next;
 399         __hc32                  hw_token;
 400         __hc32                  hw_buf[5];
 401         __hc32                  hw_buf_hi[5];
 402 } __aligned(32);
 403
 404 struct ehci_qh {
 405         struct ehci_qh_hw       *hw;            /* Must come first */
 406         /* the rest is HCD-private */
 407         dma_addr_t              qh_dma;         /* address of qh */
 408         union ehci_shadow       qh_next;        /* ptr to qh; or periodic */
 409         struct list_head        qtd_list;       /* sw qtd list */
 410         struct list_head        intr_node;      /* list of intr QHs */
 411         struct ehci_qtd         *dummy;
 412         struct list_head        unlink_node;
 413         struct ehci_per_sched   ps;             /* scheduling info */
 414
 415         unsigned                unlink_cycle;
 416
 417         u8                      qh_state;
 418 #define QH_STATE_LINKED         1               /* HC sees this */
 419 #define QH_STATE_UNLINK         2               /* HC may still see this */
 420 #define QH_STATE_IDLE           3               /* HC doesn't see this */
 421 #define QH_STATE_UNLINK_WAIT    4               /* LINKED and on unlink q */
 422 #define QH_STATE_COMPLETING     5               /* don't touch token.HALT */
 423
 424         u8                      xacterrs;       /* XactErr retry counter */
 425 #define QH_XACTERR_MAX          32              /* XactErr retry limit */
 426
 427         u8                      unlink_reason;
 428 #define QH_UNLINK_HALTED        0x01            /* Halt flag is set */
 429 #define QH_UNLINK_SHORT_READ    0x02            /* Recover from a short read */
 430 #define QH_UNLINK_DUMMY_OVERLAY 0x04            /* QH overlayed the dummy TD */
 431 #define QH_UNLINK_SHUTDOWN      0x08            /* The HC isn't running */
 432 #define QH_UNLINK_QUEUE_EMPTY   0x10            /* Reached end of the queue */
 433 #define QH_UNLINK_REQUESTED     0x20            /* Disable, reset, or dequeue */
 434
 435         u8                      gap_uf;         /* uframes split/csplit gap */
 436
 437         unsigned                is_out:1;       /* bulk or intr OUT */
 438         unsigned                clearing_tt:1;  /* Clear-TT-Buf in progress */
 439         unsigned                dequeue_during_giveback:1;
 440         unsigned                should_be_inactive:1;
 441 };
 442
 443 /*-------------------------------------------------------------------------*/
 444
 445 /* description of one iso transaction (up to 3 KB data if highspeed) */
 446 struct ehci_iso_packet {
 447         /* These will be copied to iTD when scheduling */
 448         u64                     bufp;           /* itd->hw_bufp{,_hi}[pg] |= */
 449         __hc32                  transaction;    /* itd->hw_transaction[i] |= */
 450         u8                      cross;          /* buf crosses pages */
 451         /* for full speed OUT splits */
 452         u32                     buf1;
 453 };
 454
 455 /* temporary schedule data for packets from iso urbs (both speeds)
 456  * each packet is one logical usb transaction to the device (not TT),
 457  * beginning at stream->next_uframe
 458  */
 459 struct ehci_iso_sched {
 460         struct list_head        td_list;
 461         unsigned                span;
 462         unsigned                first_packet;
 463         struct ehci_iso_packet  packet[];
 464 };
 465
 466 /*
 467  * ehci_iso_stream - groups all (s)itds for this endpoint.
 468  * acts like a qh would, if EHCI had them for ISO.
 469  */
 470 struct ehci_iso_stream {
 471         /* first field matches ehci_hq, but is NULL */
 472         struct ehci_qh_hw       *hw;
 473
 474         u8                      bEndpointAddress;
 475         u8                      highspeed;
 476         struct list_head        td_list;        /* queued itds/sitds */
 477         struct list_head        free_list;      /* list of unused itds/sitds */
 478
 479         /* output of (re)scheduling */
 480         struct ehci_per_sched   ps;             /* scheduling info */
 481         unsigned                next_uframe;
 482         __hc32                  splits;
 483
 484         /* the rest is derived from the endpoint descriptor,
 485          * including the extra info for hw_bufp[0..2]
 486          */
 487         u16                     uperiod;        /* period in uframes */
 488         u16                     maxp;
 489         unsigned                bandwidth;
 490
 491         /* This is used to initialize iTD's hw_bufp fields */
 492         __hc32                  buf0;
 493         __hc32                  buf1;
 494         __hc32                  buf2;
 495
 496         /* this is used to initialize sITD's tt info */
 497         __hc32                  address;
 498 };
 499
 500 /*-------------------------------------------------------------------------*/
 501
 502 /*
 503  * EHCI Specification 0.95 Section 3.3
 504  * Fig 3-4 "Isochronous Transaction Descriptor (iTD)"
 505  *
 506  * Schedule records for high speed iso xfers
 507  */
 508 struct ehci_itd {
 509         /* first part defined by EHCI spec */
 510         __hc32                  hw_next;           /* see EHCI 3.3.1 */
 511         __hc32                  hw_transaction[8]; /* see EHCI 3.3.2 */
 512 #define EHCI_ISOC_ACTIVE        (1<<31)        /* activate transfer this slot */
 513 #define EHCI_ISOC_BUF_ERR       (1<<30)        /* Data buffer error */
 514 #define EHCI_ISOC_BABBLE        (1<<29)        /* babble detected */
 515 #define EHCI_ISOC_XACTERR       (1<<28)        /* XactErr - transaction error */
 516 #define EHCI_ITD_LENGTH(tok)    (((tok)>>16) & 0x0fff)
 517 #define EHCI_ITD_IOC            (1 << 15)       /* interrupt on complete */
 518
 519 #define ITD_ACTIVE(ehci)        cpu_to_hc32(ehci, EHCI_ISOC_ACTIVE)
 520
 521         __hc32                  hw_bufp[7];     /* see EHCI 3.3.3 */
 522         __hc32                  hw_bufp_hi[7];  /* Appendix B */
 523
 524         /* the rest is HCD-private */
 525         dma_addr_t              itd_dma;        /* for this itd */
 526         union ehci_shadow       itd_next;       /* ptr to periodic q entry */
 527
 528         struct urb              *urb;
 529         struct ehci_iso_stream  *stream;        /* endpoint's queue */
 530         struct list_head        itd_list;       /* list of stream's itds */
 531
 532         /* any/all hw_transactions here may be used by that urb */
 533         unsigned                frame;          /* where scheduled */
 534         unsigned                pg;
 535         unsigned                index[8];       /* in urb->iso_frame_desc */
 536 } __aligned(32);
 537
 538 /*-------------------------------------------------------------------------*/
 539
 540 /*
 541  * EHCI Specification 0.95 Section 3.4
 542  * siTD, aka split-transaction isochronous Transfer Descriptor
 543  *       ... describe full speed iso xfers through TT in hubs
 544  * see Figure 3-5 "Split-transaction Isochronous Transaction Descriptor (siTD)
 545  */
 546 struct ehci_sitd {
 547         /* first part defined by EHCI spec */
 548         __hc32                  hw_next;
 549 /* uses bit field macros above - see EHCI 0.95 Table 3-8 */
 550         __hc32                  hw_fullspeed_ep;        /* EHCI table 3-9 */
 551         __hc32                  hw_uframe;              /* EHCI table 3-10 */
 552         __hc32                  hw_results;             /* EHCI table 3-11 */
 553 #define SITD_IOC        (1 << 31)       /* interrupt on completion */
 554 #define SITD_PAGE       (1 << 30)       /* buffer 0/1 */
 555 #define SITD_LENGTH(x)  (((x) >> 16) & 0x3ff)
 556 #define SITD_STS_ACTIVE (1 << 7)        /* HC may execute this */
 557 #define SITD_STS_ERR    (1 << 6)        /* error from TT */
 558 #define SITD_STS_DBE    (1 << 5)        /* data buffer error (in HC) */
 559 #define SITD_STS_BABBLE (1 << 4)        /* device was babbling */
 560 #define SITD_STS_XACT   (1 << 3)        /* illegal IN response */
 561 #define SITD_STS_MMF    (1 << 2)        /* incomplete split transaction */
 562 #define SITD_STS_STS    (1 << 1)        /* split transaction state */
 563
 564 #define SITD_ACTIVE(ehci)       cpu_to_hc32(ehci, SITD_STS_ACTIVE)
 565
 566         __hc32                  hw_buf[2];              /* EHCI table 3-12 */
 567         __hc32                  hw_backpointer;         /* EHCI table 3-13 */
 568         __hc32                  hw_buf_hi[2];           /* Appendix B */
 569
 570         /* the rest is HCD-private */
 571         dma_addr_t              sitd_dma;
 572         union ehci_shadow       sitd_next;      /* ptr to periodic q entry */
 573
 574         struct urb              *urb;
 575         struct ehci_iso_stream  *stream;        /* endpoint's queue */
 576         struct list_head        sitd_list;      /* list of stream's sitds */
 577         unsigned                frame;
 578         unsigned                index;
 579 } __aligned(32);
 580
 581 /*-------------------------------------------------------------------------*/
 582
 583 /*
 584  * EHCI Specification 0.96 Section 3.7
 585  * Periodic Frame Span Traversal Node (FSTN)
 586  *
 587  * Manages split interrupt transactions (using TT) that span frame boundaries
 588  * into uframes 0/1; see 4.12.2.2.  In those uframes, a "save place" FSTN
 589  * makes the HC jump (back) to a QH to scan for fs/ls QH completions until
 590  * it hits a "restore" FSTN; then it returns to finish other uframe 0/1 work.
 591  */
 592 struct ehci_fstn {
 593         __hc32                  hw_next;        /* any periodic q entry */
 594         __hc32                  hw_prev;        /* qh or EHCI_LIST_END */
 595
 596         /* the rest is HCD-private */
 597         dma_addr_t              fstn_dma;
 598         union ehci_shadow       fstn_next;      /* ptr to periodic q entry */
 599 } __aligned(32);
 600
 601 /*-------------------------------------------------------------------------*/
 602
 603 /*
 604  * USB-2.0 Specification Sections 11.14 and 11.18
 605  * Scheduling and budgeting split transactions using TTs
 606  *
 607  * A hub can have a single TT for all its ports, or multiple TTs (one for each
 608  * port).  The bandwidth and budgeting information for the full/low-speed bus
 609  * below each TT is self-contained and independent of the other TTs or the
 610  * high-speed bus.
 611  *
 612  * "Bandwidth" refers to the number of microseconds on the FS/LS bus allocated
 613  * to an interrupt or isochronous endpoint for each frame.  "Budget" refers to
 614  * the best-case estimate of the number of full-speed bytes allocated to an
 615  * endpoint for each microframe within an allocated frame.
 616  *
 617  * Removal of an endpoint invalidates a TT's budget.  Instead of trying to
 618  * keep an up-to-date record, we recompute the budget when it is needed.
 619  */
 620
 621 struct ehci_tt {
 622         u16                     bandwidth[EHCI_BANDWIDTH_FRAMES];
 623
 624         struct list_head        tt_list;        /* List of all ehci_tt's */
 625         struct list_head        ps_list;        /* Items using this TT */
 626         struct usb_tt           *usb_tt;
 627         int                     tt_port;        /* TT port number */
 628 };
 629
 630 /*-------------------------------------------------------------------------*/
 631
 632 /* Prepare the PORTSC wakeup flags during controller suspend/resume */
 633
 634 #define ehci_prepare_ports_for_controller_suspend(ehci, do_wakeup)      \
 635                 ehci_adjust_port_wakeup_flags(ehci, true, do_wakeup)
 636
 637 #define ehci_prepare_ports_for_controller_resume(ehci)                  \
 638                 ehci_adjust_port_wakeup_flags(ehci, false, false)
 639
 640 /*-------------------------------------------------------------------------*/
 641
 642 #ifdef CONFIG_USB_EHCI_ROOT_HUB_TT
 643
 644 /*
 645  * Some EHCI controllers have a Transaction Translator built into the
 646  * root hub. This is a non-standard feature.  Each controller will need
 647  * to add code to the following inline functions, and call them as
 648  * needed (mostly in root hub code).
 649  */
 650
 651 #define ehci_is_TDI(e)                  (ehci_to_hcd(e)->has_tt)
 652
 653 /* Returns the speed of a device attached to a port on the root hub. */
 654 static inline unsigned int
 655 ehci_port_speed(struct ehci_hcd *ehci, unsigned int portsc)
 656 {
 657         if (ehci_is_TDI(ehci)) {
 658                 switch ((portsc >> (ehci->has_hostpc ? 25 : 26)) & 3) {
 659                 case 0:
 660                         return 0;
 661                 case 1:
 662                         return USB_PORT_STAT_LOW_SPEED;
 663                 case 2:
 664                 default:
 665                         return USB_PORT_STAT_HIGH_SPEED;
 666                 }
 667         }
 668         return USB_PORT_STAT_HIGH_SPEED;
 669 }
 670
 671 #else
 672
 673 #define ehci_is_TDI(e)                  (0)
 674
 675 #define ehci_port_speed(ehci, portsc)   USB_PORT_STAT_HIGH_SPEED
 676 #endif
 677
 678 /*-------------------------------------------------------------------------*/
 679
 680 #ifdef CONFIG_PPC_83xx
 681 /* Some Freescale processors have an erratum in which the TT
 682  * port number in the queue head was 0..N-1 instead of 1..N.
 683  */
 684 #define ehci_has_fsl_portno_bug(e)              ((e)->has_fsl_port_bug)
 685 #else
 686 #define ehci_has_fsl_portno_bug(e)              (0)
 687 #endif
 688
 689 #define PORTSC_FSL_PFSC 24      /* Port Force Full-Speed Connect */
 690
 691 #if defined(CONFIG_PPC_85xx)
 692 /* Some Freescale processors have an erratum (USB A-005275) in which
 693  * incoming packets get corrupted in HS mode
 694  */
 695 #define ehci_has_fsl_hs_errata(e)       ((e)->has_fsl_hs_errata)
 696 #else
 697 #define ehci_has_fsl_hs_errata(e)       (0)
 698 #endif
 699
 700 /*
 701  * Some Freescale/NXP processors have an erratum (USB A-005697)
 702  * in which we need to wait for 10ms for bus to enter suspend mode
 703  * after setting SUSP bit.
 704  */
 705 #define ehci_has_fsl_susp_errata(e)     ((e)->has_fsl_susp_errata)
 706
 707 /*
 708  * While most USB host controllers implement their registers in
 709  * little-endian format, a minority (celleb companion chip) implement
 710  * them in big endian format.
 711  *
 712  * This attempts to support either format at compile time without a
 713  * runtime penalty, or both formats with the additional overhead
 714  * of checking a flag bit.
 715  *
 716  * ehci_big_endian_capbase is a special quirk for controllers that
 717  * implement the HC capability registers as separate registers and not
 718  * as fields of a 32-bit register.
 719  */
 720
 721 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO
 722 #define ehci_big_endian_mmio(e)         ((e)->big_endian_mmio)
 723 #define ehci_big_endian_capbase(e)      ((e)->big_endian_capbase)
 724 #else
 725 #define ehci_big_endian_mmio(e)         0
 726 #define ehci_big_endian_capbase(e)      0
 727 #endif
 728
 729 /*
 730  * Big-endian read/write functions are arch-specific.
 731  * Other arches can be added if/when they're needed.
 732  */
 733 #if defined(CONFIG_ARM) && defined(CONFIG_ARCH_IXP4XX)
 734 #define readl_be(addr)          __raw_readl((__force unsigned *)addr)
 735 #define writel_be(val, addr)    __raw_writel(val, (__force unsigned *)addr)
 736 #endif
 737
 738 static inline unsigned int ehci_readl(const struct ehci_hcd *ehci,
 739                 __u32 __iomem *regs)
 740 {
 741 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO
 742         return ehci_big_endian_mmio(ehci) ?
 743                 readl_be(regs) :
 744                 readl(regs);
 745 #else
 746         return readl(regs);
 747 #endif
 748 }
 749
 750 #ifdef CONFIG_SOC_IMX28
 751 static inline void imx28_ehci_writel(const unsigned int val,
 752                 volatile __u32 __iomem *addr)
 753 {
 754         __asm__ ("swp %0, %0, [%1]" : : "r"(val), "r"(addr));
 755 }
 756 #else
 757 static inline void imx28_ehci_writel(const unsigned int val,
 758                 volatile __u32 __iomem *addr)
 759 {
 760 }
 761 #endif
 762 static inline void ehci_writel(const struct ehci_hcd *ehci,
 763                 const unsigned int val, __u32 __iomem *regs)
 764 {
 765 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO
 766         ehci_big_endian_mmio(ehci) ?
 767                 writel_be(val, regs) :
 768                 writel(val, regs);
 769 #else
 770         if (ehci->imx28_write_fix)
 771                 imx28_ehci_writel(val, regs);
 772         else
 773                 writel(val, regs);
 774 #endif
 775 }
 776
 777 /*
 778  * On certain ppc-44x SoC there is a HW issue, that could only worked around with
 779  * explicit suspend/operate of OHCI. This function hereby makes sense only on that arch.
 780  * Other common bits are dependent on has_amcc_usb23 quirk flag.
 781  */
 782 #ifdef CONFIG_44x
 783 static inline void set_ohci_hcfs(struct ehci_hcd *ehci, int operational)
 784 {
 785         u32 hc_control;
 786
 787         hc_control = (readl_be(ehci->ohci_hcctrl_reg) & ~OHCI_CTRL_HCFS);
 788         if (operational)
 789                 hc_control |= OHCI_USB_OPER;
 790         else
 791                 hc_control |= OHCI_USB_SUSPEND;
 792
 793         writel_be(hc_control, ehci->ohci_hcctrl_reg);
 794         (void) readl_be(ehci->ohci_hcctrl_reg);
 795 }
 796 #else
 797 static inline void set_ohci_hcfs(struct ehci_hcd *ehci, int operational)
 798 { }
 799 #endif
 800
 801 /*-------------------------------------------------------------------------*/
 802
 803 /*
 804  * The AMCC 440EPx not only implements its EHCI registers in big-endian
 805  * format, but also its DMA data structures (descriptors).
 806  *
 807  * EHCI controllers accessed through PCI work normally (little-endian
 808  * everywhere), so we won't bother supporting a BE-only mode for now.
 809  */
 810 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_DESC
 811 #define ehci_big_endian_desc(e)         ((e)->big_endian_desc)
 812
 813 /* cpu to ehci */
 814 static inline __hc32 cpu_to_hc32(const struct ehci_hcd *ehci, const u32 x)
 815 {
 816         return ehci_big_endian_desc(ehci)
 817                 ? (__force __hc32)cpu_to_be32(x)
 818                 : (__force __hc32)cpu_to_le32(x);
 819 }
 820
 821 /* ehci to cpu */
 822 static inline u32 hc32_to_cpu(const struct ehci_hcd *ehci, const __hc32 x)
 823 {
 824         return ehci_big_endian_desc(ehci)
 825                 ? be32_to_cpu((__force __be32)x)
 826                 : le32_to_cpu((__force __le32)x);
 827 }
 828
 829 static inline u32 hc32_to_cpup(const struct ehci_hcd *ehci, const __hc32 *x)
 830 {
 831         return ehci_big_endian_desc(ehci)
 832                 ? be32_to_cpup((__force __be32 *)x)
 833                 : le32_to_cpup((__force __le32 *)x);
 834 }
 835
 836 #else
 837
 838 /* cpu to ehci */
 839 static inline __hc32 cpu_to_hc32(const struct ehci_hcd *ehci, const u32 x)
 840 {
 841         return cpu_to_le32(x);
 842 }
 843
 844 /* ehci to cpu */
 845 static inline u32 hc32_to_cpu(const struct ehci_hcd *ehci, const __hc32 x)
 846 {
 847         return le32_to_cpu(x);
 848 }
 849
 850 static inline u32 hc32_to_cpup(const struct ehci_hcd *ehci, const __hc32 *x)
 851 {
 852         return le32_to_cpup(x);
 853 }
 854
 855 #endif
 856
 857 /*-------------------------------------------------------------------------*/
 858
 859 #define ehci_dbg(ehci, fmt, args...) \
 860         dev_dbg(ehci_to_hcd(ehci)->self.controller, fmt, ## args)
 861 #define ehci_err(ehci, fmt, args...) \
 862         dev_err(ehci_to_hcd(ehci)->self.controller, fmt, ## args)
 863 #define ehci_info(ehci, fmt, args...) \
 864         dev_info(ehci_to_hcd(ehci)->self.controller, fmt, ## args)
 865 #define ehci_warn(ehci, fmt, args...) \
 866         dev_warn(ehci_to_hcd(ehci)->self.controller, fmt, ## args)
 867
 868 /*-------------------------------------------------------------------------*/
 869
 870 /* Declarations of things exported for use by ehci platform drivers */
 871
 872 struct ehci_driver_overrides {
 873         size_t          extra_priv_size;
 874         int             (*reset)(struct usb_hcd *hcd);
 875         int             (*port_power)(struct usb_hcd *hcd,
 876                                 int portnum, bool enable);
 877 };
 878
 879 extern void     ehci_init_driver(struct hc_driver *drv,
 880                                 const struct ehci_driver_overrides *over);
 881 extern int      ehci_setup(struct usb_hcd *hcd);
 882 extern int      ehci_handshake(struct ehci_hcd *ehci, void __iomem *ptr,
 883                                 u32 mask, u32 done, int usec);
 884 extern int      ehci_reset(struct ehci_hcd *ehci);
 885
 886 extern int      ehci_suspend(struct usb_hcd *hcd, bool do_wakeup);
 887 extern int      ehci_resume(struct usb_hcd *hcd, bool force_reset);
 888 extern void     ehci_adjust_port_wakeup_flags(struct ehci_hcd *ehci,
 889                         bool suspending, bool do_wakeup);
 890
 891 extern int      ehci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue,
 892                                  u16 wIndex, char *buf, u16 wLength);
 893
 894 #endif /* __LINUX_EHCI_HCD_H */