1 // SPDX-License-Identifier: GPL-2.0
3 * xHCI host controller driver
5 * Copyright (C) 2008 Intel Corp.
8 * Some code borrowed from the Linux EHCI driver.
12 #include <linux/slab.h>
13 #include <asm/unaligned.h>
16 #include "xhci-trace.h"
18 #define PORT_WAKE_BITS (PORT_WKOC_E | PORT_WKDISC_E | PORT_WKCONN_E)
19 #define PORT_RWC_BITS (PORT_CSC | PORT_PEC | PORT_WRC | PORT_OCC | \
20 PORT_RC | PORT_PLC | PORT_PE)
22 /* USB 3 BOS descriptor and a capability descriptors, combined.
23 * Fields will be adjusted and added later in xhci_create_usb3_bos_desc()
25 static u8 usb_bos_descriptor
[] = {
26 USB_DT_BOS_SIZE
, /* __u8 bLength, 5 bytes */
27 USB_DT_BOS
, /* __u8 bDescriptorType */
28 0x0F, 0x00, /* __le16 wTotalLength, 15 bytes */
29 0x1, /* __u8 bNumDeviceCaps */
30 /* First device capability, SuperSpeed */
31 USB_DT_USB_SS_CAP_SIZE
, /* __u8 bLength, 10 bytes */
32 USB_DT_DEVICE_CAPABILITY
, /* Device Capability */
33 USB_SS_CAP_TYPE
, /* bDevCapabilityType, SUPERSPEED_USB */
34 0x00, /* bmAttributes, LTM off by default */
35 USB_5GBPS_OPERATION
, 0x00, /* wSpeedsSupported, 5Gbps only */
36 0x03, /* bFunctionalitySupport,
38 0x00, /* bU1DevExitLat, set later. */
39 0x00, 0x00, /* __le16 bU2DevExitLat, set later. */
40 /* Second device capability, SuperSpeedPlus */
41 0x1c, /* bLength 28, will be adjusted later */
42 USB_DT_DEVICE_CAPABILITY
, /* Device Capability */
43 USB_SSP_CAP_TYPE
, /* bDevCapabilityType SUPERSPEED_PLUS */
44 0x00, /* bReserved 0 */
45 0x23, 0x00, 0x00, 0x00, /* bmAttributes, SSAC=3 SSIC=1 */
46 0x01, 0x00, /* wFunctionalitySupport */
47 0x00, 0x00, /* wReserved 0 */
48 /* Default Sublink Speed Attributes, overwrite if custom PSI exists */
49 0x34, 0x00, 0x05, 0x00, /* 5Gbps, symmetric, rx, ID = 4 */
50 0xb4, 0x00, 0x05, 0x00, /* 5Gbps, symmetric, tx, ID = 4 */
51 0x35, 0x40, 0x0a, 0x00, /* 10Gbps, SSP, symmetric, rx, ID = 5 */
52 0xb5, 0x40, 0x0a, 0x00, /* 10Gbps, SSP, symmetric, tx, ID = 5 */
55 static int xhci_create_usb3_bos_desc(struct xhci_hcd
*xhci
, char *buf
,
58 struct xhci_port_cap
*port_cap
= NULL
;
61 u16 desc_size
, ssp_cap_size
, ssa_size
= 0;
64 desc_size
= USB_DT_BOS_SIZE
+ USB_DT_USB_SS_CAP_SIZE
;
65 ssp_cap_size
= sizeof(usb_bos_descriptor
) - desc_size
;
67 /* does xhci support USB 3.1 Enhanced SuperSpeed */
68 for (i
= 0; i
< xhci
->num_port_caps
; i
++) {
69 if (xhci
->port_caps
[i
].maj_rev
== 0x03 &&
70 xhci
->port_caps
[i
].min_rev
>= 0x01) {
72 port_cap
= &xhci
->port_caps
[i
];
78 /* does xhci provide a PSI table for SSA speed attributes? */
79 if (port_cap
->psi_count
) {
80 /* two SSA entries for each unique PSI ID, RX and TX */
81 ssa_count
= port_cap
->psi_uid_count
* 2;
82 ssa_size
= ssa_count
* sizeof(u32
);
83 ssp_cap_size
-= 16; /* skip copying the default SSA */
85 desc_size
+= ssp_cap_size
;
87 memcpy(buf
, &usb_bos_descriptor
, min(desc_size
, wLength
));
90 /* modify bos descriptor bNumDeviceCaps and wTotalLength */
92 put_unaligned_le16(desc_size
+ ssa_size
, &buf
[2]);
95 if (wLength
< USB_DT_BOS_SIZE
+ USB_DT_USB_SS_CAP_SIZE
)
98 /* Indicate whether the host has LTM support. */
99 temp
= readl(&xhci
->cap_regs
->hcc_params
);
101 buf
[8] |= USB_LTM_SUPPORT
;
103 /* Set the U1 and U2 exit latencies. */
104 if ((xhci
->quirks
& XHCI_LPM_SUPPORT
)) {
105 temp
= readl(&xhci
->cap_regs
->hcs_params3
);
106 buf
[12] = HCS_U1_LATENCY(temp
);
107 put_unaligned_le16(HCS_U2_LATENCY(temp
), &buf
[13]);
110 /* If PSI table exists, add the custom speed attributes from it */
111 if (usb3_1
&& port_cap
->psi_count
) {
112 u32 ssp_cap_base
, bm_attrib
, psi
, psi_mant
, psi_exp
;
115 ssp_cap_base
= USB_DT_BOS_SIZE
+ USB_DT_USB_SS_CAP_SIZE
;
117 if (wLength
< desc_size
)
119 buf
[ssp_cap_base
] = ssp_cap_size
+ ssa_size
;
121 /* attribute count SSAC bits 4:0 and ID count SSIC bits 8:5 */
122 bm_attrib
= (ssa_count
- 1) & 0x1f;
123 bm_attrib
|= (port_cap
->psi_uid_count
- 1) << 5;
124 put_unaligned_le32(bm_attrib
, &buf
[ssp_cap_base
+ 4]);
126 if (wLength
< desc_size
+ ssa_size
)
129 * Create the Sublink Speed Attributes (SSA) array.
130 * The xhci PSI field and USB 3.1 SSA fields are very similar,
131 * but link type bits 7:6 differ for values 01b and 10b.
132 * xhci has also only one PSI entry for a symmetric link when
133 * USB 3.1 requires two SSA entries (RX and TX) for every link
136 for (i
= 0; i
< port_cap
->psi_count
; i
++) {
137 psi
= port_cap
->psi
[i
];
138 psi
&= ~USB_SSP_SUBLINK_SPEED_RSVD
;
139 psi_exp
= XHCI_EXT_PORT_PSIE(psi
);
140 psi_mant
= XHCI_EXT_PORT_PSIM(psi
);
142 /* Shift to Gbps and set SSP Link BIT(14) if 10Gpbs */
143 for (; psi_exp
< 3; psi_exp
++)
148 if ((psi
& PLT_MASK
) == PLT_SYM
) {
149 /* Symmetric, create SSA RX and TX from one PSI entry */
150 put_unaligned_le32(psi
, &buf
[offset
]);
151 psi
|= 1 << 7; /* turn entry to TX */
153 if (offset
>= desc_size
+ ssa_size
)
154 return desc_size
+ ssa_size
;
155 } else if ((psi
& PLT_MASK
) == PLT_ASYM_RX
) {
156 /* Asymetric RX, flip bits 7:6 for SSA */
159 put_unaligned_le32(psi
, &buf
[offset
]);
161 if (offset
>= desc_size
+ ssa_size
)
162 return desc_size
+ ssa_size
;
165 /* ssa_size is 0 for other than usb 3.1 hosts */
166 return desc_size
+ ssa_size
;
169 static void xhci_common_hub_descriptor(struct xhci_hcd
*xhci
,
170 struct usb_hub_descriptor
*desc
, int ports
)
174 desc
->bPwrOn2PwrGood
= 10; /* xhci section 5.4.9 says 20ms max */
175 desc
->bHubContrCurrent
= 0;
177 desc
->bNbrPorts
= ports
;
179 /* Bits 1:0 - support per-port power switching, or power always on */
180 if (HCC_PPC(xhci
->hcc_params
))
181 temp
|= HUB_CHAR_INDV_PORT_LPSM
;
183 temp
|= HUB_CHAR_NO_LPSM
;
184 /* Bit 2 - root hubs are not part of a compound device */
185 /* Bits 4:3 - individual port over current protection */
186 temp
|= HUB_CHAR_INDV_PORT_OCPM
;
187 /* Bits 6:5 - no TTs in root ports */
188 /* Bit 7 - no port indicators */
189 desc
->wHubCharacteristics
= cpu_to_le16(temp
);
192 /* Fill in the USB 2.0 roothub descriptor */
193 static void xhci_usb2_hub_descriptor(struct usb_hcd
*hcd
, struct xhci_hcd
*xhci
,
194 struct usb_hub_descriptor
*desc
)
198 __u8 port_removable
[(USB_MAXCHILDREN
+ 1 + 7) / 8];
201 struct xhci_hub
*rhub
;
203 rhub
= &xhci
->usb2_rhub
;
204 ports
= rhub
->num_ports
;
205 xhci_common_hub_descriptor(xhci
, desc
, ports
);
206 desc
->bDescriptorType
= USB_DT_HUB
;
207 temp
= 1 + (ports
/ 8);
208 desc
->bDescLength
= USB_DT_HUB_NONVAR_SIZE
+ 2 * temp
;
210 /* The Device Removable bits are reported on a byte granularity.
211 * If the port doesn't exist within that byte, the bit is set to 0.
213 memset(port_removable
, 0, sizeof(port_removable
));
214 for (i
= 0; i
< ports
; i
++) {
215 portsc
= readl(rhub
->ports
[i
]->addr
);
216 /* If a device is removable, PORTSC reports a 0, same as in the
217 * hub descriptor DeviceRemovable bits.
219 if (portsc
& PORT_DEV_REMOVE
)
220 /* This math is hairy because bit 0 of DeviceRemovable
221 * is reserved, and bit 1 is for port 1, etc.
223 port_removable
[(i
+ 1) / 8] |= 1 << ((i
+ 1) % 8);
226 /* ch11.h defines a hub descriptor that has room for USB_MAXCHILDREN
227 * ports on it. The USB 2.0 specification says that there are two
228 * variable length fields at the end of the hub descriptor:
229 * DeviceRemovable and PortPwrCtrlMask. But since we can have less than
230 * USB_MAXCHILDREN ports, we may need to use the DeviceRemovable array
231 * to set PortPwrCtrlMask bits. PortPwrCtrlMask must always be set to
232 * 0xFF, so we initialize the both arrays (DeviceRemovable and
233 * PortPwrCtrlMask) to 0xFF. Then we set the DeviceRemovable for each
234 * set of ports that actually exist.
236 memset(desc
->u
.hs
.DeviceRemovable
, 0xff,
237 sizeof(desc
->u
.hs
.DeviceRemovable
));
238 memset(desc
->u
.hs
.PortPwrCtrlMask
, 0xff,
239 sizeof(desc
->u
.hs
.PortPwrCtrlMask
));
241 for (i
= 0; i
< (ports
+ 1 + 7) / 8; i
++)
242 memset(&desc
->u
.hs
.DeviceRemovable
[i
], port_removable
[i
],
246 /* Fill in the USB 3.0 roothub descriptor */
247 static void xhci_usb3_hub_descriptor(struct usb_hcd
*hcd
, struct xhci_hcd
*xhci
,
248 struct usb_hub_descriptor
*desc
)
254 struct xhci_hub
*rhub
;
256 rhub
= &xhci
->usb3_rhub
;
257 ports
= rhub
->num_ports
;
258 xhci_common_hub_descriptor(xhci
, desc
, ports
);
259 desc
->bDescriptorType
= USB_DT_SS_HUB
;
260 desc
->bDescLength
= USB_DT_SS_HUB_SIZE
;
262 /* header decode latency should be zero for roothubs,
263 * see section 4.23.5.2.
265 desc
->u
.ss
.bHubHdrDecLat
= 0;
266 desc
->u
.ss
.wHubDelay
= 0;
269 /* bit 0 is reserved, bit 1 is for port 1, etc. */
270 for (i
= 0; i
< ports
; i
++) {
271 portsc
= readl(rhub
->ports
[i
]->addr
);
272 if (portsc
& PORT_DEV_REMOVE
)
273 port_removable
|= 1 << (i
+ 1);
276 desc
->u
.ss
.DeviceRemovable
= cpu_to_le16(port_removable
);
279 static void xhci_hub_descriptor(struct usb_hcd
*hcd
, struct xhci_hcd
*xhci
,
280 struct usb_hub_descriptor
*desc
)
283 if (hcd
->speed
>= HCD_USB3
)
284 xhci_usb3_hub_descriptor(hcd
, xhci
, desc
);
286 xhci_usb2_hub_descriptor(hcd
, xhci
, desc
);
290 static unsigned int xhci_port_speed(unsigned int port_status
)
292 if (DEV_LOWSPEED(port_status
))
293 return USB_PORT_STAT_LOW_SPEED
;
294 if (DEV_HIGHSPEED(port_status
))
295 return USB_PORT_STAT_HIGH_SPEED
;
297 * FIXME: Yes, we should check for full speed, but the core uses that as
298 * a default in portspeed() in usb/core/hub.c (which is the only place
299 * USB_PORT_STAT_*_SPEED is used).
305 * These bits are Read Only (RO) and should be saved and written to the
306 * registers: 0, 3, 10:13, 30
307 * connect status, over-current status, port speed, and device removable.
308 * connect status and port speed are also sticky - meaning they're in
309 * the AUX well and they aren't changed by a hot, warm, or cold reset.
311 #define XHCI_PORT_RO ((1<<0) | (1<<3) | (0xf<<10) | (1<<30))
313 * These bits are RW; writing a 0 clears the bit, writing a 1 sets the bit:
314 * bits 5:8, 9, 14:15, 25:27
315 * link state, port power, port indicator state, "wake on" enable state
317 #define XHCI_PORT_RWS ((0xf<<5) | (1<<9) | (0x3<<14) | (0x7<<25))
319 * These bits are RW; writing a 1 sets the bit, writing a 0 has no effect:
322 #define XHCI_PORT_RW1S ((1<<4))
324 * These bits are RW; writing a 1 clears the bit, writing a 0 has no effect:
325 * bits 1, 17, 18, 19, 20, 21, 22, 23
326 * port enable/disable, and
327 * change bits: connect, PED, warm port reset changed (reserved zero for USB 2.0 ports),
328 * over-current, reset, link state, and L1 change
330 #define XHCI_PORT_RW1CS ((1<<1) | (0x7f<<17))
332 * Bit 16 is RW, and writing a '1' to it causes the link state control to be
335 #define XHCI_PORT_RW ((1<<16))
337 * These bits are Reserved Zero (RsvdZ) and zero should be written to them:
340 #define XHCI_PORT_RZ ((1<<2) | (1<<24) | (0xf<<28))
343 * Given a port state, this function returns a value that would result in the
344 * port being in the same state, if the value was written to the port status
346 * Save Read Only (RO) bits and save read/write bits where
347 * writing a 0 clears the bit and writing a 1 sets the bit (RWS).
348 * For all other types (RW1S, RW1CS, RW, and RZ), writing a '0' has no effect.
350 u32
xhci_port_state_to_neutral(u32 state
)
352 /* Save read-only status and port state */
353 return (state
& XHCI_PORT_RO
) | (state
& XHCI_PORT_RWS
);
357 * find slot id based on port number.
358 * @port: The one-based port number from one of the two split roothubs.
360 int xhci_find_slot_id_by_port(struct usb_hcd
*hcd
, struct xhci_hcd
*xhci
,
365 enum usb_device_speed speed
;
368 for (i
= 0; i
< MAX_HC_SLOTS
; i
++) {
369 if (!xhci
->devs
[i
] || !xhci
->devs
[i
]->udev
)
371 speed
= xhci
->devs
[i
]->udev
->speed
;
372 if (((speed
>= USB_SPEED_SUPER
) == (hcd
->speed
>= HCD_USB3
))
373 && xhci
->devs
[i
]->fake_port
== port
) {
384 * It issues stop endpoint command for EP 0 to 30. And wait the last command
386 * suspend will set to 1, if suspend bit need to set in command.
388 static int xhci_stop_device(struct xhci_hcd
*xhci
, int slot_id
, int suspend
)
390 struct xhci_virt_device
*virt_dev
;
391 struct xhci_command
*cmd
;
397 virt_dev
= xhci
->devs
[slot_id
];
401 trace_xhci_stop_device(virt_dev
);
403 cmd
= xhci_alloc_command(xhci
, true, GFP_NOIO
);
407 spin_lock_irqsave(&xhci
->lock
, flags
);
408 for (i
= LAST_EP_INDEX
; i
> 0; i
--) {
409 if (virt_dev
->eps
[i
].ring
&& virt_dev
->eps
[i
].ring
->dequeue
) {
410 struct xhci_ep_ctx
*ep_ctx
;
411 struct xhci_command
*command
;
413 ep_ctx
= xhci_get_ep_ctx(xhci
, virt_dev
->out_ctx
, i
);
415 /* Check ep is running, required by AMD SNPS 3.1 xHC */
416 if (GET_EP_CTX_STATE(ep_ctx
) != EP_STATE_RUNNING
)
419 command
= xhci_alloc_command(xhci
, false, GFP_NOWAIT
);
421 spin_unlock_irqrestore(&xhci
->lock
, flags
);
426 ret
= xhci_queue_stop_endpoint(xhci
, command
, slot_id
,
429 spin_unlock_irqrestore(&xhci
->lock
, flags
);
430 xhci_free_command(xhci
, command
);
435 ret
= xhci_queue_stop_endpoint(xhci
, cmd
, slot_id
, 0, suspend
);
437 spin_unlock_irqrestore(&xhci
->lock
, flags
);
441 xhci_ring_cmd_db(xhci
);
442 spin_unlock_irqrestore(&xhci
->lock
, flags
);
444 /* Wait for last stop endpoint command to finish */
445 wait_for_completion(cmd
->completion
);
447 if (cmd
->status
== COMP_COMMAND_ABORTED
||
448 cmd
->status
== COMP_COMMAND_RING_STOPPED
) {
449 xhci_warn(xhci
, "Timeout while waiting for stop endpoint command\n");
454 xhci_free_command(xhci
, cmd
);
459 * Ring device, it rings the all doorbells unconditionally.
461 void xhci_ring_device(struct xhci_hcd
*xhci
, int slot_id
)
464 struct xhci_virt_ep
*ep
;
466 for (i
= 0; i
< LAST_EP_INDEX
+ 1; i
++) {
467 ep
= &xhci
->devs
[slot_id
]->eps
[i
];
469 if (ep
->ep_state
& EP_HAS_STREAMS
) {
470 for (s
= 1; s
< ep
->stream_info
->num_streams
; s
++)
471 xhci_ring_ep_doorbell(xhci
, slot_id
, i
, s
);
472 } else if (ep
->ring
&& ep
->ring
->dequeue
) {
473 xhci_ring_ep_doorbell(xhci
, slot_id
, i
, 0);
480 static void xhci_disable_port(struct usb_hcd
*hcd
, struct xhci_hcd
*xhci
,
481 u16 wIndex
, __le32 __iomem
*addr
, u32 port_status
)
483 /* Don't allow the USB core to disable SuperSpeed ports. */
484 if (hcd
->speed
>= HCD_USB3
) {
485 xhci_dbg(xhci
, "Ignoring request to disable "
486 "SuperSpeed port.\n");
490 if (xhci
->quirks
& XHCI_BROKEN_PORT_PED
) {
492 "Broken Port Enabled/Disabled, ignoring port disable request.\n");
496 /* Write 1 to disable the port */
497 writel(port_status
| PORT_PE
, addr
);
498 port_status
= readl(addr
);
499 xhci_dbg(xhci
, "disable port %d-%d, portsc: 0x%x\n",
500 hcd
->self
.busnum
, wIndex
+ 1, port_status
);
503 static void xhci_clear_port_change_bit(struct xhci_hcd
*xhci
, u16 wValue
,
504 u16 wIndex
, __le32 __iomem
*addr
, u32 port_status
)
506 char *port_change_bit
;
510 case USB_PORT_FEAT_C_RESET
:
512 port_change_bit
= "reset";
514 case USB_PORT_FEAT_C_BH_PORT_RESET
:
516 port_change_bit
= "warm(BH) reset";
518 case USB_PORT_FEAT_C_CONNECTION
:
520 port_change_bit
= "connect";
522 case USB_PORT_FEAT_C_OVER_CURRENT
:
524 port_change_bit
= "over-current";
526 case USB_PORT_FEAT_C_ENABLE
:
528 port_change_bit
= "enable/disable";
530 case USB_PORT_FEAT_C_SUSPEND
:
532 port_change_bit
= "suspend/resume";
534 case USB_PORT_FEAT_C_PORT_LINK_STATE
:
536 port_change_bit
= "link state";
538 case USB_PORT_FEAT_C_PORT_CONFIG_ERROR
:
540 port_change_bit
= "config error";
543 /* Should never happen */
546 /* Change bits are all write 1 to clear */
547 writel(port_status
| status
, addr
);
548 port_status
= readl(addr
);
550 xhci_dbg(xhci
, "clear port%d %s change, portsc: 0x%x\n",
551 wIndex
+ 1, port_change_bit
, port_status
);
554 struct xhci_hub
*xhci_get_rhub(struct usb_hcd
*hcd
)
556 struct xhci_hcd
*xhci
= hcd_to_xhci(hcd
);
558 if (hcd
->speed
>= HCD_USB3
)
559 return &xhci
->usb3_rhub
;
560 return &xhci
->usb2_rhub
;
564 * xhci_set_port_power() must be called with xhci->lock held.
565 * It will release and re-aquire the lock while calling ACPI
568 static void xhci_set_port_power(struct xhci_hcd
*xhci
, struct usb_hcd
*hcd
,
569 u16 index
, bool on
, unsigned long *flags
)
570 __must_hold(&xhci
->lock
)
572 struct xhci_hub
*rhub
;
573 struct xhci_port
*port
;
576 rhub
= xhci_get_rhub(hcd
);
577 port
= rhub
->ports
[index
];
578 temp
= readl(port
->addr
);
580 xhci_dbg(xhci
, "set port power %d-%d %s, portsc: 0x%x\n",
581 hcd
->self
.busnum
, index
+ 1, on
? "ON" : "OFF", temp
);
583 temp
= xhci_port_state_to_neutral(temp
);
587 writel(temp
| PORT_POWER
, port
->addr
);
591 writel(temp
& ~PORT_POWER
, port
->addr
);
594 spin_unlock_irqrestore(&xhci
->lock
, *flags
);
595 temp
= usb_acpi_power_manageable(hcd
->self
.root_hub
,
598 usb_acpi_set_power_state(hcd
->self
.root_hub
,
600 spin_lock_irqsave(&xhci
->lock
, *flags
);
603 static void xhci_port_set_test_mode(struct xhci_hcd
*xhci
,
604 u16 test_mode
, u16 wIndex
)
607 struct xhci_port
*port
;
609 /* xhci only supports test mode for usb2 ports */
610 port
= xhci
->usb2_rhub
.ports
[wIndex
];
611 temp
= readl(port
->addr
+ PORTPMSC
);
612 temp
|= test_mode
<< PORT_TEST_MODE_SHIFT
;
613 writel(temp
, port
->addr
+ PORTPMSC
);
614 xhci
->test_mode
= test_mode
;
615 if (test_mode
== USB_TEST_FORCE_ENABLE
)
619 static int xhci_enter_test_mode(struct xhci_hcd
*xhci
,
620 u16 test_mode
, u16 wIndex
, unsigned long *flags
)
621 __must_hold(&xhci
->lock
)
625 /* Disable all Device Slots */
626 xhci_dbg(xhci
, "Disable all slots\n");
627 spin_unlock_irqrestore(&xhci
->lock
, *flags
);
628 for (i
= 1; i
<= HCS_MAX_SLOTS(xhci
->hcs_params1
); i
++) {
632 retval
= xhci_disable_slot(xhci
, i
);
634 xhci_err(xhci
, "Failed to disable slot %d, %d. Enter test mode anyway\n",
637 spin_lock_irqsave(&xhci
->lock
, *flags
);
638 /* Put all ports to the Disable state by clear PP */
639 xhci_dbg(xhci
, "Disable all port (PP = 0)\n");
640 /* Power off USB3 ports*/
641 for (i
= 0; i
< xhci
->usb3_rhub
.num_ports
; i
++)
642 xhci_set_port_power(xhci
, xhci
->shared_hcd
, i
, false, flags
);
643 /* Power off USB2 ports*/
644 for (i
= 0; i
< xhci
->usb2_rhub
.num_ports
; i
++)
645 xhci_set_port_power(xhci
, xhci
->main_hcd
, i
, false, flags
);
646 /* Stop the controller */
647 xhci_dbg(xhci
, "Stop controller\n");
648 retval
= xhci_halt(xhci
);
651 /* Disable runtime PM for test mode */
652 pm_runtime_forbid(xhci_to_hcd(xhci
)->self
.controller
);
653 /* Set PORTPMSC.PTC field to enter selected test mode */
654 /* Port is selected by wIndex. port_id = wIndex + 1 */
655 xhci_dbg(xhci
, "Enter Test Mode: %d, Port_id=%d\n",
656 test_mode
, wIndex
+ 1);
657 xhci_port_set_test_mode(xhci
, test_mode
, wIndex
);
661 static int xhci_exit_test_mode(struct xhci_hcd
*xhci
)
665 if (!xhci
->test_mode
) {
666 xhci_err(xhci
, "Not in test mode, do nothing.\n");
669 if (xhci
->test_mode
== USB_TEST_FORCE_ENABLE
&&
670 !(xhci
->xhc_state
& XHCI_STATE_HALTED
)) {
671 retval
= xhci_halt(xhci
);
675 pm_runtime_allow(xhci_to_hcd(xhci
)->self
.controller
);
677 return xhci_reset(xhci
);
680 void xhci_set_link_state(struct xhci_hcd
*xhci
, struct xhci_port
*port
,
686 portsc
= readl(port
->addr
);
687 temp
= xhci_port_state_to_neutral(portsc
);
688 temp
&= ~PORT_PLS_MASK
;
689 temp
|= PORT_LINK_STROBE
| link_state
;
690 writel(temp
, port
->addr
);
692 xhci_dbg(xhci
, "Set port %d-%d link state, portsc: 0x%x, write 0x%x",
693 port
->rhub
->hcd
->self
.busnum
, port
->hcd_portnum
+ 1,
697 static void xhci_set_remote_wake_mask(struct xhci_hcd
*xhci
,
698 struct xhci_port
*port
, u16 wake_mask
)
702 temp
= readl(port
->addr
);
703 temp
= xhci_port_state_to_neutral(temp
);
705 if (wake_mask
& USB_PORT_FEAT_REMOTE_WAKE_CONNECT
)
706 temp
|= PORT_WKCONN_E
;
708 temp
&= ~PORT_WKCONN_E
;
710 if (wake_mask
& USB_PORT_FEAT_REMOTE_WAKE_DISCONNECT
)
711 temp
|= PORT_WKDISC_E
;
713 temp
&= ~PORT_WKDISC_E
;
715 if (wake_mask
& USB_PORT_FEAT_REMOTE_WAKE_OVER_CURRENT
)
718 temp
&= ~PORT_WKOC_E
;
720 writel(temp
, port
->addr
);
723 /* Test and clear port RWC bit */
724 void xhci_test_and_clear_bit(struct xhci_hcd
*xhci
, struct xhci_port
*port
,
729 temp
= readl(port
->addr
);
730 if (temp
& port_bit
) {
731 temp
= xhci_port_state_to_neutral(temp
);
733 writel(temp
, port
->addr
);
737 /* Updates Link Status for super Speed port */
738 static void xhci_hub_report_usb3_link_state(struct xhci_hcd
*xhci
,
739 u32
*status
, u32 status_reg
)
741 u32 pls
= status_reg
& PORT_PLS_MASK
;
743 /* When the CAS bit is set then warm reset
744 * should be performed on port
746 if (status_reg
& PORT_CAS
) {
747 /* The CAS bit can be set while the port is
749 * Only roothubs have CAS bit, so we
750 * pretend to be in compliance mode
751 * unless we're already in compliance
752 * or the inactive state.
754 if (pls
!= USB_SS_PORT_LS_COMP_MOD
&&
755 pls
!= USB_SS_PORT_LS_SS_INACTIVE
) {
756 pls
= USB_SS_PORT_LS_COMP_MOD
;
758 /* Return also connection bit -
759 * hub state machine resets port
760 * when this bit is set.
762 pls
|= USB_PORT_STAT_CONNECTION
;
765 * Resume state is an xHCI internal state. Do not report it to
766 * usb core, instead, pretend to be U3, thus usb core knows
767 * it's not ready for transfer.
769 if (pls
== XDEV_RESUME
) {
770 *status
|= USB_SS_PORT_LS_U3
;
775 * If CAS bit isn't set but the Port is already at
776 * Compliance Mode, fake a connection so the USB core
777 * notices the Compliance state and resets the port.
778 * This resolves an issue generated by the SN65LVPE502CP
779 * in which sometimes the port enters compliance mode
780 * caused by a delay on the host-device negotiation.
782 if ((xhci
->quirks
& XHCI_COMP_MODE_QUIRK
) &&
783 (pls
== USB_SS_PORT_LS_COMP_MOD
))
784 pls
|= USB_PORT_STAT_CONNECTION
;
787 /* update status field */
792 * Function for Compliance Mode Quirk.
794 * This Function verifies if all xhc USB3 ports have entered U0, if so,
795 * the compliance mode timer is deleted. A port won't enter
796 * compliance mode if it has previously entered U0.
798 static void xhci_del_comp_mod_timer(struct xhci_hcd
*xhci
, u32 status
,
801 u32 all_ports_seen_u0
= ((1 << xhci
->usb3_rhub
.num_ports
) - 1);
802 bool port_in_u0
= ((status
& PORT_PLS_MASK
) == XDEV_U0
);
804 if (!(xhci
->quirks
& XHCI_COMP_MODE_QUIRK
))
807 if ((xhci
->port_status_u0
!= all_ports_seen_u0
) && port_in_u0
) {
808 xhci
->port_status_u0
|= 1 << wIndex
;
809 if (xhci
->port_status_u0
== all_ports_seen_u0
) {
810 del_timer_sync(&xhci
->comp_mode_recovery_timer
);
811 xhci_dbg_trace(xhci
, trace_xhci_dbg_quirks
,
812 "All USB3 ports have entered U0 already!");
813 xhci_dbg_trace(xhci
, trace_xhci_dbg_quirks
,
814 "Compliance Mode Recovery Timer Deleted.");
819 static int xhci_handle_usb2_port_link_resume(struct xhci_port
*port
,
820 u32
*status
, u32 portsc
,
821 unsigned long *flags
)
823 struct xhci_bus_state
*bus_state
;
824 struct xhci_hcd
*xhci
;
829 hcd
= port
->rhub
->hcd
;
830 bus_state
= &port
->rhub
->bus_state
;
831 xhci
= hcd_to_xhci(hcd
);
832 wIndex
= port
->hcd_portnum
;
834 if ((portsc
& PORT_RESET
) || !(portsc
& PORT_PE
)) {
835 *status
= 0xffffffff;
838 /* did port event handler already start resume timing? */
839 if (!bus_state
->resume_done
[wIndex
]) {
840 /* If not, maybe we are in a host initated resume? */
841 if (test_bit(wIndex
, &bus_state
->resuming_ports
)) {
842 /* Host initated resume doesn't time the resume
843 * signalling using resume_done[].
844 * It manually sets RESUME state, sleeps 20ms
845 * and sets U0 state. This should probably be
846 * changed, but not right now.
849 /* port resume was discovered now and here,
850 * start resume timing
852 unsigned long timeout
= jiffies
+
853 msecs_to_jiffies(USB_RESUME_TIMEOUT
);
855 set_bit(wIndex
, &bus_state
->resuming_ports
);
856 bus_state
->resume_done
[wIndex
] = timeout
;
857 mod_timer(&hcd
->rh_timer
, timeout
);
858 usb_hcd_start_port_resume(&hcd
->self
, wIndex
);
860 /* Has resume been signalled for USB_RESUME_TIME yet? */
861 } else if (time_after_eq(jiffies
, bus_state
->resume_done
[wIndex
])) {
864 xhci_dbg(xhci
, "resume USB2 port %d-%d\n",
865 hcd
->self
.busnum
, wIndex
+ 1);
867 bus_state
->resume_done
[wIndex
] = 0;
868 clear_bit(wIndex
, &bus_state
->resuming_ports
);
870 set_bit(wIndex
, &bus_state
->rexit_ports
);
872 xhci_test_and_clear_bit(xhci
, port
, PORT_PLC
);
873 xhci_set_link_state(xhci
, port
, XDEV_U0
);
875 spin_unlock_irqrestore(&xhci
->lock
, *flags
);
876 time_left
= wait_for_completion_timeout(
877 &bus_state
->rexit_done
[wIndex
],
878 msecs_to_jiffies(XHCI_MAX_REXIT_TIMEOUT_MS
));
879 spin_lock_irqsave(&xhci
->lock
, *flags
);
882 slot_id
= xhci_find_slot_id_by_port(hcd
, xhci
,
885 xhci_dbg(xhci
, "slot_id is zero\n");
886 *status
= 0xffffffff;
889 xhci_ring_device(xhci
, slot_id
);
891 int port_status
= readl(port
->addr
);
893 xhci_warn(xhci
, "Port resume timed out, port %d-%d: 0x%x\n",
894 hcd
->self
.busnum
, wIndex
+ 1, port_status
);
895 *status
|= USB_PORT_STAT_SUSPEND
;
896 clear_bit(wIndex
, &bus_state
->rexit_ports
);
899 usb_hcd_end_port_resume(&hcd
->self
, wIndex
);
900 bus_state
->port_c_suspend
|= 1 << wIndex
;
901 bus_state
->suspended_ports
&= ~(1 << wIndex
);
904 * The resume has been signaling for less than
905 * USB_RESUME_TIME. Report the port status as SUSPEND,
906 * let the usbcore check port status again and clear
907 * resume signaling later.
909 *status
|= USB_PORT_STAT_SUSPEND
;
914 static u32
xhci_get_ext_port_status(u32 raw_port_status
, u32 port_li
)
919 /* only support rx and tx lane counts of 1 in usb3.1 spec */
920 speed_id
= DEV_PORT_SPEED(raw_port_status
);
921 ext_stat
|= speed_id
; /* bits 3:0, RX speed id */
922 ext_stat
|= speed_id
<< 4; /* bits 7:4, TX speed id */
924 ext_stat
|= PORT_RX_LANES(port_li
) << 8; /* bits 11:8 Rx lane count */
925 ext_stat
|= PORT_TX_LANES(port_li
) << 12; /* bits 15:12 Tx lane count */
930 static void xhci_get_usb3_port_status(struct xhci_port
*port
, u32
*status
,
933 struct xhci_bus_state
*bus_state
;
934 struct xhci_hcd
*xhci
;
939 bus_state
= &port
->rhub
->bus_state
;
940 xhci
= hcd_to_xhci(port
->rhub
->hcd
);
941 hcd
= port
->rhub
->hcd
;
942 link_state
= portsc
& PORT_PLS_MASK
;
943 portnum
= port
->hcd_portnum
;
945 /* USB3 specific wPortChange bits
947 * Port link change with port in resume state should not be
948 * reported to usbcore, as this is an internal state to be
949 * handled by xhci driver. Reporting PLC to usbcore may
950 * cause usbcore clearing PLC first and port change event
951 * irq won't be generated.
954 if (portsc
& PORT_PLC
&& (link_state
!= XDEV_RESUME
))
955 *status
|= USB_PORT_STAT_C_LINK_STATE
<< 16;
956 if (portsc
& PORT_WRC
)
957 *status
|= USB_PORT_STAT_C_BH_RESET
<< 16;
958 if (portsc
& PORT_CEC
)
959 *status
|= USB_PORT_STAT_C_CONFIG_ERROR
<< 16;
961 /* USB3 specific wPortStatus bits */
962 if (portsc
& PORT_POWER
) {
963 *status
|= USB_SS_PORT_STAT_POWER
;
964 /* link state handling */
965 if (link_state
== XDEV_U0
)
966 bus_state
->suspended_ports
&= ~(1 << portnum
);
969 /* remote wake resume signaling complete */
970 if (bus_state
->port_remote_wakeup
& (1 << portnum
) &&
971 link_state
!= XDEV_RESUME
&&
972 link_state
!= XDEV_RECOVERY
) {
973 bus_state
->port_remote_wakeup
&= ~(1 << portnum
);
974 usb_hcd_end_port_resume(&hcd
->self
, portnum
);
977 xhci_hub_report_usb3_link_state(xhci
, status
, portsc
);
978 xhci_del_comp_mod_timer(xhci
, portsc
, portnum
);
981 static void xhci_get_usb2_port_status(struct xhci_port
*port
, u32
*status
,
982 u32 portsc
, unsigned long *flags
)
984 struct xhci_bus_state
*bus_state
;
989 bus_state
= &port
->rhub
->bus_state
;
990 link_state
= portsc
& PORT_PLS_MASK
;
991 portnum
= port
->hcd_portnum
;
993 /* USB2 wPortStatus bits */
994 if (portsc
& PORT_POWER
) {
995 *status
|= USB_PORT_STAT_POWER
;
997 /* link state is only valid if port is powered */
998 if (link_state
== XDEV_U3
)
999 *status
|= USB_PORT_STAT_SUSPEND
;
1000 if (link_state
== XDEV_U2
)
1001 *status
|= USB_PORT_STAT_L1
;
1002 if (link_state
== XDEV_U0
) {
1003 bus_state
->resume_done
[portnum
] = 0;
1004 clear_bit(portnum
, &bus_state
->resuming_ports
);
1005 if (bus_state
->suspended_ports
& (1 << portnum
)) {
1006 bus_state
->suspended_ports
&= ~(1 << portnum
);
1007 bus_state
->port_c_suspend
|= 1 << portnum
;
1010 if (link_state
== XDEV_RESUME
) {
1011 ret
= xhci_handle_usb2_port_link_resume(port
, status
,
1020 * Converts a raw xHCI port status into the format that external USB 2.0 or USB
1023 * Possible side effects:
1024 * - Mark a port as being done with device resume,
1025 * and ring the endpoint doorbells.
1026 * - Stop the Synopsys redriver Compliance Mode polling.
1027 * - Drop and reacquire the xHCI lock, in order to wait for port resume.
1029 static u32
xhci_get_port_status(struct usb_hcd
*hcd
,
1030 struct xhci_bus_state
*bus_state
,
1031 u16 wIndex
, u32 raw_port_status
,
1032 unsigned long *flags
)
1033 __releases(&xhci
->lock
)
1034 __acquires(&xhci
->lock
)
1037 struct xhci_hub
*rhub
;
1038 struct xhci_port
*port
;
1040 rhub
= xhci_get_rhub(hcd
);
1041 port
= rhub
->ports
[wIndex
];
1043 /* common wPortChange bits */
1044 if (raw_port_status
& PORT_CSC
)
1045 status
|= USB_PORT_STAT_C_CONNECTION
<< 16;
1046 if (raw_port_status
& PORT_PEC
)
1047 status
|= USB_PORT_STAT_C_ENABLE
<< 16;
1048 if ((raw_port_status
& PORT_OCC
))
1049 status
|= USB_PORT_STAT_C_OVERCURRENT
<< 16;
1050 if ((raw_port_status
& PORT_RC
))
1051 status
|= USB_PORT_STAT_C_RESET
<< 16;
1053 /* common wPortStatus bits */
1054 if (raw_port_status
& PORT_CONNECT
) {
1055 status
|= USB_PORT_STAT_CONNECTION
;
1056 status
|= xhci_port_speed(raw_port_status
);
1058 if (raw_port_status
& PORT_PE
)
1059 status
|= USB_PORT_STAT_ENABLE
;
1060 if (raw_port_status
& PORT_OC
)
1061 status
|= USB_PORT_STAT_OVERCURRENT
;
1062 if (raw_port_status
& PORT_RESET
)
1063 status
|= USB_PORT_STAT_RESET
;
1065 /* USB2 and USB3 specific bits, including Port Link State */
1066 if (hcd
->speed
>= HCD_USB3
)
1067 xhci_get_usb3_port_status(port
, &status
, raw_port_status
);
1069 xhci_get_usb2_port_status(port
, &status
, raw_port_status
,
1072 * Clear stale usb2 resume signalling variables in case port changed
1073 * state during resume signalling. For example on error
1075 if ((bus_state
->resume_done
[wIndex
] ||
1076 test_bit(wIndex
, &bus_state
->resuming_ports
)) &&
1077 (raw_port_status
& PORT_PLS_MASK
) != XDEV_U3
&&
1078 (raw_port_status
& PORT_PLS_MASK
) != XDEV_RESUME
) {
1079 bus_state
->resume_done
[wIndex
] = 0;
1080 clear_bit(wIndex
, &bus_state
->resuming_ports
);
1081 usb_hcd_end_port_resume(&hcd
->self
, wIndex
);
1084 if (bus_state
->port_c_suspend
& (1 << wIndex
))
1085 status
|= USB_PORT_STAT_C_SUSPEND
<< 16;
1090 int xhci_hub_control(struct usb_hcd
*hcd
, u16 typeReq
, u16 wValue
,
1091 u16 wIndex
, char *buf
, u16 wLength
)
1093 struct xhci_hcd
*xhci
= hcd_to_xhci(hcd
);
1095 unsigned long flags
;
1099 struct xhci_bus_state
*bus_state
;
1104 struct xhci_hub
*rhub
;
1105 struct xhci_port
**ports
;
1107 rhub
= xhci_get_rhub(hcd
);
1108 ports
= rhub
->ports
;
1109 max_ports
= rhub
->num_ports
;
1110 bus_state
= &rhub
->bus_state
;
1112 spin_lock_irqsave(&xhci
->lock
, flags
);
1115 /* No power source, over-current reported per port */
1118 case GetHubDescriptor
:
1119 /* Check to make sure userspace is asking for the USB 3.0 hub
1120 * descriptor for the USB 3.0 roothub. If not, we stall the
1121 * endpoint, like external hubs do.
1123 if (hcd
->speed
>= HCD_USB3
&&
1124 (wLength
< USB_DT_SS_HUB_SIZE
||
1125 wValue
!= (USB_DT_SS_HUB
<< 8))) {
1126 xhci_dbg(xhci
, "Wrong hub descriptor type for "
1127 "USB 3.0 roothub.\n");
1130 xhci_hub_descriptor(hcd
, xhci
,
1131 (struct usb_hub_descriptor
*) buf
);
1133 case DeviceRequest
| USB_REQ_GET_DESCRIPTOR
:
1134 if ((wValue
& 0xff00) != (USB_DT_BOS
<< 8))
1137 if (hcd
->speed
< HCD_USB3
)
1140 retval
= xhci_create_usb3_bos_desc(xhci
, buf
, wLength
);
1141 spin_unlock_irqrestore(&xhci
->lock
, flags
);
1144 if (!wIndex
|| wIndex
> max_ports
)
1147 temp
= readl(ports
[wIndex
]->addr
);
1148 if (temp
== ~(u32
)0) {
1153 trace_xhci_get_port_status(wIndex
, temp
);
1154 status
= xhci_get_port_status(hcd
, bus_state
, wIndex
, temp
,
1156 if (status
== 0xffffffff)
1159 xhci_dbg(xhci
, "Get port status %d-%d read: 0x%x, return 0x%x",
1160 hcd
->self
.busnum
, wIndex
+ 1, temp
, status
);
1162 put_unaligned(cpu_to_le32(status
), (__le32
*) buf
);
1163 /* if USB 3.1 extended port status return additional 4 bytes */
1164 if (wValue
== 0x02) {
1167 if (hcd
->speed
< HCD_USB31
|| wLength
!= 8) {
1168 xhci_err(xhci
, "get ext port status invalid parameter\n");
1172 port_li
= readl(ports
[wIndex
]->addr
+ PORTLI
);
1173 status
= xhci_get_ext_port_status(temp
, port_li
);
1174 put_unaligned_le32(status
, &buf
[4]);
1177 case SetPortFeature
:
1178 if (wValue
== USB_PORT_FEAT_LINK_STATE
)
1179 link_state
= (wIndex
& 0xff00) >> 3;
1180 if (wValue
== USB_PORT_FEAT_REMOTE_WAKE_MASK
)
1181 wake_mask
= wIndex
& 0xff00;
1182 if (wValue
== USB_PORT_FEAT_TEST
)
1183 test_mode
= (wIndex
& 0xff00) >> 8;
1184 /* The MSB of wIndex is the U1/U2 timeout */
1185 timeout
= (wIndex
& 0xff00) >> 8;
1187 if (!wIndex
|| wIndex
> max_ports
)
1190 temp
= readl(ports
[wIndex
]->addr
);
1191 if (temp
== ~(u32
)0) {
1196 temp
= xhci_port_state_to_neutral(temp
);
1197 /* FIXME: What new port features do we need to support? */
1199 case USB_PORT_FEAT_SUSPEND
:
1200 temp
= readl(ports
[wIndex
]->addr
);
1201 if ((temp
& PORT_PLS_MASK
) != XDEV_U0
) {
1202 /* Resume the port to U0 first */
1203 xhci_set_link_state(xhci
, ports
[wIndex
],
1205 spin_unlock_irqrestore(&xhci
->lock
, flags
);
1207 spin_lock_irqsave(&xhci
->lock
, flags
);
1209 /* In spec software should not attempt to suspend
1210 * a port unless the port reports that it is in the
1211 * enabled (PED = ‘1’,PLS < ‘3’) state.
1213 temp
= readl(ports
[wIndex
]->addr
);
1214 if ((temp
& PORT_PE
) == 0 || (temp
& PORT_RESET
)
1215 || (temp
& PORT_PLS_MASK
) >= XDEV_U3
) {
1216 xhci_warn(xhci
, "USB core suspending port %d-%d not in U0/U1/U2\n",
1217 hcd
->self
.busnum
, wIndex
+ 1);
1221 slot_id
= xhci_find_slot_id_by_port(hcd
, xhci
,
1224 xhci_warn(xhci
, "slot_id is zero\n");
1227 /* unlock to execute stop endpoint commands */
1228 spin_unlock_irqrestore(&xhci
->lock
, flags
);
1229 xhci_stop_device(xhci
, slot_id
, 1);
1230 spin_lock_irqsave(&xhci
->lock
, flags
);
1232 xhci_set_link_state(xhci
, ports
[wIndex
], XDEV_U3
);
1234 spin_unlock_irqrestore(&xhci
->lock
, flags
);
1235 msleep(10); /* wait device to enter */
1236 spin_lock_irqsave(&xhci
->lock
, flags
);
1238 temp
= readl(ports
[wIndex
]->addr
);
1239 bus_state
->suspended_ports
|= 1 << wIndex
;
1241 case USB_PORT_FEAT_LINK_STATE
:
1242 temp
= readl(ports
[wIndex
]->addr
);
1244 if (link_state
== USB_SS_PORT_LS_SS_DISABLED
) {
1245 xhci_dbg(xhci
, "Disable port %d-%d\n",
1246 hcd
->self
.busnum
, wIndex
+ 1);
1247 temp
= xhci_port_state_to_neutral(temp
);
1249 * Clear all change bits, so that we get a new
1252 temp
|= PORT_CSC
| PORT_PEC
| PORT_WRC
|
1253 PORT_OCC
| PORT_RC
| PORT_PLC
|
1255 writel(temp
| PORT_PE
, ports
[wIndex
]->addr
);
1256 temp
= readl(ports
[wIndex
]->addr
);
1260 /* Put link in RxDetect (enable port) */
1261 if (link_state
== USB_SS_PORT_LS_RX_DETECT
) {
1262 xhci_dbg(xhci
, "Enable port %d-%d\n",
1263 hcd
->self
.busnum
, wIndex
+ 1);
1264 xhci_set_link_state(xhci
, ports
[wIndex
],
1266 temp
= readl(ports
[wIndex
]->addr
);
1271 * For xHCI 1.1 according to section 4.19.1.2.4.1 a
1272 * root hub port's transition to compliance mode upon
1273 * detecting LFPS timeout may be controlled by an
1274 * Compliance Transition Enabled (CTE) flag (not
1275 * software visible). This flag is set by writing 0xA
1276 * to PORTSC PLS field which will allow transition to
1277 * compliance mode the next time LFPS timeout is
1278 * encountered. A warm reset will clear it.
1280 * The CTE flag is only supported if the HCCPARAMS2 CTC
1281 * flag is set, otherwise, the compliance substate is
1282 * automatically entered as on 1.0 and prior.
1284 if (link_state
== USB_SS_PORT_LS_COMP_MOD
) {
1285 if (!HCC2_CTC(xhci
->hcc_params2
)) {
1286 xhci_dbg(xhci
, "CTC flag is 0, port already supports entering compliance mode\n");
1290 if ((temp
& PORT_CONNECT
)) {
1291 xhci_warn(xhci
, "Can't set compliance mode when port is connected\n");
1295 xhci_dbg(xhci
, "Enable compliance mode transition for port %d-%d\n",
1296 hcd
->self
.busnum
, wIndex
+ 1);
1297 xhci_set_link_state(xhci
, ports
[wIndex
],
1300 temp
= readl(ports
[wIndex
]->addr
);
1303 /* Port must be enabled */
1304 if (!(temp
& PORT_PE
)) {
1308 /* Can't set port link state above '3' (U3) */
1309 if (link_state
> USB_SS_PORT_LS_U3
) {
1310 xhci_warn(xhci
, "Cannot set port %d-%d link state %d\n",
1311 hcd
->self
.busnum
, wIndex
+ 1,
1317 * set link to U0, steps depend on current link state.
1318 * U3: set link to U0 and wait for u3exit completion.
1319 * U1/U2: no PLC complete event, only set link to U0.
1320 * Resume/Recovery: device initiated U0, only wait for
1323 if (link_state
== USB_SS_PORT_LS_U0
) {
1324 u32 pls
= temp
& PORT_PLS_MASK
;
1325 bool wait_u0
= false;
1330 if (pls
== XDEV_U3
||
1331 pls
== XDEV_RESUME
||
1332 pls
== XDEV_RECOVERY
) {
1334 reinit_completion(&bus_state
->u3exit_done
[wIndex
]);
1336 if (pls
<= XDEV_U3
) /* U1, U2, U3 */
1337 xhci_set_link_state(xhci
, ports
[wIndex
],
1344 spin_unlock_irqrestore(&xhci
->lock
, flags
);
1345 if (!wait_for_completion_timeout(&bus_state
->u3exit_done
[wIndex
],
1346 msecs_to_jiffies(100)))
1347 xhci_dbg(xhci
, "missing U0 port change event for port %d-%d\n",
1348 hcd
->self
.busnum
, wIndex
+ 1);
1349 spin_lock_irqsave(&xhci
->lock
, flags
);
1350 temp
= readl(ports
[wIndex
]->addr
);
1354 if (link_state
== USB_SS_PORT_LS_U3
) {
1356 slot_id
= xhci_find_slot_id_by_port(hcd
, xhci
,
1359 /* unlock to execute stop endpoint
1361 spin_unlock_irqrestore(&xhci
->lock
,
1363 xhci_stop_device(xhci
, slot_id
, 1);
1364 spin_lock_irqsave(&xhci
->lock
, flags
);
1366 xhci_set_link_state(xhci
, ports
[wIndex
], USB_SS_PORT_LS_U3
);
1367 spin_unlock_irqrestore(&xhci
->lock
, flags
);
1369 usleep_range(4000, 8000);
1370 temp
= readl(ports
[wIndex
]->addr
);
1371 if ((temp
& PORT_PLS_MASK
) == XDEV_U3
)
1374 spin_lock_irqsave(&xhci
->lock
, flags
);
1375 temp
= readl(ports
[wIndex
]->addr
);
1376 bus_state
->suspended_ports
|= 1 << wIndex
;
1379 case USB_PORT_FEAT_POWER
:
1381 * Turn on ports, even if there isn't per-port switching.
1382 * HC will report connect events even before this is set.
1383 * However, hub_wq will ignore the roothub events until
1384 * the roothub is registered.
1386 xhci_set_port_power(xhci
, hcd
, wIndex
, true, &flags
);
1388 case USB_PORT_FEAT_RESET
:
1389 temp
= (temp
| PORT_RESET
);
1390 writel(temp
, ports
[wIndex
]->addr
);
1392 temp
= readl(ports
[wIndex
]->addr
);
1393 xhci_dbg(xhci
, "set port reset, actual port %d-%d status = 0x%x\n",
1394 hcd
->self
.busnum
, wIndex
+ 1, temp
);
1396 case USB_PORT_FEAT_REMOTE_WAKE_MASK
:
1397 xhci_set_remote_wake_mask(xhci
, ports
[wIndex
],
1399 temp
= readl(ports
[wIndex
]->addr
);
1400 xhci_dbg(xhci
, "set port remote wake mask, actual port %d-%d status = 0x%x\n",
1401 hcd
->self
.busnum
, wIndex
+ 1, temp
);
1403 case USB_PORT_FEAT_BH_PORT_RESET
:
1405 writel(temp
, ports
[wIndex
]->addr
);
1406 temp
= readl(ports
[wIndex
]->addr
);
1408 case USB_PORT_FEAT_U1_TIMEOUT
:
1409 if (hcd
->speed
< HCD_USB3
)
1411 temp
= readl(ports
[wIndex
]->addr
+ PORTPMSC
);
1412 temp
&= ~PORT_U1_TIMEOUT_MASK
;
1413 temp
|= PORT_U1_TIMEOUT(timeout
);
1414 writel(temp
, ports
[wIndex
]->addr
+ PORTPMSC
);
1416 case USB_PORT_FEAT_U2_TIMEOUT
:
1417 if (hcd
->speed
< HCD_USB3
)
1419 temp
= readl(ports
[wIndex
]->addr
+ PORTPMSC
);
1420 temp
&= ~PORT_U2_TIMEOUT_MASK
;
1421 temp
|= PORT_U2_TIMEOUT(timeout
);
1422 writel(temp
, ports
[wIndex
]->addr
+ PORTPMSC
);
1424 case USB_PORT_FEAT_TEST
:
1425 /* 4.19.6 Port Test Modes (USB2 Test Mode) */
1426 if (hcd
->speed
!= HCD_USB2
)
1428 if (test_mode
> USB_TEST_FORCE_ENABLE
||
1429 test_mode
< USB_TEST_J
)
1431 retval
= xhci_enter_test_mode(xhci
, test_mode
, wIndex
,
1437 /* unblock any posted writes */
1438 temp
= readl(ports
[wIndex
]->addr
);
1440 case ClearPortFeature
:
1441 if (!wIndex
|| wIndex
> max_ports
)
1444 temp
= readl(ports
[wIndex
]->addr
);
1445 if (temp
== ~(u32
)0) {
1450 /* FIXME: What new port features do we need to support? */
1451 temp
= xhci_port_state_to_neutral(temp
);
1453 case USB_PORT_FEAT_SUSPEND
:
1454 temp
= readl(ports
[wIndex
]->addr
);
1455 xhci_dbg(xhci
, "clear USB_PORT_FEAT_SUSPEND\n");
1456 xhci_dbg(xhci
, "PORTSC %04x\n", temp
);
1457 if (temp
& PORT_RESET
)
1459 if ((temp
& PORT_PLS_MASK
) == XDEV_U3
) {
1460 if ((temp
& PORT_PE
) == 0)
1463 set_bit(wIndex
, &bus_state
->resuming_ports
);
1464 usb_hcd_start_port_resume(&hcd
->self
, wIndex
);
1465 xhci_set_link_state(xhci
, ports
[wIndex
],
1467 spin_unlock_irqrestore(&xhci
->lock
, flags
);
1468 msleep(USB_RESUME_TIMEOUT
);
1469 spin_lock_irqsave(&xhci
->lock
, flags
);
1470 xhci_set_link_state(xhci
, ports
[wIndex
],
1472 clear_bit(wIndex
, &bus_state
->resuming_ports
);
1473 usb_hcd_end_port_resume(&hcd
->self
, wIndex
);
1475 bus_state
->port_c_suspend
|= 1 << wIndex
;
1477 slot_id
= xhci_find_slot_id_by_port(hcd
, xhci
,
1480 xhci_dbg(xhci
, "slot_id is zero\n");
1483 xhci_ring_device(xhci
, slot_id
);
1485 case USB_PORT_FEAT_C_SUSPEND
:
1486 bus_state
->port_c_suspend
&= ~(1 << wIndex
);
1488 case USB_PORT_FEAT_C_RESET
:
1489 case USB_PORT_FEAT_C_BH_PORT_RESET
:
1490 case USB_PORT_FEAT_C_CONNECTION
:
1491 case USB_PORT_FEAT_C_OVER_CURRENT
:
1492 case USB_PORT_FEAT_C_ENABLE
:
1493 case USB_PORT_FEAT_C_PORT_LINK_STATE
:
1494 case USB_PORT_FEAT_C_PORT_CONFIG_ERROR
:
1495 xhci_clear_port_change_bit(xhci
, wValue
, wIndex
,
1496 ports
[wIndex
]->addr
, temp
);
1498 case USB_PORT_FEAT_ENABLE
:
1499 xhci_disable_port(hcd
, xhci
, wIndex
,
1500 ports
[wIndex
]->addr
, temp
);
1502 case USB_PORT_FEAT_POWER
:
1503 xhci_set_port_power(xhci
, hcd
, wIndex
, false, &flags
);
1505 case USB_PORT_FEAT_TEST
:
1506 retval
= xhci_exit_test_mode(xhci
);
1514 /* "stall" on error */
1517 spin_unlock_irqrestore(&xhci
->lock
, flags
);
1522 * Returns 0 if the status hasn't changed, or the number of bytes in buf.
1523 * Ports are 0-indexed from the HCD point of view,
1524 * and 1-indexed from the USB core pointer of view.
1526 * Note that the status change bits will be cleared as soon as a port status
1527 * change event is generated, so we use the saved status from that event.
1529 int xhci_hub_status_data(struct usb_hcd
*hcd
, char *buf
)
1531 unsigned long flags
;
1535 struct xhci_hcd
*xhci
= hcd_to_xhci(hcd
);
1537 struct xhci_bus_state
*bus_state
;
1538 bool reset_change
= false;
1539 struct xhci_hub
*rhub
;
1540 struct xhci_port
**ports
;
1542 rhub
= xhci_get_rhub(hcd
);
1543 ports
= rhub
->ports
;
1544 max_ports
= rhub
->num_ports
;
1545 bus_state
= &rhub
->bus_state
;
1547 /* Initial status is no changes */
1548 retval
= (max_ports
+ 8) / 8;
1549 memset(buf
, 0, retval
);
1552 * Inform the usbcore about resume-in-progress by returning
1553 * a non-zero value even if there are no status changes.
1555 status
= bus_state
->resuming_ports
;
1557 mask
= PORT_CSC
| PORT_PEC
| PORT_OCC
| PORT_PLC
| PORT_WRC
| PORT_CEC
;
1559 spin_lock_irqsave(&xhci
->lock
, flags
);
1560 /* For each port, did anything change? If so, set that bit in buf. */
1561 for (i
= 0; i
< max_ports
; i
++) {
1562 temp
= readl(ports
[i
]->addr
);
1563 if (temp
== ~(u32
)0) {
1568 trace_xhci_hub_status_data(i
, temp
);
1570 if ((temp
& mask
) != 0 ||
1571 (bus_state
->port_c_suspend
& 1 << i
) ||
1572 (bus_state
->resume_done
[i
] && time_after_eq(
1573 jiffies
, bus_state
->resume_done
[i
]))) {
1574 buf
[(i
+ 1) / 8] |= 1 << (i
+ 1) % 8;
1577 if ((temp
& PORT_RC
))
1578 reset_change
= true;
1582 if (!status
&& !reset_change
) {
1583 xhci_dbg(xhci
, "%s: stopping port polling.\n", __func__
);
1584 clear_bit(HCD_FLAG_POLL_RH
, &hcd
->flags
);
1586 spin_unlock_irqrestore(&xhci
->lock
, flags
);
1587 return status
? retval
: 0;
1592 int xhci_bus_suspend(struct usb_hcd
*hcd
)
1594 struct xhci_hcd
*xhci
= hcd_to_xhci(hcd
);
1595 int max_ports
, port_index
;
1596 struct xhci_bus_state
*bus_state
;
1597 unsigned long flags
;
1598 struct xhci_hub
*rhub
;
1599 struct xhci_port
**ports
;
1600 u32 portsc_buf
[USB_MAXCHILDREN
];
1603 rhub
= xhci_get_rhub(hcd
);
1604 ports
= rhub
->ports
;
1605 max_ports
= rhub
->num_ports
;
1606 bus_state
= &rhub
->bus_state
;
1607 wake_enabled
= hcd
->self
.root_hub
->do_remote_wakeup
;
1609 spin_lock_irqsave(&xhci
->lock
, flags
);
1612 if (bus_state
->resuming_ports
|| /* USB2 */
1613 bus_state
->port_remote_wakeup
) { /* USB3 */
1614 spin_unlock_irqrestore(&xhci
->lock
, flags
);
1615 xhci_dbg(xhci
, "suspend failed because a port is resuming\n");
1620 * Prepare ports for suspend, but don't write anything before all ports
1621 * are checked and we know bus suspend can proceed
1623 bus_state
->bus_suspended
= 0;
1624 port_index
= max_ports
;
1625 while (port_index
--) {
1629 t1
= readl(ports
[port_index
]->addr
);
1630 t2
= xhci_port_state_to_neutral(t1
);
1631 portsc_buf
[port_index
] = 0;
1634 * Give a USB3 port in link training time to finish, but don't
1635 * prevent suspend as port might be stuck
1637 if ((hcd
->speed
>= HCD_USB3
) && retries
-- &&
1638 (t1
& PORT_PLS_MASK
) == XDEV_POLLING
) {
1639 spin_unlock_irqrestore(&xhci
->lock
, flags
);
1640 msleep(XHCI_PORT_POLLING_LFPS_TIME
);
1641 spin_lock_irqsave(&xhci
->lock
, flags
);
1642 xhci_dbg(xhci
, "port %d-%d polling in bus suspend, waiting\n",
1643 hcd
->self
.busnum
, port_index
+ 1);
1646 /* bail out if port detected a over-current condition */
1648 bus_state
->bus_suspended
= 0;
1649 spin_unlock_irqrestore(&xhci
->lock
, flags
);
1650 xhci_dbg(xhci
, "Bus suspend bailout, port over-current detected\n");
1653 /* suspend ports in U0, or bail out for new connect changes */
1654 if ((t1
& PORT_PE
) && (t1
& PORT_PLS_MASK
) == XDEV_U0
) {
1655 if ((t1
& PORT_CSC
) && wake_enabled
) {
1656 bus_state
->bus_suspended
= 0;
1657 spin_unlock_irqrestore(&xhci
->lock
, flags
);
1658 xhci_dbg(xhci
, "Bus suspend bailout, port connect change\n");
1661 xhci_dbg(xhci
, "port %d-%d not suspended\n",
1662 hcd
->self
.busnum
, port_index
+ 1);
1663 t2
&= ~PORT_PLS_MASK
;
1664 t2
|= PORT_LINK_STROBE
| XDEV_U3
;
1665 set_bit(port_index
, &bus_state
->bus_suspended
);
1667 /* USB core sets remote wake mask for USB 3.0 hubs,
1668 * including the USB 3.0 roothub, but only if CONFIG_PM
1669 * is enabled, so also enable remote wake here.
1672 if (t1
& PORT_CONNECT
) {
1673 t2
|= PORT_WKOC_E
| PORT_WKDISC_E
;
1674 t2
&= ~PORT_WKCONN_E
;
1676 t2
|= PORT_WKOC_E
| PORT_WKCONN_E
;
1677 t2
&= ~PORT_WKDISC_E
;
1680 if ((xhci
->quirks
& XHCI_U2_DISABLE_WAKE
) &&
1681 (hcd
->speed
< HCD_USB3
)) {
1682 if (usb_amd_pt_check_port(hcd
->self
.controller
,
1684 t2
&= ~PORT_WAKE_BITS
;
1687 t2
&= ~PORT_WAKE_BITS
;
1689 t1
= xhci_port_state_to_neutral(t1
);
1691 portsc_buf
[port_index
] = t2
;
1694 /* write port settings, stopping and suspending ports if needed */
1695 port_index
= max_ports
;
1696 while (port_index
--) {
1697 if (!portsc_buf
[port_index
])
1699 if (test_bit(port_index
, &bus_state
->bus_suspended
)) {
1702 slot_id
= xhci_find_slot_id_by_port(hcd
, xhci
,
1705 spin_unlock_irqrestore(&xhci
->lock
, flags
);
1706 xhci_stop_device(xhci
, slot_id
, 1);
1707 spin_lock_irqsave(&xhci
->lock
, flags
);
1710 writel(portsc_buf
[port_index
], ports
[port_index
]->addr
);
1712 hcd
->state
= HC_STATE_SUSPENDED
;
1713 bus_state
->next_statechange
= jiffies
+ msecs_to_jiffies(10);
1714 spin_unlock_irqrestore(&xhci
->lock
, flags
);
1716 if (bus_state
->bus_suspended
)
1717 usleep_range(5000, 10000);
1723 * Workaround for missing Cold Attach Status (CAS) if device re-plugged in S3.
1724 * warm reset a USB3 device stuck in polling or compliance mode after resume.
1725 * See Intel 100/c230 series PCH specification update Doc #332692-006 Errata #8
1727 static bool xhci_port_missing_cas_quirk(struct xhci_port
*port
)
1731 portsc
= readl(port
->addr
);
1733 /* if any of these are set we are not stuck */
1734 if (portsc
& (PORT_CONNECT
| PORT_CAS
))
1737 if (((portsc
& PORT_PLS_MASK
) != XDEV_POLLING
) &&
1738 ((portsc
& PORT_PLS_MASK
) != XDEV_COMP_MODE
))
1741 /* clear wakeup/change bits, and do a warm port reset */
1742 portsc
&= ~(PORT_RWC_BITS
| PORT_CEC
| PORT_WAKE_BITS
);
1744 writel(portsc
, port
->addr
);
1750 int xhci_bus_resume(struct usb_hcd
*hcd
)
1752 struct xhci_hcd
*xhci
= hcd_to_xhci(hcd
);
1753 struct xhci_bus_state
*bus_state
;
1754 unsigned long flags
;
1755 int max_ports
, port_index
;
1760 struct xhci_hub
*rhub
;
1761 struct xhci_port
**ports
;
1763 rhub
= xhci_get_rhub(hcd
);
1764 ports
= rhub
->ports
;
1765 max_ports
= rhub
->num_ports
;
1766 bus_state
= &rhub
->bus_state
;
1768 if (time_before(jiffies
, bus_state
->next_statechange
))
1771 spin_lock_irqsave(&xhci
->lock
, flags
);
1772 if (!HCD_HW_ACCESSIBLE(hcd
)) {
1773 spin_unlock_irqrestore(&xhci
->lock
, flags
);
1777 /* delay the irqs */
1778 temp
= readl(&xhci
->op_regs
->command
);
1780 writel(temp
, &xhci
->op_regs
->command
);
1782 /* bus specific resume for ports we suspended at bus_suspend */
1783 if (hcd
->speed
>= HCD_USB3
)
1784 next_state
= XDEV_U0
;
1786 next_state
= XDEV_RESUME
;
1788 port_index
= max_ports
;
1789 while (port_index
--) {
1790 portsc
= readl(ports
[port_index
]->addr
);
1792 /* warm reset CAS limited ports stuck in polling/compliance */
1793 if ((xhci
->quirks
& XHCI_MISSING_CAS
) &&
1794 (hcd
->speed
>= HCD_USB3
) &&
1795 xhci_port_missing_cas_quirk(ports
[port_index
])) {
1796 xhci_dbg(xhci
, "reset stuck port %d-%d\n",
1797 hcd
->self
.busnum
, port_index
+ 1);
1798 clear_bit(port_index
, &bus_state
->bus_suspended
);
1801 /* resume if we suspended the link, and it is still suspended */
1802 if (test_bit(port_index
, &bus_state
->bus_suspended
))
1803 switch (portsc
& PORT_PLS_MASK
) {
1805 portsc
= xhci_port_state_to_neutral(portsc
);
1806 portsc
&= ~PORT_PLS_MASK
;
1807 portsc
|= PORT_LINK_STROBE
| next_state
;
1810 /* resume already initiated */
1813 /* not in a resumeable state, ignore it */
1814 clear_bit(port_index
,
1815 &bus_state
->bus_suspended
);
1818 /* disable wake for all ports, write new link state if needed */
1819 portsc
&= ~(PORT_RWC_BITS
| PORT_CEC
| PORT_WAKE_BITS
);
1820 writel(portsc
, ports
[port_index
]->addr
);
1823 /* USB2 specific resume signaling delay and U0 link state transition */
1824 if (hcd
->speed
< HCD_USB3
) {
1825 if (bus_state
->bus_suspended
) {
1826 spin_unlock_irqrestore(&xhci
->lock
, flags
);
1827 msleep(USB_RESUME_TIMEOUT
);
1828 spin_lock_irqsave(&xhci
->lock
, flags
);
1830 for_each_set_bit(port_index
, &bus_state
->bus_suspended
,
1832 /* Clear PLC to poll it later for U0 transition */
1833 xhci_test_and_clear_bit(xhci
, ports
[port_index
],
1835 xhci_set_link_state(xhci
, ports
[port_index
], XDEV_U0
);
1839 /* poll for U0 link state complete, both USB2 and USB3 */
1840 for_each_set_bit(port_index
, &bus_state
->bus_suspended
, BITS_PER_LONG
) {
1841 sret
= xhci_handshake(ports
[port_index
]->addr
, PORT_PLC
,
1842 PORT_PLC
, 10 * 1000);
1844 xhci_warn(xhci
, "port %d-%d resume PLC timeout\n",
1845 hcd
->self
.busnum
, port_index
+ 1);
1848 xhci_test_and_clear_bit(xhci
, ports
[port_index
], PORT_PLC
);
1849 slot_id
= xhci_find_slot_id_by_port(hcd
, xhci
, port_index
+ 1);
1851 xhci_ring_device(xhci
, slot_id
);
1853 (void) readl(&xhci
->op_regs
->command
);
1855 bus_state
->next_statechange
= jiffies
+ msecs_to_jiffies(5);
1856 /* re-enable irqs */
1857 temp
= readl(&xhci
->op_regs
->command
);
1859 writel(temp
, &xhci
->op_regs
->command
);
1860 temp
= readl(&xhci
->op_regs
->command
);
1862 spin_unlock_irqrestore(&xhci
->lock
, flags
);
1866 unsigned long xhci_get_resuming_ports(struct usb_hcd
*hcd
)
1868 struct xhci_hub
*rhub
= xhci_get_rhub(hcd
);
1870 /* USB3 port wakeups are reported via usb_wakeup_notification() */
1871 return rhub
->bus_state
.resuming_ports
; /* USB2 ports only */
1874 #endif /* CONFIG_PM */