drivers/usb/musb/davinci.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /*
   3  * Copyright (C) 2005-2006 by Texas Instruments
   4  */
   5
   6 #ifndef __MUSB_HDRDF_H__
   7 #define __MUSB_HDRDF_H__
   8
   9 /*
  10  * DaVinci-specific definitions
  11  */
  12
  13 /* Integrated highspeed/otg PHY */
  14 #define USBPHY_CTL_PADDR        0x01c40034
  15 #define USBPHY_DATAPOL          BIT(11) /* (dm355) switch D+/D- */
  16 #define USBPHY_PHYCLKGD         BIT(8)
  17 #define USBPHY_SESNDEN          BIT(7)  /* v(sess_end) comparator */
  18 #define USBPHY_VBDTCTEN         BIT(6)  /* v(bus) comparator */
  19 #define USBPHY_VBUSSENS         BIT(5)  /* (dm355,ro) is vbus > 0.5V */
  20 #define USBPHY_PHYPLLON         BIT(4)  /* override pll suspend */
  21 #define USBPHY_CLKO1SEL         BIT(3)
  22 #define USBPHY_OSCPDWN          BIT(2)
  23 #define USBPHY_OTGPDWN          BIT(1)
  24 #define USBPHY_PHYPDWN          BIT(0)
  25
  26 #define DM355_DEEPSLEEP_PADDR   0x01c40048
  27 #define DRVVBUS_FORCE           BIT(2)
  28 #define DRVVBUS_OVERRIDE        BIT(1)
  29
  30 /* For now include usb OTG module registers here */
  31 #define DAVINCI_USB_VERSION_REG         0x00
  32 #define DAVINCI_USB_CTRL_REG            0x04
  33 #define DAVINCI_USB_STAT_REG            0x08
  34 #define DAVINCI_RNDIS_REG               0x10
  35 #define DAVINCI_AUTOREQ_REG             0x14
  36 #define DAVINCI_USB_INT_SOURCE_REG      0x20
  37 #define DAVINCI_USB_INT_SET_REG         0x24
  38 #define DAVINCI_USB_INT_SRC_CLR_REG     0x28
  39 #define DAVINCI_USB_INT_MASK_REG        0x2c
  40 #define DAVINCI_USB_INT_MASK_SET_REG    0x30
  41 #define DAVINCI_USB_INT_MASK_CLR_REG    0x34
  42 #define DAVINCI_USB_INT_SRC_MASKED_REG  0x38
  43 #define DAVINCI_USB_EOI_REG             0x3c
  44 #define DAVINCI_USB_EOI_INTVEC          0x40
  45
  46 /* BEGIN CPPI-generic (?) */
  47
  48 /* CPPI related registers */
  49 #define DAVINCI_TXCPPI_CTRL_REG         0x80
  50 #define DAVINCI_TXCPPI_TEAR_REG         0x84
  51 #define DAVINCI_CPPI_EOI_REG            0x88
  52 #define DAVINCI_CPPI_INTVEC_REG         0x8c
  53 #define DAVINCI_TXCPPI_MASKED_REG       0x90
  54 #define DAVINCI_TXCPPI_RAW_REG          0x94
  55 #define DAVINCI_TXCPPI_INTENAB_REG      0x98
  56 #define DAVINCI_TXCPPI_INTCLR_REG       0x9c
  57
  58 #define DAVINCI_RXCPPI_CTRL_REG         0xC0
  59 #define DAVINCI_RXCPPI_MASKED_REG       0xD0
  60 #define DAVINCI_RXCPPI_RAW_REG          0xD4
  61 #define DAVINCI_RXCPPI_INTENAB_REG      0xD8
  62 #define DAVINCI_RXCPPI_INTCLR_REG       0xDC
  63
  64 #define DAVINCI_RXCPPI_BUFCNT0_REG      0xE0
  65 #define DAVINCI_RXCPPI_BUFCNT1_REG      0xE4
  66 #define DAVINCI_RXCPPI_BUFCNT2_REG      0xE8
  67 #define DAVINCI_RXCPPI_BUFCNT3_REG      0xEC
  68
  69 /* CPPI state RAM entries */
  70 #define DAVINCI_CPPI_STATERAM_BASE_OFFSET   0x100
  71
  72 #define DAVINCI_TXCPPI_STATERAM_OFFSET(chnum) \
  73         (DAVINCI_CPPI_STATERAM_BASE_OFFSET +       ((chnum) * 0x40))
  74 #define DAVINCI_RXCPPI_STATERAM_OFFSET(chnum) \
  75         (DAVINCI_CPPI_STATERAM_BASE_OFFSET + 0x20 + ((chnum) * 0x40))
  76
  77 /* CPPI masks */
  78 #define DAVINCI_DMA_CTRL_ENABLE         1
  79 #define DAVINCI_DMA_CTRL_DISABLE        0
  80
  81 #define DAVINCI_DMA_ALL_CHANNELS_ENABLE 0xF
  82 #define DAVINCI_DMA_ALL_CHANNELS_DISABLE 0xF
  83
  84 /* END CPPI-generic (?) */
  85
  86 #define DAVINCI_USB_TX_ENDPTS_MASK      0x1f            /* ep0 + 4 tx */
  87 #define DAVINCI_USB_RX_ENDPTS_MASK      0x1e            /* 4 rx */
  88
  89 #define DAVINCI_USB_USBINT_SHIFT        16
  90 #define DAVINCI_USB_TXINT_SHIFT         0
  91 #define DAVINCI_USB_RXINT_SHIFT         8
  92
  93 #define DAVINCI_INTR_DRVVBUS            0x0100
  94
  95 #define DAVINCI_USB_USBINT_MASK         0x01ff0000      /* 8 Mentor, DRVVBUS */
  96 #define DAVINCI_USB_TXINT_MASK \
  97         (DAVINCI_USB_TX_ENDPTS_MASK << DAVINCI_USB_TXINT_SHIFT)
  98 #define DAVINCI_USB_RXINT_MASK \
  99         (DAVINCI_USB_RX_ENDPTS_MASK << DAVINCI_USB_RXINT_SHIFT)
 100
 101 #define DAVINCI_BASE_OFFSET             0x400
 102
 103 #endif  /* __MUSB_HDRDF_H__ */