?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
Merge tag 'trace-v5.11-rc2' of git://git.kernel.org/pub/scm/linux/kernel/git/rostedt...
[linux/fpc-iii.git] / drivers / usb / musb / tusb6010.c
blobc4293769220793bc8ddab886bb8d82bdd0c854fe
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * TUSB6010 USB 2.0 OTG Dual Role controller
4 *
5 * Copyright (C) 2006 Nokia Corporation
6 * Tony Lindgren <tony@atomide.com>
7 *
8 * Notes:
9 * - Driver assumes that interface to external host (main CPU) is
10 * configured for NOR FLASH interface instead of VLYNQ serial
11 * interface.
12 */
13
14 #include <linux/module.h>
15 #include <linux/kernel.h>
16 #include <linux/errno.h>
17 #include <linux/err.h>
18 #include <linux/prefetch.h>
19 #include <linux/usb.h>
20 #include <linux/irq.h>
21 #include <linux/io.h>
22 #include <linux/device.h>
23 #include <linux/platform_device.h>
24 #include <linux/dma-mapping.h>
25 #include <linux/usb/usb_phy_generic.h>
26
27 #include "musb_core.h"
28
29 struct tusb6010_glue {
30 struct device *dev;
31 struct platform_device *musb;
32 struct platform_device *phy;
33 };
34
35 static void tusb_musb_set_vbus(struct musb *musb, int is_on);
36
37 #define TUSB_REV_MAJOR(reg_val) ((reg_val >> 4) & 0xf)
38 #define TUSB_REV_MINOR(reg_val) (reg_val & 0xf)
39
40 /*
41 * Checks the revision. We need to use the DMA register as 3.0 does not
42 * have correct versions for TUSB_PRCM_REV or TUSB_INT_CTRL_REV.
43 */
44 static u8 tusb_get_revision(struct musb *musb)
45 {
46 void __iomem *tbase = musb->ctrl_base;
47 u32 die_id;
48 u8 rev;
49
50 rev = musb_readl(tbase, TUSB_DMA_CTRL_REV) & 0xff;
51 if (TUSB_REV_MAJOR(rev) == 3) {
52 die_id = TUSB_DIDR1_HI_CHIP_REV(musb_readl(tbase,
53 TUSB_DIDR1_HI));
54 if (die_id >= TUSB_DIDR1_HI_REV_31)
55 rev |= 1;
56 }
57
58 return rev;
59 }
60
61 static void tusb_print_revision(struct musb *musb)
62 {
63 void __iomem *tbase = musb->ctrl_base;
64 u8 rev;
65
66 rev = musb->tusb_revision;
67
68 pr_info("tusb: %s%i.%i %s%i.%i %s%i.%i %s%i.%i %s%i %s%i.%i\n",
69 "prcm",
70 TUSB_REV_MAJOR(musb_readl(tbase, TUSB_PRCM_REV)),
71 TUSB_REV_MINOR(musb_readl(tbase, TUSB_PRCM_REV)),
72 "int",
73 TUSB_REV_MAJOR(musb_readl(tbase, TUSB_INT_CTRL_REV)),
74 TUSB_REV_MINOR(musb_readl(tbase, TUSB_INT_CTRL_REV)),
75 "gpio",
76 TUSB_REV_MAJOR(musb_readl(tbase, TUSB_GPIO_REV)),
77 TUSB_REV_MINOR(musb_readl(tbase, TUSB_GPIO_REV)),
78 "dma",
79 TUSB_REV_MAJOR(musb_readl(tbase, TUSB_DMA_CTRL_REV)),
80 TUSB_REV_MINOR(musb_readl(tbase, TUSB_DMA_CTRL_REV)),
81 "dieid",
82 TUSB_DIDR1_HI_CHIP_REV(musb_readl(tbase, TUSB_DIDR1_HI)),
83 "rev",
84 TUSB_REV_MAJOR(rev), TUSB_REV_MINOR(rev));
85 }
86
87 #define WBUS_QUIRK_MASK (TUSB_PHY_OTG_CTRL_TESTM2 | TUSB_PHY_OTG_CTRL_TESTM1 \
88 | TUSB_PHY_OTG_CTRL_TESTM0)
89
90 /*
91 * Workaround for spontaneous WBUS wake-up issue #2 for tusb3.0.
92 * Disables power detection in PHY for the duration of idle.
93 */
94 static void tusb_wbus_quirk(struct musb *musb, int enabled)
95 {
96 void __iomem *tbase = musb->ctrl_base;
97 static u32 phy_otg_ctrl, phy_otg_ena;
98 u32 tmp;
99
100 if (enabled) {
101 phy_otg_ctrl = musb_readl(tbase, TUSB_PHY_OTG_CTRL);
102 phy_otg_ena = musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE);
103 tmp = TUSB_PHY_OTG_CTRL_WRPROTECT
104 | phy_otg_ena | WBUS_QUIRK_MASK;
105 musb_writel(tbase, TUSB_PHY_OTG_CTRL, tmp);
106 tmp = phy_otg_ena & ~WBUS_QUIRK_MASK;
107 tmp |= TUSB_PHY_OTG_CTRL_WRPROTECT | TUSB_PHY_OTG_CTRL_TESTM2;
108 musb_writel(tbase, TUSB_PHY_OTG_CTRL_ENABLE, tmp);
109 dev_dbg(musb->controller, "Enabled tusb wbus quirk ctrl %08x ena %08x\n",
110 musb_readl(tbase, TUSB_PHY_OTG_CTRL),
111 musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE));
112 } else if (musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE)
113 & TUSB_PHY_OTG_CTRL_TESTM2) {
114 tmp = TUSB_PHY_OTG_CTRL_WRPROTECT | phy_otg_ctrl;
115 musb_writel(tbase, TUSB_PHY_OTG_CTRL, tmp);
116 tmp = TUSB_PHY_OTG_CTRL_WRPROTECT | phy_otg_ena;
117 musb_writel(tbase, TUSB_PHY_OTG_CTRL_ENABLE, tmp);
118 dev_dbg(musb->controller, "Disabled tusb wbus quirk ctrl %08x ena %08x\n",
119 musb_readl(tbase, TUSB_PHY_OTG_CTRL),
120 musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE));
121 phy_otg_ctrl = 0;
122 phy_otg_ena = 0;
123 }
124 }
125
126 static u32 tusb_fifo_offset(u8 epnum)
127 {
128 return 0x200 + (epnum * 0x20);
129 }
130
131 static u32 tusb_ep_offset(u8 epnum, u16 offset)
132 {
133 return 0x10 + offset;
134 }
135
136 /* TUSB mapping: "flat" plus ep0 special cases */
137 static void tusb_ep_select(void __iomem *mbase, u8 epnum)
138 {
139 musb_writeb(mbase, MUSB_INDEX, epnum);
140 }
141
142 /*
143 * TUSB6010 doesn't allow 8-bit access; 16-bit access is the minimum.
144 */
145 static u8 tusb_readb(void __iomem *addr, u32 offset)
146 {
147 u16 tmp;
148 u8 val;
149
150 tmp = __raw_readw(addr + (offset & ~1));
151 if (offset & 1)
152 val = (tmp >> 8);
153 else
154 val = tmp & 0xff;
155
156 return val;
157 }
158
159 static void tusb_writeb(void __iomem *addr, u32 offset, u8 data)
160 {
161 u16 tmp;
162
163 tmp = __raw_readw(addr + (offset & ~1));
164 if (offset & 1)
165 tmp = (data << 8) | (tmp & 0xff);
166 else
167 tmp = (tmp & 0xff00) | data;
168
169 __raw_writew(tmp, addr + (offset & ~1));
170 }
171
172 /*
173 * TUSB 6010 may use a parallel bus that doesn't support byte ops;
174 * so both loading and unloading FIFOs need explicit byte counts.
175 */
176
177 static inline void
178 tusb_fifo_write_unaligned(void __iomem *fifo, const u8 *buf, u16 len)
179 {
180 u32 val;
181 int i;
182
183 if (len > 4) {
184 for (i = 0; i < (len >> 2); i++) {
185 memcpy(&val, buf, 4);
186 musb_writel(fifo, 0, val);
187 buf += 4;
188 }
189 len %= 4;
190 }
191 if (len > 0) {
192 /* Write the rest 1 - 3 bytes to FIFO */
193 memcpy(&val, buf, len);
194 musb_writel(fifo, 0, val);
195 }
196 }
197
198 static inline void tusb_fifo_read_unaligned(void __iomem *fifo,
199 void *buf, u16 len)
200 {
201 u32 val;
202 int i;
203
204 if (len > 4) {
205 for (i = 0; i < (len >> 2); i++) {
206 val = musb_readl(fifo, 0);
207 memcpy(buf, &val, 4);
208 buf += 4;
209 }
210 len %= 4;
211 }
212 if (len > 0) {
213 /* Read the rest 1 - 3 bytes from FIFO */
214 val = musb_readl(fifo, 0);
215 memcpy(buf, &val, len);
216 }
217 }
218
219 static void tusb_write_fifo(struct musb_hw_ep *hw_ep, u16 len, const u8 *buf)
220 {
221 struct musb *musb = hw_ep->musb;
222 void __iomem *ep_conf = hw_ep->conf;
223 void __iomem *fifo = hw_ep->fifo;
224 u8 epnum = hw_ep->epnum;
225
226 prefetch(buf);
227
228 dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n",
229 'T', epnum, fifo, len, buf);
230
231 if (epnum)
232 musb_writel(ep_conf, TUSB_EP_TX_OFFSET,
233 TUSB_EP_CONFIG_XFR_SIZE(len));
234 else
235 musb_writel(ep_conf, 0, TUSB_EP0_CONFIG_DIR_TX |
236 TUSB_EP0_CONFIG_XFR_SIZE(len));
237
238 if (likely((0x01 & (unsigned long) buf) == 0)) {
239
240 /* Best case is 32bit-aligned destination address */
241 if ((0x02 & (unsigned long) buf) == 0) {
242 if (len >= 4) {
243 iowrite32_rep(fifo, buf, len >> 2);
244 buf += (len & ~0x03);
245 len &= 0x03;
246 }
247 } else {
248 if (len >= 2) {
249 u32 val;
250 int i;
251
252 /* Cannot use writesw, fifo is 32-bit */
253 for (i = 0; i < (len >> 2); i++) {
254 val = (u32)(*(u16 *)buf);
255 buf += 2;
256 val |= (*(u16 *)buf) << 16;
257 buf += 2;
258 musb_writel(fifo, 0, val);
259 }
260 len &= 0x03;
261 }
262 }
263 }
264
265 if (len > 0)
266 tusb_fifo_write_unaligned(fifo, buf, len);
267 }
268
269 static void tusb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *buf)
270 {
271 struct musb *musb = hw_ep->musb;
272 void __iomem *ep_conf = hw_ep->conf;
273 void __iomem *fifo = hw_ep->fifo;
274 u8 epnum = hw_ep->epnum;
275
276 dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n",
277 'R', epnum, fifo, len, buf);
278
279 if (epnum)
280 musb_writel(ep_conf, TUSB_EP_RX_OFFSET,
281 TUSB_EP_CONFIG_XFR_SIZE(len));
282 else
283 musb_writel(ep_conf, 0, TUSB_EP0_CONFIG_XFR_SIZE(len));
284
285 if (likely((0x01 & (unsigned long) buf) == 0)) {
286
287 /* Best case is 32bit-aligned destination address */
288 if ((0x02 & (unsigned long) buf) == 0) {
289 if (len >= 4) {
290 ioread32_rep(fifo, buf, len >> 2);
291 buf += (len & ~0x03);
292 len &= 0x03;
293 }
294 } else {
295 if (len >= 2) {
296 u32 val;
297 int i;
298
299 /* Cannot use readsw, fifo is 32-bit */
300 for (i = 0; i < (len >> 2); i++) {
301 val = musb_readl(fifo, 0);
302 *(u16 *)buf = (u16)(val & 0xffff);
303 buf += 2;
304 *(u16 *)buf = (u16)(val >> 16);
305 buf += 2;
306 }
307 len &= 0x03;
308 }
309 }
310 }
311
312 if (len > 0)
313 tusb_fifo_read_unaligned(fifo, buf, len);
314 }
315
316 static struct musb *the_musb;
317
318 /* This is used by gadget drivers, and OTG transceiver logic, allowing
319 * at most mA current to be drawn from VBUS during a Default-B session
320 * (that is, while VBUS exceeds 4.4V). In Default-A (including pure host
321 * mode), or low power Default-B sessions, something else supplies power.
322 * Caller must take care of locking.
323 */
324 static int tusb_draw_power(struct usb_phy *x, unsigned mA)
325 {
326 struct musb *musb = the_musb;
327 void __iomem *tbase = musb->ctrl_base;
328 u32 reg;
329
330 /* tps65030 seems to consume max 100mA, with maybe 60mA available
331 * (measured on one board) for things other than tps and tusb.
332 *
333 * Boards sharing the CPU clock with CLKIN will need to prevent
334 * certain idle sleep states while the USB link is active.
335 *
336 * REVISIT we could use VBUS to supply only _one_ of { 1.5V, 3.3V }.
337 * The actual current usage would be very board-specific. For now,
338 * it's simpler to just use an aggregate (also board-specific).
339 */
340 if (x->otg->default_a || mA < (musb->min_power << 1))
341 mA = 0;
342
343 reg = musb_readl(tbase, TUSB_PRCM_MNGMT);
344 if (mA) {
345 musb->is_bus_powered = 1;
346 reg |= TUSB_PRCM_MNGMT_15_SW_EN | TUSB_PRCM_MNGMT_33_SW_EN;
347 } else {
348 musb->is_bus_powered = 0;
349 reg &= ~(TUSB_PRCM_MNGMT_15_SW_EN | TUSB_PRCM_MNGMT_33_SW_EN);
350 }
351 musb_writel(tbase, TUSB_PRCM_MNGMT, reg);
352
353 dev_dbg(musb->controller, "draw max %d mA VBUS\n", mA);
354 return 0;
355 }
356
357 /* workaround for issue 13: change clock during chip idle
358 * (to be fixed in rev3 silicon) ... symptoms include disconnect
359 * or looping suspend/resume cycles
360 */
361 static void tusb_set_clock_source(struct musb *musb, unsigned mode)
362 {
363 void __iomem *tbase = musb->ctrl_base;
364 u32 reg;
365
366 reg = musb_readl(tbase, TUSB_PRCM_CONF);
367 reg &= ~TUSB_PRCM_CONF_SYS_CLKSEL(0x3);
368
369 /* 0 = refclk (clkin, XI)
370 * 1 = PHY 60 MHz (internal PLL)
371 * 2 = not supported
372 * 3 = what?
373 */
374 if (mode > 0)
375 reg |= TUSB_PRCM_CONF_SYS_CLKSEL(mode & 0x3);
376
377 musb_writel(tbase, TUSB_PRCM_CONF, reg);
378
379 /* FIXME tusb6010_platform_retime(mode == 0); */
380 }
381
382 /*
383 * Idle TUSB6010 until next wake-up event; NOR access always wakes.
384 * Other code ensures that we idle unless we're connected _and_ the
385 * USB link is not suspended ... and tells us the relevant wakeup
386 * events. SW_EN for voltage is handled separately.
387 */
388 static void tusb_allow_idle(struct musb *musb, u32 wakeup_enables)
389 {
390 void __iomem *tbase = musb->ctrl_base;
391 u32 reg;
392
393 if ((wakeup_enables & TUSB_PRCM_WBUS)
394 && (musb->tusb_revision == TUSB_REV_30))
395 tusb_wbus_quirk(musb, 1);
396
397 tusb_set_clock_source(musb, 0);
398
399 wakeup_enables |= TUSB_PRCM_WNORCS;
400 musb_writel(tbase, TUSB_PRCM_WAKEUP_MASK, ~wakeup_enables);
401
402 /* REVISIT writeup of WID implies that if WID set and ID is grounded,
403 * TUSB_PHY_OTG_CTRL.TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP must be cleared.
404 * Presumably that's mostly to save power, hence WID is immaterial ...
405 */
406
407 reg = musb_readl(tbase, TUSB_PRCM_MNGMT);
408 /* issue 4: when driving vbus, use hipower (vbus_det) comparator */
409 if (is_host_active(musb)) {
410 reg |= TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN;
411 reg &= ~TUSB_PRCM_MNGMT_OTG_SESS_END_EN;
412 } else {
413 reg |= TUSB_PRCM_MNGMT_OTG_SESS_END_EN;
414 reg &= ~TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN;
415 }
416 reg |= TUSB_PRCM_MNGMT_PM_IDLE | TUSB_PRCM_MNGMT_DEV_IDLE;
417 musb_writel(tbase, TUSB_PRCM_MNGMT, reg);
418
419 dev_dbg(musb->controller, "idle, wake on %02x\n", wakeup_enables);
420 }
421
422 /*
423 * Updates cable VBUS status. Caller must take care of locking.
424 */
425 static int tusb_musb_vbus_status(struct musb *musb)
426 {
427 void __iomem *tbase = musb->ctrl_base;
428 u32 otg_stat, prcm_mngmt;
429 int ret = 0;
430
431 otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT);
432 prcm_mngmt = musb_readl(tbase, TUSB_PRCM_MNGMT);
433
434 /* Temporarily enable VBUS detection if it was disabled for
435 * suspend mode. Unless it's enabled otg_stat and devctl will
436 * not show correct VBUS state.
437 */
438 if (!(prcm_mngmt & TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN)) {
439 u32 tmp = prcm_mngmt;
440 tmp |= TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN;
441 musb_writel(tbase, TUSB_PRCM_MNGMT, tmp);
442 otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT);
443 musb_writel(tbase, TUSB_PRCM_MNGMT, prcm_mngmt);
444 }
445
446 if (otg_stat & TUSB_DEV_OTG_STAT_VBUS_VALID)
447 ret = 1;
448
449 return ret;
450 }
451
452 static void musb_do_idle(struct timer_list *t)
453 {
454 struct musb *musb = from_timer(musb, t, dev_timer);
455 unsigned long flags;
456
457 spin_lock_irqsave(&musb->lock, flags);
458
459 switch (musb->xceiv->otg->state) {
460 case OTG_STATE_A_WAIT_BCON:
461 if ((musb->a_wait_bcon != 0)
462 && (musb->idle_timeout == 0
463 || time_after(jiffies, musb->idle_timeout))) {
464 dev_dbg(musb->controller, "Nothing connected %s, turning off VBUS\n",
465 usb_otg_state_string(musb->xceiv->otg->state));
466 }
467 fallthrough;
468 case OTG_STATE_A_IDLE:
469 tusb_musb_set_vbus(musb, 0);
470 break;
471 default:
472 break;
473 }
474
475 if (!musb->is_active) {
476 u32 wakeups;
477
478 /* wait until hub_wq handles port change status */
479 if (is_host_active(musb) && (musb->port1_status >> 16))
480 goto done;
481
482 if (!musb->gadget_driver) {
483 wakeups = 0;
484 } else {
485 wakeups = TUSB_PRCM_WHOSTDISCON
486 | TUSB_PRCM_WBUS
487 | TUSB_PRCM_WVBUS;
488 wakeups |= TUSB_PRCM_WID;
489 }
490 tusb_allow_idle(musb, wakeups);
491 }
492 done:
493 spin_unlock_irqrestore(&musb->lock, flags);
494 }
495
496 /*
497 * Maybe put TUSB6010 into idle mode mode depending on USB link status,
498 * like "disconnected" or "suspended". We'll be woken out of it by
499 * connect, resume, or disconnect.
500 *
501 * Needs to be called as the last function everywhere where there is
502 * register access to TUSB6010 because of NOR flash wake-up.
503 * Caller should own controller spinlock.
504 *
505 * Delay because peripheral enables D+ pullup 3msec after SE0, and
506 * we don't want to treat that full speed J as a wakeup event.
507 * ... peripherals must draw only suspend current after 10 msec.
508 */
509 static void tusb_musb_try_idle(struct musb *musb, unsigned long timeout)
510 {
511 unsigned long default_timeout = jiffies + msecs_to_jiffies(3);
512 static unsigned long last_timer;
513
514 if (timeout == 0)
515 timeout = default_timeout;
516
517 /* Never idle if active, or when VBUS timeout is not set as host */
518 if (musb->is_active || ((musb->a_wait_bcon == 0)
519 && (musb->xceiv->otg->state == OTG_STATE_A_WAIT_BCON))) {
520 dev_dbg(musb->controller, "%s active, deleting timer\n",
521 usb_otg_state_string(musb->xceiv->otg->state));
522 del_timer(&musb->dev_timer);
523 last_timer = jiffies;
524 return;
525 }
526
527 if (time_after(last_timer, timeout)) {
528 if (!timer_pending(&musb->dev_timer))
529 last_timer = timeout;
530 else {
531 dev_dbg(musb->controller, "Longer idle timer already pending, ignoring\n");
532 return;
533 }
534 }
535 last_timer = timeout;
536
537 dev_dbg(musb->controller, "%s inactive, for idle timer for %lu ms\n",
538 usb_otg_state_string(musb->xceiv->otg->state),
539 (unsigned long)jiffies_to_msecs(timeout - jiffies));
540 mod_timer(&musb->dev_timer, timeout);
541 }
542
543 /* ticks of 60 MHz clock */
544 #define DEVCLOCK 60000000
545 #define OTG_TIMER_MS(msecs) ((msecs) \
546 ? (TUSB_DEV_OTG_TIMER_VAL((DEVCLOCK/1000)*(msecs)) \
547 | TUSB_DEV_OTG_TIMER_ENABLE) \
548 : 0)
549
550 static void tusb_musb_set_vbus(struct musb *musb, int is_on)
551 {
552 void __iomem *tbase = musb->ctrl_base;
553 u32 conf, prcm, timer;
554 u8 devctl;
555 struct usb_otg *otg = musb->xceiv->otg;
556
557 /* HDRC controls CPEN, but beware current surges during device
558 * connect. They can trigger transient overcurrent conditions
559 * that must be ignored.
560 */
561
562 prcm = musb_readl(tbase, TUSB_PRCM_MNGMT);
563 conf = musb_readl(tbase, TUSB_DEV_CONF);
564 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
565
566 if (is_on) {
567 timer = OTG_TIMER_MS(OTG_TIME_A_WAIT_VRISE);
568 otg->default_a = 1;
569 musb->xceiv->otg->state = OTG_STATE_A_WAIT_VRISE;
570 devctl |= MUSB_DEVCTL_SESSION;
571
572 conf |= TUSB_DEV_CONF_USB_HOST_MODE;
573 MUSB_HST_MODE(musb);
574 } else {
575 u32 otg_stat;
576
577 timer = 0;
578
579 /* If ID pin is grounded, we want to be a_idle */
580 otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT);
581 if (!(otg_stat & TUSB_DEV_OTG_STAT_ID_STATUS)) {
582 switch (musb->xceiv->otg->state) {
583 case OTG_STATE_A_WAIT_VRISE:
584 case OTG_STATE_A_WAIT_BCON:
585 musb->xceiv->otg->state = OTG_STATE_A_WAIT_VFALL;
586 break;
587 case OTG_STATE_A_WAIT_VFALL:
588 musb->xceiv->otg->state = OTG_STATE_A_IDLE;
589 break;
590 default:
591 musb->xceiv->otg->state = OTG_STATE_A_IDLE;
592 }
593 musb->is_active = 0;
594 otg->default_a = 1;
595 MUSB_HST_MODE(musb);
596 } else {
597 musb->is_active = 0;
598 otg->default_a = 0;
599 musb->xceiv->otg->state = OTG_STATE_B_IDLE;
600 MUSB_DEV_MODE(musb);
601 }
602
603 devctl &= ~MUSB_DEVCTL_SESSION;
604 conf &= ~TUSB_DEV_CONF_USB_HOST_MODE;
605 }
606 prcm &= ~(TUSB_PRCM_MNGMT_15_SW_EN | TUSB_PRCM_MNGMT_33_SW_EN);
607
608 musb_writel(tbase, TUSB_PRCM_MNGMT, prcm);
609 musb_writel(tbase, TUSB_DEV_OTG_TIMER, timer);
610 musb_writel(tbase, TUSB_DEV_CONF, conf);
611 musb_writeb(musb->mregs, MUSB_DEVCTL, devctl);
612
613 dev_dbg(musb->controller, "VBUS %s, devctl %02x otg %3x conf %08x prcm %08x\n",
614 usb_otg_state_string(musb->xceiv->otg->state),
615 musb_readb(musb->mregs, MUSB_DEVCTL),
616 musb_readl(tbase, TUSB_DEV_OTG_STAT),
617 conf, prcm);
618 }
619
620 /*
621 * Sets the mode to OTG, peripheral or host by changing the ID detection.
622 * Caller must take care of locking.
623 *
624 * Note that if a mini-A cable is plugged in the ID line will stay down as
625 * the weak ID pull-up is not able to pull the ID up.
626 */
627 static int tusb_musb_set_mode(struct musb *musb, u8 musb_mode)
628 {
629 void __iomem *tbase = musb->ctrl_base;
630 u32 otg_stat, phy_otg_ctrl, phy_otg_ena, dev_conf;
631
632 otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT);
633 phy_otg_ctrl = musb_readl(tbase, TUSB_PHY_OTG_CTRL);
634 phy_otg_ena = musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE);
635 dev_conf = musb_readl(tbase, TUSB_DEV_CONF);
636
637 switch (musb_mode) {
638
639 case MUSB_HOST: /* Disable PHY ID detect, ground ID */
640 phy_otg_ctrl &= ~TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP;
641 phy_otg_ena |= TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP;
642 dev_conf |= TUSB_DEV_CONF_ID_SEL;
643 dev_conf &= ~TUSB_DEV_CONF_SOFT_ID;
644 break;
645 case MUSB_PERIPHERAL: /* Disable PHY ID detect, keep ID pull-up on */
646 phy_otg_ctrl |= TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP;
647 phy_otg_ena |= TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP;
648 dev_conf |= (TUSB_DEV_CONF_ID_SEL | TUSB_DEV_CONF_SOFT_ID);
649 break;
650 case MUSB_OTG: /* Use PHY ID detection */
651 phy_otg_ctrl |= TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP;
652 phy_otg_ena |= TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP;
653 dev_conf &= ~(TUSB_DEV_CONF_ID_SEL | TUSB_DEV_CONF_SOFT_ID);
654 break;
655
656 default:
657 dev_dbg(musb->controller, "Trying to set mode %i\n", musb_mode);
658 return -EINVAL;
659 }
660
661 musb_writel(tbase, TUSB_PHY_OTG_CTRL,
662 TUSB_PHY_OTG_CTRL_WRPROTECT | phy_otg_ctrl);
663 musb_writel(tbase, TUSB_PHY_OTG_CTRL_ENABLE,
664 TUSB_PHY_OTG_CTRL_WRPROTECT | phy_otg_ena);
665 musb_writel(tbase, TUSB_DEV_CONF, dev_conf);
666
667 otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT);
668 if ((musb_mode == MUSB_PERIPHERAL) &&
669 !(otg_stat & TUSB_DEV_OTG_STAT_ID_STATUS))
670 INFO("Cannot be peripheral with mini-A cable "
671 "otg_stat: %08x\n", otg_stat);
672
673 return 0;
674 }
675
676 static inline unsigned long
677 tusb_otg_ints(struct musb *musb, u32 int_src, void __iomem *tbase)
678 {
679 u32 otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT);
680 unsigned long idle_timeout = 0;
681 struct usb_otg *otg = musb->xceiv->otg;
682
683 /* ID pin */
684 if ((int_src & TUSB_INT_SRC_ID_STATUS_CHNG)) {
685 int default_a;
686
687 default_a = !(otg_stat & TUSB_DEV_OTG_STAT_ID_STATUS);
688 dev_dbg(musb->controller, "Default-%c\n", default_a ? 'A' : 'B');
689 otg->default_a = default_a;
690 tusb_musb_set_vbus(musb, default_a);
691
692 /* Don't allow idling immediately */
693 if (default_a)
694 idle_timeout = jiffies + (HZ * 3);
695 }
696
697 /* VBUS state change */
698 if (int_src & TUSB_INT_SRC_VBUS_SENSE_CHNG) {
699
700 /* B-dev state machine: no vbus ~= disconnect */
701 if (!otg->default_a) {
702 /* ? musb_root_disconnect(musb); */
703 musb->port1_status &=
704 ~(USB_PORT_STAT_CONNECTION
705 | USB_PORT_STAT_ENABLE
706 | USB_PORT_STAT_LOW_SPEED
707 | USB_PORT_STAT_HIGH_SPEED
708 | USB_PORT_STAT_TEST
709 );
710
711 if (otg_stat & TUSB_DEV_OTG_STAT_SESS_END) {
712 dev_dbg(musb->controller, "Forcing disconnect (no interrupt)\n");
713 if (musb->xceiv->otg->state != OTG_STATE_B_IDLE) {
714 /* INTR_DISCONNECT can hide... */
715 musb->xceiv->otg->state = OTG_STATE_B_IDLE;
716 musb->int_usb |= MUSB_INTR_DISCONNECT;
717 }
718 musb->is_active = 0;
719 }
720 dev_dbg(musb->controller, "vbus change, %s, otg %03x\n",
721 usb_otg_state_string(musb->xceiv->otg->state), otg_stat);
722 idle_timeout = jiffies + (1 * HZ);
723 schedule_delayed_work(&musb->irq_work, 0);
724
725 } else /* A-dev state machine */ {
726 dev_dbg(musb->controller, "vbus change, %s, otg %03x\n",
727 usb_otg_state_string(musb->xceiv->otg->state), otg_stat);
728
729 switch (musb->xceiv->otg->state) {
730 case OTG_STATE_A_IDLE:
731 dev_dbg(musb->controller, "Got SRP, turning on VBUS\n");
732 musb_platform_set_vbus(musb, 1);
733
734 /* CONNECT can wake if a_wait_bcon is set */
735 if (musb->a_wait_bcon != 0)
736 musb->is_active = 0;
737 else
738 musb->is_active = 1;
739
740 /*
741 * OPT FS A TD.4.6 needs few seconds for
742 * A_WAIT_VRISE
743 */
744 idle_timeout = jiffies + (2 * HZ);
745
746 break;
747 case OTG_STATE_A_WAIT_VRISE:
748 /* ignore; A-session-valid < VBUS_VALID/2,
749 * we monitor this with the timer
750 */
751 break;
752 case OTG_STATE_A_WAIT_VFALL:
753 /* REVISIT this irq triggers during short
754 * spikes caused by enumeration ...
755 */
756 if (musb->vbuserr_retry) {
757 musb->vbuserr_retry--;
758 tusb_musb_set_vbus(musb, 1);
759 } else {
760 musb->vbuserr_retry
761 = VBUSERR_RETRY_COUNT;
762 tusb_musb_set_vbus(musb, 0);
763 }
764 break;
765 default:
766 break;
767 }
768 }
769 }
770
771 /* OTG timer expiration */
772 if (int_src & TUSB_INT_SRC_OTG_TIMEOUT) {
773 u8 devctl;
774
775 dev_dbg(musb->controller, "%s timer, %03x\n",
776 usb_otg_state_string(musb->xceiv->otg->state), otg_stat);
777
778 switch (musb->xceiv->otg->state) {
779 case OTG_STATE_A_WAIT_VRISE:
780 /* VBUS has probably been valid for a while now,
781 * but may well have bounced out of range a bit
782 */
783 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
784 if (otg_stat & TUSB_DEV_OTG_STAT_VBUS_VALID) {
785 if ((devctl & MUSB_DEVCTL_VBUS)
786 != MUSB_DEVCTL_VBUS) {
787 dev_dbg(musb->controller, "devctl %02x\n", devctl);
788 break;
789 }
790 musb->xceiv->otg->state = OTG_STATE_A_WAIT_BCON;
791 musb->is_active = 0;
792 idle_timeout = jiffies
793 + msecs_to_jiffies(musb->a_wait_bcon);
794 } else {
795 /* REVISIT report overcurrent to hub? */
796 ERR("vbus too slow, devctl %02x\n", devctl);
797 tusb_musb_set_vbus(musb, 0);
798 }
799 break;
800 case OTG_STATE_A_WAIT_BCON:
801 if (musb->a_wait_bcon != 0)
802 idle_timeout = jiffies
803 + msecs_to_jiffies(musb->a_wait_bcon);
804 break;
805 case OTG_STATE_A_SUSPEND:
806 break;
807 case OTG_STATE_B_WAIT_ACON:
808 break;
809 default:
810 break;
811 }
812 }
813 schedule_delayed_work(&musb->irq_work, 0);
814
815 return idle_timeout;
816 }
817
818 static irqreturn_t tusb_musb_interrupt(int irq, void *__hci)
819 {
820 struct musb *musb = __hci;
821 void __iomem *tbase = musb->ctrl_base;
822 unsigned long flags, idle_timeout = 0;
823 u32 int_mask, int_src;
824
825 spin_lock_irqsave(&musb->lock, flags);
826
827 /* Mask all interrupts to allow using both edge and level GPIO irq */
828 int_mask = musb_readl(tbase, TUSB_INT_MASK);
829 musb_writel(tbase, TUSB_INT_MASK, ~TUSB_INT_MASK_RESERVED_BITS);
830
831 int_src = musb_readl(tbase, TUSB_INT_SRC) & ~TUSB_INT_SRC_RESERVED_BITS;
832 dev_dbg(musb->controller, "TUSB IRQ %08x\n", int_src);
833
834 musb->int_usb = (u8) int_src;
835
836 /* Acknowledge wake-up source interrupts */
837 if (int_src & TUSB_INT_SRC_DEV_WAKEUP) {
838 u32 reg;
839 u32 i;
840
841 if (musb->tusb_revision == TUSB_REV_30)
842 tusb_wbus_quirk(musb, 0);
843
844 /* there are issues re-locking the PLL on wakeup ... */
845
846 /* work around issue 8 */
847 for (i = 0xf7f7f7; i > 0xf7f7f7 - 1000; i--) {
848 musb_writel(tbase, TUSB_SCRATCH_PAD, 0);
849 musb_writel(tbase, TUSB_SCRATCH_PAD, i);
850 reg = musb_readl(tbase, TUSB_SCRATCH_PAD);
851 if (reg == i)
852 break;
853 dev_dbg(musb->controller, "TUSB NOR not ready\n");
854 }
855
856 /* work around issue 13 (2nd half) */
857 tusb_set_clock_source(musb, 1);
858
859 reg = musb_readl(tbase, TUSB_PRCM_WAKEUP_SOURCE);
860 musb_writel(tbase, TUSB_PRCM_WAKEUP_CLEAR, reg);
861 if (reg & ~TUSB_PRCM_WNORCS) {
862 musb->is_active = 1;
863 schedule_delayed_work(&musb->irq_work, 0);
864 }
865 dev_dbg(musb->controller, "wake %sactive %02x\n",
866 musb->is_active ? "" : "in", reg);
867
868 /* REVISIT host side TUSB_PRCM_WHOSTDISCON, TUSB_PRCM_WBUS */
869 }
870
871 if (int_src & TUSB_INT_SRC_USB_IP_CONN)
872 del_timer(&musb->dev_timer);
873
874 /* OTG state change reports (annoyingly) not issued by Mentor core */
875 if (int_src & (TUSB_INT_SRC_VBUS_SENSE_CHNG
876 | TUSB_INT_SRC_OTG_TIMEOUT
877 | TUSB_INT_SRC_ID_STATUS_CHNG))
878 idle_timeout = tusb_otg_ints(musb, int_src, tbase);
879
880 /*
881 * Just clear the DMA interrupt if it comes as the completion for both
882 * TX and RX is handled by the DMA callback in tusb6010_omap
883 */
884 if ((int_src & TUSB_INT_SRC_TXRX_DMA_DONE)) {
885 u32 dma_src = musb_readl(tbase, TUSB_DMA_INT_SRC);
886
887 dev_dbg(musb->controller, "DMA IRQ %08x\n", dma_src);
888 musb_writel(tbase, TUSB_DMA_INT_CLEAR, dma_src);
889 }
890
891 /* EP interrupts. In OCP mode tusb6010 mirrors the MUSB interrupts */
892 if (int_src & (TUSB_INT_SRC_USB_IP_TX | TUSB_INT_SRC_USB_IP_RX)) {
893 u32 musb_src = musb_readl(tbase, TUSB_USBIP_INT_SRC);
894
895 musb_writel(tbase, TUSB_USBIP_INT_CLEAR, musb_src);
896 musb->int_rx = (((musb_src >> 16) & 0xffff) << 1);
897 musb->int_tx = (musb_src & 0xffff);
898 } else {
899 musb->int_rx = 0;
900 musb->int_tx = 0;
901 }
902
903 if (int_src & (TUSB_INT_SRC_USB_IP_TX | TUSB_INT_SRC_USB_IP_RX | 0xff))
904 musb_interrupt(musb);
905
906 /* Acknowledge TUSB interrupts. Clear only non-reserved bits */
907 musb_writel(tbase, TUSB_INT_SRC_CLEAR,
908 int_src & ~TUSB_INT_MASK_RESERVED_BITS);
909
910 tusb_musb_try_idle(musb, idle_timeout);
911
912 musb_writel(tbase, TUSB_INT_MASK, int_mask);
913 spin_unlock_irqrestore(&musb->lock, flags);
914
915 return IRQ_HANDLED;
916 }
917
918 static int dma_off;
919
920 /*
921 * Enables TUSB6010. Caller must take care of locking.
922 * REVISIT:
923 * - Check what is unnecessary in MGC_HdrcStart()
924 */
925 static void tusb_musb_enable(struct musb *musb)
926 {
927 void __iomem *tbase = musb->ctrl_base;
928
929 /* Setup TUSB6010 main interrupt mask. Enable all interrupts except SOF.
930 * REVISIT: Enable and deal with TUSB_INT_SRC_USB_IP_SOF */
931 musb_writel(tbase, TUSB_INT_MASK, TUSB_INT_SRC_USB_IP_SOF);
932
933 /* Setup TUSB interrupt, disable DMA and GPIO interrupts */
934 musb_writel(tbase, TUSB_USBIP_INT_MASK, 0);
935 musb_writel(tbase, TUSB_DMA_INT_MASK, 0x7fffffff);
936 musb_writel(tbase, TUSB_GPIO_INT_MASK, 0x1ff);
937
938 /* Clear all subsystem interrups */
939 musb_writel(tbase, TUSB_USBIP_INT_CLEAR, 0x7fffffff);
940 musb_writel(tbase, TUSB_DMA_INT_CLEAR, 0x7fffffff);
941 musb_writel(tbase, TUSB_GPIO_INT_CLEAR, 0x1ff);
942
943 /* Acknowledge pending interrupt(s) */
944 musb_writel(tbase, TUSB_INT_SRC_CLEAR, ~TUSB_INT_MASK_RESERVED_BITS);
945
946 /* Only 0 clock cycles for minimum interrupt de-assertion time and
947 * interrupt polarity active low seems to work reliably here */
948 musb_writel(tbase, TUSB_INT_CTRL_CONF,
949 TUSB_INT_CTRL_CONF_INT_RELCYC(0));
950
951 irq_set_irq_type(musb->nIrq, IRQ_TYPE_LEVEL_LOW);
952
953 /* maybe force into the Default-A OTG state machine */
954 if (!(musb_readl(tbase, TUSB_DEV_OTG_STAT)
955 & TUSB_DEV_OTG_STAT_ID_STATUS))
956 musb_writel(tbase, TUSB_INT_SRC_SET,
957 TUSB_INT_SRC_ID_STATUS_CHNG);
958
959 if (is_dma_capable() && dma_off)
960 printk(KERN_WARNING "%s %s: dma not reactivated\n",
961 __FILE__, __func__);
962 else
963 dma_off = 1;
964 }
965
966 /*
967 * Disables TUSB6010. Caller must take care of locking.
968 */
969 static void tusb_musb_disable(struct musb *musb)
970 {
971 void __iomem *tbase = musb->ctrl_base;
972
973 /* FIXME stop DMA, IRQs, timers, ... */
974
975 /* disable all IRQs */
976 musb_writel(tbase, TUSB_INT_MASK, ~TUSB_INT_MASK_RESERVED_BITS);
977 musb_writel(tbase, TUSB_USBIP_INT_MASK, 0x7fffffff);
978 musb_writel(tbase, TUSB_DMA_INT_MASK, 0x7fffffff);
979 musb_writel(tbase, TUSB_GPIO_INT_MASK, 0x1ff);
980
981 del_timer(&musb->dev_timer);
982
983 if (is_dma_capable() && !dma_off) {
984 printk(KERN_WARNING "%s %s: dma still active\n",
985 __FILE__, __func__);
986 dma_off = 1;
987 }
988 }
989
990 /*
991 * Sets up TUSB6010 CPU interface specific signals and registers
992 * Note: Settings optimized for OMAP24xx
993 */
994 static void tusb_setup_cpu_interface(struct musb *musb)
995 {
996 void __iomem *tbase = musb->ctrl_base;
997
998 /*
999 * Disable GPIO[5:0] pullups (used as output DMA requests)
1000 * Don't disable GPIO[7:6] as they are needed for wake-up.
1001 */
1002 musb_writel(tbase, TUSB_PULLUP_1_CTRL, 0x0000003F);
1003
1004 /* Disable all pullups on NOR IF, DMAREQ0 and DMAREQ1 */
1005 musb_writel(tbase, TUSB_PULLUP_2_CTRL, 0x01FFFFFF);
1006
1007 /* Turn GPIO[5:0] to DMAREQ[5:0] signals */
1008 musb_writel(tbase, TUSB_GPIO_CONF, TUSB_GPIO_CONF_DMAREQ(0x3f));
1009
1010 /* Burst size 16x16 bits, all six DMA requests enabled, DMA request
1011 * de-assertion time 2 system clocks p 62 */
1012 musb_writel(tbase, TUSB_DMA_REQ_CONF,
1013 TUSB_DMA_REQ_CONF_BURST_SIZE(2) |
1014 TUSB_DMA_REQ_CONF_DMA_REQ_EN(0x3f) |
1015 TUSB_DMA_REQ_CONF_DMA_REQ_ASSER(2));
1016
1017 /* Set 0 wait count for synchronous burst access */
1018 musb_writel(tbase, TUSB_WAIT_COUNT, 1);
1019 }
1020
1021 static int tusb_musb_start(struct musb *musb)
1022 {
1023 void __iomem *tbase = musb->ctrl_base;
1024 int ret = 0;
1025 unsigned long flags;
1026 u32 reg;
1027
1028 if (musb->board_set_power)
1029 ret = musb->board_set_power(1);
1030 if (ret != 0) {
1031 printk(KERN_ERR "tusb: Cannot enable TUSB6010\n");
1032 return ret;
1033 }
1034
1035 spin_lock_irqsave(&musb->lock, flags);
1036
1037 if (musb_readl(tbase, TUSB_PROD_TEST_RESET) !=
1038 TUSB_PROD_TEST_RESET_VAL) {
1039 printk(KERN_ERR "tusb: Unable to detect TUSB6010\n");
1040 goto err;
1041 }
1042
1043 musb->tusb_revision = tusb_get_revision(musb);
1044 tusb_print_revision(musb);
1045 if (musb->tusb_revision < 2) {
1046 printk(KERN_ERR "tusb: Unsupported TUSB6010 revision %i\n",
1047 musb->tusb_revision);
1048 goto err;
1049 }
1050
1051 /* The uint bit for "USB non-PDR interrupt enable" has to be 1 when
1052 * NOR FLASH interface is used */
1053 musb_writel(tbase, TUSB_VLYNQ_CTRL, 8);
1054
1055 /* Select PHY free running 60MHz as a system clock */
1056 tusb_set_clock_source(musb, 1);
1057
1058 /* VBus valid timer 1us, disable DFT/Debug and VLYNQ clocks for
1059 * power saving, enable VBus detect and session end comparators,
1060 * enable IDpullup, enable VBus charging */
1061 musb_writel(tbase, TUSB_PRCM_MNGMT,
1062 TUSB_PRCM_MNGMT_VBUS_VALID_TIMER(0xa) |
1063 TUSB_PRCM_MNGMT_VBUS_VALID_FLT_EN |
1064 TUSB_PRCM_MNGMT_OTG_SESS_END_EN |
1065 TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN |
1066 TUSB_PRCM_MNGMT_OTG_ID_PULLUP);
1067 tusb_setup_cpu_interface(musb);
1068
1069 /* simplify: always sense/pullup ID pins, as if in OTG mode */
1070 reg = musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE);
1071 reg |= TUSB_PHY_OTG_CTRL_WRPROTECT | TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP;
1072 musb_writel(tbase, TUSB_PHY_OTG_CTRL_ENABLE, reg);
1073
1074 reg = musb_readl(tbase, TUSB_PHY_OTG_CTRL);
1075 reg |= TUSB_PHY_OTG_CTRL_WRPROTECT | TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP;
1076 musb_writel(tbase, TUSB_PHY_OTG_CTRL, reg);
1077
1078 spin_unlock_irqrestore(&musb->lock, flags);
1079
1080 return 0;
1081
1082 err:
1083 spin_unlock_irqrestore(&musb->lock, flags);
1084
1085 if (musb->board_set_power)
1086 musb->board_set_power(0);
1087
1088 return -ENODEV;
1089 }
1090
1091 static int tusb_musb_init(struct musb *musb)
1092 {
1093 struct platform_device *pdev;
1094 struct resource *mem;
1095 void __iomem *sync = NULL;
1096 int ret;
1097
1098 musb->xceiv = usb_get_phy(USB_PHY_TYPE_USB2);
1099 if (IS_ERR_OR_NULL(musb->xceiv))
1100 return -EPROBE_DEFER;
1101
1102 pdev = to_platform_device(musb->controller);
1103
1104 /* dma address for async dma */
1105 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1106 musb->async = mem->start;
1107
1108 /* dma address for sync dma */
1109 mem = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1110 if (!mem) {
1111 pr_debug("no sync dma resource?\n");
1112 ret = -ENODEV;
1113 goto done;
1114 }
1115 musb->sync = mem->start;
1116
1117 sync = ioremap(mem->start, resource_size(mem));
1118 if (!sync) {
1119 pr_debug("ioremap for sync failed\n");
1120 ret = -ENOMEM;
1121 goto done;
1122 }
1123 musb->sync_va = sync;
1124
1125 /* Offsets from base: VLYNQ at 0x000, MUSB regs at 0x400,
1126 * FIFOs at 0x600, TUSB at 0x800
1127 */
1128 musb->mregs += TUSB_BASE_OFFSET;
1129
1130 ret = tusb_musb_start(musb);
1131 if (ret) {
1132 printk(KERN_ERR "Could not start tusb6010 (%d)\n",
1133 ret);
1134 goto done;
1135 }
1136 musb->isr = tusb_musb_interrupt;
1137
1138 musb->xceiv->set_power = tusb_draw_power;
1139 the_musb = musb;
1140
1141 timer_setup(&musb->dev_timer, musb_do_idle, 0);
1142
1143 done:
1144 if (ret < 0) {
1145 if (sync)
1146 iounmap(sync);
1147
1148 usb_put_phy(musb->xceiv);
1149 }
1150 return ret;
1151 }
1152
1153 static int tusb_musb_exit(struct musb *musb)
1154 {
1155 del_timer_sync(&musb->dev_timer);
1156 the_musb = NULL;
1157
1158 if (musb->board_set_power)
1159 musb->board_set_power(0);
1160
1161 iounmap(musb->sync_va);
1162
1163 usb_put_phy(musb->xceiv);
1164 return 0;
1165 }
1166
1167 static const struct musb_platform_ops tusb_ops = {
1168 .quirks = MUSB_DMA_TUSB_OMAP | MUSB_IN_TUSB |
1169 MUSB_G_NO_SKB_RESERVE,
1170 .init = tusb_musb_init,
1171 .exit = tusb_musb_exit,
1172
1173 .ep_offset = tusb_ep_offset,
1174 .ep_select = tusb_ep_select,
1175 .fifo_offset = tusb_fifo_offset,
1176 .readb = tusb_readb,
1177 .writeb = tusb_writeb,
1178 .read_fifo = tusb_read_fifo,
1179 .write_fifo = tusb_write_fifo,
1180 #ifdef CONFIG_USB_TUSB_OMAP_DMA
1181 .dma_init = tusb_dma_controller_create,
1182 .dma_exit = tusb_dma_controller_destroy,
1183 #endif
1184 .enable = tusb_musb_enable,
1185 .disable = tusb_musb_disable,
1186
1187 .set_mode = tusb_musb_set_mode,
1188 .try_idle = tusb_musb_try_idle,
1189
1190 .vbus_status = tusb_musb_vbus_status,
1191 .set_vbus = tusb_musb_set_vbus,
1192 };
1193
1194 static const struct platform_device_info tusb_dev_info = {
1195 .name = "musb-hdrc",
1196 .id = PLATFORM_DEVID_AUTO,
1197 .dma_mask = DMA_BIT_MASK(32),
1198 };
1199
1200 static int tusb_probe(struct platform_device *pdev)
1201 {
1202 struct resource musb_resources[3];
1203 struct musb_hdrc_platform_data *pdata = dev_get_platdata(&pdev->dev);
1204 struct platform_device *musb;
1205 struct tusb6010_glue *glue;
1206 struct platform_device_info pinfo;
1207 int ret;
1208
1209 glue = devm_kzalloc(&pdev->dev, sizeof(*glue), GFP_KERNEL);
1210 if (!glue)
1211 return -ENOMEM;
1212
1213 glue->dev = &pdev->dev;
1214
1215 pdata->platform_ops = &tusb_ops;
1216
1217 usb_phy_generic_register();
1218 platform_set_drvdata(pdev, glue);
1219
1220 memset(musb_resources, 0x00, sizeof(*musb_resources) *
1221 ARRAY_SIZE(musb_resources));
1222
1223 musb_resources[0].name = pdev->resource[0].name;
1224 musb_resources[0].start = pdev->resource[0].start;
1225 musb_resources[0].end = pdev->resource[0].end;
1226 musb_resources[0].flags = pdev->resource[0].flags;
1227
1228 musb_resources[1].name = pdev->resource[1].name;
1229 musb_resources[1].start = pdev->resource[1].start;
1230 musb_resources[1].end = pdev->resource[1].end;
1231 musb_resources[1].flags = pdev->resource[1].flags;
1232
1233 musb_resources[2].name = pdev->resource[2].name;
1234 musb_resources[2].start = pdev->resource[2].start;
1235 musb_resources[2].end = pdev->resource[2].end;
1236 musb_resources[2].flags = pdev->resource[2].flags;
1237
1238 pinfo = tusb_dev_info;
1239 pinfo.parent = &pdev->dev;
1240 pinfo.res = musb_resources;
1241 pinfo.num_res = ARRAY_SIZE(musb_resources);
1242 pinfo.data = pdata;
1243 pinfo.size_data = sizeof(*pdata);
1244
1245 glue->musb = musb = platform_device_register_full(&pinfo);
1246 if (IS_ERR(musb)) {
1247 ret = PTR_ERR(musb);
1248 dev_err(&pdev->dev, "failed to register musb device: %d\n", ret);
1249 return ret;
1250 }
1251
1252 return 0;
1253 }
1254
1255 static int tusb_remove(struct platform_device *pdev)
1256 {
1257 struct tusb6010_glue *glue = platform_get_drvdata(pdev);
1258
1259 platform_device_unregister(glue->musb);
1260 usb_phy_generic_unregister(glue->phy);
1261
1262 return 0;
1263 }
1264
1265 static struct platform_driver tusb_driver = {
1266 .probe = tusb_probe,
1267 .remove = tusb_remove,
1268 .driver = {
1269 .name = "musb-tusb",
1270 },
1271 };
1272
1273 MODULE_DESCRIPTION("TUSB6010 MUSB Glue Layer");
1274 MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
1275 MODULE_LICENSE("GPL v2");
1276 module_platform_driver(tusb_driver);
Linux with added FPC-III support