drivers/video/fbdev/acornfb.h

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2 /*
   3  *  linux/drivers/video/acornfb.h
   4  *
   5  *  Copyright (C) 1998,1999 Russell King
   6  *
   7  *  Frame buffer code for Acorn platforms
   8  */
   9 #if defined(HAS_VIDC20)
  10 #include <asm/hardware/iomd.h>
  11 #define VIDC_PALETTE_SIZE       256
  12 #define VIDC_NAME               "VIDC20"
  13 #endif
  14
  15 #define EXTEND8(x) ((x)|(x)<<8)
  16 #define EXTEND4(x) ((x)|(x)<<4|(x)<<8|(x)<<12)
  17
  18 struct vidc20_palette {
  19         u_int red:8;
  20         u_int green:8;
  21         u_int blue:8;
  22         u_int ext:4;
  23         u_int unused:4;
  24 };
  25
  26 struct vidc_palette {
  27         u_int red:4;
  28         u_int green:4;
  29         u_int blue:4;
  30         u_int trans:1;
  31         u_int sbz1:13;
  32         u_int reg:4;
  33         u_int sbz2:2;
  34 };
  35
  36 union palette {
  37         struct vidc20_palette   vidc20;
  38         struct vidc_palette     vidc;
  39         u_int   p;
  40 };
  41
  42 struct acornfb_par {
  43         struct device   *dev;
  44         unsigned long   screen_end;
  45         unsigned int    dram_size;
  46         unsigned int    vram_half_sam;
  47         unsigned int    palette_size;
  48           signed int    montype;
  49         unsigned int    using_vram      : 1;
  50         unsigned int    dpms            : 1;
  51
  52         union palette palette[VIDC_PALETTE_SIZE];
  53
  54         u32             pseudo_palette[16];
  55 };
  56
  57 struct vidc_timing {
  58         u_int   h_cycle;
  59         u_int   h_sync_width;
  60         u_int   h_border_start;
  61         u_int   h_display_start;
  62         u_int   h_display_end;
  63         u_int   h_border_end;
  64         u_int   h_interlace;
  65
  66         u_int   v_cycle;
  67         u_int   v_sync_width;
  68         u_int   v_border_start;
  69         u_int   v_display_start;
  70         u_int   v_display_end;
  71         u_int   v_border_end;
  72
  73         u_int   control;
  74
  75         /* VIDC20 only */
  76         u_int   pll_ctl;
  77 };
  78
  79 struct modey_params {
  80         u_int   y_res;
  81         u_int   u_margin;
  82         u_int   b_margin;
  83         u_int   vsync_len;
  84         u_int   vf;
  85 };
  86
  87 struct modex_params {
  88         u_int   x_res;
  89         u_int   l_margin;
  90         u_int   r_margin;
  91         u_int   hsync_len;
  92         u_int   clock;
  93         u_int   hf;
  94         const struct modey_params *modey;
  95 };
  96
  97 #ifdef HAS_VIDC20
  98 /*
  99  * VIDC20 registers
 100  */
 101 #define VIDC20_CTRL             0xe0000000
 102 #define VIDC20_CTRL_PIX_VCLK    (0 << 0)
 103 #define VIDC20_CTRL_PIX_HCLK    (1 << 0)
 104 #define VIDC20_CTRL_PIX_RCLK    (2 << 0)
 105 #define VIDC20_CTRL_PIX_CK      (0 << 2)
 106 #define VIDC20_CTRL_PIX_CK2     (1 << 2)
 107 #define VIDC20_CTRL_PIX_CK3     (2 << 2)
 108 #define VIDC20_CTRL_PIX_CK4     (3 << 2)
 109 #define VIDC20_CTRL_PIX_CK5     (4 << 2)
 110 #define VIDC20_CTRL_PIX_CK6     (5 << 2)
 111 #define VIDC20_CTRL_PIX_CK7     (6 << 2)
 112 #define VIDC20_CTRL_PIX_CK8     (7 << 2)
 113 #define VIDC20_CTRL_1BPP        (0 << 5)
 114 #define VIDC20_CTRL_2BPP        (1 << 5)
 115 #define VIDC20_CTRL_4BPP        (2 << 5)
 116 #define VIDC20_CTRL_8BPP        (3 << 5)
 117 #define VIDC20_CTRL_16BPP       (4 << 5)
 118 #define VIDC20_CTRL_32BPP       (6 << 5)
 119 #define VIDC20_CTRL_FIFO_NS     (0 << 8)
 120 #define VIDC20_CTRL_FIFO_4      (1 << 8)
 121 #define VIDC20_CTRL_FIFO_8      (2 << 8)
 122 #define VIDC20_CTRL_FIFO_12     (3 << 8)
 123 #define VIDC20_CTRL_FIFO_16     (4 << 8)
 124 #define VIDC20_CTRL_FIFO_20     (5 << 8)
 125 #define VIDC20_CTRL_FIFO_24     (6 << 8)
 126 #define VIDC20_CTRL_FIFO_28     (7 << 8)
 127 #define VIDC20_CTRL_INT         (1 << 12)
 128 #define VIDC20_CTRL_DUP         (1 << 13)
 129 #define VIDC20_CTRL_PDOWN       (1 << 14)
 130
 131 #define VIDC20_ECTL             0xc0000000
 132 #define VIDC20_ECTL_REG(x)      ((x) & 0xf3)
 133 #define VIDC20_ECTL_ECK         (1 << 2)
 134 #define VIDC20_ECTL_REDPED      (1 << 8)
 135 #define VIDC20_ECTL_GREENPED    (1 << 9)
 136 #define VIDC20_ECTL_BLUEPED     (1 << 10)
 137 #define VIDC20_ECTL_DAC         (1 << 12)
 138 #define VIDC20_ECTL_LCDGS       (1 << 13)
 139 #define VIDC20_ECTL_HRM         (1 << 14)
 140
 141 #define VIDC20_ECTL_HS_MASK     (3 << 16)
 142 #define VIDC20_ECTL_HS_HSYNC    (0 << 16)
 143 #define VIDC20_ECTL_HS_NHSYNC   (1 << 16)
 144 #define VIDC20_ECTL_HS_CSYNC    (2 << 16)
 145 #define VIDC20_ECTL_HS_NCSYNC   (3 << 16)
 146
 147 #define VIDC20_ECTL_VS_MASK     (3 << 18)
 148 #define VIDC20_ECTL_VS_VSYNC    (0 << 18)
 149 #define VIDC20_ECTL_VS_NVSYNC   (1 << 18)
 150 #define VIDC20_ECTL_VS_CSYNC    (2 << 18)
 151 #define VIDC20_ECTL_VS_NCSYNC   (3 << 18)
 152
 153 #define VIDC20_DCTL             0xf0000000
 154 /* 0-9 = number of words in scanline */
 155 #define VIDC20_DCTL_SNA         (1 << 12)
 156 #define VIDC20_DCTL_HDIS        (1 << 13)
 157 #define VIDC20_DCTL_BUS_NS      (0 << 16)
 158 #define VIDC20_DCTL_BUS_D31_0   (1 << 16)
 159 #define VIDC20_DCTL_BUS_D63_32  (2 << 16)
 160 #define VIDC20_DCTL_BUS_D63_0   (3 << 16)
 161 #define VIDC20_DCTL_VRAM_DIS    (0 << 18)
 162 #define VIDC20_DCTL_VRAM_PXCLK  (1 << 18)
 163 #define VIDC20_DCTL_VRAM_PXCLK2 (2 << 18)
 164 #define VIDC20_DCTL_VRAM_PXCLK4 (3 << 18)
 165
 166 #endif