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Merge tag 'trace-v5.11-rc2' of git://git.kernel.org/pub/scm/linux/kernel/git/rostedt...
[linux/fpc-iii.git] / drivers / video / fbdev / da8xx-fb.c
blobe38c0e3f9c61423e5f506a264bdfbf52dcf76e9d
1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * Copyright (C) 2008-2009 MontaVista Software Inc.
4 * Copyright (C) 2008-2009 Texas Instruments Inc
5 *
6 * Based on the LCD driver for TI Avalanche processors written by
7 * Ajay Singh and Shalom Hai.
8 */
9 #include <linux/module.h>
10 #include <linux/kernel.h>
11 #include <linux/fb.h>
12 #include <linux/dma-mapping.h>
13 #include <linux/device.h>
14 #include <linux/platform_device.h>
15 #include <linux/uaccess.h>
16 #include <linux/pm_runtime.h>
17 #include <linux/interrupt.h>
18 #include <linux/wait.h>
19 #include <linux/clk.h>
20 #include <linux/cpufreq.h>
21 #include <linux/console.h>
22 #include <linux/regulator/consumer.h>
23 #include <linux/spinlock.h>
24 #include <linux/slab.h>
25 #include <linux/delay.h>
26 #include <linux/lcm.h>
27 #include <video/da8xx-fb.h>
28 #include <asm/div64.h>
29
30 #define DRIVER_NAME "da8xx_lcdc"
31
32 #define LCD_VERSION_1 1
33 #define LCD_VERSION_2 2
34
35 /* LCD Status Register */
36 #define LCD_END_OF_FRAME1 BIT(9)
37 #define LCD_END_OF_FRAME0 BIT(8)
38 #define LCD_PL_LOAD_DONE BIT(6)
39 #define LCD_FIFO_UNDERFLOW BIT(5)
40 #define LCD_SYNC_LOST BIT(2)
41 #define LCD_FRAME_DONE BIT(0)
42
43 /* LCD DMA Control Register */
44 #define LCD_DMA_BURST_SIZE(x) ((x) << 4)
45 #define LCD_DMA_BURST_1 0x0
46 #define LCD_DMA_BURST_2 0x1
47 #define LCD_DMA_BURST_4 0x2
48 #define LCD_DMA_BURST_8 0x3
49 #define LCD_DMA_BURST_16 0x4
50 #define LCD_V1_END_OF_FRAME_INT_ENA BIT(2)
51 #define LCD_V2_END_OF_FRAME0_INT_ENA BIT(8)
52 #define LCD_V2_END_OF_FRAME1_INT_ENA BIT(9)
53 #define LCD_DUAL_FRAME_BUFFER_ENABLE BIT(0)
54
55 /* LCD Control Register */
56 #define LCD_CLK_DIVISOR(x) ((x) << 8)
57 #define LCD_RASTER_MODE 0x01
58
59 /* LCD Raster Control Register */
60 #define LCD_PALETTE_LOAD_MODE(x) ((x) << 20)
61 #define PALETTE_AND_DATA 0x00
62 #define PALETTE_ONLY 0x01
63 #define DATA_ONLY 0x02
64
65 #define LCD_MONO_8BIT_MODE BIT(9)
66 #define LCD_RASTER_ORDER BIT(8)
67 #define LCD_TFT_MODE BIT(7)
68 #define LCD_V1_UNDERFLOW_INT_ENA BIT(6)
69 #define LCD_V2_UNDERFLOW_INT_ENA BIT(5)
70 #define LCD_V1_PL_INT_ENA BIT(4)
71 #define LCD_V2_PL_INT_ENA BIT(6)
72 #define LCD_MONOCHROME_MODE BIT(1)
73 #define LCD_RASTER_ENABLE BIT(0)
74 #define LCD_TFT_ALT_ENABLE BIT(23)
75 #define LCD_STN_565_ENABLE BIT(24)
76 #define LCD_V2_DMA_CLK_EN BIT(2)
77 #define LCD_V2_LIDD_CLK_EN BIT(1)
78 #define LCD_V2_CORE_CLK_EN BIT(0)
79 #define LCD_V2_LPP_B10 26
80 #define LCD_V2_TFT_24BPP_MODE BIT(25)
81 #define LCD_V2_TFT_24BPP_UNPACK BIT(26)
82
83 /* LCD Raster Timing 2 Register */
84 #define LCD_AC_BIAS_TRANSITIONS_PER_INT(x) ((x) << 16)
85 #define LCD_AC_BIAS_FREQUENCY(x) ((x) << 8)
86 #define LCD_SYNC_CTRL BIT(25)
87 #define LCD_SYNC_EDGE BIT(24)
88 #define LCD_INVERT_PIXEL_CLOCK BIT(22)
89 #define LCD_INVERT_LINE_CLOCK BIT(21)
90 #define LCD_INVERT_FRAME_CLOCK BIT(20)
91
92 /* LCD Block */
93 #define LCD_PID_REG 0x0
94 #define LCD_CTRL_REG 0x4
95 #define LCD_STAT_REG 0x8
96 #define LCD_RASTER_CTRL_REG 0x28
97 #define LCD_RASTER_TIMING_0_REG 0x2C
98 #define LCD_RASTER_TIMING_1_REG 0x30
99 #define LCD_RASTER_TIMING_2_REG 0x34
100 #define LCD_DMA_CTRL_REG 0x40
101 #define LCD_DMA_FRM_BUF_BASE_ADDR_0_REG 0x44
102 #define LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG 0x48
103 #define LCD_DMA_FRM_BUF_BASE_ADDR_1_REG 0x4C
104 #define LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG 0x50
105
106 /* Interrupt Registers available only in Version 2 */
107 #define LCD_RAW_STAT_REG 0x58
108 #define LCD_MASKED_STAT_REG 0x5c
109 #define LCD_INT_ENABLE_SET_REG 0x60
110 #define LCD_INT_ENABLE_CLR_REG 0x64
111 #define LCD_END_OF_INT_IND_REG 0x68
112
113 /* Clock registers available only on Version 2 */
114 #define LCD_CLK_ENABLE_REG 0x6c
115 #define LCD_CLK_RESET_REG 0x70
116 #define LCD_CLK_MAIN_RESET BIT(3)
117
118 #define LCD_NUM_BUFFERS 2
119
120 #define PALETTE_SIZE 256
121
122 #define CLK_MIN_DIV 2
123 #define CLK_MAX_DIV 255
124
125 static void __iomem *da8xx_fb_reg_base;
126 static unsigned int lcd_revision;
127 static irq_handler_t lcdc_irq_handler;
128 static wait_queue_head_t frame_done_wq;
129 static int frame_done_flag;
130
131 static unsigned int lcdc_read(unsigned int addr)
132 {
133 return (unsigned int)__raw_readl(da8xx_fb_reg_base + (addr));
134 }
135
136 static void lcdc_write(unsigned int val, unsigned int addr)
137 {
138 __raw_writel(val, da8xx_fb_reg_base + (addr));
139 }
140
141 struct da8xx_fb_par {
142 struct device *dev;
143 dma_addr_t p_palette_base;
144 unsigned char *v_palette_base;
145 dma_addr_t vram_phys;
146 unsigned long vram_size;
147 void *vram_virt;
148 unsigned int dma_start;
149 unsigned int dma_end;
150 struct clk *lcdc_clk;
151 int irq;
152 unsigned int palette_sz;
153 int blank;
154 wait_queue_head_t vsync_wait;
155 int vsync_flag;
156 int vsync_timeout;
157 spinlock_t lock_for_chan_update;
158
159 /*
160 * LCDC has 2 ping pong DMA channels, channel 0
161 * and channel 1.
162 */
163 unsigned int which_dma_channel_done;
164 #ifdef CONFIG_CPU_FREQ
165 struct notifier_block freq_transition;
166 #endif
167 unsigned int lcdc_clk_rate;
168 struct regulator *lcd_supply;
169 u32 pseudo_palette[16];
170 struct fb_videomode mode;
171 struct lcd_ctrl_config cfg;
172 };
173
174 static struct fb_var_screeninfo da8xx_fb_var;
175
176 static struct fb_fix_screeninfo da8xx_fb_fix = {
177 .id = "DA8xx FB Drv",
178 .type = FB_TYPE_PACKED_PIXELS,
179 .type_aux = 0,
180 .visual = FB_VISUAL_PSEUDOCOLOR,
181 .xpanstep = 0,
182 .ypanstep = 1,
183 .ywrapstep = 0,
184 .accel = FB_ACCEL_NONE
185 };
186
187 static struct fb_videomode known_lcd_panels[] = {
188 /* Sharp LCD035Q3DG01 */
189 [0] = {
190 .name = "Sharp_LCD035Q3DG01",
191 .xres = 320,
192 .yres = 240,
193 .pixclock = KHZ2PICOS(4607),
194 .left_margin = 6,
195 .right_margin = 8,
196 .upper_margin = 2,
197 .lower_margin = 2,
198 .hsync_len = 0,
199 .vsync_len = 0,
200 .sync = FB_SYNC_CLK_INVERT,
201 },
202 /* Sharp LK043T1DG01 */
203 [1] = {
204 .name = "Sharp_LK043T1DG01",
205 .xres = 480,
206 .yres = 272,
207 .pixclock = KHZ2PICOS(7833),
208 .left_margin = 2,
209 .right_margin = 2,
210 .upper_margin = 2,
211 .lower_margin = 2,
212 .hsync_len = 41,
213 .vsync_len = 10,
214 .sync = 0,
215 .flag = 0,
216 },
217 [2] = {
218 /* Hitachi SP10Q010 */
219 .name = "SP10Q010",
220 .xres = 320,
221 .yres = 240,
222 .pixclock = KHZ2PICOS(7833),
223 .left_margin = 10,
224 .right_margin = 10,
225 .upper_margin = 10,
226 .lower_margin = 10,
227 .hsync_len = 10,
228 .vsync_len = 10,
229 .sync = 0,
230 .flag = 0,
231 },
232 [3] = {
233 /* Densitron 84-0023-001T */
234 .name = "Densitron_84-0023-001T",
235 .xres = 320,
236 .yres = 240,
237 .pixclock = KHZ2PICOS(6400),
238 .left_margin = 0,
239 .right_margin = 0,
240 .upper_margin = 0,
241 .lower_margin = 0,
242 .hsync_len = 30,
243 .vsync_len = 3,
244 .sync = 0,
245 },
246 };
247
248 static bool da8xx_fb_is_raster_enabled(void)
249 {
250 return !!(lcdc_read(LCD_RASTER_CTRL_REG) & LCD_RASTER_ENABLE);
251 }
252
253 /* Enable the Raster Engine of the LCD Controller */
254 static void lcd_enable_raster(void)
255 {
256 u32 reg;
257
258 /* Put LCDC in reset for several cycles */
259 if (lcd_revision == LCD_VERSION_2)
260 /* Write 1 to reset LCDC */
261 lcdc_write(LCD_CLK_MAIN_RESET, LCD_CLK_RESET_REG);
262 mdelay(1);
263
264 /* Bring LCDC out of reset */
265 if (lcd_revision == LCD_VERSION_2)
266 lcdc_write(0, LCD_CLK_RESET_REG);
267 mdelay(1);
268
269 /* Above reset sequence doesnot reset register context */
270 reg = lcdc_read(LCD_RASTER_CTRL_REG);
271 if (!(reg & LCD_RASTER_ENABLE))
272 lcdc_write(reg | LCD_RASTER_ENABLE, LCD_RASTER_CTRL_REG);
273 }
274
275 /* Disable the Raster Engine of the LCD Controller */
276 static void lcd_disable_raster(enum da8xx_frame_complete wait_for_frame_done)
277 {
278 u32 reg;
279 int ret;
280
281 reg = lcdc_read(LCD_RASTER_CTRL_REG);
282 if (reg & LCD_RASTER_ENABLE)
283 lcdc_write(reg & ~LCD_RASTER_ENABLE, LCD_RASTER_CTRL_REG);
284 else
285 /* return if already disabled */
286 return;
287
288 if ((wait_for_frame_done == DA8XX_FRAME_WAIT) &&
289 (lcd_revision == LCD_VERSION_2)) {
290 frame_done_flag = 0;
291 ret = wait_event_interruptible_timeout(frame_done_wq,
292 frame_done_flag != 0,
293 msecs_to_jiffies(50));
294 if (ret == 0)
295 pr_err("LCD Controller timed out\n");
296 }
297 }
298
299 static void lcd_blit(int load_mode, struct da8xx_fb_par *par)
300 {
301 u32 start;
302 u32 end;
303 u32 reg_ras;
304 u32 reg_dma;
305 u32 reg_int;
306
307 /* init reg to clear PLM (loading mode) fields */
308 reg_ras = lcdc_read(LCD_RASTER_CTRL_REG);
309 reg_ras &= ~(3 << 20);
310
311 reg_dma = lcdc_read(LCD_DMA_CTRL_REG);
312
313 if (load_mode == LOAD_DATA) {
314 start = par->dma_start;
315 end = par->dma_end;
316
317 reg_ras |= LCD_PALETTE_LOAD_MODE(DATA_ONLY);
318 if (lcd_revision == LCD_VERSION_1) {
319 reg_dma |= LCD_V1_END_OF_FRAME_INT_ENA;
320 } else {
321 reg_int = lcdc_read(LCD_INT_ENABLE_SET_REG) |
322 LCD_V2_END_OF_FRAME0_INT_ENA |
323 LCD_V2_END_OF_FRAME1_INT_ENA |
324 LCD_FRAME_DONE | LCD_SYNC_LOST;
325 lcdc_write(reg_int, LCD_INT_ENABLE_SET_REG);
326 }
327 reg_dma |= LCD_DUAL_FRAME_BUFFER_ENABLE;
328
329 lcdc_write(start, LCD_DMA_FRM_BUF_BASE_ADDR_0_REG);
330 lcdc_write(end, LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG);
331 lcdc_write(start, LCD_DMA_FRM_BUF_BASE_ADDR_1_REG);
332 lcdc_write(end, LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG);
333 } else if (load_mode == LOAD_PALETTE) {
334 start = par->p_palette_base;
335 end = start + par->palette_sz - 1;
336
337 reg_ras |= LCD_PALETTE_LOAD_MODE(PALETTE_ONLY);
338
339 if (lcd_revision == LCD_VERSION_1) {
340 reg_ras |= LCD_V1_PL_INT_ENA;
341 } else {
342 reg_int = lcdc_read(LCD_INT_ENABLE_SET_REG) |
343 LCD_V2_PL_INT_ENA;
344 lcdc_write(reg_int, LCD_INT_ENABLE_SET_REG);
345 }
346
347 lcdc_write(start, LCD_DMA_FRM_BUF_BASE_ADDR_0_REG);
348 lcdc_write(end, LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG);
349 }
350
351 lcdc_write(reg_dma, LCD_DMA_CTRL_REG);
352 lcdc_write(reg_ras, LCD_RASTER_CTRL_REG);
353
354 /*
355 * The Raster enable bit must be set after all other control fields are
356 * set.
357 */
358 lcd_enable_raster();
359 }
360
361 /* Configure the Burst Size and fifo threhold of DMA */
362 static int lcd_cfg_dma(int burst_size, int fifo_th)
363 {
364 u32 reg;
365
366 reg = lcdc_read(LCD_DMA_CTRL_REG) & 0x00000001;
367 switch (burst_size) {
368 case 1:
369 reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_1);
370 break;
371 case 2:
372 reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_2);
373 break;
374 case 4:
375 reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_4);
376 break;
377 case 8:
378 reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_8);
379 break;
380 case 16:
381 default:
382 reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_16);
383 break;
384 }
385
386 reg |= (fifo_th << 8);
387
388 lcdc_write(reg, LCD_DMA_CTRL_REG);
389
390 return 0;
391 }
392
393 static void lcd_cfg_ac_bias(int period, int transitions_per_int)
394 {
395 u32 reg;
396
397 /* Set the AC Bias Period and Number of Transisitons per Interrupt */
398 reg = lcdc_read(LCD_RASTER_TIMING_2_REG) & 0xFFF00000;
399 reg |= LCD_AC_BIAS_FREQUENCY(period) |
400 LCD_AC_BIAS_TRANSITIONS_PER_INT(transitions_per_int);
401 lcdc_write(reg, LCD_RASTER_TIMING_2_REG);
402 }
403
404 static void lcd_cfg_horizontal_sync(int back_porch, int pulse_width,
405 int front_porch)
406 {
407 u32 reg;
408
409 reg = lcdc_read(LCD_RASTER_TIMING_0_REG) & 0x3ff;
410 reg |= (((back_porch-1) & 0xff) << 24)
411 | (((front_porch-1) & 0xff) << 16)
412 | (((pulse_width-1) & 0x3f) << 10);
413 lcdc_write(reg, LCD_RASTER_TIMING_0_REG);
414
415 /*
416 * LCDC Version 2 adds some extra bits that increase the allowable
417 * size of the horizontal timing registers.
418 * remember that the registers use 0 to represent 1 so all values
419 * that get set into register need to be decremented by 1
420 */
421 if (lcd_revision == LCD_VERSION_2) {
422 /* Mask off the bits we want to change */
423 reg = lcdc_read(LCD_RASTER_TIMING_2_REG) & ~0x780000ff;
424 reg |= ((front_porch-1) & 0x300) >> 8;
425 reg |= ((back_porch-1) & 0x300) >> 4;
426 reg |= ((pulse_width-1) & 0x3c0) << 21;
427 lcdc_write(reg, LCD_RASTER_TIMING_2_REG);
428 }
429 }
430
431 static void lcd_cfg_vertical_sync(int back_porch, int pulse_width,
432 int front_porch)
433 {
434 u32 reg;
435
436 reg = lcdc_read(LCD_RASTER_TIMING_1_REG) & 0x3ff;
437 reg |= ((back_porch & 0xff) << 24)
438 | ((front_porch & 0xff) << 16)
439 | (((pulse_width-1) & 0x3f) << 10);
440 lcdc_write(reg, LCD_RASTER_TIMING_1_REG);
441 }
442
443 static int lcd_cfg_display(const struct lcd_ctrl_config *cfg,
444 struct fb_videomode *panel)
445 {
446 u32 reg;
447 u32 reg_int;
448
449 reg = lcdc_read(LCD_RASTER_CTRL_REG) & ~(LCD_TFT_MODE |
450 LCD_MONO_8BIT_MODE |
451 LCD_MONOCHROME_MODE);
452
453 switch (cfg->panel_shade) {
454 case MONOCHROME:
455 reg |= LCD_MONOCHROME_MODE;
456 if (cfg->mono_8bit_mode)
457 reg |= LCD_MONO_8BIT_MODE;
458 break;
459 case COLOR_ACTIVE:
460 reg |= LCD_TFT_MODE;
461 if (cfg->tft_alt_mode)
462 reg |= LCD_TFT_ALT_ENABLE;
463 break;
464
465 case COLOR_PASSIVE:
466 /* AC bias applicable only for Pasive panels */
467 lcd_cfg_ac_bias(cfg->ac_bias, cfg->ac_bias_intrpt);
468 if (cfg->bpp == 12 && cfg->stn_565_mode)
469 reg |= LCD_STN_565_ENABLE;
470 break;
471
472 default:
473 return -EINVAL;
474 }
475
476 /* enable additional interrupts here */
477 if (lcd_revision == LCD_VERSION_1) {
478 reg |= LCD_V1_UNDERFLOW_INT_ENA;
479 } else {
480 reg_int = lcdc_read(LCD_INT_ENABLE_SET_REG) |
481 LCD_V2_UNDERFLOW_INT_ENA;
482 lcdc_write(reg_int, LCD_INT_ENABLE_SET_REG);
483 }
484
485 lcdc_write(reg, LCD_RASTER_CTRL_REG);
486
487 reg = lcdc_read(LCD_RASTER_TIMING_2_REG);
488
489 reg |= LCD_SYNC_CTRL;
490
491 if (cfg->sync_edge)
492 reg |= LCD_SYNC_EDGE;
493 else
494 reg &= ~LCD_SYNC_EDGE;
495
496 if ((panel->sync & FB_SYNC_HOR_HIGH_ACT) == 0)
497 reg |= LCD_INVERT_LINE_CLOCK;
498 else
499 reg &= ~LCD_INVERT_LINE_CLOCK;
500
501 if ((panel->sync & FB_SYNC_VERT_HIGH_ACT) == 0)
502 reg |= LCD_INVERT_FRAME_CLOCK;
503 else
504 reg &= ~LCD_INVERT_FRAME_CLOCK;
505
506 lcdc_write(reg, LCD_RASTER_TIMING_2_REG);
507
508 return 0;
509 }
510
511 static int lcd_cfg_frame_buffer(struct da8xx_fb_par *par, u32 width, u32 height,
512 u32 bpp, u32 raster_order)
513 {
514 u32 reg;
515
516 if (bpp > 16 && lcd_revision == LCD_VERSION_1)
517 return -EINVAL;
518
519 /* Set the Panel Width */
520 /* Pixels per line = (PPL + 1)*16 */
521 if (lcd_revision == LCD_VERSION_1) {
522 /*
523 * 0x3F in bits 4..9 gives max horizontal resolution = 1024
524 * pixels.
525 */
526 width &= 0x3f0;
527 } else {
528 /*
529 * 0x7F in bits 4..10 gives max horizontal resolution = 2048
530 * pixels.
531 */
532 width &= 0x7f0;
533 }
534
535 reg = lcdc_read(LCD_RASTER_TIMING_0_REG);
536 reg &= 0xfffffc00;
537 if (lcd_revision == LCD_VERSION_1) {
538 reg |= ((width >> 4) - 1) << 4;
539 } else {
540 width = (width >> 4) - 1;
541 reg |= ((width & 0x3f) << 4) | ((width & 0x40) >> 3);
542 }
543 lcdc_write(reg, LCD_RASTER_TIMING_0_REG);
544
545 /* Set the Panel Height */
546 /* Set bits 9:0 of Lines Per Pixel */
547 reg = lcdc_read(LCD_RASTER_TIMING_1_REG);
548 reg = ((height - 1) & 0x3ff) | (reg & 0xfffffc00);
549 lcdc_write(reg, LCD_RASTER_TIMING_1_REG);
550
551 /* Set bit 10 of Lines Per Pixel */
552 if (lcd_revision == LCD_VERSION_2) {
553 reg = lcdc_read(LCD_RASTER_TIMING_2_REG);
554 reg |= ((height - 1) & 0x400) << 16;
555 lcdc_write(reg, LCD_RASTER_TIMING_2_REG);
556 }
557
558 /* Set the Raster Order of the Frame Buffer */
559 reg = lcdc_read(LCD_RASTER_CTRL_REG) & ~(1 << 8);
560 if (raster_order)
561 reg |= LCD_RASTER_ORDER;
562
563 par->palette_sz = 16 * 2;
564
565 switch (bpp) {
566 case 1:
567 case 2:
568 case 4:
569 case 16:
570 break;
571 case 24:
572 reg |= LCD_V2_TFT_24BPP_MODE;
573 break;
574 case 32:
575 reg |= LCD_V2_TFT_24BPP_MODE;
576 reg |= LCD_V2_TFT_24BPP_UNPACK;
577 break;
578 case 8:
579 par->palette_sz = 256 * 2;
580 break;
581
582 default:
583 return -EINVAL;
584 }
585
586 lcdc_write(reg, LCD_RASTER_CTRL_REG);
587
588 return 0;
589 }
590
591 #define CNVT_TOHW(val, width) ((((val) << (width)) + 0x7FFF - (val)) >> 16)
592 static int fb_setcolreg(unsigned regno, unsigned red, unsigned green,
593 unsigned blue, unsigned transp,
594 struct fb_info *info)
595 {
596 struct da8xx_fb_par *par = info->par;
597 unsigned short *palette = (unsigned short *) par->v_palette_base;
598 u_short pal;
599 int update_hw = 0;
600
601 if (regno > 255)
602 return 1;
603
604 if (info->fix.visual == FB_VISUAL_DIRECTCOLOR)
605 return 1;
606
607 if (info->var.bits_per_pixel > 16 && lcd_revision == LCD_VERSION_1)
608 return -EINVAL;
609
610 switch (info->fix.visual) {
611 case FB_VISUAL_TRUECOLOR:
612 red = CNVT_TOHW(red, info->var.red.length);
613 green = CNVT_TOHW(green, info->var.green.length);
614 blue = CNVT_TOHW(blue, info->var.blue.length);
615 break;
616 case FB_VISUAL_PSEUDOCOLOR:
617 switch (info->var.bits_per_pixel) {
618 case 4:
619 if (regno > 15)
620 return -EINVAL;
621
622 if (info->var.grayscale) {
623 pal = regno;
624 } else {
625 red >>= 4;
626 green >>= 8;
627 blue >>= 12;
628
629 pal = red & 0x0f00;
630 pal |= green & 0x00f0;
631 pal |= blue & 0x000f;
632 }
633 if (regno == 0)
634 pal |= 0x2000;
635 palette[regno] = pal;
636 break;
637
638 case 8:
639 red >>= 4;
640 green >>= 8;
641 blue >>= 12;
642
643 pal = (red & 0x0f00);
644 pal |= (green & 0x00f0);
645 pal |= (blue & 0x000f);
646
647 if (palette[regno] != pal) {
648 update_hw = 1;
649 palette[regno] = pal;
650 }
651 break;
652 }
653 break;
654 }
655
656 /* Truecolor has hardware independent palette */
657 if (info->fix.visual == FB_VISUAL_TRUECOLOR) {
658 u32 v;
659
660 if (regno > 15)
661 return -EINVAL;
662
663 v = (red << info->var.red.offset) |
664 (green << info->var.green.offset) |
665 (blue << info->var.blue.offset);
666
667 ((u32 *) (info->pseudo_palette))[regno] = v;
668 if (palette[0] != 0x4000) {
669 update_hw = 1;
670 palette[0] = 0x4000;
671 }
672 }
673
674 /* Update the palette in the h/w as needed. */
675 if (update_hw)
676 lcd_blit(LOAD_PALETTE, par);
677
678 return 0;
679 }
680 #undef CNVT_TOHW
681
682 static void da8xx_fb_lcd_reset(void)
683 {
684 /* DMA has to be disabled */
685 lcdc_write(0, LCD_DMA_CTRL_REG);
686 lcdc_write(0, LCD_RASTER_CTRL_REG);
687
688 if (lcd_revision == LCD_VERSION_2) {
689 lcdc_write(0, LCD_INT_ENABLE_SET_REG);
690 /* Write 1 to reset */
691 lcdc_write(LCD_CLK_MAIN_RESET, LCD_CLK_RESET_REG);
692 lcdc_write(0, LCD_CLK_RESET_REG);
693 }
694 }
695
696 static int da8xx_fb_config_clk_divider(struct da8xx_fb_par *par,
697 unsigned lcdc_clk_div,
698 unsigned lcdc_clk_rate)
699 {
700 int ret;
701
702 if (par->lcdc_clk_rate != lcdc_clk_rate) {
703 ret = clk_set_rate(par->lcdc_clk, lcdc_clk_rate);
704 if (ret) {
705 dev_err(par->dev,
706 "unable to set clock rate at %u\n",
707 lcdc_clk_rate);
708 return ret;
709 }
710 par->lcdc_clk_rate = clk_get_rate(par->lcdc_clk);
711 }
712
713 /* Configure the LCD clock divisor. */
714 lcdc_write(LCD_CLK_DIVISOR(lcdc_clk_div) |
715 (LCD_RASTER_MODE & 0x1), LCD_CTRL_REG);
716
717 if (lcd_revision == LCD_VERSION_2)
718 lcdc_write(LCD_V2_DMA_CLK_EN | LCD_V2_LIDD_CLK_EN |
719 LCD_V2_CORE_CLK_EN, LCD_CLK_ENABLE_REG);
720
721 return 0;
722 }
723
724 static unsigned int da8xx_fb_calc_clk_divider(struct da8xx_fb_par *par,
725 unsigned pixclock,
726 unsigned *lcdc_clk_rate)
727 {
728 unsigned lcdc_clk_div;
729
730 pixclock = PICOS2KHZ(pixclock) * 1000;
731
732 *lcdc_clk_rate = par->lcdc_clk_rate;
733
734 if (pixclock < (*lcdc_clk_rate / CLK_MAX_DIV)) {
735 *lcdc_clk_rate = clk_round_rate(par->lcdc_clk,
736 pixclock * CLK_MAX_DIV);
737 lcdc_clk_div = CLK_MAX_DIV;
738 } else if (pixclock > (*lcdc_clk_rate / CLK_MIN_DIV)) {
739 *lcdc_clk_rate = clk_round_rate(par->lcdc_clk,
740 pixclock * CLK_MIN_DIV);
741 lcdc_clk_div = CLK_MIN_DIV;
742 } else {
743 lcdc_clk_div = *lcdc_clk_rate / pixclock;
744 }
745
746 return lcdc_clk_div;
747 }
748
749 static int da8xx_fb_calc_config_clk_divider(struct da8xx_fb_par *par,
750 struct fb_videomode *mode)
751 {
752 unsigned lcdc_clk_rate;
753 unsigned lcdc_clk_div = da8xx_fb_calc_clk_divider(par, mode->pixclock,
754 &lcdc_clk_rate);
755
756 return da8xx_fb_config_clk_divider(par, lcdc_clk_div, lcdc_clk_rate);
757 }
758
759 static unsigned da8xx_fb_round_clk(struct da8xx_fb_par *par,
760 unsigned pixclock)
761 {
762 unsigned lcdc_clk_div, lcdc_clk_rate;
763
764 lcdc_clk_div = da8xx_fb_calc_clk_divider(par, pixclock, &lcdc_clk_rate);
765 return KHZ2PICOS(lcdc_clk_rate / (1000 * lcdc_clk_div));
766 }
767
768 static int lcd_init(struct da8xx_fb_par *par, const struct lcd_ctrl_config *cfg,
769 struct fb_videomode *panel)
770 {
771 u32 bpp;
772 int ret = 0;
773
774 ret = da8xx_fb_calc_config_clk_divider(par, panel);
775 if (ret) {
776 dev_err(par->dev, "unable to configure clock\n");
777 return ret;
778 }
779
780 if (panel->sync & FB_SYNC_CLK_INVERT)
781 lcdc_write((lcdc_read(LCD_RASTER_TIMING_2_REG) |
782 LCD_INVERT_PIXEL_CLOCK), LCD_RASTER_TIMING_2_REG);
783 else
784 lcdc_write((lcdc_read(LCD_RASTER_TIMING_2_REG) &
785 ~LCD_INVERT_PIXEL_CLOCK), LCD_RASTER_TIMING_2_REG);
786
787 /* Configure the DMA burst size and fifo threshold. */
788 ret = lcd_cfg_dma(cfg->dma_burst_sz, cfg->fifo_th);
789 if (ret < 0)
790 return ret;
791
792 /* Configure the vertical and horizontal sync properties. */
793 lcd_cfg_vertical_sync(panel->upper_margin, panel->vsync_len,
794 panel->lower_margin);
795 lcd_cfg_horizontal_sync(panel->left_margin, panel->hsync_len,
796 panel->right_margin);
797
798 /* Configure for disply */
799 ret = lcd_cfg_display(cfg, panel);
800 if (ret < 0)
801 return ret;
802
803 bpp = cfg->bpp;
804
805 if (bpp == 12)
806 bpp = 16;
807 ret = lcd_cfg_frame_buffer(par, (unsigned int)panel->xres,
808 (unsigned int)panel->yres, bpp,
809 cfg->raster_order);
810 if (ret < 0)
811 return ret;
812
813 /* Configure FDD */
814 lcdc_write((lcdc_read(LCD_RASTER_CTRL_REG) & 0xfff00fff) |
815 (cfg->fdd << 12), LCD_RASTER_CTRL_REG);
816
817 return 0;
818 }
819
820 /* IRQ handler for version 2 of LCDC */
821 static irqreturn_t lcdc_irq_handler_rev02(int irq, void *arg)
822 {
823 struct da8xx_fb_par *par = arg;
824 u32 stat = lcdc_read(LCD_MASKED_STAT_REG);
825
826 if ((stat & LCD_SYNC_LOST) && (stat & LCD_FIFO_UNDERFLOW)) {
827 lcd_disable_raster(DA8XX_FRAME_NOWAIT);
828 lcdc_write(stat, LCD_MASKED_STAT_REG);
829 lcd_enable_raster();
830 } else if (stat & LCD_PL_LOAD_DONE) {
831 /*
832 * Must disable raster before changing state of any control bit.
833 * And also must be disabled before clearing the PL loading
834 * interrupt via the following write to the status register. If
835 * this is done after then one gets multiple PL done interrupts.
836 */
837 lcd_disable_raster(DA8XX_FRAME_NOWAIT);
838
839 lcdc_write(stat, LCD_MASKED_STAT_REG);
840
841 /* Disable PL completion interrupt */
842 lcdc_write(LCD_V2_PL_INT_ENA, LCD_INT_ENABLE_CLR_REG);
843
844 /* Setup and start data loading mode */
845 lcd_blit(LOAD_DATA, par);
846 } else {
847 lcdc_write(stat, LCD_MASKED_STAT_REG);
848
849 if (stat & LCD_END_OF_FRAME0) {
850 par->which_dma_channel_done = 0;
851 lcdc_write(par->dma_start,
852 LCD_DMA_FRM_BUF_BASE_ADDR_0_REG);
853 lcdc_write(par->dma_end,
854 LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG);
855 par->vsync_flag = 1;
856 wake_up_interruptible(&par->vsync_wait);
857 }
858
859 if (stat & LCD_END_OF_FRAME1) {
860 par->which_dma_channel_done = 1;
861 lcdc_write(par->dma_start,
862 LCD_DMA_FRM_BUF_BASE_ADDR_1_REG);
863 lcdc_write(par->dma_end,
864 LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG);
865 par->vsync_flag = 1;
866 wake_up_interruptible(&par->vsync_wait);
867 }
868
869 /* Set only when controller is disabled and at the end of
870 * active frame
871 */
872 if (stat & BIT(0)) {
873 frame_done_flag = 1;
874 wake_up_interruptible(&frame_done_wq);
875 }
876 }
877
878 lcdc_write(0, LCD_END_OF_INT_IND_REG);
879 return IRQ_HANDLED;
880 }
881
882 /* IRQ handler for version 1 LCDC */
883 static irqreturn_t lcdc_irq_handler_rev01(int irq, void *arg)
884 {
885 struct da8xx_fb_par *par = arg;
886 u32 stat = lcdc_read(LCD_STAT_REG);
887 u32 reg_ras;
888
889 if ((stat & LCD_SYNC_LOST) && (stat & LCD_FIFO_UNDERFLOW)) {
890 lcd_disable_raster(DA8XX_FRAME_NOWAIT);
891 lcdc_write(stat, LCD_STAT_REG);
892 lcd_enable_raster();
893 } else if (stat & LCD_PL_LOAD_DONE) {
894 /*
895 * Must disable raster before changing state of any control bit.
896 * And also must be disabled before clearing the PL loading
897 * interrupt via the following write to the status register. If
898 * this is done after then one gets multiple PL done interrupts.
899 */
900 lcd_disable_raster(DA8XX_FRAME_NOWAIT);
901
902 lcdc_write(stat, LCD_STAT_REG);
903
904 /* Disable PL completion inerrupt */
905 reg_ras = lcdc_read(LCD_RASTER_CTRL_REG);
906 reg_ras &= ~LCD_V1_PL_INT_ENA;
907 lcdc_write(reg_ras, LCD_RASTER_CTRL_REG);
908
909 /* Setup and start data loading mode */
910 lcd_blit(LOAD_DATA, par);
911 } else {
912 lcdc_write(stat, LCD_STAT_REG);
913
914 if (stat & LCD_END_OF_FRAME0) {
915 par->which_dma_channel_done = 0;
916 lcdc_write(par->dma_start,
917 LCD_DMA_FRM_BUF_BASE_ADDR_0_REG);
918 lcdc_write(par->dma_end,
919 LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG);
920 par->vsync_flag = 1;
921 wake_up_interruptible(&par->vsync_wait);
922 }
923
924 if (stat & LCD_END_OF_FRAME1) {
925 par->which_dma_channel_done = 1;
926 lcdc_write(par->dma_start,
927 LCD_DMA_FRM_BUF_BASE_ADDR_1_REG);
928 lcdc_write(par->dma_end,
929 LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG);
930 par->vsync_flag = 1;
931 wake_up_interruptible(&par->vsync_wait);
932 }
933 }
934
935 return IRQ_HANDLED;
936 }
937
938 static int fb_check_var(struct fb_var_screeninfo *var,
939 struct fb_info *info)
940 {
941 int err = 0;
942 struct da8xx_fb_par *par = info->par;
943 int bpp = var->bits_per_pixel >> 3;
944 unsigned long line_size = var->xres_virtual * bpp;
945
946 if (var->bits_per_pixel > 16 && lcd_revision == LCD_VERSION_1)
947 return -EINVAL;
948
949 switch (var->bits_per_pixel) {
950 case 1:
951 case 8:
952 var->red.offset = 0;
953 var->red.length = 8;
954 var->green.offset = 0;
955 var->green.length = 8;
956 var->blue.offset = 0;
957 var->blue.length = 8;
958 var->transp.offset = 0;
959 var->transp.length = 0;
960 var->nonstd = 0;
961 break;
962 case 4:
963 var->red.offset = 0;
964 var->red.length = 4;
965 var->green.offset = 0;
966 var->green.length = 4;
967 var->blue.offset = 0;
968 var->blue.length = 4;
969 var->transp.offset = 0;
970 var->transp.length = 0;
971 var->nonstd = FB_NONSTD_REV_PIX_IN_B;
972 break;
973 case 16: /* RGB 565 */
974 var->red.offset = 11;
975 var->red.length = 5;
976 var->green.offset = 5;
977 var->green.length = 6;
978 var->blue.offset = 0;
979 var->blue.length = 5;
980 var->transp.offset = 0;
981 var->transp.length = 0;
982 var->nonstd = 0;
983 break;
984 case 24:
985 var->red.offset = 16;
986 var->red.length = 8;
987 var->green.offset = 8;
988 var->green.length = 8;
989 var->blue.offset = 0;
990 var->blue.length = 8;
991 var->nonstd = 0;
992 break;
993 case 32:
994 var->transp.offset = 24;
995 var->transp.length = 8;
996 var->red.offset = 16;
997 var->red.length = 8;
998 var->green.offset = 8;
999 var->green.length = 8;
1000 var->blue.offset = 0;
1001 var->blue.length = 8;
1002 var->nonstd = 0;
1003 break;
1004 default:
1005 err = -EINVAL;
1006 }
1007
1008 var->red.msb_right = 0;
1009 var->green.msb_right = 0;
1010 var->blue.msb_right = 0;
1011 var->transp.msb_right = 0;
1012
1013 if (line_size * var->yres_virtual > par->vram_size)
1014 var->yres_virtual = par->vram_size / line_size;
1015
1016 if (var->yres > var->yres_virtual)
1017 var->yres = var->yres_virtual;
1018
1019 if (var->xres > var->xres_virtual)
1020 var->xres = var->xres_virtual;
1021
1022 if (var->xres + var->xoffset > var->xres_virtual)
1023 var->xoffset = var->xres_virtual - var->xres;
1024 if (var->yres + var->yoffset > var->yres_virtual)
1025 var->yoffset = var->yres_virtual - var->yres;
1026
1027 var->pixclock = da8xx_fb_round_clk(par, var->pixclock);
1028
1029 return err;
1030 }
1031
1032 #ifdef CONFIG_CPU_FREQ
1033 static int lcd_da8xx_cpufreq_transition(struct notifier_block *nb,
1034 unsigned long val, void *data)
1035 {
1036 struct da8xx_fb_par *par;
1037
1038 par = container_of(nb, struct da8xx_fb_par, freq_transition);
1039 if (val == CPUFREQ_POSTCHANGE) {
1040 if (par->lcdc_clk_rate != clk_get_rate(par->lcdc_clk)) {
1041 par->lcdc_clk_rate = clk_get_rate(par->lcdc_clk);
1042 lcd_disable_raster(DA8XX_FRAME_WAIT);
1043 da8xx_fb_calc_config_clk_divider(par, &par->mode);
1044 if (par->blank == FB_BLANK_UNBLANK)
1045 lcd_enable_raster();
1046 }
1047 }
1048
1049 return 0;
1050 }
1051
1052 static int lcd_da8xx_cpufreq_register(struct da8xx_fb_par *par)
1053 {
1054 par->freq_transition.notifier_call = lcd_da8xx_cpufreq_transition;
1055
1056 return cpufreq_register_notifier(&par->freq_transition,
1057 CPUFREQ_TRANSITION_NOTIFIER);
1058 }
1059
1060 static void lcd_da8xx_cpufreq_deregister(struct da8xx_fb_par *par)
1061 {
1062 cpufreq_unregister_notifier(&par->freq_transition,
1063 CPUFREQ_TRANSITION_NOTIFIER);
1064 }
1065 #endif
1066
1067 static int fb_remove(struct platform_device *dev)
1068 {
1069 struct fb_info *info = dev_get_drvdata(&dev->dev);
1070 struct da8xx_fb_par *par = info->par;
1071 int ret;
1072
1073 #ifdef CONFIG_CPU_FREQ
1074 lcd_da8xx_cpufreq_deregister(par);
1075 #endif
1076 if (par->lcd_supply) {
1077 ret = regulator_disable(par->lcd_supply);
1078 if (ret)
1079 return ret;
1080 }
1081
1082 lcd_disable_raster(DA8XX_FRAME_WAIT);
1083 lcdc_write(0, LCD_RASTER_CTRL_REG);
1084
1085 /* disable DMA */
1086 lcdc_write(0, LCD_DMA_CTRL_REG);
1087
1088 unregister_framebuffer(info);
1089 fb_dealloc_cmap(&info->cmap);
1090 pm_runtime_put_sync(&dev->dev);
1091 pm_runtime_disable(&dev->dev);
1092 framebuffer_release(info);
1093
1094 return 0;
1095 }
1096
1097 /*
1098 * Function to wait for vertical sync which for this LCD peripheral
1099 * translates into waiting for the current raster frame to complete.
1100 */
1101 static int fb_wait_for_vsync(struct fb_info *info)
1102 {
1103 struct da8xx_fb_par *par = info->par;
1104 int ret;
1105
1106 /*
1107 * Set flag to 0 and wait for isr to set to 1. It would seem there is a
1108 * race condition here where the ISR could have occurred just before or
1109 * just after this set. But since we are just coarsely waiting for
1110 * a frame to complete then that's OK. i.e. if the frame completed
1111 * just before this code executed then we have to wait another full
1112 * frame time but there is no way to avoid such a situation. On the
1113 * other hand if the frame completed just after then we don't need
1114 * to wait long at all. Either way we are guaranteed to return to the
1115 * user immediately after a frame completion which is all that is
1116 * required.
1117 */
1118 par->vsync_flag = 0;
1119 ret = wait_event_interruptible_timeout(par->vsync_wait,
1120 par->vsync_flag != 0,
1121 par->vsync_timeout);
1122 if (ret < 0)
1123 return ret;
1124 if (ret == 0)
1125 return -ETIMEDOUT;
1126
1127 return 0;
1128 }
1129
1130 static int fb_ioctl(struct fb_info *info, unsigned int cmd,
1131 unsigned long arg)
1132 {
1133 struct lcd_sync_arg sync_arg;
1134
1135 switch (cmd) {
1136 case FBIOGET_CONTRAST:
1137 case FBIOPUT_CONTRAST:
1138 case FBIGET_BRIGHTNESS:
1139 case FBIPUT_BRIGHTNESS:
1140 case FBIGET_COLOR:
1141 case FBIPUT_COLOR:
1142 return -ENOTTY;
1143 case FBIPUT_HSYNC:
1144 if (copy_from_user(&sync_arg, (char *)arg,
1145 sizeof(struct lcd_sync_arg)))
1146 return -EFAULT;
1147 lcd_cfg_horizontal_sync(sync_arg.back_porch,
1148 sync_arg.pulse_width,
1149 sync_arg.front_porch);
1150 break;
1151 case FBIPUT_VSYNC:
1152 if (copy_from_user(&sync_arg, (char *)arg,
1153 sizeof(struct lcd_sync_arg)))
1154 return -EFAULT;
1155 lcd_cfg_vertical_sync(sync_arg.back_porch,
1156 sync_arg.pulse_width,
1157 sync_arg.front_porch);
1158 break;
1159 case FBIO_WAITFORVSYNC:
1160 return fb_wait_for_vsync(info);
1161 default:
1162 return -EINVAL;
1163 }
1164 return 0;
1165 }
1166
1167 static int cfb_blank(int blank, struct fb_info *info)
1168 {
1169 struct da8xx_fb_par *par = info->par;
1170 int ret = 0;
1171
1172 if (par->blank == blank)
1173 return 0;
1174
1175 par->blank = blank;
1176 switch (blank) {
1177 case FB_BLANK_UNBLANK:
1178 lcd_enable_raster();
1179
1180 if (par->lcd_supply) {
1181 ret = regulator_enable(par->lcd_supply);
1182 if (ret)
1183 return ret;
1184 }
1185 break;
1186 case FB_BLANK_NORMAL:
1187 case FB_BLANK_VSYNC_SUSPEND:
1188 case FB_BLANK_HSYNC_SUSPEND:
1189 case FB_BLANK_POWERDOWN:
1190 if (par->lcd_supply) {
1191 ret = regulator_disable(par->lcd_supply);
1192 if (ret)
1193 return ret;
1194 }
1195
1196 lcd_disable_raster(DA8XX_FRAME_WAIT);
1197 break;
1198 default:
1199 ret = -EINVAL;
1200 }
1201
1202 return ret;
1203 }
1204
1205 /*
1206 * Set new x,y offsets in the virtual display for the visible area and switch
1207 * to the new mode.
1208 */
1209 static int da8xx_pan_display(struct fb_var_screeninfo *var,
1210 struct fb_info *fbi)
1211 {
1212 int ret = 0;
1213 struct fb_var_screeninfo new_var;
1214 struct da8xx_fb_par *par = fbi->par;
1215 struct fb_fix_screeninfo *fix = &fbi->fix;
1216 unsigned int end;
1217 unsigned int start;
1218 unsigned long irq_flags;
1219
1220 if (var->xoffset != fbi->var.xoffset ||
1221 var->yoffset != fbi->var.yoffset) {
1222 memcpy(&new_var, &fbi->var, sizeof(new_var));
1223 new_var.xoffset = var->xoffset;
1224 new_var.yoffset = var->yoffset;
1225 if (fb_check_var(&new_var, fbi))
1226 ret = -EINVAL;
1227 else {
1228 memcpy(&fbi->var, &new_var, sizeof(new_var));
1229
1230 start = fix->smem_start +
1231 new_var.yoffset * fix->line_length +
1232 new_var.xoffset * fbi->var.bits_per_pixel / 8;
1233 end = start + fbi->var.yres * fix->line_length - 1;
1234 par->dma_start = start;
1235 par->dma_end = end;
1236 spin_lock_irqsave(&par->lock_for_chan_update,
1237 irq_flags);
1238 if (par->which_dma_channel_done == 0) {
1239 lcdc_write(par->dma_start,
1240 LCD_DMA_FRM_BUF_BASE_ADDR_0_REG);
1241 lcdc_write(par->dma_end,
1242 LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG);
1243 } else if (par->which_dma_channel_done == 1) {
1244 lcdc_write(par->dma_start,
1245 LCD_DMA_FRM_BUF_BASE_ADDR_1_REG);
1246 lcdc_write(par->dma_end,
1247 LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG);
1248 }
1249 spin_unlock_irqrestore(&par->lock_for_chan_update,
1250 irq_flags);
1251 }
1252 }
1253
1254 return ret;
1255 }
1256
1257 static int da8xxfb_set_par(struct fb_info *info)
1258 {
1259 struct da8xx_fb_par *par = info->par;
1260 int ret;
1261 bool raster = da8xx_fb_is_raster_enabled();
1262
1263 if (raster)
1264 lcd_disable_raster(DA8XX_FRAME_WAIT);
1265
1266 fb_var_to_videomode(&par->mode, &info->var);
1267
1268 par->cfg.bpp = info->var.bits_per_pixel;
1269
1270 info->fix.visual = (par->cfg.bpp <= 8) ?
1271 FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_TRUECOLOR;
1272 info->fix.line_length = (par->mode.xres * par->cfg.bpp) / 8;
1273
1274 ret = lcd_init(par, &par->cfg, &par->mode);
1275 if (ret < 0) {
1276 dev_err(par->dev, "lcd init failed\n");
1277 return ret;
1278 }
1279
1280 par->dma_start = info->fix.smem_start +
1281 info->var.yoffset * info->fix.line_length +
1282 info->var.xoffset * info->var.bits_per_pixel / 8;
1283 par->dma_end = par->dma_start +
1284 info->var.yres * info->fix.line_length - 1;
1285
1286 lcdc_write(par->dma_start, LCD_DMA_FRM_BUF_BASE_ADDR_0_REG);
1287 lcdc_write(par->dma_end, LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG);
1288 lcdc_write(par->dma_start, LCD_DMA_FRM_BUF_BASE_ADDR_1_REG);
1289 lcdc_write(par->dma_end, LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG);
1290
1291 if (raster)
1292 lcd_enable_raster();
1293
1294 return 0;
1295 }
1296
1297 static const struct fb_ops da8xx_fb_ops = {
1298 .owner = THIS_MODULE,
1299 .fb_check_var = fb_check_var,
1300 .fb_set_par = da8xxfb_set_par,
1301 .fb_setcolreg = fb_setcolreg,
1302 .fb_pan_display = da8xx_pan_display,
1303 .fb_ioctl = fb_ioctl,
1304 .fb_fillrect = cfb_fillrect,
1305 .fb_copyarea = cfb_copyarea,
1306 .fb_imageblit = cfb_imageblit,
1307 .fb_blank = cfb_blank,
1308 };
1309
1310 static struct fb_videomode *da8xx_fb_get_videomode(struct platform_device *dev)
1311 {
1312 struct da8xx_lcdc_platform_data *fb_pdata = dev_get_platdata(&dev->dev);
1313 struct fb_videomode *lcdc_info;
1314 int i;
1315
1316 for (i = 0, lcdc_info = known_lcd_panels;
1317 i < ARRAY_SIZE(known_lcd_panels); i++, lcdc_info++) {
1318 if (strcmp(fb_pdata->type, lcdc_info->name) == 0)
1319 break;
1320 }
1321
1322 if (i == ARRAY_SIZE(known_lcd_panels)) {
1323 dev_err(&dev->dev, "no panel found\n");
1324 return NULL;
1325 }
1326 dev_info(&dev->dev, "found %s panel\n", lcdc_info->name);
1327
1328 return lcdc_info;
1329 }
1330
1331 static int fb_probe(struct platform_device *device)
1332 {
1333 struct da8xx_lcdc_platform_data *fb_pdata =
1334 dev_get_platdata(&device->dev);
1335 struct lcd_ctrl_config *lcd_cfg;
1336 struct fb_videomode *lcdc_info;
1337 struct fb_info *da8xx_fb_info;
1338 struct da8xx_fb_par *par;
1339 struct clk *tmp_lcdc_clk;
1340 int ret;
1341 unsigned long ulcm;
1342
1343 if (fb_pdata == NULL) {
1344 dev_err(&device->dev, "Can not get platform data\n");
1345 return -ENOENT;
1346 }
1347
1348 lcdc_info = da8xx_fb_get_videomode(device);
1349 if (lcdc_info == NULL)
1350 return -ENODEV;
1351
1352 da8xx_fb_reg_base = devm_platform_ioremap_resource(device, 0);
1353 if (IS_ERR(da8xx_fb_reg_base))
1354 return PTR_ERR(da8xx_fb_reg_base);
1355
1356 tmp_lcdc_clk = devm_clk_get(&device->dev, "fck");
1357 if (IS_ERR(tmp_lcdc_clk)) {
1358 dev_err(&device->dev, "Can not get device clock\n");
1359 return PTR_ERR(tmp_lcdc_clk);
1360 }
1361
1362 pm_runtime_enable(&device->dev);
1363 pm_runtime_get_sync(&device->dev);
1364
1365 /* Determine LCD IP Version */
1366 switch (lcdc_read(LCD_PID_REG)) {
1367 case 0x4C100102:
1368 lcd_revision = LCD_VERSION_1;
1369 break;
1370 case 0x4F200800:
1371 case 0x4F201000:
1372 lcd_revision = LCD_VERSION_2;
1373 break;
1374 default:
1375 dev_warn(&device->dev, "Unknown PID Reg value 0x%x, "
1376 "defaulting to LCD revision 1\n",
1377 lcdc_read(LCD_PID_REG));
1378 lcd_revision = LCD_VERSION_1;
1379 break;
1380 }
1381
1382 lcd_cfg = (struct lcd_ctrl_config *)fb_pdata->controller_data;
1383
1384 if (!lcd_cfg) {
1385 ret = -EINVAL;
1386 goto err_pm_runtime_disable;
1387 }
1388
1389 da8xx_fb_info = framebuffer_alloc(sizeof(struct da8xx_fb_par),
1390 &device->dev);
1391 if (!da8xx_fb_info) {
1392 ret = -ENOMEM;
1393 goto err_pm_runtime_disable;
1394 }
1395
1396 par = da8xx_fb_info->par;
1397 par->dev = &device->dev;
1398 par->lcdc_clk = tmp_lcdc_clk;
1399 par->lcdc_clk_rate = clk_get_rate(par->lcdc_clk);
1400
1401 par->lcd_supply = devm_regulator_get_optional(&device->dev, "lcd");
1402 if (IS_ERR(par->lcd_supply)) {
1403 if (PTR_ERR(par->lcd_supply) == -EPROBE_DEFER) {
1404 ret = -EPROBE_DEFER;
1405 goto err_release_fb;
1406 }
1407
1408 par->lcd_supply = NULL;
1409 } else {
1410 ret = regulator_enable(par->lcd_supply);
1411 if (ret)
1412 goto err_release_fb;
1413 }
1414
1415 fb_videomode_to_var(&da8xx_fb_var, lcdc_info);
1416 par->cfg = *lcd_cfg;
1417
1418 da8xx_fb_lcd_reset();
1419
1420 /* allocate frame buffer */
1421 par->vram_size = lcdc_info->xres * lcdc_info->yres * lcd_cfg->bpp;
1422 ulcm = lcm((lcdc_info->xres * lcd_cfg->bpp)/8, PAGE_SIZE);
1423 par->vram_size = roundup(par->vram_size/8, ulcm);
1424 par->vram_size = par->vram_size * LCD_NUM_BUFFERS;
1425
1426 par->vram_virt = dmam_alloc_coherent(par->dev,
1427 par->vram_size,
1428 &par->vram_phys,
1429 GFP_KERNEL | GFP_DMA);
1430 if (!par->vram_virt) {
1431 dev_err(&device->dev,
1432 "GLCD: kmalloc for frame buffer failed\n");
1433 ret = -EINVAL;
1434 goto err_release_fb;
1435 }
1436
1437 da8xx_fb_info->screen_base = (char __iomem *) par->vram_virt;
1438 da8xx_fb_fix.smem_start = par->vram_phys;
1439 da8xx_fb_fix.smem_len = par->vram_size;
1440 da8xx_fb_fix.line_length = (lcdc_info->xres * lcd_cfg->bpp) / 8;
1441
1442 par->dma_start = par->vram_phys;
1443 par->dma_end = par->dma_start + lcdc_info->yres *
1444 da8xx_fb_fix.line_length - 1;
1445
1446 /* allocate palette buffer */
1447 par->v_palette_base = dmam_alloc_coherent(par->dev, PALETTE_SIZE,
1448 &par->p_palette_base,
1449 GFP_KERNEL | GFP_DMA);
1450 if (!par->v_palette_base) {
1451 dev_err(&device->dev,
1452 "GLCD: kmalloc for palette buffer failed\n");
1453 ret = -EINVAL;
1454 goto err_release_fb;
1455 }
1456
1457 par->irq = platform_get_irq(device, 0);
1458 if (par->irq < 0) {
1459 ret = -ENOENT;
1460 goto err_release_fb;
1461 }
1462
1463 da8xx_fb_var.grayscale =
1464 lcd_cfg->panel_shade == MONOCHROME ? 1 : 0;
1465 da8xx_fb_var.bits_per_pixel = lcd_cfg->bpp;
1466
1467 /* Initialize fbinfo */
1468 da8xx_fb_info->flags = FBINFO_FLAG_DEFAULT;
1469 da8xx_fb_info->fix = da8xx_fb_fix;
1470 da8xx_fb_info->var = da8xx_fb_var;
1471 da8xx_fb_info->fbops = &da8xx_fb_ops;
1472 da8xx_fb_info->pseudo_palette = par->pseudo_palette;
1473 da8xx_fb_info->fix.visual = (da8xx_fb_info->var.bits_per_pixel <= 8) ?
1474 FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_TRUECOLOR;
1475
1476 ret = fb_alloc_cmap(&da8xx_fb_info->cmap, PALETTE_SIZE, 0);
1477 if (ret)
1478 goto err_release_fb;
1479 da8xx_fb_info->cmap.len = par->palette_sz;
1480
1481 /* initialize var_screeninfo */
1482 da8xx_fb_var.activate = FB_ACTIVATE_FORCE;
1483 fb_set_var(da8xx_fb_info, &da8xx_fb_var);
1484
1485 dev_set_drvdata(&device->dev, da8xx_fb_info);
1486
1487 /* initialize the vsync wait queue */
1488 init_waitqueue_head(&par->vsync_wait);
1489 par->vsync_timeout = HZ / 5;
1490 par->which_dma_channel_done = -1;
1491 spin_lock_init(&par->lock_for_chan_update);
1492
1493 /* Register the Frame Buffer */
1494 if (register_framebuffer(da8xx_fb_info) < 0) {
1495 dev_err(&device->dev,
1496 "GLCD: Frame Buffer Registration Failed!\n");
1497 ret = -EINVAL;
1498 goto err_dealloc_cmap;
1499 }
1500
1501 #ifdef CONFIG_CPU_FREQ
1502 ret = lcd_da8xx_cpufreq_register(par);
1503 if (ret) {
1504 dev_err(&device->dev, "failed to register cpufreq\n");
1505 goto err_cpu_freq;
1506 }
1507 #endif
1508
1509 if (lcd_revision == LCD_VERSION_1)
1510 lcdc_irq_handler = lcdc_irq_handler_rev01;
1511 else {
1512 init_waitqueue_head(&frame_done_wq);
1513 lcdc_irq_handler = lcdc_irq_handler_rev02;
1514 }
1515
1516 ret = devm_request_irq(&device->dev, par->irq, lcdc_irq_handler, 0,
1517 DRIVER_NAME, par);
1518 if (ret)
1519 goto irq_freq;
1520 return 0;
1521
1522 irq_freq:
1523 #ifdef CONFIG_CPU_FREQ
1524 lcd_da8xx_cpufreq_deregister(par);
1525 err_cpu_freq:
1526 #endif
1527 unregister_framebuffer(da8xx_fb_info);
1528
1529 err_dealloc_cmap:
1530 fb_dealloc_cmap(&da8xx_fb_info->cmap);
1531
1532 err_release_fb:
1533 framebuffer_release(da8xx_fb_info);
1534
1535 err_pm_runtime_disable:
1536 pm_runtime_put_sync(&device->dev);
1537 pm_runtime_disable(&device->dev);
1538
1539 return ret;
1540 }
1541
1542 #ifdef CONFIG_PM_SLEEP
1543 static struct lcdc_context {
1544 u32 clk_enable;
1545 u32 ctrl;
1546 u32 dma_ctrl;
1547 u32 raster_timing_0;
1548 u32 raster_timing_1;
1549 u32 raster_timing_2;
1550 u32 int_enable_set;
1551 u32 dma_frm_buf_base_addr_0;
1552 u32 dma_frm_buf_ceiling_addr_0;
1553 u32 dma_frm_buf_base_addr_1;
1554 u32 dma_frm_buf_ceiling_addr_1;
1555 u32 raster_ctrl;
1556 } reg_context;
1557
1558 static void lcd_context_save(void)
1559 {
1560 if (lcd_revision == LCD_VERSION_2) {
1561 reg_context.clk_enable = lcdc_read(LCD_CLK_ENABLE_REG);
1562 reg_context.int_enable_set = lcdc_read(LCD_INT_ENABLE_SET_REG);
1563 }
1564
1565 reg_context.ctrl = lcdc_read(LCD_CTRL_REG);
1566 reg_context.dma_ctrl = lcdc_read(LCD_DMA_CTRL_REG);
1567 reg_context.raster_timing_0 = lcdc_read(LCD_RASTER_TIMING_0_REG);
1568 reg_context.raster_timing_1 = lcdc_read(LCD_RASTER_TIMING_1_REG);
1569 reg_context.raster_timing_2 = lcdc_read(LCD_RASTER_TIMING_2_REG);
1570 reg_context.dma_frm_buf_base_addr_0 =
1571 lcdc_read(LCD_DMA_FRM_BUF_BASE_ADDR_0_REG);
1572 reg_context.dma_frm_buf_ceiling_addr_0 =
1573 lcdc_read(LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG);
1574 reg_context.dma_frm_buf_base_addr_1 =
1575 lcdc_read(LCD_DMA_FRM_BUF_BASE_ADDR_1_REG);
1576 reg_context.dma_frm_buf_ceiling_addr_1 =
1577 lcdc_read(LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG);
1578 reg_context.raster_ctrl = lcdc_read(LCD_RASTER_CTRL_REG);
1579 return;
1580 }
1581
1582 static void lcd_context_restore(void)
1583 {
1584 if (lcd_revision == LCD_VERSION_2) {
1585 lcdc_write(reg_context.clk_enable, LCD_CLK_ENABLE_REG);
1586 lcdc_write(reg_context.int_enable_set, LCD_INT_ENABLE_SET_REG);
1587 }
1588
1589 lcdc_write(reg_context.ctrl, LCD_CTRL_REG);
1590 lcdc_write(reg_context.dma_ctrl, LCD_DMA_CTRL_REG);
1591 lcdc_write(reg_context.raster_timing_0, LCD_RASTER_TIMING_0_REG);
1592 lcdc_write(reg_context.raster_timing_1, LCD_RASTER_TIMING_1_REG);
1593 lcdc_write(reg_context.raster_timing_2, LCD_RASTER_TIMING_2_REG);
1594 lcdc_write(reg_context.dma_frm_buf_base_addr_0,
1595 LCD_DMA_FRM_BUF_BASE_ADDR_0_REG);
1596 lcdc_write(reg_context.dma_frm_buf_ceiling_addr_0,
1597 LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG);
1598 lcdc_write(reg_context.dma_frm_buf_base_addr_1,
1599 LCD_DMA_FRM_BUF_BASE_ADDR_1_REG);
1600 lcdc_write(reg_context.dma_frm_buf_ceiling_addr_1,
1601 LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG);
1602 lcdc_write(reg_context.raster_ctrl, LCD_RASTER_CTRL_REG);
1603 return;
1604 }
1605
1606 static int fb_suspend(struct device *dev)
1607 {
1608 struct fb_info *info = dev_get_drvdata(dev);
1609 struct da8xx_fb_par *par = info->par;
1610 int ret;
1611
1612 console_lock();
1613 if (par->lcd_supply) {
1614 ret = regulator_disable(par->lcd_supply);
1615 if (ret)
1616 return ret;
1617 }
1618
1619 fb_set_suspend(info, 1);
1620 lcd_disable_raster(DA8XX_FRAME_WAIT);
1621 lcd_context_save();
1622 pm_runtime_put_sync(dev);
1623 console_unlock();
1624
1625 return 0;
1626 }
1627 static int fb_resume(struct device *dev)
1628 {
1629 struct fb_info *info = dev_get_drvdata(dev);
1630 struct da8xx_fb_par *par = info->par;
1631 int ret;
1632
1633 console_lock();
1634 pm_runtime_get_sync(dev);
1635 lcd_context_restore();
1636 if (par->blank == FB_BLANK_UNBLANK) {
1637 lcd_enable_raster();
1638
1639 if (par->lcd_supply) {
1640 ret = regulator_enable(par->lcd_supply);
1641 if (ret)
1642 return ret;
1643 }
1644 }
1645
1646 fb_set_suspend(info, 0);
1647 console_unlock();
1648
1649 return 0;
1650 }
1651 #endif
1652
1653 static SIMPLE_DEV_PM_OPS(fb_pm_ops, fb_suspend, fb_resume);
1654
1655 static struct platform_driver da8xx_fb_driver = {
1656 .probe = fb_probe,
1657 .remove = fb_remove,
1658 .driver = {
1659 .name = DRIVER_NAME,
1660 .pm = &fb_pm_ops,
1661 },
1662 };
1663 module_platform_driver(da8xx_fb_driver);
1664
1665 MODULE_DESCRIPTION("Framebuffer driver for TI da8xx/omap-l1xx");
1666 MODULE_AUTHOR("Texas Instruments");
1667 MODULE_LICENSE("GPL");
Linux with added FPC-III support