drivers/video/fbdev/matrox/matroxfb_Ti3026.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  *
   4  * Hardware accelerated Matrox Millennium I, II, Mystique, G100, G200 and G400
   5  *
   6  * (c) 1998-2002 Petr Vandrovec <vandrove@vc.cvut.cz>
   7  *
   8  * Portions Copyright (c) 2001 Matrox Graphics Inc.
   9  *
  10  * Version: 1.65 2002/08/14
  11  *
  12  * MTRR stuff: 1998 Tom Rini <trini@kernel.crashing.org>
  13  *
  14  * Contributors: "menion?" <menion@mindless.com>
  15  *                     Betatesting, fixes, ideas
  16  *
  17  *               "Kurt Garloff" <garloff@suse.de>
  18  *                     Betatesting, fixes, ideas, videomodes, videomodes timmings
  19  *
  20  *               "Tom Rini" <trini@kernel.crashing.org>
  21  *                     MTRR stuff, PPC cleanups, betatesting, fixes, ideas
  22  *
  23  *               "Bibek Sahu" <scorpio@dodds.net>
  24  *                     Access device through readb|w|l and write b|w|l
  25  *                     Extensive debugging stuff
  26  *
  27  *               "Daniel Haun" <haund@usa.net>
  28  *                     Testing, hardware cursor fixes
  29  *
  30  *               "Scott Wood" <sawst46+@pitt.edu>
  31  *                     Fixes
  32  *
  33  *               "Gerd Knorr" <kraxel@goldbach.isdn.cs.tu-berlin.de>
  34  *                     Betatesting
  35  *
  36  *               "Kelly French" <targon@hazmat.com>
  37  *               "Fernando Herrera" <fherrera@eurielec.etsit.upm.es>
  38  *                     Betatesting, bug reporting
  39  *
  40  *               "Pablo Bianucci" <pbian@pccp.com.ar>
  41  *                     Fixes, ideas, betatesting
  42  *
  43  *               "Inaky Perez Gonzalez" <inaky@peloncho.fis.ucm.es>
  44  *                     Fixes, enhandcements, ideas, betatesting
  45  *
  46  *               "Ryuichi Oikawa" <roikawa@rr.iiij4u.or.jp>
  47  *                     PPC betatesting, PPC support, backward compatibility
  48  *
  49  *               "Paul Womar" <Paul@pwomar.demon.co.uk>
  50  *               "Owen Waller" <O.Waller@ee.qub.ac.uk>
  51  *                     PPC betatesting
  52  *
  53  *               "Thomas Pornin" <pornin@bolet.ens.fr>
  54  *                     Alpha betatesting
  55  *
  56  *               "Pieter van Leuven" <pvl@iae.nl>
  57  *               "Ulf Jaenicke-Roessler" <ujr@physik.phy.tu-dresden.de>
  58  *                     G100 testing
  59  *
  60  *               "H. Peter Arvin" <hpa@transmeta.com>
  61  *                     Ideas
  62  *
  63  *               "Cort Dougan" <cort@cs.nmt.edu>
  64  *                     CHRP fixes and PReP cleanup
  65  *
  66  *               "Mark Vojkovich" <mvojkovi@ucsd.edu>
  67  *                     G400 support
  68  *
  69  * (following author is not in any relation with this code, but his code
  70  *  is included in this driver)
  71  *
  72  * Based on framebuffer driver for VBE 2.0 compliant graphic boards
  73  *     (c) 1998 Gerd Knorr <kraxel@cs.tu-berlin.de>
  74  *
  75  * (following author is not in any relation with this code, but his ideas
  76  *  were used when writing this driver)
  77  *
  78  *               FreeVBE/AF (Matrox), "Shawn Hargreaves" <shawn@talula.demon.co.uk>
  79  *
  80  */
  81
  82
  83 #include "matroxfb_Ti3026.h"
  84 #include "matroxfb_misc.h"
  85 #include "matroxfb_accel.h"
  86 #include <linux/matroxfb.h>
  87
  88 #ifdef CONFIG_FB_MATROX_MILLENIUM
  89 #define outTi3026 matroxfb_DAC_out
  90 #define inTi3026 matroxfb_DAC_in
  91
  92 #define TVP3026_INDEX           0x00
  93 #define TVP3026_PALWRADD        0x00
  94 #define TVP3026_PALDATA         0x01
  95 #define TVP3026_PIXRDMSK        0x02
  96 #define TVP3026_PALRDADD        0x03
  97 #define TVP3026_CURCOLWRADD     0x04
  98 #define     TVP3026_CLOVERSCAN          0x00
  99 #define     TVP3026_CLCOLOR0            0x01
 100 #define     TVP3026_CLCOLOR1            0x02
 101 #define     TVP3026_CLCOLOR2            0x03
 102 #define TVP3026_CURCOLDATA      0x05
 103 #define TVP3026_CURCOLRDADD     0x07
 104 #define TVP3026_CURCTRL         0x09
 105 #define TVP3026_X_DATAREG       0x0A
 106 #define TVP3026_CURRAMDATA      0x0B
 107 #define TVP3026_CURPOSXL        0x0C
 108 #define TVP3026_CURPOSXH        0x0D
 109 #define TVP3026_CURPOSYL        0x0E
 110 #define TVP3026_CURPOSYH        0x0F
 111
 112 #define TVP3026_XSILICONREV     0x01
 113 #define TVP3026_XCURCTRL        0x06
 114 #define     TVP3026_XCURCTRL_DIS        0x00    /* transparent, transparent, transparent, transparent */
 115 #define     TVP3026_XCURCTRL_3COLOR     0x01    /* transparent, 0, 1, 2 */
 116 #define     TVP3026_XCURCTRL_XGA        0x02    /* 0, 1, transparent, complement */
 117 #define     TVP3026_XCURCTRL_XWIN       0x03    /* transparent, transparent, 0, 1 */
 118 #define     TVP3026_XCURCTRL_BLANK2048  0x00
 119 #define     TVP3026_XCURCTRL_BLANK4096  0x10
 120 #define     TVP3026_XCURCTRL_INTERLACED 0x20
 121 #define     TVP3026_XCURCTRL_ODD        0x00 /* ext.signal ODD/\EVEN */
 122 #define     TVP3026_XCURCTRL_EVEN       0x40 /* ext.signal EVEN/\ODD */
 123 #define     TVP3026_XCURCTRL_INDIRECT   0x00
 124 #define     TVP3026_XCURCTRL_DIRECT     0x80
 125 #define TVP3026_XLATCHCTRL      0x0F
 126 #define     TVP3026_XLATCHCTRL_1_1      0x06
 127 #define     TVP3026_XLATCHCTRL_2_1      0x07
 128 #define     TVP3026_XLATCHCTRL_4_1      0x06
 129 #define     TVP3026_XLATCHCTRL_8_1      0x06
 130 #define     TVP3026_XLATCHCTRL_16_1     0x06
 131 #define     TVP3026A_XLATCHCTRL_4_3     0x06    /* ??? do not understand... but it works... !!! */
 132 #define     TVP3026A_XLATCHCTRL_8_3     0x07
 133 #define     TVP3026B_XLATCHCTRL_4_3     0x08
 134 #define     TVP3026B_XLATCHCTRL_8_3     0x06    /* ??? do not understand... but it works... !!! */
 135 #define TVP3026_XTRUECOLORCTRL  0x18
 136 #define     TVP3026_XTRUECOLORCTRL_VRAM_SHIFT_ACCEL     0x00
 137 #define     TVP3026_XTRUECOLORCTRL_VRAM_SHIFT_TVP       0x20
 138 #define     TVP3026_XTRUECOLORCTRL_PSEUDOCOLOR          0x80
 139 #define     TVP3026_XTRUECOLORCTRL_TRUECOLOR            0x40 /* paletized */
 140 #define     TVP3026_XTRUECOLORCTRL_DIRECTCOLOR          0x00
 141 #define     TVP3026_XTRUECOLORCTRL_24_ALTERNATE         0x08 /* 5:4/5:2 instead of 4:3/8:3 */
 142 #define     TVP3026_XTRUECOLORCTRL_RGB_888              0x16 /* 4:3/8:3 (or 5:4/5:2) */
 143 #define     TVP3026_XTRUECOLORCTRL_BGR_888              0x17
 144 #define     TVP3026_XTRUECOLORCTRL_ORGB_8888            0x06
 145 #define     TVP3026_XTRUECOLORCTRL_BGRO_8888            0x07
 146 #define     TVP3026_XTRUECOLORCTRL_RGB_565              0x05
 147 #define     TVP3026_XTRUECOLORCTRL_ORGB_1555            0x04
 148 #define     TVP3026_XTRUECOLORCTRL_RGB_664              0x03
 149 #define     TVP3026_XTRUECOLORCTRL_RGBO_4444            0x01
 150 #define TVP3026_XMUXCTRL        0x19
 151 #define     TVP3026_XMUXCTRL_MEMORY_8BIT                        0x01 /* - */
 152 #define     TVP3026_XMUXCTRL_MEMORY_16BIT                       0x02 /* - */
 153 #define     TVP3026_XMUXCTRL_MEMORY_32BIT                       0x03 /* 2MB RAM, 512K * 4 */
 154 #define     TVP3026_XMUXCTRL_MEMORY_64BIT                       0x04 /* >2MB RAM, 512K * 8 & more */
 155 #define     TVP3026_XMUXCTRL_PIXEL_4BIT                         0x40 /* L0,H0,L1,H1... */
 156 #define     TVP3026_XMUXCTRL_PIXEL_4BIT_SWAPPED                 0x60 /* H0,L0,H1,L1... */
 157 #define     TVP3026_XMUXCTRL_PIXEL_8BIT                         0x48
 158 #define     TVP3026_XMUXCTRL_PIXEL_16BIT                        0x50
 159 #define     TVP3026_XMUXCTRL_PIXEL_32BIT                        0x58
 160 #define     TVP3026_XMUXCTRL_VGA                                0x98 /* VGA MEMORY, 8BIT PIXEL */
 161 #define TVP3026_XCLKCTRL        0x1A
 162 #define     TVP3026_XCLKCTRL_DIV1       0x00
 163 #define     TVP3026_XCLKCTRL_DIV2       0x10
 164 #define     TVP3026_XCLKCTRL_DIV4       0x20
 165 #define     TVP3026_XCLKCTRL_DIV8       0x30
 166 #define     TVP3026_XCLKCTRL_DIV16      0x40
 167 #define     TVP3026_XCLKCTRL_DIV32      0x50
 168 #define     TVP3026_XCLKCTRL_DIV64      0x60
 169 #define     TVP3026_XCLKCTRL_CLKSTOPPED 0x70
 170 #define     TVP3026_XCLKCTRL_SRC_CLK0   0x00
 171 #define     TVP3026_XCLKCTRL_SRC_CLK1   0x01
 172 #define     TVP3026_XCLKCTRL_SRC_CLK2   0x02    /* CLK2 is TTL source*/
 173 #define     TVP3026_XCLKCTRL_SRC_NCLK2  0x03    /* not CLK2 is TTL source */
 174 #define     TVP3026_XCLKCTRL_SRC_ECLK2  0x04    /* CLK2 and not CLK2 is ECL source */
 175 #define     TVP3026_XCLKCTRL_SRC_PLL    0x05
 176 #define     TVP3026_XCLKCTRL_SRC_DIS    0x06    /* disable & poweroff internal clock */
 177 #define     TVP3026_XCLKCTRL_SRC_CLK0VGA 0x07
 178 #define TVP3026_XPALETTEPAGE    0x1C
 179 #define TVP3026_XGENCTRL        0x1D
 180 #define     TVP3026_XGENCTRL_HSYNC_POS  0x00
 181 #define     TVP3026_XGENCTRL_HSYNC_NEG  0x01
 182 #define     TVP3026_XGENCTRL_VSYNC_POS  0x00
 183 #define     TVP3026_XGENCTRL_VSYNC_NEG  0x02
 184 #define     TVP3026_XGENCTRL_LITTLE_ENDIAN 0x00
 185 #define     TVP3026_XGENCTRL_BIG_ENDIAN    0x08
 186 #define     TVP3026_XGENCTRL_BLACK_0IRE         0x00
 187 #define     TVP3026_XGENCTRL_BLACK_75IRE        0x10
 188 #define     TVP3026_XGENCTRL_NO_SYNC_ON_GREEN   0x00
 189 #define     TVP3026_XGENCTRL_SYNC_ON_GREEN      0x20
 190 #define     TVP3026_XGENCTRL_OVERSCAN_DIS       0x00
 191 #define     TVP3026_XGENCTRL_OVERSCAN_EN        0x40
 192 #define TVP3026_XMISCCTRL       0x1E
 193 #define     TVP3026_XMISCCTRL_DAC_PUP   0x00
 194 #define     TVP3026_XMISCCTRL_DAC_PDOWN 0x01
 195 #define     TVP3026_XMISCCTRL_DAC_EXT   0x00 /* or 8, bit 3 is ignored */
 196 #define     TVP3026_XMISCCTRL_DAC_6BIT  0x04
 197 #define     TVP3026_XMISCCTRL_DAC_8BIT  0x0C
 198 #define     TVP3026_XMISCCTRL_PSEL_DIS  0x00
 199 #define     TVP3026_XMISCCTRL_PSEL_EN   0x10
 200 #define     TVP3026_XMISCCTRL_PSEL_LOW  0x00 /* PSEL high selects directcolor */
 201 #define     TVP3026_XMISCCTRL_PSEL_HIGH 0x20 /* PSEL high selects truecolor or pseudocolor */
 202 #define TVP3026_XGENIOCTRL      0x2A
 203 #define TVP3026_XGENIODATA      0x2B
 204 #define TVP3026_XPLLADDR        0x2C
 205 #define     TVP3026_XPLLADDR_X(LOOP,MCLK,PIX) (((LOOP)<<4) | ((MCLK)<<2) | (PIX))
 206 #define     TVP3026_XPLLDATA_N          0x00
 207 #define     TVP3026_XPLLDATA_M          0x01
 208 #define     TVP3026_XPLLDATA_P          0x02
 209 #define     TVP3026_XPLLDATA_STAT       0x03
 210 #define TVP3026_XPIXPLLDATA     0x2D
 211 #define TVP3026_XMEMPLLDATA     0x2E
 212 #define TVP3026_XLOOPPLLDATA    0x2F
 213 #define TVP3026_XCOLKEYOVRMIN   0x30
 214 #define TVP3026_XCOLKEYOVRMAX   0x31
 215 #define TVP3026_XCOLKEYREDMIN   0x32
 216 #define TVP3026_XCOLKEYREDMAX   0x33
 217 #define TVP3026_XCOLKEYGREENMIN 0x34
 218 #define TVP3026_XCOLKEYGREENMAX 0x35
 219 #define TVP3026_XCOLKEYBLUEMIN  0x36
 220 #define TVP3026_XCOLKEYBLUEMAX  0x37
 221 #define TVP3026_XCOLKEYCTRL     0x38
 222 #define     TVP3026_XCOLKEYCTRL_OVR_EN  0x01
 223 #define     TVP3026_XCOLKEYCTRL_RED_EN  0x02
 224 #define     TVP3026_XCOLKEYCTRL_GREEN_EN 0x04
 225 #define     TVP3026_XCOLKEYCTRL_BLUE_EN 0x08
 226 #define     TVP3026_XCOLKEYCTRL_NEGATE  0x10
 227 #define     TVP3026_XCOLKEYCTRL_ZOOM1   0x00
 228 #define     TVP3026_XCOLKEYCTRL_ZOOM2   0x20
 229 #define     TVP3026_XCOLKEYCTRL_ZOOM4   0x40
 230 #define     TVP3026_XCOLKEYCTRL_ZOOM8   0x60
 231 #define     TVP3026_XCOLKEYCTRL_ZOOM16  0x80
 232 #define     TVP3026_XCOLKEYCTRL_ZOOM32  0xA0
 233 #define TVP3026_XMEMPLLCTRL     0x39
 234 #define     TVP3026_XMEMPLLCTRL_DIV(X)  (((X)-1)>>1)    /* 2,4,6,8,10,12,14,16, division applied to LOOP PLL after divide by 2^P */
 235 #define     TVP3026_XMEMPLLCTRL_STROBEMKC4      0x08
 236 #define     TVP3026_XMEMPLLCTRL_MCLK_DOTCLOCK   0x00    /* MKC4 */
 237 #define     TVP3026_XMEMPLLCTRL_MCLK_MCLKPLL    0x10    /* MKC4 */
 238 #define     TVP3026_XMEMPLLCTRL_RCLK_PIXPLL     0x00
 239 #define     TVP3026_XMEMPLLCTRL_RCLK_LOOPPLL    0x20
 240 #define     TVP3026_XMEMPLLCTRL_RCLK_DOTDIVN    0x40    /* dot clock divided by loop pclk N prescaler */
 241 #define TVP3026_XSENSETEST      0x3A
 242 #define TVP3026_XTESTMODEDATA   0x3B
 243 #define TVP3026_XCRCREML        0x3C
 244 #define TVP3026_XCRCREMH        0x3D
 245 #define TVP3026_XCRCBITSEL      0x3E
 246 #define TVP3026_XID             0x3F
 247
 248 static const unsigned char DACseq[] =
 249 { TVP3026_XLATCHCTRL, TVP3026_XTRUECOLORCTRL,
 250   TVP3026_XMUXCTRL, TVP3026_XCLKCTRL,
 251   TVP3026_XPALETTEPAGE,
 252   TVP3026_XGENCTRL,
 253   TVP3026_XMISCCTRL,
 254   TVP3026_XGENIOCTRL,
 255   TVP3026_XGENIODATA,
 256   TVP3026_XCOLKEYOVRMIN, TVP3026_XCOLKEYOVRMAX, TVP3026_XCOLKEYREDMIN, TVP3026_XCOLKEYREDMAX,
 257   TVP3026_XCOLKEYGREENMIN, TVP3026_XCOLKEYGREENMAX, TVP3026_XCOLKEYBLUEMIN, TVP3026_XCOLKEYBLUEMAX,
 258   TVP3026_XCOLKEYCTRL,
 259   TVP3026_XMEMPLLCTRL, TVP3026_XSENSETEST, TVP3026_XCURCTRL };
 260
 261 #define POS3026_XLATCHCTRL      0
 262 #define POS3026_XTRUECOLORCTRL  1
 263 #define POS3026_XMUXCTRL        2
 264 #define POS3026_XCLKCTRL        3
 265 #define POS3026_XGENCTRL        5
 266 #define POS3026_XMISCCTRL       6
 267 #define POS3026_XMEMPLLCTRL     18
 268 #define POS3026_XCURCTRL        20
 269
 270 static const unsigned char MGADACbpp32[] =
 271 { TVP3026_XLATCHCTRL_2_1, TVP3026_XTRUECOLORCTRL_DIRECTCOLOR | TVP3026_XTRUECOLORCTRL_ORGB_8888,
 272   0x00, TVP3026_XCLKCTRL_DIV1 | TVP3026_XCLKCTRL_SRC_PLL,
 273   0x00,
 274   TVP3026_XGENCTRL_HSYNC_POS | TVP3026_XGENCTRL_VSYNC_POS | TVP3026_XGENCTRL_LITTLE_ENDIAN | TVP3026_XGENCTRL_BLACK_0IRE | TVP3026_XGENCTRL_NO_SYNC_ON_GREEN | TVP3026_XGENCTRL_OVERSCAN_DIS,
 275   TVP3026_XMISCCTRL_DAC_PUP | TVP3026_XMISCCTRL_DAC_8BIT | TVP3026_XMISCCTRL_PSEL_DIS | TVP3026_XMISCCTRL_PSEL_HIGH,
 276   0x00,
 277   0x1E,
 278   0xFF, 0xFF, 0xFF, 0xFF,
 279   0xFF, 0xFF, 0xFF, 0xFF,
 280   TVP3026_XCOLKEYCTRL_ZOOM1,
 281   0x00, 0x00, TVP3026_XCURCTRL_DIS };
 282
 283 static int Ti3026_calcclock(const struct matrox_fb_info *minfo,
 284                             unsigned int freq, unsigned int fmax, int *in,
 285                             int *feed, int *post)
 286 {
 287         unsigned int fvco;
 288         unsigned int lin, lfeed, lpost;
 289
 290         DBG(__func__)
 291
 292         fvco = PLL_calcclock(minfo, freq, fmax, &lin, &lfeed, &lpost);
 293         fvco >>= (*post = lpost);
 294         *in = 64 - lin;
 295         *feed = 64 - lfeed;
 296         return fvco;
 297 }
 298
 299 static int Ti3026_setpclk(struct matrox_fb_info *minfo, int clk)
 300 {
 301         unsigned int f_pll;
 302         unsigned int pixfeed, pixin, pixpost;
 303         struct matrox_hw_state *hw = &minfo->hw;
 304
 305         DBG(__func__)
 306
 307         f_pll = Ti3026_calcclock(minfo, clk, minfo->max_pixel_clock, &pixin, &pixfeed, &pixpost);
 308
 309         hw->DACclk[0] = pixin | 0xC0;
 310         hw->DACclk[1] = pixfeed;
 311         hw->DACclk[2] = pixpost | 0xB0;
 312
 313         {
 314                 unsigned int loopfeed, loopin, looppost, loopdiv, z;
 315                 unsigned int Bpp;
 316
 317                 Bpp = minfo->curr.final_bppShift;
 318
 319                 if (minfo->fbcon.var.bits_per_pixel == 24) {
 320                         loopfeed = 3;           /* set lm to any possible value */
 321                         loopin = 3 * 32 / Bpp;
 322                 } else {
 323                         loopfeed = 4;
 324                         loopin = 4 * 32 / Bpp;
 325                 }
 326                 z = (110000 * loopin) / (f_pll * loopfeed);
 327                 loopdiv = 0; /* div 2 */
 328                 if (z < 2)
 329                         looppost = 0;
 330                 else if (z < 4)
 331                         looppost = 1;
 332                 else if (z < 8)
 333                         looppost = 2;
 334                 else {
 335                         looppost = 3;
 336                         loopdiv = z/16;
 337                 }
 338                 if (minfo->fbcon.var.bits_per_pixel == 24) {
 339                         hw->DACclk[3] = ((65 - loopin) & 0x3F) | 0xC0;
 340                         hw->DACclk[4] = (65 - loopfeed) | 0x80;
 341                         if (minfo->accel.ramdac_rev > 0x20) {
 342                                 if (isInterleave(minfo))
 343                                         hw->DACreg[POS3026_XLATCHCTRL] = TVP3026B_XLATCHCTRL_8_3;
 344                                 else {
 345                                         hw->DACclk[4] &= ~0xC0;
 346                                         hw->DACreg[POS3026_XLATCHCTRL] = TVP3026B_XLATCHCTRL_4_3;
 347                                 }
 348                         } else {
 349                                 if (isInterleave(minfo))
 350                                         ;       /* default... */
 351                                 else {
 352                                         hw->DACclk[4] ^= 0xC0;  /* change from 0x80 to 0x40 */
 353                                         hw->DACreg[POS3026_XLATCHCTRL] = TVP3026A_XLATCHCTRL_4_3;
 354                                 }
 355                         }
 356                         hw->DACclk[5] = looppost | 0xF8;
 357                         if (minfo->devflags.mga_24bpp_fix)
 358                                 hw->DACclk[5] ^= 0x40;
 359                 } else {
 360                         hw->DACclk[3] = ((65 - loopin) & 0x3F) | 0xC0;
 361                         hw->DACclk[4] = 65 - loopfeed;
 362                         hw->DACclk[5] = looppost | 0xF0;
 363                 }
 364                 hw->DACreg[POS3026_XMEMPLLCTRL] = loopdiv | TVP3026_XMEMPLLCTRL_MCLK_MCLKPLL | TVP3026_XMEMPLLCTRL_RCLK_LOOPPLL;
 365         }
 366         return 0;
 367 }
 368
 369 static int Ti3026_init(struct matrox_fb_info *minfo, struct my_timming *m)
 370 {
 371         u_int8_t muxctrl = isInterleave(minfo) ? TVP3026_XMUXCTRL_MEMORY_64BIT : TVP3026_XMUXCTRL_MEMORY_32BIT;
 372         struct matrox_hw_state *hw = &minfo->hw;
 373
 374         DBG(__func__)
 375
 376         memcpy(hw->DACreg, MGADACbpp32, sizeof(MGADACbpp32));
 377         switch (minfo->fbcon.var.bits_per_pixel) {
 378                 case 4: hw->DACreg[POS3026_XLATCHCTRL] = TVP3026_XLATCHCTRL_16_1;       /* or _8_1, they are same */
 379                         hw->DACreg[POS3026_XTRUECOLORCTRL] = TVP3026_XTRUECOLORCTRL_PSEUDOCOLOR;
 380                         hw->DACreg[POS3026_XMUXCTRL] = muxctrl | TVP3026_XMUXCTRL_PIXEL_4BIT;
 381                         hw->DACreg[POS3026_XCLKCTRL] = TVP3026_XCLKCTRL_SRC_PLL | TVP3026_XCLKCTRL_DIV8;
 382                         hw->DACreg[POS3026_XMISCCTRL] = TVP3026_XMISCCTRL_DAC_PUP | TVP3026_XMISCCTRL_DAC_8BIT | TVP3026_XMISCCTRL_PSEL_DIS | TVP3026_XMISCCTRL_PSEL_LOW;
 383                         break;
 384                 case 8: hw->DACreg[POS3026_XLATCHCTRL] = TVP3026_XLATCHCTRL_8_1;        /* or _4_1, they are same */
 385                         hw->DACreg[POS3026_XTRUECOLORCTRL] = TVP3026_XTRUECOLORCTRL_PSEUDOCOLOR;
 386                         hw->DACreg[POS3026_XMUXCTRL] = muxctrl | TVP3026_XMUXCTRL_PIXEL_8BIT;
 387                         hw->DACreg[POS3026_XCLKCTRL] = TVP3026_XCLKCTRL_SRC_PLL | TVP3026_XCLKCTRL_DIV4;
 388                         hw->DACreg[POS3026_XMISCCTRL] = TVP3026_XMISCCTRL_DAC_PUP | TVP3026_XMISCCTRL_DAC_8BIT | TVP3026_XMISCCTRL_PSEL_DIS | TVP3026_XMISCCTRL_PSEL_LOW;
 389                         break;
 390                 case 16:
 391                         /* XLATCHCTRL should be _4_1 / _2_1... Why is not? (_2_1 is used every time) */
 392                         hw->DACreg[POS3026_XTRUECOLORCTRL] = (minfo->fbcon.var.green.length == 5) ? (TVP3026_XTRUECOLORCTRL_DIRECTCOLOR | TVP3026_XTRUECOLORCTRL_ORGB_1555) : (TVP3026_XTRUECOLORCTRL_DIRECTCOLOR | TVP3026_XTRUECOLORCTRL_RGB_565);
 393                         hw->DACreg[POS3026_XMUXCTRL] = muxctrl | TVP3026_XMUXCTRL_PIXEL_16BIT;
 394                         hw->DACreg[POS3026_XCLKCTRL] = TVP3026_XCLKCTRL_SRC_PLL | TVP3026_XCLKCTRL_DIV2;
 395                         break;
 396                 case 24:
 397                         /* XLATCHCTRL is: for (A) use _4_3 (?_8_3 is same? TBD), for (B) it is set in setpclk */
 398                         hw->DACreg[POS3026_XTRUECOLORCTRL] = TVP3026_XTRUECOLORCTRL_DIRECTCOLOR | TVP3026_XTRUECOLORCTRL_RGB_888;
 399                         hw->DACreg[POS3026_XMUXCTRL] = muxctrl | TVP3026_XMUXCTRL_PIXEL_32BIT;
 400                         hw->DACreg[POS3026_XCLKCTRL] = TVP3026_XCLKCTRL_SRC_PLL | TVP3026_XCLKCTRL_DIV4;
 401                         break;
 402                 case 32:
 403                         /* XLATCHCTRL should be _2_1 / _1_1... Why is not? (_2_1 is used every time) */
 404                         hw->DACreg[POS3026_XMUXCTRL] = muxctrl | TVP3026_XMUXCTRL_PIXEL_32BIT;
 405                         break;
 406                 default:
 407                         return 1;       /* TODO: failed */
 408         }
 409         if (matroxfb_vgaHWinit(minfo, m)) return 1;
 410
 411         /* set SYNC */
 412         hw->MiscOutReg = 0xCB;
 413         if (m->sync & FB_SYNC_HOR_HIGH_ACT)
 414                 hw->DACreg[POS3026_XGENCTRL] |= TVP3026_XGENCTRL_HSYNC_NEG;
 415         if (m->sync & FB_SYNC_VERT_HIGH_ACT)
 416                 hw->DACreg[POS3026_XGENCTRL] |= TVP3026_XGENCTRL_VSYNC_NEG;
 417         if (m->sync & FB_SYNC_ON_GREEN)
 418                 hw->DACreg[POS3026_XGENCTRL] |= TVP3026_XGENCTRL_SYNC_ON_GREEN;
 419
 420         /* set DELAY */
 421         if (minfo->video.len < 0x400000)
 422                 hw->CRTCEXT[3] |= 0x08;
 423         else if (minfo->video.len > 0x400000)
 424                 hw->CRTCEXT[3] |= 0x10;
 425
 426         /* set HWCURSOR */
 427         if (m->interlaced) {
 428                 hw->DACreg[POS3026_XCURCTRL] |= TVP3026_XCURCTRL_INTERLACED;
 429         }
 430         if (m->HTotal >= 1536)
 431                 hw->DACreg[POS3026_XCURCTRL] |= TVP3026_XCURCTRL_BLANK4096;
 432
 433         /* set interleaving */
 434         hw->MXoptionReg &= ~0x00001000;
 435         if (isInterleave(minfo)) hw->MXoptionReg |= 0x00001000;
 436
 437         /* set DAC */
 438         Ti3026_setpclk(minfo, m->pixclock);
 439         return 0;
 440 }
 441
 442 static void ti3026_setMCLK(struct matrox_fb_info *minfo, int fout)
 443 {
 444         unsigned int f_pll;
 445         unsigned int pclk_m, pclk_n, pclk_p;
 446         unsigned int mclk_m, mclk_n, mclk_p;
 447         unsigned int rfhcnt, mclk_ctl;
 448         int tmout;
 449
 450         DBG(__func__)
 451
 452         f_pll = Ti3026_calcclock(minfo, fout, minfo->max_pixel_clock, &mclk_n, &mclk_m, &mclk_p);
 453
 454         /* save pclk */
 455         outTi3026(minfo, TVP3026_XPLLADDR, 0xFC);
 456         pclk_n = inTi3026(minfo, TVP3026_XPIXPLLDATA);
 457         outTi3026(minfo, TVP3026_XPLLADDR, 0xFD);
 458         pclk_m = inTi3026(minfo, TVP3026_XPIXPLLDATA);
 459         outTi3026(minfo, TVP3026_XPLLADDR, 0xFE);
 460         pclk_p = inTi3026(minfo, TVP3026_XPIXPLLDATA);
 461
 462         /* stop pclk */
 463         outTi3026(minfo, TVP3026_XPLLADDR, 0xFE);
 464         outTi3026(minfo, TVP3026_XPIXPLLDATA, 0x00);
 465
 466         /* set pclk to new mclk */
 467         outTi3026(minfo, TVP3026_XPLLADDR, 0xFC);
 468         outTi3026(minfo, TVP3026_XPIXPLLDATA, mclk_n | 0xC0);
 469         outTi3026(minfo, TVP3026_XPIXPLLDATA, mclk_m);
 470         outTi3026(minfo, TVP3026_XPIXPLLDATA, mclk_p | 0xB0);
 471
 472         /* wait for PLL to lock */
 473         for (tmout = 500000; tmout; tmout--) {
 474                 if (inTi3026(minfo, TVP3026_XPIXPLLDATA) & 0x40)
 475                         break;
 476                 udelay(10);
 477         }
 478         if (!tmout)
 479                 printk(KERN_ERR "matroxfb: Temporary pixel PLL not locked after 5 secs\n");
 480
 481         /* output pclk on mclk pin */
 482         mclk_ctl = inTi3026(minfo, TVP3026_XMEMPLLCTRL);
 483         outTi3026(minfo, TVP3026_XMEMPLLCTRL, mclk_ctl & 0xE7);
 484         outTi3026(minfo, TVP3026_XMEMPLLCTRL, (mclk_ctl & 0xE7) | TVP3026_XMEMPLLCTRL_STROBEMKC4);
 485
 486         /* stop MCLK */
 487         outTi3026(minfo, TVP3026_XPLLADDR, 0xFB);
 488         outTi3026(minfo, TVP3026_XMEMPLLDATA, 0x00);
 489
 490         /* set mclk to new freq */
 491         outTi3026(minfo, TVP3026_XPLLADDR, 0xF3);
 492         outTi3026(minfo, TVP3026_XMEMPLLDATA, mclk_n | 0xC0);
 493         outTi3026(minfo, TVP3026_XMEMPLLDATA, mclk_m);
 494         outTi3026(minfo, TVP3026_XMEMPLLDATA, mclk_p | 0xB0);
 495
 496         /* wait for PLL to lock */
 497         for (tmout = 500000; tmout; tmout--) {
 498                 if (inTi3026(minfo, TVP3026_XMEMPLLDATA) & 0x40)
 499                         break;
 500                 udelay(10);
 501         }
 502         if (!tmout)
 503                 printk(KERN_ERR "matroxfb: Memory PLL not locked after 5 secs\n");
 504
 505         f_pll = f_pll * 333 / (10000 << mclk_p);
 506         if (isMilleniumII(minfo)) {
 507                 rfhcnt = (f_pll - 128) / 256;
 508                 if (rfhcnt > 15)
 509                         rfhcnt = 15;
 510         } else {
 511                 rfhcnt = (f_pll - 64) / 128;
 512                 if (rfhcnt > 15)
 513                         rfhcnt = 0;
 514         }
 515         minfo->hw.MXoptionReg = (minfo->hw.MXoptionReg & ~0x000F0000) | (rfhcnt << 16);
 516         pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, minfo->hw.MXoptionReg);
 517
 518         /* output MCLK to MCLK pin */
 519         outTi3026(minfo, TVP3026_XMEMPLLCTRL, (mclk_ctl & 0xE7) | TVP3026_XMEMPLLCTRL_MCLK_MCLKPLL);
 520         outTi3026(minfo, TVP3026_XMEMPLLCTRL, (mclk_ctl       ) | TVP3026_XMEMPLLCTRL_MCLK_MCLKPLL | TVP3026_XMEMPLLCTRL_STROBEMKC4);
 521
 522         /* stop PCLK */
 523         outTi3026(minfo, TVP3026_XPLLADDR, 0xFE);
 524         outTi3026(minfo, TVP3026_XPIXPLLDATA, 0x00);
 525
 526         /* restore pclk */
 527         outTi3026(minfo, TVP3026_XPLLADDR, 0xFC);
 528         outTi3026(minfo, TVP3026_XPIXPLLDATA, pclk_n);
 529         outTi3026(minfo, TVP3026_XPIXPLLDATA, pclk_m);
 530         outTi3026(minfo, TVP3026_XPIXPLLDATA, pclk_p);
 531
 532         /* wait for PLL to lock */
 533         for (tmout = 500000; tmout; tmout--) {
 534                 if (inTi3026(minfo, TVP3026_XPIXPLLDATA) & 0x40)
 535                         break;
 536                 udelay(10);
 537         }
 538         if (!tmout)
 539                 printk(KERN_ERR "matroxfb: Pixel PLL not locked after 5 secs\n");
 540 }
 541
 542 static void ti3026_ramdac_init(struct matrox_fb_info *minfo)
 543 {
 544         DBG(__func__)
 545
 546         minfo->features.pll.vco_freq_min = 110000;
 547         minfo->features.pll.ref_freq     = 114545;
 548         minfo->features.pll.feed_div_min = 2;
 549         minfo->features.pll.feed_div_max = 24;
 550         minfo->features.pll.in_div_min   = 2;
 551         minfo->features.pll.in_div_max   = 63;
 552         minfo->features.pll.post_shift_max = 3;
 553         if (minfo->devflags.noinit)
 554                 return;
 555         ti3026_setMCLK(minfo, 60000);
 556 }
 557
 558 static void Ti3026_restore(struct matrox_fb_info *minfo)
 559 {
 560         int i;
 561         unsigned char progdac[6];
 562         struct matrox_hw_state *hw = &minfo->hw;
 563         CRITFLAGS
 564
 565         DBG(__func__)
 566
 567 #ifdef DEBUG
 568         dprintk(KERN_INFO "EXTVGA regs: ");
 569         for (i = 0; i < 6; i++)
 570                 dprintk("%02X:", hw->CRTCEXT[i]);
 571         dprintk("\n");
 572 #endif
 573
 574         CRITBEGIN
 575
 576         pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, hw->MXoptionReg);
 577
 578         CRITEND
 579
 580         matroxfb_vgaHWrestore(minfo);
 581
 582         CRITBEGIN
 583
 584         minfo->crtc1.panpos = -1;
 585         for (i = 0; i < 6; i++)
 586                 mga_setr(M_EXTVGA_INDEX, i, hw->CRTCEXT[i]);
 587
 588         for (i = 0; i < 21; i++) {
 589                 outTi3026(minfo, DACseq[i], hw->DACreg[i]);
 590         }
 591
 592         outTi3026(minfo, TVP3026_XPLLADDR, 0x00);
 593         progdac[0] = inTi3026(minfo, TVP3026_XPIXPLLDATA);
 594         progdac[3] = inTi3026(minfo, TVP3026_XLOOPPLLDATA);
 595         outTi3026(minfo, TVP3026_XPLLADDR, 0x15);
 596         progdac[1] = inTi3026(minfo, TVP3026_XPIXPLLDATA);
 597         progdac[4] = inTi3026(minfo, TVP3026_XLOOPPLLDATA);
 598         outTi3026(minfo, TVP3026_XPLLADDR, 0x2A);
 599         progdac[2] = inTi3026(minfo, TVP3026_XPIXPLLDATA);
 600         progdac[5] = inTi3026(minfo, TVP3026_XLOOPPLLDATA);
 601
 602         CRITEND
 603         if (memcmp(hw->DACclk, progdac, 6)) {
 604                 /* agrhh... setting up PLL is very slow on Millennium... */
 605                 /* Mystique PLL is locked in few ms, but Millennium PLL lock takes about 0.15 s... */
 606                 /* Maybe even we should call schedule() ? */
 607
 608                 CRITBEGIN
 609                 outTi3026(minfo, TVP3026_XCLKCTRL, hw->DACreg[POS3026_XCLKCTRL]);
 610                 outTi3026(minfo, TVP3026_XPLLADDR, 0x2A);
 611                 outTi3026(minfo, TVP3026_XLOOPPLLDATA, 0);
 612                 outTi3026(minfo, TVP3026_XPIXPLLDATA, 0);
 613
 614                 outTi3026(minfo, TVP3026_XPLLADDR, 0x00);
 615                 for (i = 0; i < 3; i++)
 616                         outTi3026(minfo, TVP3026_XPIXPLLDATA, hw->DACclk[i]);
 617                 /* wait for PLL only if PLL clock requested (always for PowerMode, never for VGA) */
 618                 if (hw->MiscOutReg & 0x08) {
 619                         int tmout;
 620                         outTi3026(minfo, TVP3026_XPLLADDR, 0x3F);
 621                         for (tmout = 500000; tmout; --tmout) {
 622                                 if (inTi3026(minfo, TVP3026_XPIXPLLDATA) & 0x40)
 623                                         break;
 624                                 udelay(10);
 625                         }
 626
 627                         CRITEND
 628
 629                         if (!tmout)
 630                                 printk(KERN_ERR "matroxfb: Pixel PLL not locked after 5 secs\n");
 631                         else
 632                                 dprintk(KERN_INFO "PixelPLL: %d\n", 500000-tmout);
 633                         CRITBEGIN
 634                 }
 635                 outTi3026(minfo, TVP3026_XMEMPLLCTRL, hw->DACreg[POS3026_XMEMPLLCTRL]);
 636                 outTi3026(minfo, TVP3026_XPLLADDR, 0x00);
 637                 for (i = 3; i < 6; i++)
 638                         outTi3026(minfo, TVP3026_XLOOPPLLDATA, hw->DACclk[i]);
 639                 CRITEND
 640                 if ((hw->MiscOutReg & 0x08) && ((hw->DACclk[5] & 0x80) == 0x80)) {
 641                         int tmout;
 642
 643                         CRITBEGIN
 644                         outTi3026(minfo, TVP3026_XPLLADDR, 0x3F);
 645                         for (tmout = 500000; tmout; --tmout) {
 646                                 if (inTi3026(minfo, TVP3026_XLOOPPLLDATA) & 0x40)
 647                                         break;
 648                                 udelay(10);
 649                         }
 650                         CRITEND
 651                         if (!tmout)
 652                                 printk(KERN_ERR "matroxfb: Loop PLL not locked after 5 secs\n");
 653                         else
 654                                 dprintk(KERN_INFO "LoopPLL: %d\n", 500000-tmout);
 655                 }
 656         }
 657
 658 #ifdef DEBUG
 659         dprintk(KERN_DEBUG "3026DACregs ");
 660         for (i = 0; i < 21; i++) {
 661                 dprintk("R%02X=%02X ", DACseq[i], hw->DACreg[i]);
 662                 if ((i & 0x7) == 0x7) dprintk(KERN_DEBUG "continuing... ");
 663         }
 664         dprintk(KERN_DEBUG "DACclk ");
 665         for (i = 0; i < 6; i++)
 666                 dprintk("C%02X=%02X ", i, hw->DACclk[i]);
 667         dprintk("\n");
 668 #endif
 669 }
 670
 671 static void Ti3026_reset(struct matrox_fb_info *minfo)
 672 {
 673         DBG(__func__)
 674
 675         ti3026_ramdac_init(minfo);
 676 }
 677
 678 static struct matrox_altout ti3026_output = {
 679         .name    = "Primary output",
 680 };
 681
 682 static int Ti3026_preinit(struct matrox_fb_info *minfo)
 683 {
 684         static const int vxres_mill2[] = { 512,        640, 768,  800,  832,  960,
 685                                           1024, 1152, 1280,      1600, 1664, 1920,
 686                                           2048, 0};
 687         static const int vxres_mill1[] = {             640, 768,  800,        960,
 688                                           1024, 1152, 1280,      1600,       1920,
 689                                           2048, 0};
 690         struct matrox_hw_state *hw = &minfo->hw;
 691
 692         DBG(__func__)
 693
 694         minfo->millenium = 1;
 695         minfo->milleniumII = (minfo->pcidev->device != PCI_DEVICE_ID_MATROX_MIL);
 696         minfo->capable.cfb4 = 1;
 697         minfo->capable.text = 1; /* isMilleniumII(minfo); */
 698         minfo->capable.vxres = isMilleniumII(minfo) ? vxres_mill2 : vxres_mill1;
 699
 700         minfo->outputs[0].data = minfo;
 701         minfo->outputs[0].output = &ti3026_output;
 702         minfo->outputs[0].src = minfo->outputs[0].default_src;
 703         minfo->outputs[0].mode = MATROXFB_OUTPUT_MODE_MONITOR;
 704
 705         if (minfo->devflags.noinit)
 706                 return 0;
 707         /* preserve VGA I/O, BIOS and PPC */
 708         hw->MXoptionReg &= 0xC0000100;
 709         hw->MXoptionReg |= 0x002C0000;
 710         if (minfo->devflags.novga)
 711                 hw->MXoptionReg &= ~0x00000100;
 712         if (minfo->devflags.nobios)
 713                 hw->MXoptionReg &= ~0x40000000;
 714         if (minfo->devflags.nopciretry)
 715                 hw->MXoptionReg |=  0x20000000;
 716         pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, hw->MXoptionReg);
 717
 718         minfo->accel.ramdac_rev = inTi3026(minfo, TVP3026_XSILICONREV);
 719
 720         outTi3026(minfo, TVP3026_XCLKCTRL, TVP3026_XCLKCTRL_SRC_CLK0VGA | TVP3026_XCLKCTRL_CLKSTOPPED);
 721         outTi3026(minfo, TVP3026_XTRUECOLORCTRL, TVP3026_XTRUECOLORCTRL_PSEUDOCOLOR);
 722         outTi3026(minfo, TVP3026_XMUXCTRL, TVP3026_XMUXCTRL_VGA);
 723
 724         outTi3026(minfo, TVP3026_XPLLADDR, 0x2A);
 725         outTi3026(minfo, TVP3026_XLOOPPLLDATA, 0x00);
 726         outTi3026(minfo, TVP3026_XPIXPLLDATA, 0x00);
 727
 728         mga_outb(M_MISC_REG, 0x67);
 729
 730         outTi3026(minfo, TVP3026_XMEMPLLCTRL, TVP3026_XMEMPLLCTRL_STROBEMKC4 | TVP3026_XMEMPLLCTRL_MCLK_MCLKPLL);
 731
 732         mga_outl(M_RESET, 1);
 733         udelay(250);
 734         mga_outl(M_RESET, 0);
 735         udelay(250);
 736         mga_outl(M_MACCESS, 0x00008000);
 737         udelay(10);
 738         return 0;
 739 }
 740
 741 struct matrox_switch matrox_millennium = {
 742         .preinit        = Ti3026_preinit,
 743         .reset          = Ti3026_reset,
 744         .init           = Ti3026_init,
 745         .restore        = Ti3026_restore
 746 };
 747 EXPORT_SYMBOL(matrox_millennium);
 748 #endif
 749 MODULE_LICENSE("GPL");