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Merge tag 'trace-v5.11-rc2' of git://git.kernel.org/pub/scm/linux/kernel/git/rostedt...
[linux/fpc-iii.git] / drivers / video / fbdev / omap2 / omapfb / dss / dispc.c
blobb2d6e6df2161563667a5d5369cf6f3885ebc56fe
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * linux/drivers/video/omap2/dss/dispc.c
4 *
5 * Copyright (C) 2009 Nokia Corporation
6 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
7 *
8 * Some code and ideas taken from drivers/video/omap/ driver
9 * by Imre Deak.
10 */
11
12 #define DSS_SUBSYS_NAME "DISPC"
13
14 #include <linux/kernel.h>
15 #include <linux/dma-mapping.h>
16 #include <linux/vmalloc.h>
17 #include <linux/export.h>
18 #include <linux/clk.h>
19 #include <linux/io.h>
20 #include <linux/jiffies.h>
21 #include <linux/seq_file.h>
22 #include <linux/delay.h>
23 #include <linux/workqueue.h>
24 #include <linux/hardirq.h>
25 #include <linux/platform_device.h>
26 #include <linux/pm_runtime.h>
27 #include <linux/sizes.h>
28 #include <linux/mfd/syscon.h>
29 #include <linux/regmap.h>
30 #include <linux/of.h>
31 #include <linux/component.h>
32
33 #include <video/omapfb_dss.h>
34
35 #include "dss.h"
36 #include "dss_features.h"
37 #include "dispc.h"
38
39 /* DISPC */
40 #define DISPC_SZ_REGS SZ_4K
41
42 enum omap_burst_size {
43 BURST_SIZE_X2 = 0,
44 BURST_SIZE_X4 = 1,
45 BURST_SIZE_X8 = 2,
46 };
47
48 #define REG_GET(idx, start, end) \
49 FLD_GET(dispc_read_reg(idx), start, end)
50
51 #define REG_FLD_MOD(idx, val, start, end) \
52 dispc_write_reg(idx, FLD_MOD(dispc_read_reg(idx), val, start, end))
53
54 struct dispc_features {
55 u8 sw_start;
56 u8 fp_start;
57 u8 bp_start;
58 u16 sw_max;
59 u16 vp_max;
60 u16 hp_max;
61 u8 mgr_width_start;
62 u8 mgr_height_start;
63 u16 mgr_width_max;
64 u16 mgr_height_max;
65 unsigned long max_lcd_pclk;
66 unsigned long max_tv_pclk;
67 int (*calc_scaling) (unsigned long pclk, unsigned long lclk,
68 const struct omap_video_timings *mgr_timings,
69 u16 width, u16 height, u16 out_width, u16 out_height,
70 enum omap_color_mode color_mode, bool *five_taps,
71 int *x_predecim, int *y_predecim, int *decim_x, int *decim_y,
72 u16 pos_x, unsigned long *core_clk, bool mem_to_mem);
73 unsigned long (*calc_core_clk) (unsigned long pclk,
74 u16 width, u16 height, u16 out_width, u16 out_height,
75 bool mem_to_mem);
76 u8 num_fifos;
77
78 /* swap GFX & WB fifos */
79 bool gfx_fifo_workaround:1;
80
81 /* no DISPC_IRQ_FRAMEDONETV on this SoC */
82 bool no_framedone_tv:1;
83
84 /* revert to the OMAP4 mechanism of DISPC Smart Standby operation */
85 bool mstandby_workaround:1;
86
87 bool set_max_preload:1;
88
89 /* PIXEL_INC is not added to the last pixel of a line */
90 bool last_pixel_inc_missing:1;
91
92 /* POL_FREQ has ALIGN bit */
93 bool supports_sync_align:1;
94
95 bool has_writeback:1;
96 };
97
98 #define DISPC_MAX_NR_FIFOS 5
99
100 static struct {
101 struct platform_device *pdev;
102 void __iomem *base;
103
104 int irq;
105 irq_handler_t user_handler;
106 void *user_data;
107
108 unsigned long core_clk_rate;
109 unsigned long tv_pclk_rate;
110
111 u32 fifo_size[DISPC_MAX_NR_FIFOS];
112 /* maps which plane is using a fifo. fifo-id -> plane-id */
113 int fifo_assignment[DISPC_MAX_NR_FIFOS];
114
115 bool ctx_valid;
116 u32 ctx[DISPC_SZ_REGS / sizeof(u32)];
117
118 const struct dispc_features *feat;
119
120 bool is_enabled;
121
122 struct regmap *syscon_pol;
123 u32 syscon_pol_offset;
124
125 /* DISPC_CONTROL & DISPC_CONFIG lock*/
126 spinlock_t control_lock;
127 } dispc;
128
129 enum omap_color_component {
130 /* used for all color formats for OMAP3 and earlier
131 * and for RGB and Y color component on OMAP4
132 */
133 DISPC_COLOR_COMPONENT_RGB_Y = 1 << 0,
134 /* used for UV component for
135 * OMAP_DSS_COLOR_YUV2, OMAP_DSS_COLOR_UYVY, OMAP_DSS_COLOR_NV12
136 * color formats on OMAP4
137 */
138 DISPC_COLOR_COMPONENT_UV = 1 << 1,
139 };
140
141 enum mgr_reg_fields {
142 DISPC_MGR_FLD_ENABLE,
143 DISPC_MGR_FLD_STNTFT,
144 DISPC_MGR_FLD_GO,
145 DISPC_MGR_FLD_TFTDATALINES,
146 DISPC_MGR_FLD_STALLMODE,
147 DISPC_MGR_FLD_TCKENABLE,
148 DISPC_MGR_FLD_TCKSELECTION,
149 DISPC_MGR_FLD_CPR,
150 DISPC_MGR_FLD_FIFOHANDCHECK,
151 /* used to maintain a count of the above fields */
152 DISPC_MGR_FLD_NUM,
153 };
154
155 struct dispc_reg_field {
156 u16 reg;
157 u8 high;
158 u8 low;
159 };
160
161 static const struct {
162 const char *name;
163 u32 vsync_irq;
164 u32 framedone_irq;
165 u32 sync_lost_irq;
166 struct dispc_reg_field reg_desc[DISPC_MGR_FLD_NUM];
167 } mgr_desc[] = {
168 [OMAP_DSS_CHANNEL_LCD] = {
169 .name = "LCD",
170 .vsync_irq = DISPC_IRQ_VSYNC,
171 .framedone_irq = DISPC_IRQ_FRAMEDONE,
172 .sync_lost_irq = DISPC_IRQ_SYNC_LOST,
173 .reg_desc = {
174 [DISPC_MGR_FLD_ENABLE] = { DISPC_CONTROL, 0, 0 },
175 [DISPC_MGR_FLD_STNTFT] = { DISPC_CONTROL, 3, 3 },
176 [DISPC_MGR_FLD_GO] = { DISPC_CONTROL, 5, 5 },
177 [DISPC_MGR_FLD_TFTDATALINES] = { DISPC_CONTROL, 9, 8 },
178 [DISPC_MGR_FLD_STALLMODE] = { DISPC_CONTROL, 11, 11 },
179 [DISPC_MGR_FLD_TCKENABLE] = { DISPC_CONFIG, 10, 10 },
180 [DISPC_MGR_FLD_TCKSELECTION] = { DISPC_CONFIG, 11, 11 },
181 [DISPC_MGR_FLD_CPR] = { DISPC_CONFIG, 15, 15 },
182 [DISPC_MGR_FLD_FIFOHANDCHECK] = { DISPC_CONFIG, 16, 16 },
183 },
184 },
185 [OMAP_DSS_CHANNEL_DIGIT] = {
186 .name = "DIGIT",
187 .vsync_irq = DISPC_IRQ_EVSYNC_ODD | DISPC_IRQ_EVSYNC_EVEN,
188 .framedone_irq = DISPC_IRQ_FRAMEDONETV,
189 .sync_lost_irq = DISPC_IRQ_SYNC_LOST_DIGIT,
190 .reg_desc = {
191 [DISPC_MGR_FLD_ENABLE] = { DISPC_CONTROL, 1, 1 },
192 [DISPC_MGR_FLD_STNTFT] = { },
193 [DISPC_MGR_FLD_GO] = { DISPC_CONTROL, 6, 6 },
194 [DISPC_MGR_FLD_TFTDATALINES] = { },
195 [DISPC_MGR_FLD_STALLMODE] = { },
196 [DISPC_MGR_FLD_TCKENABLE] = { DISPC_CONFIG, 12, 12 },
197 [DISPC_MGR_FLD_TCKSELECTION] = { DISPC_CONFIG, 13, 13 },
198 [DISPC_MGR_FLD_CPR] = { },
199 [DISPC_MGR_FLD_FIFOHANDCHECK] = { DISPC_CONFIG, 16, 16 },
200 },
201 },
202 [OMAP_DSS_CHANNEL_LCD2] = {
203 .name = "LCD2",
204 .vsync_irq = DISPC_IRQ_VSYNC2,
205 .framedone_irq = DISPC_IRQ_FRAMEDONE2,
206 .sync_lost_irq = DISPC_IRQ_SYNC_LOST2,
207 .reg_desc = {
208 [DISPC_MGR_FLD_ENABLE] = { DISPC_CONTROL2, 0, 0 },
209 [DISPC_MGR_FLD_STNTFT] = { DISPC_CONTROL2, 3, 3 },
210 [DISPC_MGR_FLD_GO] = { DISPC_CONTROL2, 5, 5 },
211 [DISPC_MGR_FLD_TFTDATALINES] = { DISPC_CONTROL2, 9, 8 },
212 [DISPC_MGR_FLD_STALLMODE] = { DISPC_CONTROL2, 11, 11 },
213 [DISPC_MGR_FLD_TCKENABLE] = { DISPC_CONFIG2, 10, 10 },
214 [DISPC_MGR_FLD_TCKSELECTION] = { DISPC_CONFIG2, 11, 11 },
215 [DISPC_MGR_FLD_CPR] = { DISPC_CONFIG2, 15, 15 },
216 [DISPC_MGR_FLD_FIFOHANDCHECK] = { DISPC_CONFIG2, 16, 16 },
217 },
218 },
219 [OMAP_DSS_CHANNEL_LCD3] = {
220 .name = "LCD3",
221 .vsync_irq = DISPC_IRQ_VSYNC3,
222 .framedone_irq = DISPC_IRQ_FRAMEDONE3,
223 .sync_lost_irq = DISPC_IRQ_SYNC_LOST3,
224 .reg_desc = {
225 [DISPC_MGR_FLD_ENABLE] = { DISPC_CONTROL3, 0, 0 },
226 [DISPC_MGR_FLD_STNTFT] = { DISPC_CONTROL3, 3, 3 },
227 [DISPC_MGR_FLD_GO] = { DISPC_CONTROL3, 5, 5 },
228 [DISPC_MGR_FLD_TFTDATALINES] = { DISPC_CONTROL3, 9, 8 },
229 [DISPC_MGR_FLD_STALLMODE] = { DISPC_CONTROL3, 11, 11 },
230 [DISPC_MGR_FLD_TCKENABLE] = { DISPC_CONFIG3, 10, 10 },
231 [DISPC_MGR_FLD_TCKSELECTION] = { DISPC_CONFIG3, 11, 11 },
232 [DISPC_MGR_FLD_CPR] = { DISPC_CONFIG3, 15, 15 },
233 [DISPC_MGR_FLD_FIFOHANDCHECK] = { DISPC_CONFIG3, 16, 16 },
234 },
235 },
236 };
237
238 struct color_conv_coef {
239 int ry, rcr, rcb, gy, gcr, gcb, by, bcr, bcb;
240 int full_range;
241 };
242
243 static unsigned long dispc_fclk_rate(void);
244 static unsigned long dispc_core_clk_rate(void);
245 static unsigned long dispc_mgr_lclk_rate(enum omap_channel channel);
246 static unsigned long dispc_mgr_pclk_rate(enum omap_channel channel);
247
248 static unsigned long dispc_plane_pclk_rate(enum omap_plane plane);
249 static unsigned long dispc_plane_lclk_rate(enum omap_plane plane);
250
251 static inline void dispc_write_reg(const u16 idx, u32 val)
252 {
253 __raw_writel(val, dispc.base + idx);
254 }
255
256 static inline u32 dispc_read_reg(const u16 idx)
257 {
258 return __raw_readl(dispc.base + idx);
259 }
260
261 static u32 mgr_fld_read(enum omap_channel channel, enum mgr_reg_fields regfld)
262 {
263 const struct dispc_reg_field rfld = mgr_desc[channel].reg_desc[regfld];
264 return REG_GET(rfld.reg, rfld.high, rfld.low);
265 }
266
267 static void mgr_fld_write(enum omap_channel channel,
268 enum mgr_reg_fields regfld, int val) {
269 const struct dispc_reg_field rfld = mgr_desc[channel].reg_desc[regfld];
270 const bool need_lock = rfld.reg == DISPC_CONTROL || rfld.reg == DISPC_CONFIG;
271 unsigned long flags;
272
273 if (need_lock)
274 spin_lock_irqsave(&dispc.control_lock, flags);
275
276 REG_FLD_MOD(rfld.reg, val, rfld.high, rfld.low);
277
278 if (need_lock)
279 spin_unlock_irqrestore(&dispc.control_lock, flags);
280 }
281
282 #define SR(reg) \
283 dispc.ctx[DISPC_##reg / sizeof(u32)] = dispc_read_reg(DISPC_##reg)
284 #define RR(reg) \
285 dispc_write_reg(DISPC_##reg, dispc.ctx[DISPC_##reg / sizeof(u32)])
286
287 static void dispc_save_context(void)
288 {
289 int i, j;
290
291 DSSDBG("dispc_save_context\n");
292
293 SR(IRQENABLE);
294 SR(CONTROL);
295 SR(CONFIG);
296 SR(LINE_NUMBER);
297 if (dss_has_feature(FEAT_ALPHA_FIXED_ZORDER) ||
298 dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
299 SR(GLOBAL_ALPHA);
300 if (dss_has_feature(FEAT_MGR_LCD2)) {
301 SR(CONTROL2);
302 SR(CONFIG2);
303 }
304 if (dss_has_feature(FEAT_MGR_LCD3)) {
305 SR(CONTROL3);
306 SR(CONFIG3);
307 }
308
309 for (i = 0; i < dss_feat_get_num_mgrs(); i++) {
310 SR(DEFAULT_COLOR(i));
311 SR(TRANS_COLOR(i));
312 SR(SIZE_MGR(i));
313 if (i == OMAP_DSS_CHANNEL_DIGIT)
314 continue;
315 SR(TIMING_H(i));
316 SR(TIMING_V(i));
317 SR(POL_FREQ(i));
318 SR(DIVISORo(i));
319
320 SR(DATA_CYCLE1(i));
321 SR(DATA_CYCLE2(i));
322 SR(DATA_CYCLE3(i));
323
324 if (dss_has_feature(FEAT_CPR)) {
325 SR(CPR_COEF_R(i));
326 SR(CPR_COEF_G(i));
327 SR(CPR_COEF_B(i));
328 }
329 }
330
331 for (i = 0; i < dss_feat_get_num_ovls(); i++) {
332 SR(OVL_BA0(i));
333 SR(OVL_BA1(i));
334 SR(OVL_POSITION(i));
335 SR(OVL_SIZE(i));
336 SR(OVL_ATTRIBUTES(i));
337 SR(OVL_FIFO_THRESHOLD(i));
338 SR(OVL_ROW_INC(i));
339 SR(OVL_PIXEL_INC(i));
340 if (dss_has_feature(FEAT_PRELOAD))
341 SR(OVL_PRELOAD(i));
342 if (i == OMAP_DSS_GFX) {
343 SR(OVL_WINDOW_SKIP(i));
344 SR(OVL_TABLE_BA(i));
345 continue;
346 }
347 SR(OVL_FIR(i));
348 SR(OVL_PICTURE_SIZE(i));
349 SR(OVL_ACCU0(i));
350 SR(OVL_ACCU1(i));
351
352 for (j = 0; j < 8; j++)
353 SR(OVL_FIR_COEF_H(i, j));
354
355 for (j = 0; j < 8; j++)
356 SR(OVL_FIR_COEF_HV(i, j));
357
358 for (j = 0; j < 5; j++)
359 SR(OVL_CONV_COEF(i, j));
360
361 if (dss_has_feature(FEAT_FIR_COEF_V)) {
362 for (j = 0; j < 8; j++)
363 SR(OVL_FIR_COEF_V(i, j));
364 }
365
366 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
367 SR(OVL_BA0_UV(i));
368 SR(OVL_BA1_UV(i));
369 SR(OVL_FIR2(i));
370 SR(OVL_ACCU2_0(i));
371 SR(OVL_ACCU2_1(i));
372
373 for (j = 0; j < 8; j++)
374 SR(OVL_FIR_COEF_H2(i, j));
375
376 for (j = 0; j < 8; j++)
377 SR(OVL_FIR_COEF_HV2(i, j));
378
379 for (j = 0; j < 8; j++)
380 SR(OVL_FIR_COEF_V2(i, j));
381 }
382 if (dss_has_feature(FEAT_ATTR2))
383 SR(OVL_ATTRIBUTES2(i));
384 }
385
386 if (dss_has_feature(FEAT_CORE_CLK_DIV))
387 SR(DIVISOR);
388
389 dispc.ctx_valid = true;
390
391 DSSDBG("context saved\n");
392 }
393
394 static void dispc_restore_context(void)
395 {
396 int i, j;
397
398 DSSDBG("dispc_restore_context\n");
399
400 if (!dispc.ctx_valid)
401 return;
402
403 /*RR(IRQENABLE);*/
404 /*RR(CONTROL);*/
405 RR(CONFIG);
406 RR(LINE_NUMBER);
407 if (dss_has_feature(FEAT_ALPHA_FIXED_ZORDER) ||
408 dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
409 RR(GLOBAL_ALPHA);
410 if (dss_has_feature(FEAT_MGR_LCD2))
411 RR(CONFIG2);
412 if (dss_has_feature(FEAT_MGR_LCD3))
413 RR(CONFIG3);
414
415 for (i = 0; i < dss_feat_get_num_mgrs(); i++) {
416 RR(DEFAULT_COLOR(i));
417 RR(TRANS_COLOR(i));
418 RR(SIZE_MGR(i));
419 if (i == OMAP_DSS_CHANNEL_DIGIT)
420 continue;
421 RR(TIMING_H(i));
422 RR(TIMING_V(i));
423 RR(POL_FREQ(i));
424 RR(DIVISORo(i));
425
426 RR(DATA_CYCLE1(i));
427 RR(DATA_CYCLE2(i));
428 RR(DATA_CYCLE3(i));
429
430 if (dss_has_feature(FEAT_CPR)) {
431 RR(CPR_COEF_R(i));
432 RR(CPR_COEF_G(i));
433 RR(CPR_COEF_B(i));
434 }
435 }
436
437 for (i = 0; i < dss_feat_get_num_ovls(); i++) {
438 RR(OVL_BA0(i));
439 RR(OVL_BA1(i));
440 RR(OVL_POSITION(i));
441 RR(OVL_SIZE(i));
442 RR(OVL_ATTRIBUTES(i));
443 RR(OVL_FIFO_THRESHOLD(i));
444 RR(OVL_ROW_INC(i));
445 RR(OVL_PIXEL_INC(i));
446 if (dss_has_feature(FEAT_PRELOAD))
447 RR(OVL_PRELOAD(i));
448 if (i == OMAP_DSS_GFX) {
449 RR(OVL_WINDOW_SKIP(i));
450 RR(OVL_TABLE_BA(i));
451 continue;
452 }
453 RR(OVL_FIR(i));
454 RR(OVL_PICTURE_SIZE(i));
455 RR(OVL_ACCU0(i));
456 RR(OVL_ACCU1(i));
457
458 for (j = 0; j < 8; j++)
459 RR(OVL_FIR_COEF_H(i, j));
460
461 for (j = 0; j < 8; j++)
462 RR(OVL_FIR_COEF_HV(i, j));
463
464 for (j = 0; j < 5; j++)
465 RR(OVL_CONV_COEF(i, j));
466
467 if (dss_has_feature(FEAT_FIR_COEF_V)) {
468 for (j = 0; j < 8; j++)
469 RR(OVL_FIR_COEF_V(i, j));
470 }
471
472 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
473 RR(OVL_BA0_UV(i));
474 RR(OVL_BA1_UV(i));
475 RR(OVL_FIR2(i));
476 RR(OVL_ACCU2_0(i));
477 RR(OVL_ACCU2_1(i));
478
479 for (j = 0; j < 8; j++)
480 RR(OVL_FIR_COEF_H2(i, j));
481
482 for (j = 0; j < 8; j++)
483 RR(OVL_FIR_COEF_HV2(i, j));
484
485 for (j = 0; j < 8; j++)
486 RR(OVL_FIR_COEF_V2(i, j));
487 }
488 if (dss_has_feature(FEAT_ATTR2))
489 RR(OVL_ATTRIBUTES2(i));
490 }
491
492 if (dss_has_feature(FEAT_CORE_CLK_DIV))
493 RR(DIVISOR);
494
495 /* enable last, because LCD & DIGIT enable are here */
496 RR(CONTROL);
497 if (dss_has_feature(FEAT_MGR_LCD2))
498 RR(CONTROL2);
499 if (dss_has_feature(FEAT_MGR_LCD3))
500 RR(CONTROL3);
501 /* clear spurious SYNC_LOST_DIGIT interrupts */
502 dispc_clear_irqstatus(DISPC_IRQ_SYNC_LOST_DIGIT);
503
504 /*
505 * enable last so IRQs won't trigger before
506 * the context is fully restored
507 */
508 RR(IRQENABLE);
509
510 DSSDBG("context restored\n");
511 }
512
513 #undef SR
514 #undef RR
515
516 int dispc_runtime_get(void)
517 {
518 int r;
519
520 DSSDBG("dispc_runtime_get\n");
521
522 r = pm_runtime_get_sync(&dispc.pdev->dev);
523 if (WARN_ON(r < 0)) {
524 pm_runtime_put_sync(&dispc.pdev->dev);
525 return r;
526 }
527 return 0;
528 }
529 EXPORT_SYMBOL(dispc_runtime_get);
530
531 void dispc_runtime_put(void)
532 {
533 int r;
534
535 DSSDBG("dispc_runtime_put\n");
536
537 r = pm_runtime_put_sync(&dispc.pdev->dev);
538 WARN_ON(r < 0 && r != -ENOSYS);
539 }
540 EXPORT_SYMBOL(dispc_runtime_put);
541
542 u32 dispc_mgr_get_vsync_irq(enum omap_channel channel)
543 {
544 return mgr_desc[channel].vsync_irq;
545 }
546 EXPORT_SYMBOL(dispc_mgr_get_vsync_irq);
547
548 u32 dispc_mgr_get_framedone_irq(enum omap_channel channel)
549 {
550 if (channel == OMAP_DSS_CHANNEL_DIGIT && dispc.feat->no_framedone_tv)
551 return 0;
552
553 return mgr_desc[channel].framedone_irq;
554 }
555 EXPORT_SYMBOL(dispc_mgr_get_framedone_irq);
556
557 u32 dispc_mgr_get_sync_lost_irq(enum omap_channel channel)
558 {
559 return mgr_desc[channel].sync_lost_irq;
560 }
561 EXPORT_SYMBOL(dispc_mgr_get_sync_lost_irq);
562
563 bool dispc_mgr_go_busy(enum omap_channel channel)
564 {
565 return mgr_fld_read(channel, DISPC_MGR_FLD_GO) == 1;
566 }
567 EXPORT_SYMBOL(dispc_mgr_go_busy);
568
569 void dispc_mgr_go(enum omap_channel channel)
570 {
571 WARN_ON(!dispc_mgr_is_enabled(channel));
572 WARN_ON(dispc_mgr_go_busy(channel));
573
574 DSSDBG("GO %s\n", mgr_desc[channel].name);
575
576 mgr_fld_write(channel, DISPC_MGR_FLD_GO, 1);
577 }
578 EXPORT_SYMBOL(dispc_mgr_go);
579
580 static void dispc_ovl_write_firh_reg(enum omap_plane plane, int reg, u32 value)
581 {
582 dispc_write_reg(DISPC_OVL_FIR_COEF_H(plane, reg), value);
583 }
584
585 static void dispc_ovl_write_firhv_reg(enum omap_plane plane, int reg, u32 value)
586 {
587 dispc_write_reg(DISPC_OVL_FIR_COEF_HV(plane, reg), value);
588 }
589
590 static void dispc_ovl_write_firv_reg(enum omap_plane plane, int reg, u32 value)
591 {
592 dispc_write_reg(DISPC_OVL_FIR_COEF_V(plane, reg), value);
593 }
594
595 static void dispc_ovl_write_firh2_reg(enum omap_plane plane, int reg, u32 value)
596 {
597 BUG_ON(plane == OMAP_DSS_GFX);
598
599 dispc_write_reg(DISPC_OVL_FIR_COEF_H2(plane, reg), value);
600 }
601
602 static void dispc_ovl_write_firhv2_reg(enum omap_plane plane, int reg,
603 u32 value)
604 {
605 BUG_ON(plane == OMAP_DSS_GFX);
606
607 dispc_write_reg(DISPC_OVL_FIR_COEF_HV2(plane, reg), value);
608 }
609
610 static void dispc_ovl_write_firv2_reg(enum omap_plane plane, int reg, u32 value)
611 {
612 BUG_ON(plane == OMAP_DSS_GFX);
613
614 dispc_write_reg(DISPC_OVL_FIR_COEF_V2(plane, reg), value);
615 }
616
617 static void dispc_ovl_set_scale_coef(enum omap_plane plane, int fir_hinc,
618 int fir_vinc, int five_taps,
619 enum omap_color_component color_comp)
620 {
621 const struct dispc_coef *h_coef, *v_coef;
622 int i;
623
624 h_coef = dispc_ovl_get_scale_coef(fir_hinc, true);
625 v_coef = dispc_ovl_get_scale_coef(fir_vinc, five_taps);
626
627 for (i = 0; i < 8; i++) {
628 u32 h, hv;
629
630 h = FLD_VAL(h_coef[i].hc0_vc00, 7, 0)
631 | FLD_VAL(h_coef[i].hc1_vc0, 15, 8)
632 | FLD_VAL(h_coef[i].hc2_vc1, 23, 16)
633 | FLD_VAL(h_coef[i].hc3_vc2, 31, 24);
634 hv = FLD_VAL(h_coef[i].hc4_vc22, 7, 0)
635 | FLD_VAL(v_coef[i].hc1_vc0, 15, 8)
636 | FLD_VAL(v_coef[i].hc2_vc1, 23, 16)
637 | FLD_VAL(v_coef[i].hc3_vc2, 31, 24);
638
639 if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y) {
640 dispc_ovl_write_firh_reg(plane, i, h);
641 dispc_ovl_write_firhv_reg(plane, i, hv);
642 } else {
643 dispc_ovl_write_firh2_reg(plane, i, h);
644 dispc_ovl_write_firhv2_reg(plane, i, hv);
645 }
646
647 }
648
649 if (five_taps) {
650 for (i = 0; i < 8; i++) {
651 u32 v;
652 v = FLD_VAL(v_coef[i].hc0_vc00, 7, 0)
653 | FLD_VAL(v_coef[i].hc4_vc22, 15, 8);
654 if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y)
655 dispc_ovl_write_firv_reg(plane, i, v);
656 else
657 dispc_ovl_write_firv2_reg(plane, i, v);
658 }
659 }
660 }
661
662
663 static void dispc_ovl_write_color_conv_coef(enum omap_plane plane,
664 const struct color_conv_coef *ct)
665 {
666 #define CVAL(x, y) (FLD_VAL(x, 26, 16) | FLD_VAL(y, 10, 0))
667
668 dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 0), CVAL(ct->rcr, ct->ry));
669 dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 1), CVAL(ct->gy, ct->rcb));
670 dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 2), CVAL(ct->gcb, ct->gcr));
671 dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 3), CVAL(ct->bcr, ct->by));
672 dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 4), CVAL(0, ct->bcb));
673
674 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), ct->full_range, 11, 11);
675
676 #undef CVAL
677 }
678
679 static void dispc_setup_color_conv_coef(void)
680 {
681 int i;
682 int num_ovl = dss_feat_get_num_ovls();
683 const struct color_conv_coef ctbl_bt601_5_ovl = {
684 /* YUV -> RGB */
685 298, 409, 0, 298, -208, -100, 298, 0, 517, 0,
686 };
687 const struct color_conv_coef ctbl_bt601_5_wb = {
688 /* RGB -> YUV */
689 66, 129, 25, 112, -94, -18, -38, -74, 112, 0,
690 };
691
692 for (i = 1; i < num_ovl; i++)
693 dispc_ovl_write_color_conv_coef(i, &ctbl_bt601_5_ovl);
694
695 if (dispc.feat->has_writeback)
696 dispc_ovl_write_color_conv_coef(OMAP_DSS_WB, &ctbl_bt601_5_wb);
697 }
698
699 static void dispc_ovl_set_ba0(enum omap_plane plane, u32 paddr)
700 {
701 dispc_write_reg(DISPC_OVL_BA0(plane), paddr);
702 }
703
704 static void dispc_ovl_set_ba1(enum omap_plane plane, u32 paddr)
705 {
706 dispc_write_reg(DISPC_OVL_BA1(plane), paddr);
707 }
708
709 static void dispc_ovl_set_ba0_uv(enum omap_plane plane, u32 paddr)
710 {
711 dispc_write_reg(DISPC_OVL_BA0_UV(plane), paddr);
712 }
713
714 static void dispc_ovl_set_ba1_uv(enum omap_plane plane, u32 paddr)
715 {
716 dispc_write_reg(DISPC_OVL_BA1_UV(plane), paddr);
717 }
718
719 static void dispc_ovl_set_pos(enum omap_plane plane,
720 enum omap_overlay_caps caps, int x, int y)
721 {
722 u32 val;
723
724 if ((caps & OMAP_DSS_OVL_CAP_POS) == 0)
725 return;
726
727 val = FLD_VAL(y, 26, 16) | FLD_VAL(x, 10, 0);
728
729 dispc_write_reg(DISPC_OVL_POSITION(plane), val);
730 }
731
732 static void dispc_ovl_set_input_size(enum omap_plane plane, int width,
733 int height)
734 {
735 u32 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
736
737 if (plane == OMAP_DSS_GFX || plane == OMAP_DSS_WB)
738 dispc_write_reg(DISPC_OVL_SIZE(plane), val);
739 else
740 dispc_write_reg(DISPC_OVL_PICTURE_SIZE(plane), val);
741 }
742
743 static void dispc_ovl_set_output_size(enum omap_plane plane, int width,
744 int height)
745 {
746 u32 val;
747
748 BUG_ON(plane == OMAP_DSS_GFX);
749
750 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
751
752 if (plane == OMAP_DSS_WB)
753 dispc_write_reg(DISPC_OVL_PICTURE_SIZE(plane), val);
754 else
755 dispc_write_reg(DISPC_OVL_SIZE(plane), val);
756 }
757
758 static void dispc_ovl_set_zorder(enum omap_plane plane,
759 enum omap_overlay_caps caps, u8 zorder)
760 {
761 if ((caps & OMAP_DSS_OVL_CAP_ZORDER) == 0)
762 return;
763
764 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), zorder, 27, 26);
765 }
766
767 static void dispc_ovl_enable_zorder_planes(void)
768 {
769 int i;
770
771 if (!dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
772 return;
773
774 for (i = 0; i < dss_feat_get_num_ovls(); i++)
775 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(i), 1, 25, 25);
776 }
777
778 static void dispc_ovl_set_pre_mult_alpha(enum omap_plane plane,
779 enum omap_overlay_caps caps, bool enable)
780 {
781 if ((caps & OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA) == 0)
782 return;
783
784 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 28, 28);
785 }
786
787 static void dispc_ovl_setup_global_alpha(enum omap_plane plane,
788 enum omap_overlay_caps caps, u8 global_alpha)
789 {
790 static const unsigned shifts[] = { 0, 8, 16, 24, };
791 int shift;
792
793 if ((caps & OMAP_DSS_OVL_CAP_GLOBAL_ALPHA) == 0)
794 return;
795
796 shift = shifts[plane];
797 REG_FLD_MOD(DISPC_GLOBAL_ALPHA, global_alpha, shift + 7, shift);
798 }
799
800 static void dispc_ovl_set_pix_inc(enum omap_plane plane, s32 inc)
801 {
802 dispc_write_reg(DISPC_OVL_PIXEL_INC(plane), inc);
803 }
804
805 static void dispc_ovl_set_row_inc(enum omap_plane plane, s32 inc)
806 {
807 dispc_write_reg(DISPC_OVL_ROW_INC(plane), inc);
808 }
809
810 static void dispc_ovl_set_color_mode(enum omap_plane plane,
811 enum omap_color_mode color_mode)
812 {
813 u32 m = 0;
814 if (plane != OMAP_DSS_GFX) {
815 switch (color_mode) {
816 case OMAP_DSS_COLOR_NV12:
817 m = 0x0; break;
818 case OMAP_DSS_COLOR_RGBX16:
819 m = 0x1; break;
820 case OMAP_DSS_COLOR_RGBA16:
821 m = 0x2; break;
822 case OMAP_DSS_COLOR_RGB12U:
823 m = 0x4; break;
824 case OMAP_DSS_COLOR_ARGB16:
825 m = 0x5; break;
826 case OMAP_DSS_COLOR_RGB16:
827 m = 0x6; break;
828 case OMAP_DSS_COLOR_ARGB16_1555:
829 m = 0x7; break;
830 case OMAP_DSS_COLOR_RGB24U:
831 m = 0x8; break;
832 case OMAP_DSS_COLOR_RGB24P:
833 m = 0x9; break;
834 case OMAP_DSS_COLOR_YUV2:
835 m = 0xa; break;
836 case OMAP_DSS_COLOR_UYVY:
837 m = 0xb; break;
838 case OMAP_DSS_COLOR_ARGB32:
839 m = 0xc; break;
840 case OMAP_DSS_COLOR_RGBA32:
841 m = 0xd; break;
842 case OMAP_DSS_COLOR_RGBX32:
843 m = 0xe; break;
844 case OMAP_DSS_COLOR_XRGB16_1555:
845 m = 0xf; break;
846 default:
847 BUG(); return;
848 }
849 } else {
850 switch (color_mode) {
851 case OMAP_DSS_COLOR_CLUT1:
852 m = 0x0; break;
853 case OMAP_DSS_COLOR_CLUT2:
854 m = 0x1; break;
855 case OMAP_DSS_COLOR_CLUT4:
856 m = 0x2; break;
857 case OMAP_DSS_COLOR_CLUT8:
858 m = 0x3; break;
859 case OMAP_DSS_COLOR_RGB12U:
860 m = 0x4; break;
861 case OMAP_DSS_COLOR_ARGB16:
862 m = 0x5; break;
863 case OMAP_DSS_COLOR_RGB16:
864 m = 0x6; break;
865 case OMAP_DSS_COLOR_ARGB16_1555:
866 m = 0x7; break;
867 case OMAP_DSS_COLOR_RGB24U:
868 m = 0x8; break;
869 case OMAP_DSS_COLOR_RGB24P:
870 m = 0x9; break;
871 case OMAP_DSS_COLOR_RGBX16:
872 m = 0xa; break;
873 case OMAP_DSS_COLOR_RGBA16:
874 m = 0xb; break;
875 case OMAP_DSS_COLOR_ARGB32:
876 m = 0xc; break;
877 case OMAP_DSS_COLOR_RGBA32:
878 m = 0xd; break;
879 case OMAP_DSS_COLOR_RGBX32:
880 m = 0xe; break;
881 case OMAP_DSS_COLOR_XRGB16_1555:
882 m = 0xf; break;
883 default:
884 BUG(); return;
885 }
886 }
887
888 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), m, 4, 1);
889 }
890
891 static void dispc_ovl_configure_burst_type(enum omap_plane plane,
892 enum omap_dss_rotation_type rotation_type)
893 {
894 if (!dss_has_feature(FEAT_BURST_2D))
895 return;
896
897 if (rotation_type == OMAP_DSS_ROT_TILER)
898 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), 1, 29, 29);
899 else
900 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), 0, 29, 29);
901 }
902
903 void dispc_ovl_set_channel_out(enum omap_plane plane, enum omap_channel channel)
904 {
905 int shift;
906 u32 val;
907 int chan = 0, chan2 = 0;
908
909 switch (plane) {
910 case OMAP_DSS_GFX:
911 shift = 8;
912 break;
913 case OMAP_DSS_VIDEO1:
914 case OMAP_DSS_VIDEO2:
915 case OMAP_DSS_VIDEO3:
916 shift = 16;
917 break;
918 default:
919 BUG();
920 return;
921 }
922
923 val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
924 if (dss_has_feature(FEAT_MGR_LCD2)) {
925 switch (channel) {
926 case OMAP_DSS_CHANNEL_LCD:
927 chan = 0;
928 chan2 = 0;
929 break;
930 case OMAP_DSS_CHANNEL_DIGIT:
931 chan = 1;
932 chan2 = 0;
933 break;
934 case OMAP_DSS_CHANNEL_LCD2:
935 chan = 0;
936 chan2 = 1;
937 break;
938 case OMAP_DSS_CHANNEL_LCD3:
939 if (dss_has_feature(FEAT_MGR_LCD3)) {
940 chan = 0;
941 chan2 = 2;
942 } else {
943 BUG();
944 return;
945 }
946 break;
947 case OMAP_DSS_CHANNEL_WB:
948 chan = 0;
949 chan2 = 3;
950 break;
951 default:
952 BUG();
953 return;
954 }
955
956 val = FLD_MOD(val, chan, shift, shift);
957 val = FLD_MOD(val, chan2, 31, 30);
958 } else {
959 val = FLD_MOD(val, channel, shift, shift);
960 }
961 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), val);
962 }
963 EXPORT_SYMBOL(dispc_ovl_set_channel_out);
964
965 static enum omap_channel dispc_ovl_get_channel_out(enum omap_plane plane)
966 {
967 int shift;
968 u32 val;
969
970 switch (plane) {
971 case OMAP_DSS_GFX:
972 shift = 8;
973 break;
974 case OMAP_DSS_VIDEO1:
975 case OMAP_DSS_VIDEO2:
976 case OMAP_DSS_VIDEO3:
977 shift = 16;
978 break;
979 default:
980 BUG();
981 return 0;
982 }
983
984 val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
985
986 if (FLD_GET(val, shift, shift) == 1)
987 return OMAP_DSS_CHANNEL_DIGIT;
988
989 if (!dss_has_feature(FEAT_MGR_LCD2))
990 return OMAP_DSS_CHANNEL_LCD;
991
992 switch (FLD_GET(val, 31, 30)) {
993 case 0:
994 default:
995 return OMAP_DSS_CHANNEL_LCD;
996 case 1:
997 return OMAP_DSS_CHANNEL_LCD2;
998 case 2:
999 return OMAP_DSS_CHANNEL_LCD3;
1000 case 3:
1001 return OMAP_DSS_CHANNEL_WB;
1002 }
1003 }
1004
1005 static void dispc_ovl_set_burst_size(enum omap_plane plane,
1006 enum omap_burst_size burst_size)
1007 {
1008 static const unsigned shifts[] = { 6, 14, 14, 14, 14, };
1009 int shift;
1010
1011 shift = shifts[plane];
1012 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), burst_size, shift + 1, shift);
1013 }
1014
1015 static void dispc_configure_burst_sizes(void)
1016 {
1017 int i;
1018 const int burst_size = BURST_SIZE_X8;
1019
1020 /* Configure burst size always to maximum size */
1021 for (i = 0; i < dss_feat_get_num_ovls(); ++i)
1022 dispc_ovl_set_burst_size(i, burst_size);
1023 if (dispc.feat->has_writeback)
1024 dispc_ovl_set_burst_size(OMAP_DSS_WB, burst_size);
1025 }
1026
1027 static u32 dispc_ovl_get_burst_size(enum omap_plane plane)
1028 {
1029 unsigned unit = dss_feat_get_burst_size_unit();
1030 /* burst multiplier is always x8 (see dispc_configure_burst_sizes()) */
1031 return unit * 8;
1032 }
1033
1034 void dispc_enable_gamma_table(bool enable)
1035 {
1036 /*
1037 * This is partially implemented to support only disabling of
1038 * the gamma table.
1039 */
1040 if (enable) {
1041 DSSWARN("Gamma table enabling for TV not yet supported");
1042 return;
1043 }
1044
1045 REG_FLD_MOD(DISPC_CONFIG, enable, 9, 9);
1046 }
1047
1048 static void dispc_mgr_enable_cpr(enum omap_channel channel, bool enable)
1049 {
1050 if (channel == OMAP_DSS_CHANNEL_DIGIT)
1051 return;
1052
1053 mgr_fld_write(channel, DISPC_MGR_FLD_CPR, enable);
1054 }
1055
1056 static void dispc_mgr_set_cpr_coef(enum omap_channel channel,
1057 const struct omap_dss_cpr_coefs *coefs)
1058 {
1059 u32 coef_r, coef_g, coef_b;
1060
1061 if (!dss_mgr_is_lcd(channel))
1062 return;
1063
1064 coef_r = FLD_VAL(coefs->rr, 31, 22) | FLD_VAL(coefs->rg, 20, 11) |
1065 FLD_VAL(coefs->rb, 9, 0);
1066 coef_g = FLD_VAL(coefs->gr, 31, 22) | FLD_VAL(coefs->gg, 20, 11) |
1067 FLD_VAL(coefs->gb, 9, 0);
1068 coef_b = FLD_VAL(coefs->br, 31, 22) | FLD_VAL(coefs->bg, 20, 11) |
1069 FLD_VAL(coefs->bb, 9, 0);
1070
1071 dispc_write_reg(DISPC_CPR_COEF_R(channel), coef_r);
1072 dispc_write_reg(DISPC_CPR_COEF_G(channel), coef_g);
1073 dispc_write_reg(DISPC_CPR_COEF_B(channel), coef_b);
1074 }
1075
1076 static void dispc_ovl_set_vid_color_conv(enum omap_plane plane, bool enable)
1077 {
1078 u32 val;
1079
1080 BUG_ON(plane == OMAP_DSS_GFX);
1081
1082 val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
1083 val = FLD_MOD(val, enable, 9, 9);
1084 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), val);
1085 }
1086
1087 static void dispc_ovl_enable_replication(enum omap_plane plane,
1088 enum omap_overlay_caps caps, bool enable)
1089 {
1090 static const unsigned shifts[] = { 5, 10, 10, 10 };
1091 int shift;
1092
1093 if ((caps & OMAP_DSS_OVL_CAP_REPLICATION) == 0)
1094 return;
1095
1096 shift = shifts[plane];
1097 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable, shift, shift);
1098 }
1099
1100 static void dispc_mgr_set_size(enum omap_channel channel, u16 width,
1101 u16 height)
1102 {
1103 u32 val;
1104
1105 val = FLD_VAL(height - 1, dispc.feat->mgr_height_start, 16) |
1106 FLD_VAL(width - 1, dispc.feat->mgr_width_start, 0);
1107
1108 dispc_write_reg(DISPC_SIZE_MGR(channel), val);
1109 }
1110
1111 static void dispc_init_fifos(void)
1112 {
1113 u32 size;
1114 int fifo;
1115 u8 start, end;
1116 u32 unit;
1117 int i;
1118
1119 unit = dss_feat_get_buffer_size_unit();
1120
1121 dss_feat_get_reg_field(FEAT_REG_FIFOSIZE, &start, &end);
1122
1123 for (fifo = 0; fifo < dispc.feat->num_fifos; ++fifo) {
1124 size = REG_GET(DISPC_OVL_FIFO_SIZE_STATUS(fifo), start, end);
1125 size *= unit;
1126 dispc.fifo_size[fifo] = size;
1127
1128 /*
1129 * By default fifos are mapped directly to overlays, fifo 0 to
1130 * ovl 0, fifo 1 to ovl 1, etc.
1131 */
1132 dispc.fifo_assignment[fifo] = fifo;
1133 }
1134
1135 /*
1136 * The GFX fifo on OMAP4 is smaller than the other fifos. The small fifo
1137 * causes problems with certain use cases, like using the tiler in 2D
1138 * mode. The below hack swaps the fifos of GFX and WB planes, thus
1139 * giving GFX plane a larger fifo. WB but should work fine with a
1140 * smaller fifo.
1141 */
1142 if (dispc.feat->gfx_fifo_workaround) {
1143 u32 v;
1144
1145 v = dispc_read_reg(DISPC_GLOBAL_BUFFER);
1146
1147 v = FLD_MOD(v, 4, 2, 0); /* GFX BUF top to WB */
1148 v = FLD_MOD(v, 4, 5, 3); /* GFX BUF bottom to WB */
1149 v = FLD_MOD(v, 0, 26, 24); /* WB BUF top to GFX */
1150 v = FLD_MOD(v, 0, 29, 27); /* WB BUF bottom to GFX */
1151
1152 dispc_write_reg(DISPC_GLOBAL_BUFFER, v);
1153
1154 dispc.fifo_assignment[OMAP_DSS_GFX] = OMAP_DSS_WB;
1155 dispc.fifo_assignment[OMAP_DSS_WB] = OMAP_DSS_GFX;
1156 }
1157
1158 /*
1159 * Setup default fifo thresholds.
1160 */
1161 for (i = 0; i < dss_feat_get_num_ovls(); ++i) {
1162 u32 low, high;
1163 const bool use_fifomerge = false;
1164 const bool manual_update = false;
1165
1166 dispc_ovl_compute_fifo_thresholds(i, &low, &high,
1167 use_fifomerge, manual_update);
1168
1169 dispc_ovl_set_fifo_threshold(i, low, high);
1170 }
1171
1172 if (dispc.feat->has_writeback) {
1173 u32 low, high;
1174 const bool use_fifomerge = false;
1175 const bool manual_update = false;
1176
1177 dispc_ovl_compute_fifo_thresholds(OMAP_DSS_WB, &low, &high,
1178 use_fifomerge, manual_update);
1179
1180 dispc_ovl_set_fifo_threshold(OMAP_DSS_WB, low, high);
1181 }
1182 }
1183
1184 static u32 dispc_ovl_get_fifo_size(enum omap_plane plane)
1185 {
1186 int fifo;
1187 u32 size = 0;
1188
1189 for (fifo = 0; fifo < dispc.feat->num_fifos; ++fifo) {
1190 if (dispc.fifo_assignment[fifo] == plane)
1191 size += dispc.fifo_size[fifo];
1192 }
1193
1194 return size;
1195 }
1196
1197 void dispc_ovl_set_fifo_threshold(enum omap_plane plane, u32 low, u32 high)
1198 {
1199 u8 hi_start, hi_end, lo_start, lo_end;
1200 u32 unit;
1201
1202 unit = dss_feat_get_buffer_size_unit();
1203
1204 WARN_ON(low % unit != 0);
1205 WARN_ON(high % unit != 0);
1206
1207 low /= unit;
1208 high /= unit;
1209
1210 dss_feat_get_reg_field(FEAT_REG_FIFOHIGHTHRESHOLD, &hi_start, &hi_end);
1211 dss_feat_get_reg_field(FEAT_REG_FIFOLOWTHRESHOLD, &lo_start, &lo_end);
1212
1213 DSSDBG("fifo(%d) threshold (bytes), old %u/%u, new %u/%u\n",
1214 plane,
1215 REG_GET(DISPC_OVL_FIFO_THRESHOLD(plane),
1216 lo_start, lo_end) * unit,
1217 REG_GET(DISPC_OVL_FIFO_THRESHOLD(plane),
1218 hi_start, hi_end) * unit,
1219 low * unit, high * unit);
1220
1221 dispc_write_reg(DISPC_OVL_FIFO_THRESHOLD(plane),
1222 FLD_VAL(high, hi_start, hi_end) |
1223 FLD_VAL(low, lo_start, lo_end));
1224
1225 /*
1226 * configure the preload to the pipeline's high threhold, if HT it's too
1227 * large for the preload field, set the threshold to the maximum value
1228 * that can be held by the preload register
1229 */
1230 if (dss_has_feature(FEAT_PRELOAD) && dispc.feat->set_max_preload &&
1231 plane != OMAP_DSS_WB)
1232 dispc_write_reg(DISPC_OVL_PRELOAD(plane), min(high, 0xfffu));
1233 }
1234
1235 void dispc_enable_fifomerge(bool enable)
1236 {
1237 if (!dss_has_feature(FEAT_FIFO_MERGE)) {
1238 WARN_ON(enable);
1239 return;
1240 }
1241
1242 DSSDBG("FIFO merge %s\n", enable ? "enabled" : "disabled");
1243 REG_FLD_MOD(DISPC_CONFIG, enable ? 1 : 0, 14, 14);
1244 }
1245
1246 void dispc_ovl_compute_fifo_thresholds(enum omap_plane plane,
1247 u32 *fifo_low, u32 *fifo_high, bool use_fifomerge,
1248 bool manual_update)
1249 {
1250 /*
1251 * All sizes are in bytes. Both the buffer and burst are made of
1252 * buffer_units, and the fifo thresholds must be buffer_unit aligned.
1253 */
1254
1255 unsigned buf_unit = dss_feat_get_buffer_size_unit();
1256 unsigned ovl_fifo_size, total_fifo_size, burst_size;
1257 int i;
1258
1259 burst_size = dispc_ovl_get_burst_size(plane);
1260 ovl_fifo_size = dispc_ovl_get_fifo_size(plane);
1261
1262 if (use_fifomerge) {
1263 total_fifo_size = 0;
1264 for (i = 0; i < dss_feat_get_num_ovls(); ++i)
1265 total_fifo_size += dispc_ovl_get_fifo_size(i);
1266 } else {
1267 total_fifo_size = ovl_fifo_size;
1268 }
1269
1270 /*
1271 * We use the same low threshold for both fifomerge and non-fifomerge
1272 * cases, but for fifomerge we calculate the high threshold using the
1273 * combined fifo size
1274 */
1275
1276 if (manual_update && dss_has_feature(FEAT_OMAP3_DSI_FIFO_BUG)) {
1277 *fifo_low = ovl_fifo_size - burst_size * 2;
1278 *fifo_high = total_fifo_size - burst_size;
1279 } else if (plane == OMAP_DSS_WB) {
1280 /*
1281 * Most optimal configuration for writeback is to push out data
1282 * to the interconnect the moment writeback pushes enough pixels
1283 * in the FIFO to form a burst
1284 */
1285 *fifo_low = 0;
1286 *fifo_high = burst_size;
1287 } else {
1288 *fifo_low = ovl_fifo_size - burst_size;
1289 *fifo_high = total_fifo_size - buf_unit;
1290 }
1291 }
1292
1293 static void dispc_ovl_set_mflag(enum omap_plane plane, bool enable)
1294 {
1295 int bit;
1296
1297 if (plane == OMAP_DSS_GFX)
1298 bit = 14;
1299 else
1300 bit = 23;
1301
1302 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable, bit, bit);
1303 }
1304
1305 static void dispc_ovl_set_mflag_threshold(enum omap_plane plane,
1306 int low, int high)
1307 {
1308 dispc_write_reg(DISPC_OVL_MFLAG_THRESHOLD(plane),
1309 FLD_VAL(high, 31, 16) | FLD_VAL(low, 15, 0));
1310 }
1311
1312 static void dispc_init_mflag(void)
1313 {
1314 int i;
1315
1316 /*
1317 * HACK: NV12 color format and MFLAG seem to have problems working
1318 * together: using two displays, and having an NV12 overlay on one of
1319 * the displays will cause underflows/synclosts when MFLAG_CTRL=2.
1320 * Changing MFLAG thresholds and PRELOAD to certain values seem to
1321 * remove the errors, but there doesn't seem to be a clear logic on
1322 * which values work and which not.
1323 *
1324 * As a work-around, set force MFLAG to always on.
1325 */
1326 dispc_write_reg(DISPC_GLOBAL_MFLAG_ATTRIBUTE,
1327 (1 << 0) | /* MFLAG_CTRL = force always on */
1328 (0 << 2)); /* MFLAG_START = disable */
1329
1330 for (i = 0; i < dss_feat_get_num_ovls(); ++i) {
1331 u32 size = dispc_ovl_get_fifo_size(i);
1332 u32 unit = dss_feat_get_buffer_size_unit();
1333 u32 low, high;
1334
1335 dispc_ovl_set_mflag(i, true);
1336
1337 /*
1338 * Simulation team suggests below thesholds:
1339 * HT = fifosize * 5 / 8;
1340 * LT = fifosize * 4 / 8;
1341 */
1342
1343 low = size * 4 / 8 / unit;
1344 high = size * 5 / 8 / unit;
1345
1346 dispc_ovl_set_mflag_threshold(i, low, high);
1347 }
1348
1349 if (dispc.feat->has_writeback) {
1350 u32 size = dispc_ovl_get_fifo_size(OMAP_DSS_WB);
1351 u32 unit = dss_feat_get_buffer_size_unit();
1352 u32 low, high;
1353
1354 dispc_ovl_set_mflag(OMAP_DSS_WB, true);
1355
1356 /*
1357 * Simulation team suggests below thesholds:
1358 * HT = fifosize * 5 / 8;
1359 * LT = fifosize * 4 / 8;
1360 */
1361
1362 low = size * 4 / 8 / unit;
1363 high = size * 5 / 8 / unit;
1364
1365 dispc_ovl_set_mflag_threshold(OMAP_DSS_WB, low, high);
1366 }
1367 }
1368
1369 static void dispc_ovl_set_fir(enum omap_plane plane,
1370 int hinc, int vinc,
1371 enum omap_color_component color_comp)
1372 {
1373 u32 val;
1374
1375 if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y) {
1376 u8 hinc_start, hinc_end, vinc_start, vinc_end;
1377
1378 dss_feat_get_reg_field(FEAT_REG_FIRHINC,
1379 &hinc_start, &hinc_end);
1380 dss_feat_get_reg_field(FEAT_REG_FIRVINC,
1381 &vinc_start, &vinc_end);
1382 val = FLD_VAL(vinc, vinc_start, vinc_end) |
1383 FLD_VAL(hinc, hinc_start, hinc_end);
1384
1385 dispc_write_reg(DISPC_OVL_FIR(plane), val);
1386 } else {
1387 val = FLD_VAL(vinc, 28, 16) | FLD_VAL(hinc, 12, 0);
1388 dispc_write_reg(DISPC_OVL_FIR2(plane), val);
1389 }
1390 }
1391
1392 static void dispc_ovl_set_vid_accu0(enum omap_plane plane, int haccu, int vaccu)
1393 {
1394 u32 val;
1395 u8 hor_start, hor_end, vert_start, vert_end;
1396
1397 dss_feat_get_reg_field(FEAT_REG_HORIZONTALACCU, &hor_start, &hor_end);
1398 dss_feat_get_reg_field(FEAT_REG_VERTICALACCU, &vert_start, &vert_end);
1399
1400 val = FLD_VAL(vaccu, vert_start, vert_end) |
1401 FLD_VAL(haccu, hor_start, hor_end);
1402
1403 dispc_write_reg(DISPC_OVL_ACCU0(plane), val);
1404 }
1405
1406 static void dispc_ovl_set_vid_accu1(enum omap_plane plane, int haccu, int vaccu)
1407 {
1408 u32 val;
1409 u8 hor_start, hor_end, vert_start, vert_end;
1410
1411 dss_feat_get_reg_field(FEAT_REG_HORIZONTALACCU, &hor_start, &hor_end);
1412 dss_feat_get_reg_field(FEAT_REG_VERTICALACCU, &vert_start, &vert_end);
1413
1414 val = FLD_VAL(vaccu, vert_start, vert_end) |
1415 FLD_VAL(haccu, hor_start, hor_end);
1416
1417 dispc_write_reg(DISPC_OVL_ACCU1(plane), val);
1418 }
1419
1420 static void dispc_ovl_set_vid_accu2_0(enum omap_plane plane, int haccu,
1421 int vaccu)
1422 {
1423 u32 val;
1424
1425 val = FLD_VAL(vaccu, 26, 16) | FLD_VAL(haccu, 10, 0);
1426 dispc_write_reg(DISPC_OVL_ACCU2_0(plane), val);
1427 }
1428
1429 static void dispc_ovl_set_vid_accu2_1(enum omap_plane plane, int haccu,
1430 int vaccu)
1431 {
1432 u32 val;
1433
1434 val = FLD_VAL(vaccu, 26, 16) | FLD_VAL(haccu, 10, 0);
1435 dispc_write_reg(DISPC_OVL_ACCU2_1(plane), val);
1436 }
1437
1438 static void dispc_ovl_set_scale_param(enum omap_plane plane,
1439 u16 orig_width, u16 orig_height,
1440 u16 out_width, u16 out_height,
1441 bool five_taps, u8 rotation,
1442 enum omap_color_component color_comp)
1443 {
1444 int fir_hinc, fir_vinc;
1445
1446 fir_hinc = 1024 * orig_width / out_width;
1447 fir_vinc = 1024 * orig_height / out_height;
1448
1449 dispc_ovl_set_scale_coef(plane, fir_hinc, fir_vinc, five_taps,
1450 color_comp);
1451 dispc_ovl_set_fir(plane, fir_hinc, fir_vinc, color_comp);
1452 }
1453
1454 static void dispc_ovl_set_accu_uv(enum omap_plane plane,
1455 u16 orig_width, u16 orig_height, u16 out_width, u16 out_height,
1456 bool ilace, enum omap_color_mode color_mode, u8 rotation)
1457 {
1458 int h_accu2_0, h_accu2_1;
1459 int v_accu2_0, v_accu2_1;
1460 int chroma_hinc, chroma_vinc;
1461 int idx;
1462
1463 struct accu {
1464 s8 h0_m, h0_n;
1465 s8 h1_m, h1_n;
1466 s8 v0_m, v0_n;
1467 s8 v1_m, v1_n;
1468 };
1469
1470 const struct accu *accu_table;
1471 const struct accu *accu_val;
1472
1473 static const struct accu accu_nv12[4] = {
1474 { 0, 1, 0, 1 , -1, 2, 0, 1 },
1475 { 1, 2, -3, 4 , 0, 1, 0, 1 },
1476 { -1, 1, 0, 1 , -1, 2, 0, 1 },
1477 { -1, 2, -1, 2 , -1, 1, 0, 1 },
1478 };
1479
1480 static const struct accu accu_nv12_ilace[4] = {
1481 { 0, 1, 0, 1 , -3, 4, -1, 4 },
1482 { -1, 4, -3, 4 , 0, 1, 0, 1 },
1483 { -1, 1, 0, 1 , -1, 4, -3, 4 },
1484 { -3, 4, -3, 4 , -1, 1, 0, 1 },
1485 };
1486
1487 static const struct accu accu_yuv[4] = {
1488 { 0, 1, 0, 1, 0, 1, 0, 1 },
1489 { 0, 1, 0, 1, 0, 1, 0, 1 },
1490 { -1, 1, 0, 1, 0, 1, 0, 1 },
1491 { 0, 1, 0, 1, -1, 1, 0, 1 },
1492 };
1493
1494 switch (rotation) {
1495 case OMAP_DSS_ROT_0:
1496 idx = 0;
1497 break;
1498 case OMAP_DSS_ROT_90:
1499 idx = 1;
1500 break;
1501 case OMAP_DSS_ROT_180:
1502 idx = 2;
1503 break;
1504 case OMAP_DSS_ROT_270:
1505 idx = 3;
1506 break;
1507 default:
1508 BUG();
1509 return;
1510 }
1511
1512 switch (color_mode) {
1513 case OMAP_DSS_COLOR_NV12:
1514 if (ilace)
1515 accu_table = accu_nv12_ilace;
1516 else
1517 accu_table = accu_nv12;
1518 break;
1519 case OMAP_DSS_COLOR_YUV2:
1520 case OMAP_DSS_COLOR_UYVY:
1521 accu_table = accu_yuv;
1522 break;
1523 default:
1524 BUG();
1525 return;
1526 }
1527
1528 accu_val = &accu_table[idx];
1529
1530 chroma_hinc = 1024 * orig_width / out_width;
1531 chroma_vinc = 1024 * orig_height / out_height;
1532
1533 h_accu2_0 = (accu_val->h0_m * chroma_hinc / accu_val->h0_n) % 1024;
1534 h_accu2_1 = (accu_val->h1_m * chroma_hinc / accu_val->h1_n) % 1024;
1535 v_accu2_0 = (accu_val->v0_m * chroma_vinc / accu_val->v0_n) % 1024;
1536 v_accu2_1 = (accu_val->v1_m * chroma_vinc / accu_val->v1_n) % 1024;
1537
1538 dispc_ovl_set_vid_accu2_0(plane, h_accu2_0, v_accu2_0);
1539 dispc_ovl_set_vid_accu2_1(plane, h_accu2_1, v_accu2_1);
1540 }
1541
1542 static void dispc_ovl_set_scaling_common(enum omap_plane plane,
1543 u16 orig_width, u16 orig_height,
1544 u16 out_width, u16 out_height,
1545 bool ilace, bool five_taps,
1546 bool fieldmode, enum omap_color_mode color_mode,
1547 u8 rotation)
1548 {
1549 int accu0 = 0;
1550 int accu1 = 0;
1551 u32 l;
1552
1553 dispc_ovl_set_scale_param(plane, orig_width, orig_height,
1554 out_width, out_height, five_taps,
1555 rotation, DISPC_COLOR_COMPONENT_RGB_Y);
1556 l = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
1557
1558 /* RESIZEENABLE and VERTICALTAPS */
1559 l &= ~((0x3 << 5) | (0x1 << 21));
1560 l |= (orig_width != out_width) ? (1 << 5) : 0;
1561 l |= (orig_height != out_height) ? (1 << 6) : 0;
1562 l |= five_taps ? (1 << 21) : 0;
1563
1564 /* VRESIZECONF and HRESIZECONF */
1565 if (dss_has_feature(FEAT_RESIZECONF)) {
1566 l &= ~(0x3 << 7);
1567 l |= (orig_width <= out_width) ? 0 : (1 << 7);
1568 l |= (orig_height <= out_height) ? 0 : (1 << 8);
1569 }
1570
1571 /* LINEBUFFERSPLIT */
1572 if (dss_has_feature(FEAT_LINEBUFFERSPLIT)) {
1573 l &= ~(0x1 << 22);
1574 l |= five_taps ? (1 << 22) : 0;
1575 }
1576
1577 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), l);
1578
1579 /*
1580 * field 0 = even field = bottom field
1581 * field 1 = odd field = top field
1582 */
1583 if (ilace && !fieldmode) {
1584 accu1 = 0;
1585 accu0 = ((1024 * orig_height / out_height) / 2) & 0x3ff;
1586 if (accu0 >= 1024/2) {
1587 accu1 = 1024/2;
1588 accu0 -= accu1;
1589 }
1590 }
1591
1592 dispc_ovl_set_vid_accu0(plane, 0, accu0);
1593 dispc_ovl_set_vid_accu1(plane, 0, accu1);
1594 }
1595
1596 static void dispc_ovl_set_scaling_uv(enum omap_plane plane,
1597 u16 orig_width, u16 orig_height,
1598 u16 out_width, u16 out_height,
1599 bool ilace, bool five_taps,
1600 bool fieldmode, enum omap_color_mode color_mode,
1601 u8 rotation)
1602 {
1603 int scale_x = out_width != orig_width;
1604 int scale_y = out_height != orig_height;
1605 bool chroma_upscale = plane != OMAP_DSS_WB;
1606
1607 if (!dss_has_feature(FEAT_HANDLE_UV_SEPARATE))
1608 return;
1609 if ((color_mode != OMAP_DSS_COLOR_YUV2 &&
1610 color_mode != OMAP_DSS_COLOR_UYVY &&
1611 color_mode != OMAP_DSS_COLOR_NV12)) {
1612 /* reset chroma resampling for RGB formats */
1613 if (plane != OMAP_DSS_WB)
1614 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane), 0, 8, 8);
1615 return;
1616 }
1617
1618 dispc_ovl_set_accu_uv(plane, orig_width, orig_height, out_width,
1619 out_height, ilace, color_mode, rotation);
1620
1621 switch (color_mode) {
1622 case OMAP_DSS_COLOR_NV12:
1623 if (chroma_upscale) {
1624 /* UV is subsampled by 2 horizontally and vertically */
1625 orig_height >>= 1;
1626 orig_width >>= 1;
1627 } else {
1628 /* UV is downsampled by 2 horizontally and vertically */
1629 orig_height <<= 1;
1630 orig_width <<= 1;
1631 }
1632
1633 break;
1634 case OMAP_DSS_COLOR_YUV2:
1635 case OMAP_DSS_COLOR_UYVY:
1636 /* For YUV422 with 90/270 rotation, we don't upsample chroma */
1637 if (rotation == OMAP_DSS_ROT_0 ||
1638 rotation == OMAP_DSS_ROT_180) {
1639 if (chroma_upscale)
1640 /* UV is subsampled by 2 horizontally */
1641 orig_width >>= 1;
1642 else
1643 /* UV is downsampled by 2 horizontally */
1644 orig_width <<= 1;
1645 }
1646
1647 /* must use FIR for YUV422 if rotated */
1648 if (rotation != OMAP_DSS_ROT_0)
1649 scale_x = scale_y = true;
1650
1651 break;
1652 default:
1653 BUG();
1654 return;
1655 }
1656
1657 if (out_width != orig_width)
1658 scale_x = true;
1659 if (out_height != orig_height)
1660 scale_y = true;
1661
1662 dispc_ovl_set_scale_param(plane, orig_width, orig_height,
1663 out_width, out_height, five_taps,
1664 rotation, DISPC_COLOR_COMPONENT_UV);
1665
1666 if (plane != OMAP_DSS_WB)
1667 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane),
1668 (scale_x || scale_y) ? 1 : 0, 8, 8);
1669
1670 /* set H scaling */
1671 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), scale_x ? 1 : 0, 5, 5);
1672 /* set V scaling */
1673 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), scale_y ? 1 : 0, 6, 6);
1674 }
1675
1676 static void dispc_ovl_set_scaling(enum omap_plane plane,
1677 u16 orig_width, u16 orig_height,
1678 u16 out_width, u16 out_height,
1679 bool ilace, bool five_taps,
1680 bool fieldmode, enum omap_color_mode color_mode,
1681 u8 rotation)
1682 {
1683 BUG_ON(plane == OMAP_DSS_GFX);
1684
1685 dispc_ovl_set_scaling_common(plane,
1686 orig_width, orig_height,
1687 out_width, out_height,
1688 ilace, five_taps,
1689 fieldmode, color_mode,
1690 rotation);
1691
1692 dispc_ovl_set_scaling_uv(plane,
1693 orig_width, orig_height,
1694 out_width, out_height,
1695 ilace, five_taps,
1696 fieldmode, color_mode,
1697 rotation);
1698 }
1699
1700 static void dispc_ovl_set_rotation_attrs(enum omap_plane plane, u8 rotation,
1701 enum omap_dss_rotation_type rotation_type,
1702 bool mirroring, enum omap_color_mode color_mode)
1703 {
1704 bool row_repeat = false;
1705 int vidrot = 0;
1706
1707 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1708 color_mode == OMAP_DSS_COLOR_UYVY) {
1709
1710 if (mirroring) {
1711 switch (rotation) {
1712 case OMAP_DSS_ROT_0:
1713 vidrot = 2;
1714 break;
1715 case OMAP_DSS_ROT_90:
1716 vidrot = 1;
1717 break;
1718 case OMAP_DSS_ROT_180:
1719 vidrot = 0;
1720 break;
1721 case OMAP_DSS_ROT_270:
1722 vidrot = 3;
1723 break;
1724 }
1725 } else {
1726 switch (rotation) {
1727 case OMAP_DSS_ROT_0:
1728 vidrot = 0;
1729 break;
1730 case OMAP_DSS_ROT_90:
1731 vidrot = 1;
1732 break;
1733 case OMAP_DSS_ROT_180:
1734 vidrot = 2;
1735 break;
1736 case OMAP_DSS_ROT_270:
1737 vidrot = 3;
1738 break;
1739 }
1740 }
1741
1742 if (rotation == OMAP_DSS_ROT_90 || rotation == OMAP_DSS_ROT_270)
1743 row_repeat = true;
1744 else
1745 row_repeat = false;
1746 }
1747
1748 /*
1749 * OMAP4/5 Errata i631:
1750 * NV12 in 1D mode must use ROTATION=1. Otherwise DSS will fetch extra
1751 * rows beyond the framebuffer, which may cause OCP error.
1752 */
1753 if (color_mode == OMAP_DSS_COLOR_NV12 &&
1754 rotation_type != OMAP_DSS_ROT_TILER)
1755 vidrot = 1;
1756
1757 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), vidrot, 13, 12);
1758 if (dss_has_feature(FEAT_ROWREPEATENABLE))
1759 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane),
1760 row_repeat ? 1 : 0, 18, 18);
1761
1762 if (color_mode == OMAP_DSS_COLOR_NV12) {
1763 bool doublestride = (rotation_type == OMAP_DSS_ROT_TILER) &&
1764 (rotation == OMAP_DSS_ROT_0 ||
1765 rotation == OMAP_DSS_ROT_180);
1766 /* DOUBLESTRIDE */
1767 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), doublestride, 22, 22);
1768 }
1769
1770 }
1771
1772 static int color_mode_to_bpp(enum omap_color_mode color_mode)
1773 {
1774 switch (color_mode) {
1775 case OMAP_DSS_COLOR_CLUT1:
1776 return 1;
1777 case OMAP_DSS_COLOR_CLUT2:
1778 return 2;
1779 case OMAP_DSS_COLOR_CLUT4:
1780 return 4;
1781 case OMAP_DSS_COLOR_CLUT8:
1782 case OMAP_DSS_COLOR_NV12:
1783 return 8;
1784 case OMAP_DSS_COLOR_RGB12U:
1785 case OMAP_DSS_COLOR_RGB16:
1786 case OMAP_DSS_COLOR_ARGB16:
1787 case OMAP_DSS_COLOR_YUV2:
1788 case OMAP_DSS_COLOR_UYVY:
1789 case OMAP_DSS_COLOR_RGBA16:
1790 case OMAP_DSS_COLOR_RGBX16:
1791 case OMAP_DSS_COLOR_ARGB16_1555:
1792 case OMAP_DSS_COLOR_XRGB16_1555:
1793 return 16;
1794 case OMAP_DSS_COLOR_RGB24P:
1795 return 24;
1796 case OMAP_DSS_COLOR_RGB24U:
1797 case OMAP_DSS_COLOR_ARGB32:
1798 case OMAP_DSS_COLOR_RGBA32:
1799 case OMAP_DSS_COLOR_RGBX32:
1800 return 32;
1801 default:
1802 BUG();
1803 return 0;
1804 }
1805 }
1806
1807 static s32 pixinc(int pixels, u8 ps)
1808 {
1809 if (pixels == 1)
1810 return 1;
1811 else if (pixels > 1)
1812 return 1 + (pixels - 1) * ps;
1813 else if (pixels < 0)
1814 return 1 - (-pixels + 1) * ps;
1815 else
1816 BUG();
1817 return 0;
1818 }
1819
1820 static void calc_vrfb_rotation_offset(u8 rotation, bool mirror,
1821 u16 screen_width,
1822 u16 width, u16 height,
1823 enum omap_color_mode color_mode, bool fieldmode,
1824 unsigned int field_offset,
1825 unsigned *offset0, unsigned *offset1,
1826 s32 *row_inc, s32 *pix_inc, int x_predecim, int y_predecim)
1827 {
1828 u8 ps;
1829
1830 /* FIXME CLUT formats */
1831 switch (color_mode) {
1832 case OMAP_DSS_COLOR_CLUT1:
1833 case OMAP_DSS_COLOR_CLUT2:
1834 case OMAP_DSS_COLOR_CLUT4:
1835 case OMAP_DSS_COLOR_CLUT8:
1836 BUG();
1837 return;
1838 case OMAP_DSS_COLOR_YUV2:
1839 case OMAP_DSS_COLOR_UYVY:
1840 ps = 4;
1841 break;
1842 default:
1843 ps = color_mode_to_bpp(color_mode) / 8;
1844 break;
1845 }
1846
1847 DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation, screen_width,
1848 width, height);
1849
1850 /*
1851 * field 0 = even field = bottom field
1852 * field 1 = odd field = top field
1853 */
1854 switch (rotation + mirror * 4) {
1855 case OMAP_DSS_ROT_0:
1856 case OMAP_DSS_ROT_180:
1857 /*
1858 * If the pixel format is YUV or UYVY divide the width
1859 * of the image by 2 for 0 and 180 degree rotation.
1860 */
1861 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1862 color_mode == OMAP_DSS_COLOR_UYVY)
1863 width = width >> 1;
1864 fallthrough;
1865 case OMAP_DSS_ROT_90:
1866 case OMAP_DSS_ROT_270:
1867 *offset1 = 0;
1868 if (field_offset)
1869 *offset0 = field_offset * screen_width * ps;
1870 else
1871 *offset0 = 0;
1872
1873 *row_inc = pixinc(1 +
1874 (y_predecim * screen_width - x_predecim * width) +
1875 (fieldmode ? screen_width : 0), ps);
1876 *pix_inc = pixinc(x_predecim, ps);
1877 break;
1878
1879 case OMAP_DSS_ROT_0 + 4:
1880 case OMAP_DSS_ROT_180 + 4:
1881 /* If the pixel format is YUV or UYVY divide the width
1882 * of the image by 2 for 0 degree and 180 degree
1883 */
1884 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1885 color_mode == OMAP_DSS_COLOR_UYVY)
1886 width = width >> 1;
1887 fallthrough;
1888 case OMAP_DSS_ROT_90 + 4:
1889 case OMAP_DSS_ROT_270 + 4:
1890 *offset1 = 0;
1891 if (field_offset)
1892 *offset0 = field_offset * screen_width * ps;
1893 else
1894 *offset0 = 0;
1895 *row_inc = pixinc(1 -
1896 (y_predecim * screen_width + x_predecim * width) -
1897 (fieldmode ? screen_width : 0), ps);
1898 *pix_inc = pixinc(x_predecim, ps);
1899 break;
1900
1901 default:
1902 BUG();
1903 return;
1904 }
1905 }
1906
1907 static void calc_dma_rotation_offset(u8 rotation, bool mirror,
1908 u16 screen_width,
1909 u16 width, u16 height,
1910 enum omap_color_mode color_mode, bool fieldmode,
1911 unsigned int field_offset,
1912 unsigned *offset0, unsigned *offset1,
1913 s32 *row_inc, s32 *pix_inc, int x_predecim, int y_predecim)
1914 {
1915 u8 ps;
1916 u16 fbw, fbh;
1917
1918 /* FIXME CLUT formats */
1919 switch (color_mode) {
1920 case OMAP_DSS_COLOR_CLUT1:
1921 case OMAP_DSS_COLOR_CLUT2:
1922 case OMAP_DSS_COLOR_CLUT4:
1923 case OMAP_DSS_COLOR_CLUT8:
1924 BUG();
1925 return;
1926 default:
1927 ps = color_mode_to_bpp(color_mode) / 8;
1928 break;
1929 }
1930
1931 DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation, screen_width,
1932 width, height);
1933
1934 /* width & height are overlay sizes, convert to fb sizes */
1935
1936 if (rotation == OMAP_DSS_ROT_0 || rotation == OMAP_DSS_ROT_180) {
1937 fbw = width;
1938 fbh = height;
1939 } else {
1940 fbw = height;
1941 fbh = width;
1942 }
1943
1944 /*
1945 * field 0 = even field = bottom field
1946 * field 1 = odd field = top field
1947 */
1948 switch (rotation + mirror * 4) {
1949 case OMAP_DSS_ROT_0:
1950 *offset1 = 0;
1951 if (field_offset)
1952 *offset0 = *offset1 + field_offset * screen_width * ps;
1953 else
1954 *offset0 = *offset1;
1955 *row_inc = pixinc(1 +
1956 (y_predecim * screen_width - fbw * x_predecim) +
1957 (fieldmode ? screen_width : 0), ps);
1958 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1959 color_mode == OMAP_DSS_COLOR_UYVY)
1960 *pix_inc = pixinc(x_predecim, 2 * ps);
1961 else
1962 *pix_inc = pixinc(x_predecim, ps);
1963 break;
1964 case OMAP_DSS_ROT_90:
1965 *offset1 = screen_width * (fbh - 1) * ps;
1966 if (field_offset)
1967 *offset0 = *offset1 + field_offset * ps;
1968 else
1969 *offset0 = *offset1;
1970 *row_inc = pixinc(screen_width * (fbh * x_predecim - 1) +
1971 y_predecim + (fieldmode ? 1 : 0), ps);
1972 *pix_inc = pixinc(-x_predecim * screen_width, ps);
1973 break;
1974 case OMAP_DSS_ROT_180:
1975 *offset1 = (screen_width * (fbh - 1) + fbw - 1) * ps;
1976 if (field_offset)
1977 *offset0 = *offset1 - field_offset * screen_width * ps;
1978 else
1979 *offset0 = *offset1;
1980 *row_inc = pixinc(-1 -
1981 (y_predecim * screen_width - fbw * x_predecim) -
1982 (fieldmode ? screen_width : 0), ps);
1983 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1984 color_mode == OMAP_DSS_COLOR_UYVY)
1985 *pix_inc = pixinc(-x_predecim, 2 * ps);
1986 else
1987 *pix_inc = pixinc(-x_predecim, ps);
1988 break;
1989 case OMAP_DSS_ROT_270:
1990 *offset1 = (fbw - 1) * ps;
1991 if (field_offset)
1992 *offset0 = *offset1 - field_offset * ps;
1993 else
1994 *offset0 = *offset1;
1995 *row_inc = pixinc(-screen_width * (fbh * x_predecim - 1) -
1996 y_predecim - (fieldmode ? 1 : 0), ps);
1997 *pix_inc = pixinc(x_predecim * screen_width, ps);
1998 break;
1999
2000 /* mirroring */
2001 case OMAP_DSS_ROT_0 + 4:
2002 *offset1 = (fbw - 1) * ps;
2003 if (field_offset)
2004 *offset0 = *offset1 + field_offset * screen_width * ps;
2005 else
2006 *offset0 = *offset1;
2007 *row_inc = pixinc(y_predecim * screen_width * 2 - 1 +
2008 (fieldmode ? screen_width : 0),
2009 ps);
2010 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
2011 color_mode == OMAP_DSS_COLOR_UYVY)
2012 *pix_inc = pixinc(-x_predecim, 2 * ps);
2013 else
2014 *pix_inc = pixinc(-x_predecim, ps);
2015 break;
2016
2017 case OMAP_DSS_ROT_90 + 4:
2018 *offset1 = 0;
2019 if (field_offset)
2020 *offset0 = *offset1 + field_offset * ps;
2021 else
2022 *offset0 = *offset1;
2023 *row_inc = pixinc(-screen_width * (fbh * x_predecim - 1) +
2024 y_predecim + (fieldmode ? 1 : 0),
2025 ps);
2026 *pix_inc = pixinc(x_predecim * screen_width, ps);
2027 break;
2028
2029 case OMAP_DSS_ROT_180 + 4:
2030 *offset1 = screen_width * (fbh - 1) * ps;
2031 if (field_offset)
2032 *offset0 = *offset1 - field_offset * screen_width * ps;
2033 else
2034 *offset0 = *offset1;
2035 *row_inc = pixinc(1 - y_predecim * screen_width * 2 -
2036 (fieldmode ? screen_width : 0),
2037 ps);
2038 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
2039 color_mode == OMAP_DSS_COLOR_UYVY)
2040 *pix_inc = pixinc(x_predecim, 2 * ps);
2041 else
2042 *pix_inc = pixinc(x_predecim, ps);
2043 break;
2044
2045 case OMAP_DSS_ROT_270 + 4:
2046 *offset1 = (screen_width * (fbh - 1) + fbw - 1) * ps;
2047 if (field_offset)
2048 *offset0 = *offset1 - field_offset * ps;
2049 else
2050 *offset0 = *offset1;
2051 *row_inc = pixinc(screen_width * (fbh * x_predecim - 1) -
2052 y_predecim - (fieldmode ? 1 : 0),
2053 ps);
2054 *pix_inc = pixinc(-x_predecim * screen_width, ps);
2055 break;
2056
2057 default:
2058 BUG();
2059 return;
2060 }
2061 }
2062
2063 static void calc_tiler_rotation_offset(u16 screen_width, u16 width,
2064 enum omap_color_mode color_mode, bool fieldmode,
2065 unsigned int field_offset, unsigned *offset0, unsigned *offset1,
2066 s32 *row_inc, s32 *pix_inc, int x_predecim, int y_predecim)
2067 {
2068 u8 ps;
2069
2070 switch (color_mode) {
2071 case OMAP_DSS_COLOR_CLUT1:
2072 case OMAP_DSS_COLOR_CLUT2:
2073 case OMAP_DSS_COLOR_CLUT4:
2074 case OMAP_DSS_COLOR_CLUT8:
2075 BUG();
2076 return;
2077 default:
2078 ps = color_mode_to_bpp(color_mode) / 8;
2079 break;
2080 }
2081
2082 DSSDBG("scrw %d, width %d\n", screen_width, width);
2083
2084 /*
2085 * field 0 = even field = bottom field
2086 * field 1 = odd field = top field
2087 */
2088 *offset1 = 0;
2089 if (field_offset)
2090 *offset0 = *offset1 + field_offset * screen_width * ps;
2091 else
2092 *offset0 = *offset1;
2093 *row_inc = pixinc(1 + (y_predecim * screen_width - width * x_predecim) +
2094 (fieldmode ? screen_width : 0), ps);
2095 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
2096 color_mode == OMAP_DSS_COLOR_UYVY)
2097 *pix_inc = pixinc(x_predecim, 2 * ps);
2098 else
2099 *pix_inc = pixinc(x_predecim, ps);
2100 }
2101
2102 /*
2103 * This function is used to avoid synclosts in OMAP3, because of some
2104 * undocumented horizontal position and timing related limitations.
2105 */
2106 static int check_horiz_timing_omap3(unsigned long pclk, unsigned long lclk,
2107 const struct omap_video_timings *t, u16 pos_x,
2108 u16 width, u16 height, u16 out_width, u16 out_height,
2109 bool five_taps)
2110 {
2111 const int ds = DIV_ROUND_UP(height, out_height);
2112 unsigned long nonactive;
2113 static const u8 limits[3] = { 8, 10, 20 };
2114 u64 val, blank;
2115 int i;
2116
2117 nonactive = t->x_res + t->hfp + t->hsw + t->hbp - out_width;
2118
2119 i = 0;
2120 if (out_height < height)
2121 i++;
2122 if (out_width < width)
2123 i++;
2124 blank = div_u64((u64)(t->hbp + t->hsw + t->hfp) * lclk, pclk);
2125 DSSDBG("blanking period + ppl = %llu (limit = %u)\n", blank, limits[i]);
2126 if (blank <= limits[i])
2127 return -EINVAL;
2128
2129 /* FIXME add checks for 3-tap filter once the limitations are known */
2130 if (!five_taps)
2131 return 0;
2132
2133 /*
2134 * Pixel data should be prepared before visible display point starts.
2135 * So, atleast DS-2 lines must have already been fetched by DISPC
2136 * during nonactive - pos_x period.
2137 */
2138 val = div_u64((u64)(nonactive - pos_x) * lclk, pclk);
2139 DSSDBG("(nonactive - pos_x) * pcd = %llu max(0, DS - 2) * width = %d\n",
2140 val, max(0, ds - 2) * width);
2141 if (val < max(0, ds - 2) * width)
2142 return -EINVAL;
2143
2144 /*
2145 * All lines need to be refilled during the nonactive period of which
2146 * only one line can be loaded during the active period. So, atleast
2147 * DS - 1 lines should be loaded during nonactive period.
2148 */
2149 val = div_u64((u64)nonactive * lclk, pclk);
2150 DSSDBG("nonactive * pcd = %llu, max(0, DS - 1) * width = %d\n",
2151 val, max(0, ds - 1) * width);
2152 if (val < max(0, ds - 1) * width)
2153 return -EINVAL;
2154
2155 return 0;
2156 }
2157
2158 static unsigned long calc_core_clk_five_taps(unsigned long pclk,
2159 const struct omap_video_timings *mgr_timings, u16 width,
2160 u16 height, u16 out_width, u16 out_height,
2161 enum omap_color_mode color_mode)
2162 {
2163 u32 core_clk = 0;
2164 u64 tmp;
2165
2166 if (height <= out_height && width <= out_width)
2167 return (unsigned long) pclk;
2168
2169 if (height > out_height) {
2170 unsigned int ppl = mgr_timings->x_res;
2171
2172 tmp = (u64)pclk * height * out_width;
2173 do_div(tmp, 2 * out_height * ppl);
2174 core_clk = tmp;
2175
2176 if (height > 2 * out_height) {
2177 if (ppl == out_width)
2178 return 0;
2179
2180 tmp = (u64)pclk * (height - 2 * out_height) * out_width;
2181 do_div(tmp, 2 * out_height * (ppl - out_width));
2182 core_clk = max_t(u32, core_clk, tmp);
2183 }
2184 }
2185
2186 if (width > out_width) {
2187 tmp = (u64)pclk * width;
2188 do_div(tmp, out_width);
2189 core_clk = max_t(u32, core_clk, tmp);
2190
2191 if (color_mode == OMAP_DSS_COLOR_RGB24U)
2192 core_clk <<= 1;
2193 }
2194
2195 return core_clk;
2196 }
2197
2198 static unsigned long calc_core_clk_24xx(unsigned long pclk, u16 width,
2199 u16 height, u16 out_width, u16 out_height, bool mem_to_mem)
2200 {
2201 if (height > out_height && width > out_width)
2202 return pclk * 4;
2203 else
2204 return pclk * 2;
2205 }
2206
2207 static unsigned long calc_core_clk_34xx(unsigned long pclk, u16 width,
2208 u16 height, u16 out_width, u16 out_height, bool mem_to_mem)
2209 {
2210 unsigned int hf, vf;
2211
2212 /*
2213 * FIXME how to determine the 'A' factor
2214 * for the no downscaling case ?
2215 */
2216
2217 if (width > 3 * out_width)
2218 hf = 4;
2219 else if (width > 2 * out_width)
2220 hf = 3;
2221 else if (width > out_width)
2222 hf = 2;
2223 else
2224 hf = 1;
2225 if (height > out_height)
2226 vf = 2;
2227 else
2228 vf = 1;
2229
2230 return pclk * vf * hf;
2231 }
2232
2233 static unsigned long calc_core_clk_44xx(unsigned long pclk, u16 width,
2234 u16 height, u16 out_width, u16 out_height, bool mem_to_mem)
2235 {
2236 /*
2237 * If the overlay/writeback is in mem to mem mode, there are no
2238 * downscaling limitations with respect to pixel clock, return 1 as
2239 * required core clock to represent that we have sufficient enough
2240 * core clock to do maximum downscaling
2241 */
2242 if (mem_to_mem)
2243 return 1;
2244
2245 if (width > out_width)
2246 return DIV_ROUND_UP(pclk, out_width) * width;
2247 else
2248 return pclk;
2249 }
2250
2251 static int dispc_ovl_calc_scaling_24xx(unsigned long pclk, unsigned long lclk,
2252 const struct omap_video_timings *mgr_timings,
2253 u16 width, u16 height, u16 out_width, u16 out_height,
2254 enum omap_color_mode color_mode, bool *five_taps,
2255 int *x_predecim, int *y_predecim, int *decim_x, int *decim_y,
2256 u16 pos_x, unsigned long *core_clk, bool mem_to_mem)
2257 {
2258 int error;
2259 u16 in_width, in_height;
2260 int min_factor = min(*decim_x, *decim_y);
2261 const int maxsinglelinewidth =
2262 dss_feat_get_param_max(FEAT_PARAM_LINEWIDTH);
2263
2264 *five_taps = false;
2265
2266 do {
2267 in_height = height / *decim_y;
2268 in_width = width / *decim_x;
2269 *core_clk = dispc.feat->calc_core_clk(pclk, in_width,
2270 in_height, out_width, out_height, mem_to_mem);
2271 error = (in_width > maxsinglelinewidth || !*core_clk ||
2272 *core_clk > dispc_core_clk_rate());
2273 if (error) {
2274 if (*decim_x == *decim_y) {
2275 *decim_x = min_factor;
2276 ++*decim_y;
2277 } else {
2278 swap(*decim_x, *decim_y);
2279 if (*decim_x < *decim_y)
2280 ++*decim_x;
2281 }
2282 }
2283 } while (*decim_x <= *x_predecim && *decim_y <= *y_predecim && error);
2284
2285 if (error) {
2286 DSSERR("failed to find scaling settings\n");
2287 return -EINVAL;
2288 }
2289
2290 if (in_width > maxsinglelinewidth) {
2291 DSSERR("Cannot scale max input width exceeded");
2292 return -EINVAL;
2293 }
2294 return 0;
2295 }
2296
2297 static int dispc_ovl_calc_scaling_34xx(unsigned long pclk, unsigned long lclk,
2298 const struct omap_video_timings *mgr_timings,
2299 u16 width, u16 height, u16 out_width, u16 out_height,
2300 enum omap_color_mode color_mode, bool *five_taps,
2301 int *x_predecim, int *y_predecim, int *decim_x, int *decim_y,
2302 u16 pos_x, unsigned long *core_clk, bool mem_to_mem)
2303 {
2304 int error;
2305 u16 in_width, in_height;
2306 const int maxsinglelinewidth =
2307 dss_feat_get_param_max(FEAT_PARAM_LINEWIDTH);
2308
2309 do {
2310 in_height = height / *decim_y;
2311 in_width = width / *decim_x;
2312 *five_taps = in_height > out_height;
2313
2314 if (in_width > maxsinglelinewidth)
2315 if (in_height > out_height &&
2316 in_height < out_height * 2)
2317 *five_taps = false;
2318 again:
2319 if (*five_taps)
2320 *core_clk = calc_core_clk_five_taps(pclk, mgr_timings,
2321 in_width, in_height, out_width,
2322 out_height, color_mode);
2323 else
2324 *core_clk = dispc.feat->calc_core_clk(pclk, in_width,
2325 in_height, out_width, out_height,
2326 mem_to_mem);
2327
2328 error = check_horiz_timing_omap3(pclk, lclk, mgr_timings,
2329 pos_x, in_width, in_height, out_width,
2330 out_height, *five_taps);
2331 if (error && *five_taps) {
2332 *five_taps = false;
2333 goto again;
2334 }
2335
2336 error = (error || in_width > maxsinglelinewidth * 2 ||
2337 (in_width > maxsinglelinewidth && *five_taps) ||
2338 !*core_clk || *core_clk > dispc_core_clk_rate());
2339
2340 if (!error) {
2341 /* verify that we're inside the limits of scaler */
2342 if (in_width / 4 > out_width)
2343 error = 1;
2344
2345 if (*five_taps) {
2346 if (in_height / 4 > out_height)
2347 error = 1;
2348 } else {
2349 if (in_height / 2 > out_height)
2350 error = 1;
2351 }
2352 }
2353
2354 if (error)
2355 ++*decim_y;
2356 } while (*decim_x <= *x_predecim && *decim_y <= *y_predecim && error);
2357
2358 if (error) {
2359 DSSERR("failed to find scaling settings\n");
2360 return -EINVAL;
2361 }
2362
2363 if (check_horiz_timing_omap3(pclk, lclk, mgr_timings, pos_x, in_width,
2364 in_height, out_width, out_height, *five_taps)) {
2365 DSSERR("horizontal timing too tight\n");
2366 return -EINVAL;
2367 }
2368
2369 if (in_width > (maxsinglelinewidth * 2)) {
2370 DSSERR("Cannot setup scaling");
2371 DSSERR("width exceeds maximum width possible");
2372 return -EINVAL;
2373 }
2374
2375 if (in_width > maxsinglelinewidth && *five_taps) {
2376 DSSERR("cannot setup scaling with five taps");
2377 return -EINVAL;
2378 }
2379 return 0;
2380 }
2381
2382 static int dispc_ovl_calc_scaling_44xx(unsigned long pclk, unsigned long lclk,
2383 const struct omap_video_timings *mgr_timings,
2384 u16 width, u16 height, u16 out_width, u16 out_height,
2385 enum omap_color_mode color_mode, bool *five_taps,
2386 int *x_predecim, int *y_predecim, int *decim_x, int *decim_y,
2387 u16 pos_x, unsigned long *core_clk, bool mem_to_mem)
2388 {
2389 u16 in_width, in_width_max;
2390 int decim_x_min = *decim_x;
2391 u16 in_height = height / *decim_y;
2392 const int maxsinglelinewidth =
2393 dss_feat_get_param_max(FEAT_PARAM_LINEWIDTH);
2394 const int maxdownscale = dss_feat_get_param_max(FEAT_PARAM_DOWNSCALE);
2395
2396 if (mem_to_mem) {
2397 in_width_max = out_width * maxdownscale;
2398 } else {
2399 in_width_max = dispc_core_clk_rate() /
2400 DIV_ROUND_UP(pclk, out_width);
2401 }
2402
2403 *decim_x = DIV_ROUND_UP(width, in_width_max);
2404
2405 *decim_x = *decim_x > decim_x_min ? *decim_x : decim_x_min;
2406 if (*decim_x > *x_predecim)
2407 return -EINVAL;
2408
2409 do {
2410 in_width = width / *decim_x;
2411 } while (*decim_x <= *x_predecim &&
2412 in_width > maxsinglelinewidth && ++*decim_x);
2413
2414 if (in_width > maxsinglelinewidth) {
2415 DSSERR("Cannot scale width exceeds max line width");
2416 return -EINVAL;
2417 }
2418
2419 *core_clk = dispc.feat->calc_core_clk(pclk, in_width, in_height,
2420 out_width, out_height, mem_to_mem);
2421 return 0;
2422 }
2423
2424 #define DIV_FRAC(dividend, divisor) \
2425 ((dividend) * 100 / (divisor) - ((dividend) / (divisor) * 100))
2426
2427 static int dispc_ovl_calc_scaling(unsigned long pclk, unsigned long lclk,
2428 enum omap_overlay_caps caps,
2429 const struct omap_video_timings *mgr_timings,
2430 u16 width, u16 height, u16 out_width, u16 out_height,
2431 enum omap_color_mode color_mode, bool *five_taps,
2432 int *x_predecim, int *y_predecim, u16 pos_x,
2433 enum omap_dss_rotation_type rotation_type, bool mem_to_mem)
2434 {
2435 const int maxdownscale = dss_feat_get_param_max(FEAT_PARAM_DOWNSCALE);
2436 const int max_decim_limit = 16;
2437 unsigned long core_clk = 0;
2438 int decim_x, decim_y, ret;
2439
2440 if (width == out_width && height == out_height)
2441 return 0;
2442
2443 if (!mem_to_mem && (pclk == 0 || mgr_timings->pixelclock == 0)) {
2444 DSSERR("cannot calculate scaling settings: pclk is zero\n");
2445 return -EINVAL;
2446 }
2447
2448 if ((caps & OMAP_DSS_OVL_CAP_SCALE) == 0)
2449 return -EINVAL;
2450
2451 if (mem_to_mem) {
2452 *x_predecim = *y_predecim = 1;
2453 } else {
2454 *x_predecim = max_decim_limit;
2455 *y_predecim = (rotation_type == OMAP_DSS_ROT_TILER &&
2456 dss_has_feature(FEAT_BURST_2D)) ?
2457 2 : max_decim_limit;
2458 }
2459
2460 if (color_mode == OMAP_DSS_COLOR_CLUT1 ||
2461 color_mode == OMAP_DSS_COLOR_CLUT2 ||
2462 color_mode == OMAP_DSS_COLOR_CLUT4 ||
2463 color_mode == OMAP_DSS_COLOR_CLUT8) {
2464 *x_predecim = 1;
2465 *y_predecim = 1;
2466 *five_taps = false;
2467 return 0;
2468 }
2469
2470 decim_x = DIV_ROUND_UP(DIV_ROUND_UP(width, out_width), maxdownscale);
2471 decim_y = DIV_ROUND_UP(DIV_ROUND_UP(height, out_height), maxdownscale);
2472
2473 if (decim_x > *x_predecim || out_width > width * 8)
2474 return -EINVAL;
2475
2476 if (decim_y > *y_predecim || out_height > height * 8)
2477 return -EINVAL;
2478
2479 ret = dispc.feat->calc_scaling(pclk, lclk, mgr_timings, width, height,
2480 out_width, out_height, color_mode, five_taps,
2481 x_predecim, y_predecim, &decim_x, &decim_y, pos_x, &core_clk,
2482 mem_to_mem);
2483 if (ret)
2484 return ret;
2485
2486 DSSDBG("%dx%d -> %dx%d (%d.%02d x %d.%02d), decim %dx%d %dx%d (%d.%02d x %d.%02d), taps %d, req clk %lu, cur clk %lu\n",
2487 width, height,
2488 out_width, out_height,
2489 out_width / width, DIV_FRAC(out_width, width),
2490 out_height / height, DIV_FRAC(out_height, height),
2491
2492 decim_x, decim_y,
2493 width / decim_x, height / decim_y,
2494 out_width / (width / decim_x), DIV_FRAC(out_width, width / decim_x),
2495 out_height / (height / decim_y), DIV_FRAC(out_height, height / decim_y),
2496
2497 *five_taps ? 5 : 3,
2498 core_clk, dispc_core_clk_rate());
2499
2500 if (!core_clk || core_clk > dispc_core_clk_rate()) {
2501 DSSERR("failed to set up scaling, "
2502 "required core clk rate = %lu Hz, "
2503 "current core clk rate = %lu Hz\n",
2504 core_clk, dispc_core_clk_rate());
2505 return -EINVAL;
2506 }
2507
2508 *x_predecim = decim_x;
2509 *y_predecim = decim_y;
2510 return 0;
2511 }
2512
2513 int dispc_ovl_check(enum omap_plane plane, enum omap_channel channel,
2514 const struct omap_overlay_info *oi,
2515 const struct omap_video_timings *timings,
2516 int *x_predecim, int *y_predecim)
2517 {
2518 enum omap_overlay_caps caps = dss_feat_get_overlay_caps(plane);
2519 bool five_taps = true;
2520 bool fieldmode = false;
2521 u16 in_height = oi->height;
2522 u16 in_width = oi->width;
2523 bool ilace = timings->interlace;
2524 u16 out_width, out_height;
2525 int pos_x = oi->pos_x;
2526 unsigned long pclk = dispc_mgr_pclk_rate(channel);
2527 unsigned long lclk = dispc_mgr_lclk_rate(channel);
2528
2529 out_width = oi->out_width == 0 ? oi->width : oi->out_width;
2530 out_height = oi->out_height == 0 ? oi->height : oi->out_height;
2531
2532 if (ilace && oi->height == out_height)
2533 fieldmode = true;
2534
2535 if (ilace) {
2536 if (fieldmode)
2537 in_height /= 2;
2538 out_height /= 2;
2539
2540 DSSDBG("adjusting for ilace: height %d, out_height %d\n",
2541 in_height, out_height);
2542 }
2543
2544 if (!dss_feat_color_mode_supported(plane, oi->color_mode))
2545 return -EINVAL;
2546
2547 return dispc_ovl_calc_scaling(pclk, lclk, caps, timings, in_width,
2548 in_height, out_width, out_height, oi->color_mode,
2549 &five_taps, x_predecim, y_predecim, pos_x,
2550 oi->rotation_type, false);
2551 }
2552 EXPORT_SYMBOL(dispc_ovl_check);
2553
2554 static int dispc_ovl_setup_common(enum omap_plane plane,
2555 enum omap_overlay_caps caps, u32 paddr, u32 p_uv_addr,
2556 u16 screen_width, int pos_x, int pos_y, u16 width, u16 height,
2557 u16 out_width, u16 out_height, enum omap_color_mode color_mode,
2558 u8 rotation, bool mirror, u8 zorder, u8 pre_mult_alpha,
2559 u8 global_alpha, enum omap_dss_rotation_type rotation_type,
2560 bool replication, const struct omap_video_timings *mgr_timings,
2561 bool mem_to_mem)
2562 {
2563 bool five_taps = true;
2564 bool fieldmode = false;
2565 int r, cconv = 0;
2566 unsigned offset0, offset1;
2567 s32 row_inc;
2568 s32 pix_inc;
2569 u16 frame_width, frame_height;
2570 unsigned int field_offset = 0;
2571 u16 in_height = height;
2572 u16 in_width = width;
2573 int x_predecim = 1, y_predecim = 1;
2574 bool ilace = mgr_timings->interlace;
2575 unsigned long pclk = dispc_plane_pclk_rate(plane);
2576 unsigned long lclk = dispc_plane_lclk_rate(plane);
2577
2578 if (paddr == 0 && rotation_type != OMAP_DSS_ROT_TILER)
2579 return -EINVAL;
2580
2581 switch (color_mode) {
2582 case OMAP_DSS_COLOR_YUV2:
2583 case OMAP_DSS_COLOR_UYVY:
2584 case OMAP_DSS_COLOR_NV12:
2585 if (in_width & 1) {
2586 DSSERR("input width %d is not even for YUV format\n",
2587 in_width);
2588 return -EINVAL;
2589 }
2590 break;
2591
2592 default:
2593 break;
2594 }
2595
2596 out_width = out_width == 0 ? width : out_width;
2597 out_height = out_height == 0 ? height : out_height;
2598
2599 if (ilace && height == out_height)
2600 fieldmode = true;
2601
2602 if (ilace) {
2603 if (fieldmode)
2604 in_height /= 2;
2605 pos_y /= 2;
2606 out_height /= 2;
2607
2608 DSSDBG("adjusting for ilace: height %d, pos_y %d, "
2609 "out_height %d\n", in_height, pos_y,
2610 out_height);
2611 }
2612
2613 if (!dss_feat_color_mode_supported(plane, color_mode))
2614 return -EINVAL;
2615
2616 r = dispc_ovl_calc_scaling(pclk, lclk, caps, mgr_timings, in_width,
2617 in_height, out_width, out_height, color_mode,
2618 &five_taps, &x_predecim, &y_predecim, pos_x,
2619 rotation_type, mem_to_mem);
2620 if (r)
2621 return r;
2622
2623 in_width = in_width / x_predecim;
2624 in_height = in_height / y_predecim;
2625
2626 if (x_predecim > 1 || y_predecim > 1)
2627 DSSDBG("predecimation %d x %x, new input size %d x %d\n",
2628 x_predecim, y_predecim, in_width, in_height);
2629
2630 switch (color_mode) {
2631 case OMAP_DSS_COLOR_YUV2:
2632 case OMAP_DSS_COLOR_UYVY:
2633 case OMAP_DSS_COLOR_NV12:
2634 if (in_width & 1) {
2635 DSSDBG("predecimated input width is not even for YUV format\n");
2636 DSSDBG("adjusting input width %d -> %d\n",
2637 in_width, in_width & ~1);
2638
2639 in_width &= ~1;
2640 }
2641 break;
2642
2643 default:
2644 break;
2645 }
2646
2647 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
2648 color_mode == OMAP_DSS_COLOR_UYVY ||
2649 color_mode == OMAP_DSS_COLOR_NV12)
2650 cconv = 1;
2651
2652 if (ilace && !fieldmode) {
2653 /*
2654 * when downscaling the bottom field may have to start several
2655 * source lines below the top field. Unfortunately ACCUI
2656 * registers will only hold the fractional part of the offset
2657 * so the integer part must be added to the base address of the
2658 * bottom field.
2659 */
2660 if (!in_height || in_height == out_height)
2661 field_offset = 0;
2662 else
2663 field_offset = in_height / out_height / 2;
2664 }
2665
2666 /* Fields are independent but interleaved in memory. */
2667 if (fieldmode)
2668 field_offset = 1;
2669
2670 offset0 = 0;
2671 offset1 = 0;
2672 row_inc = 0;
2673 pix_inc = 0;
2674
2675 if (plane == OMAP_DSS_WB) {
2676 frame_width = out_width;
2677 frame_height = out_height;
2678 } else {
2679 frame_width = in_width;
2680 frame_height = height;
2681 }
2682
2683 if (rotation_type == OMAP_DSS_ROT_TILER)
2684 calc_tiler_rotation_offset(screen_width, frame_width,
2685 color_mode, fieldmode, field_offset,
2686 &offset0, &offset1, &row_inc, &pix_inc,
2687 x_predecim, y_predecim);
2688 else if (rotation_type == OMAP_DSS_ROT_DMA)
2689 calc_dma_rotation_offset(rotation, mirror, screen_width,
2690 frame_width, frame_height,
2691 color_mode, fieldmode, field_offset,
2692 &offset0, &offset1, &row_inc, &pix_inc,
2693 x_predecim, y_predecim);
2694 else
2695 calc_vrfb_rotation_offset(rotation, mirror,
2696 screen_width, frame_width, frame_height,
2697 color_mode, fieldmode, field_offset,
2698 &offset0, &offset1, &row_inc, &pix_inc,
2699 x_predecim, y_predecim);
2700
2701 DSSDBG("offset0 %u, offset1 %u, row_inc %d, pix_inc %d\n",
2702 offset0, offset1, row_inc, pix_inc);
2703
2704 dispc_ovl_set_color_mode(plane, color_mode);
2705
2706 dispc_ovl_configure_burst_type(plane, rotation_type);
2707
2708 dispc_ovl_set_ba0(plane, paddr + offset0);
2709 dispc_ovl_set_ba1(plane, paddr + offset1);
2710
2711 if (OMAP_DSS_COLOR_NV12 == color_mode) {
2712 dispc_ovl_set_ba0_uv(plane, p_uv_addr + offset0);
2713 dispc_ovl_set_ba1_uv(plane, p_uv_addr + offset1);
2714 }
2715
2716 if (dispc.feat->last_pixel_inc_missing)
2717 row_inc += pix_inc - 1;
2718
2719 dispc_ovl_set_row_inc(plane, row_inc);
2720 dispc_ovl_set_pix_inc(plane, pix_inc);
2721
2722 DSSDBG("%d,%d %dx%d -> %dx%d\n", pos_x, pos_y, in_width,
2723 in_height, out_width, out_height);
2724
2725 dispc_ovl_set_pos(plane, caps, pos_x, pos_y);
2726
2727 dispc_ovl_set_input_size(plane, in_width, in_height);
2728
2729 if (caps & OMAP_DSS_OVL_CAP_SCALE) {
2730 dispc_ovl_set_scaling(plane, in_width, in_height, out_width,
2731 out_height, ilace, five_taps, fieldmode,
2732 color_mode, rotation);
2733 dispc_ovl_set_output_size(plane, out_width, out_height);
2734 dispc_ovl_set_vid_color_conv(plane, cconv);
2735 }
2736
2737 dispc_ovl_set_rotation_attrs(plane, rotation, rotation_type, mirror,
2738 color_mode);
2739
2740 dispc_ovl_set_zorder(plane, caps, zorder);
2741 dispc_ovl_set_pre_mult_alpha(plane, caps, pre_mult_alpha);
2742 dispc_ovl_setup_global_alpha(plane, caps, global_alpha);
2743
2744 dispc_ovl_enable_replication(plane, caps, replication);
2745
2746 return 0;
2747 }
2748
2749 int dispc_ovl_setup(enum omap_plane plane, const struct omap_overlay_info *oi,
2750 bool replication, const struct omap_video_timings *mgr_timings,
2751 bool mem_to_mem)
2752 {
2753 int r;
2754 enum omap_overlay_caps caps = dss_feat_get_overlay_caps(plane);
2755 enum omap_channel channel;
2756
2757 channel = dispc_ovl_get_channel_out(plane);
2758
2759 DSSDBG("dispc_ovl_setup %d, pa %pad, pa_uv %pad, sw %d, %d,%d, %dx%d ->"
2760 " %dx%d, cmode %x, rot %d, mir %d, chan %d repl %d\n",
2761 plane, &oi->paddr, &oi->p_uv_addr, oi->screen_width, oi->pos_x,
2762 oi->pos_y, oi->width, oi->height, oi->out_width, oi->out_height,
2763 oi->color_mode, oi->rotation, oi->mirror, channel, replication);
2764
2765 r = dispc_ovl_setup_common(plane, caps, oi->paddr, oi->p_uv_addr,
2766 oi->screen_width, oi->pos_x, oi->pos_y, oi->width, oi->height,
2767 oi->out_width, oi->out_height, oi->color_mode, oi->rotation,
2768 oi->mirror, oi->zorder, oi->pre_mult_alpha, oi->global_alpha,
2769 oi->rotation_type, replication, mgr_timings, mem_to_mem);
2770
2771 return r;
2772 }
2773 EXPORT_SYMBOL(dispc_ovl_setup);
2774
2775 int dispc_ovl_enable(enum omap_plane plane, bool enable)
2776 {
2777 DSSDBG("dispc_enable_plane %d, %d\n", plane, enable);
2778
2779 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 0, 0);
2780
2781 return 0;
2782 }
2783 EXPORT_SYMBOL(dispc_ovl_enable);
2784
2785 bool dispc_ovl_enabled(enum omap_plane plane)
2786 {
2787 return REG_GET(DISPC_OVL_ATTRIBUTES(plane), 0, 0);
2788 }
2789 EXPORT_SYMBOL(dispc_ovl_enabled);
2790
2791 void dispc_mgr_enable(enum omap_channel channel, bool enable)
2792 {
2793 mgr_fld_write(channel, DISPC_MGR_FLD_ENABLE, enable);
2794 /* flush posted write */
2795 mgr_fld_read(channel, DISPC_MGR_FLD_ENABLE);
2796 }
2797 EXPORT_SYMBOL(dispc_mgr_enable);
2798
2799 bool dispc_mgr_is_enabled(enum omap_channel channel)
2800 {
2801 return !!mgr_fld_read(channel, DISPC_MGR_FLD_ENABLE);
2802 }
2803 EXPORT_SYMBOL(dispc_mgr_is_enabled);
2804
2805 static void dispc_lcd_enable_signal_polarity(bool act_high)
2806 {
2807 if (!dss_has_feature(FEAT_LCDENABLEPOL))
2808 return;
2809
2810 REG_FLD_MOD(DISPC_CONTROL, act_high ? 1 : 0, 29, 29);
2811 }
2812
2813 void dispc_lcd_enable_signal(bool enable)
2814 {
2815 if (!dss_has_feature(FEAT_LCDENABLESIGNAL))
2816 return;
2817
2818 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 28, 28);
2819 }
2820
2821 void dispc_pck_free_enable(bool enable)
2822 {
2823 if (!dss_has_feature(FEAT_PCKFREEENABLE))
2824 return;
2825
2826 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 27, 27);
2827 }
2828
2829 static void dispc_mgr_enable_fifohandcheck(enum omap_channel channel, bool enable)
2830 {
2831 mgr_fld_write(channel, DISPC_MGR_FLD_FIFOHANDCHECK, enable);
2832 }
2833
2834
2835 static void dispc_mgr_set_lcd_type_tft(enum omap_channel channel)
2836 {
2837 mgr_fld_write(channel, DISPC_MGR_FLD_STNTFT, 1);
2838 }
2839
2840 static void dispc_set_loadmode(enum omap_dss_load_mode mode)
2841 {
2842 REG_FLD_MOD(DISPC_CONFIG, mode, 2, 1);
2843 }
2844
2845
2846 static void dispc_mgr_set_default_color(enum omap_channel channel, u32 color)
2847 {
2848 dispc_write_reg(DISPC_DEFAULT_COLOR(channel), color);
2849 }
2850
2851 static void dispc_mgr_set_trans_key(enum omap_channel ch,
2852 enum omap_dss_trans_key_type type,
2853 u32 trans_key)
2854 {
2855 mgr_fld_write(ch, DISPC_MGR_FLD_TCKSELECTION, type);
2856
2857 dispc_write_reg(DISPC_TRANS_COLOR(ch), trans_key);
2858 }
2859
2860 static void dispc_mgr_enable_trans_key(enum omap_channel ch, bool enable)
2861 {
2862 mgr_fld_write(ch, DISPC_MGR_FLD_TCKENABLE, enable);
2863 }
2864
2865 static void dispc_mgr_enable_alpha_fixed_zorder(enum omap_channel ch,
2866 bool enable)
2867 {
2868 if (!dss_has_feature(FEAT_ALPHA_FIXED_ZORDER))
2869 return;
2870
2871 if (ch == OMAP_DSS_CHANNEL_LCD)
2872 REG_FLD_MOD(DISPC_CONFIG, enable, 18, 18);
2873 else if (ch == OMAP_DSS_CHANNEL_DIGIT)
2874 REG_FLD_MOD(DISPC_CONFIG, enable, 19, 19);
2875 }
2876
2877 void dispc_mgr_setup(enum omap_channel channel,
2878 const struct omap_overlay_manager_info *info)
2879 {
2880 dispc_mgr_set_default_color(channel, info->default_color);
2881 dispc_mgr_set_trans_key(channel, info->trans_key_type, info->trans_key);
2882 dispc_mgr_enable_trans_key(channel, info->trans_enabled);
2883 dispc_mgr_enable_alpha_fixed_zorder(channel,
2884 info->partial_alpha_enabled);
2885 if (dss_has_feature(FEAT_CPR)) {
2886 dispc_mgr_enable_cpr(channel, info->cpr_enable);
2887 dispc_mgr_set_cpr_coef(channel, &info->cpr_coefs);
2888 }
2889 }
2890 EXPORT_SYMBOL(dispc_mgr_setup);
2891
2892 static void dispc_mgr_set_tft_data_lines(enum omap_channel channel, u8 data_lines)
2893 {
2894 int code;
2895
2896 switch (data_lines) {
2897 case 12:
2898 code = 0;
2899 break;
2900 case 16:
2901 code = 1;
2902 break;
2903 case 18:
2904 code = 2;
2905 break;
2906 case 24:
2907 code = 3;
2908 break;
2909 default:
2910 BUG();
2911 return;
2912 }
2913
2914 mgr_fld_write(channel, DISPC_MGR_FLD_TFTDATALINES, code);
2915 }
2916
2917 static void dispc_mgr_set_io_pad_mode(enum dss_io_pad_mode mode)
2918 {
2919 u32 l;
2920 int gpout0, gpout1;
2921
2922 switch (mode) {
2923 case DSS_IO_PAD_MODE_RESET:
2924 gpout0 = 0;
2925 gpout1 = 0;
2926 break;
2927 case DSS_IO_PAD_MODE_RFBI:
2928 gpout0 = 1;
2929 gpout1 = 0;
2930 break;
2931 case DSS_IO_PAD_MODE_BYPASS:
2932 gpout0 = 1;
2933 gpout1 = 1;
2934 break;
2935 default:
2936 BUG();
2937 return;
2938 }
2939
2940 l = dispc_read_reg(DISPC_CONTROL);
2941 l = FLD_MOD(l, gpout0, 15, 15);
2942 l = FLD_MOD(l, gpout1, 16, 16);
2943 dispc_write_reg(DISPC_CONTROL, l);
2944 }
2945
2946 static void dispc_mgr_enable_stallmode(enum omap_channel channel, bool enable)
2947 {
2948 mgr_fld_write(channel, DISPC_MGR_FLD_STALLMODE, enable);
2949 }
2950
2951 void dispc_mgr_set_lcd_config(enum omap_channel channel,
2952 const struct dss_lcd_mgr_config *config)
2953 {
2954 dispc_mgr_set_io_pad_mode(config->io_pad_mode);
2955
2956 dispc_mgr_enable_stallmode(channel, config->stallmode);
2957 dispc_mgr_enable_fifohandcheck(channel, config->fifohandcheck);
2958
2959 dispc_mgr_set_clock_div(channel, &config->clock_info);
2960
2961 dispc_mgr_set_tft_data_lines(channel, config->video_port_width);
2962
2963 dispc_lcd_enable_signal_polarity(config->lcden_sig_polarity);
2964
2965 dispc_mgr_set_lcd_type_tft(channel);
2966 }
2967 EXPORT_SYMBOL(dispc_mgr_set_lcd_config);
2968
2969 static bool _dispc_mgr_size_ok(u16 width, u16 height)
2970 {
2971 return width <= dispc.feat->mgr_width_max &&
2972 height <= dispc.feat->mgr_height_max;
2973 }
2974
2975 static bool _dispc_lcd_timings_ok(int hsw, int hfp, int hbp,
2976 int vsw, int vfp, int vbp)
2977 {
2978 if (hsw < 1 || hsw > dispc.feat->sw_max ||
2979 hfp < 1 || hfp > dispc.feat->hp_max ||
2980 hbp < 1 || hbp > dispc.feat->hp_max ||
2981 vsw < 1 || vsw > dispc.feat->sw_max ||
2982 vfp < 0 || vfp > dispc.feat->vp_max ||
2983 vbp < 0 || vbp > dispc.feat->vp_max)
2984 return false;
2985 return true;
2986 }
2987
2988 static bool _dispc_mgr_pclk_ok(enum omap_channel channel,
2989 unsigned long pclk)
2990 {
2991 if (dss_mgr_is_lcd(channel))
2992 return pclk <= dispc.feat->max_lcd_pclk;
2993 else
2994 return pclk <= dispc.feat->max_tv_pclk;
2995 }
2996
2997 bool dispc_mgr_timings_ok(enum omap_channel channel,
2998 const struct omap_video_timings *timings)
2999 {
3000 if (!_dispc_mgr_size_ok(timings->x_res, timings->y_res))
3001 return false;
3002
3003 if (!_dispc_mgr_pclk_ok(channel, timings->pixelclock))
3004 return false;
3005
3006 if (dss_mgr_is_lcd(channel)) {
3007 /* TODO: OMAP4+ supports interlace for LCD outputs */
3008 if (timings->interlace)
3009 return false;
3010
3011 if (!_dispc_lcd_timings_ok(timings->hsw, timings->hfp,
3012 timings->hbp, timings->vsw, timings->vfp,
3013 timings->vbp))
3014 return false;
3015 }
3016
3017 return true;
3018 }
3019
3020 static void _dispc_mgr_set_lcd_timings(enum omap_channel channel, int hsw,
3021 int hfp, int hbp, int vsw, int vfp, int vbp,
3022 enum omap_dss_signal_level vsync_level,
3023 enum omap_dss_signal_level hsync_level,
3024 enum omap_dss_signal_edge data_pclk_edge,
3025 enum omap_dss_signal_level de_level,
3026 enum omap_dss_signal_edge sync_pclk_edge)
3027
3028 {
3029 u32 timing_h, timing_v, l;
3030 bool onoff, rf, ipc, vs, hs, de;
3031
3032 timing_h = FLD_VAL(hsw-1, dispc.feat->sw_start, 0) |
3033 FLD_VAL(hfp-1, dispc.feat->fp_start, 8) |
3034 FLD_VAL(hbp-1, dispc.feat->bp_start, 20);
3035 timing_v = FLD_VAL(vsw-1, dispc.feat->sw_start, 0) |
3036 FLD_VAL(vfp, dispc.feat->fp_start, 8) |
3037 FLD_VAL(vbp, dispc.feat->bp_start, 20);
3038
3039 dispc_write_reg(DISPC_TIMING_H(channel), timing_h);
3040 dispc_write_reg(DISPC_TIMING_V(channel), timing_v);
3041
3042 switch (vsync_level) {
3043 case OMAPDSS_SIG_ACTIVE_LOW:
3044 vs = true;
3045 break;
3046 case OMAPDSS_SIG_ACTIVE_HIGH:
3047 vs = false;
3048 break;
3049 default:
3050 BUG();
3051 }
3052
3053 switch (hsync_level) {
3054 case OMAPDSS_SIG_ACTIVE_LOW:
3055 hs = true;
3056 break;
3057 case OMAPDSS_SIG_ACTIVE_HIGH:
3058 hs = false;
3059 break;
3060 default:
3061 BUG();
3062 }
3063
3064 switch (de_level) {
3065 case OMAPDSS_SIG_ACTIVE_LOW:
3066 de = true;
3067 break;
3068 case OMAPDSS_SIG_ACTIVE_HIGH:
3069 de = false;
3070 break;
3071 default:
3072 BUG();
3073 }
3074
3075 switch (data_pclk_edge) {
3076 case OMAPDSS_DRIVE_SIG_RISING_EDGE:
3077 ipc = false;
3078 break;
3079 case OMAPDSS_DRIVE_SIG_FALLING_EDGE:
3080 ipc = true;
3081 break;
3082 default:
3083 BUG();
3084 }
3085
3086 /* always use the 'rf' setting */
3087 onoff = true;
3088
3089 switch (sync_pclk_edge) {
3090 case OMAPDSS_DRIVE_SIG_FALLING_EDGE:
3091 rf = false;
3092 break;
3093 case OMAPDSS_DRIVE_SIG_RISING_EDGE:
3094 rf = true;
3095 break;
3096 default:
3097 BUG();
3098 }
3099
3100 l = FLD_VAL(onoff, 17, 17) |
3101 FLD_VAL(rf, 16, 16) |
3102 FLD_VAL(de, 15, 15) |
3103 FLD_VAL(ipc, 14, 14) |
3104 FLD_VAL(hs, 13, 13) |
3105 FLD_VAL(vs, 12, 12);
3106
3107 /* always set ALIGN bit when available */
3108 if (dispc.feat->supports_sync_align)
3109 l |= (1 << 18);
3110
3111 dispc_write_reg(DISPC_POL_FREQ(channel), l);
3112
3113 if (dispc.syscon_pol) {
3114 const int shifts[] = {
3115 [OMAP_DSS_CHANNEL_LCD] = 0,
3116 [OMAP_DSS_CHANNEL_LCD2] = 1,
3117 [OMAP_DSS_CHANNEL_LCD3] = 2,
3118 };
3119
3120 u32 mask, val;
3121
3122 mask = (1 << 0) | (1 << 3) | (1 << 6);
3123 val = (rf << 0) | (ipc << 3) | (onoff << 6);
3124
3125 mask <<= 16 + shifts[channel];
3126 val <<= 16 + shifts[channel];
3127
3128 regmap_update_bits(dispc.syscon_pol, dispc.syscon_pol_offset,
3129 mask, val);
3130 }
3131 }
3132
3133 /* change name to mode? */
3134 void dispc_mgr_set_timings(enum omap_channel channel,
3135 const struct omap_video_timings *timings)
3136 {
3137 unsigned xtot, ytot;
3138 unsigned long ht, vt;
3139 struct omap_video_timings t = *timings;
3140
3141 DSSDBG("channel %d xres %u yres %u\n", channel, t.x_res, t.y_res);
3142
3143 if (!dispc_mgr_timings_ok(channel, &t)) {
3144 BUG();
3145 return;
3146 }
3147
3148 if (dss_mgr_is_lcd(channel)) {
3149 _dispc_mgr_set_lcd_timings(channel, t.hsw, t.hfp, t.hbp, t.vsw,
3150 t.vfp, t.vbp, t.vsync_level, t.hsync_level,
3151 t.data_pclk_edge, t.de_level, t.sync_pclk_edge);
3152
3153 xtot = t.x_res + t.hfp + t.hsw + t.hbp;
3154 ytot = t.y_res + t.vfp + t.vsw + t.vbp;
3155
3156 ht = timings->pixelclock / xtot;
3157 vt = timings->pixelclock / xtot / ytot;
3158
3159 DSSDBG("pck %u\n", timings->pixelclock);
3160 DSSDBG("hsw %d hfp %d hbp %d vsw %d vfp %d vbp %d\n",
3161 t.hsw, t.hfp, t.hbp, t.vsw, t.vfp, t.vbp);
3162 DSSDBG("vsync_level %d hsync_level %d data_pclk_edge %d de_level %d sync_pclk_edge %d\n",
3163 t.vsync_level, t.hsync_level, t.data_pclk_edge,
3164 t.de_level, t.sync_pclk_edge);
3165
3166 DSSDBG("hsync %luHz, vsync %luHz\n", ht, vt);
3167 } else {
3168 if (t.interlace)
3169 t.y_res /= 2;
3170 }
3171
3172 dispc_mgr_set_size(channel, t.x_res, t.y_res);
3173 }
3174 EXPORT_SYMBOL(dispc_mgr_set_timings);
3175
3176 static void dispc_mgr_set_lcd_divisor(enum omap_channel channel, u16 lck_div,
3177 u16 pck_div)
3178 {
3179 BUG_ON(lck_div < 1);
3180 BUG_ON(pck_div < 1);
3181
3182 dispc_write_reg(DISPC_DIVISORo(channel),
3183 FLD_VAL(lck_div, 23, 16) | FLD_VAL(pck_div, 7, 0));
3184
3185 if (!dss_has_feature(FEAT_CORE_CLK_DIV) &&
3186 channel == OMAP_DSS_CHANNEL_LCD)
3187 dispc.core_clk_rate = dispc_fclk_rate() / lck_div;
3188 }
3189
3190 static void dispc_mgr_get_lcd_divisor(enum omap_channel channel, int *lck_div,
3191 int *pck_div)
3192 {
3193 u32 l;
3194 l = dispc_read_reg(DISPC_DIVISORo(channel));
3195 *lck_div = FLD_GET(l, 23, 16);
3196 *pck_div = FLD_GET(l, 7, 0);
3197 }
3198
3199 static unsigned long dispc_fclk_rate(void)
3200 {
3201 struct dss_pll *pll;
3202 unsigned long r = 0;
3203
3204 switch (dss_get_dispc_clk_source()) {
3205 case OMAP_DSS_CLK_SRC_FCK:
3206 r = dss_get_dispc_clk_rate();
3207 break;
3208 case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC:
3209 pll = dss_pll_find("dsi0");
3210 if (!pll)
3211 pll = dss_pll_find("video0");
3212
3213 r = pll->cinfo.clkout[0];
3214 break;
3215 case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC:
3216 pll = dss_pll_find("dsi1");
3217 if (!pll)
3218 pll = dss_pll_find("video1");
3219
3220 r = pll->cinfo.clkout[0];
3221 break;
3222 default:
3223 BUG();
3224 return 0;
3225 }
3226
3227 return r;
3228 }
3229
3230 static unsigned long dispc_mgr_lclk_rate(enum omap_channel channel)
3231 {
3232 struct dss_pll *pll;
3233 int lcd;
3234 unsigned long r;
3235 u32 l;
3236
3237 if (dss_mgr_is_lcd(channel)) {
3238 l = dispc_read_reg(DISPC_DIVISORo(channel));
3239
3240 lcd = FLD_GET(l, 23, 16);
3241
3242 switch (dss_get_lcd_clk_source(channel)) {
3243 case OMAP_DSS_CLK_SRC_FCK:
3244 r = dss_get_dispc_clk_rate();
3245 break;
3246 case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC:
3247 pll = dss_pll_find("dsi0");
3248 if (!pll)
3249 pll = dss_pll_find("video0");
3250
3251 r = pll->cinfo.clkout[0];
3252 break;
3253 case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC:
3254 pll = dss_pll_find("dsi1");
3255 if (!pll)
3256 pll = dss_pll_find("video1");
3257
3258 r = pll->cinfo.clkout[0];
3259 break;
3260 default:
3261 BUG();
3262 return 0;
3263 }
3264
3265 return r / lcd;
3266 } else {
3267 return dispc_fclk_rate();
3268 }
3269 }
3270
3271 static unsigned long dispc_mgr_pclk_rate(enum omap_channel channel)
3272 {
3273 unsigned long r;
3274
3275 if (dss_mgr_is_lcd(channel)) {
3276 int pcd;
3277 u32 l;
3278
3279 l = dispc_read_reg(DISPC_DIVISORo(channel));
3280
3281 pcd = FLD_GET(l, 7, 0);
3282
3283 r = dispc_mgr_lclk_rate(channel);
3284
3285 return r / pcd;
3286 } else {
3287 return dispc.tv_pclk_rate;
3288 }
3289 }
3290
3291 void dispc_set_tv_pclk(unsigned long pclk)
3292 {
3293 dispc.tv_pclk_rate = pclk;
3294 }
3295
3296 static unsigned long dispc_core_clk_rate(void)
3297 {
3298 return dispc.core_clk_rate;
3299 }
3300
3301 static unsigned long dispc_plane_pclk_rate(enum omap_plane plane)
3302 {
3303 enum omap_channel channel;
3304
3305 if (plane == OMAP_DSS_WB)
3306 return 0;
3307
3308 channel = dispc_ovl_get_channel_out(plane);
3309
3310 return dispc_mgr_pclk_rate(channel);
3311 }
3312
3313 static unsigned long dispc_plane_lclk_rate(enum omap_plane plane)
3314 {
3315 enum omap_channel channel;
3316
3317 if (plane == OMAP_DSS_WB)
3318 return 0;
3319
3320 channel = dispc_ovl_get_channel_out(plane);
3321
3322 return dispc_mgr_lclk_rate(channel);
3323 }
3324
3325 static void dispc_dump_clocks_channel(struct seq_file *s, enum omap_channel channel)
3326 {
3327 int lcd, pcd;
3328 enum omap_dss_clk_source lcd_clk_src;
3329
3330 seq_printf(s, "- %s -\n", mgr_desc[channel].name);
3331
3332 lcd_clk_src = dss_get_lcd_clk_source(channel);
3333
3334 seq_printf(s, "%s clk source = %s (%s)\n", mgr_desc[channel].name,
3335 dss_get_generic_clk_source_name(lcd_clk_src),
3336 dss_feat_get_clk_source_name(lcd_clk_src));
3337
3338 dispc_mgr_get_lcd_divisor(channel, &lcd, &pcd);
3339
3340 seq_printf(s, "lck\t\t%-16lulck div\t%u\n",
3341 dispc_mgr_lclk_rate(channel), lcd);
3342 seq_printf(s, "pck\t\t%-16lupck div\t%u\n",
3343 dispc_mgr_pclk_rate(channel), pcd);
3344 }
3345
3346 void dispc_dump_clocks(struct seq_file *s)
3347 {
3348 int lcd;
3349 u32 l;
3350 enum omap_dss_clk_source dispc_clk_src = dss_get_dispc_clk_source();
3351
3352 if (dispc_runtime_get())
3353 return;
3354
3355 seq_printf(s, "- DISPC -\n");
3356
3357 seq_printf(s, "dispc fclk source = %s (%s)\n",
3358 dss_get_generic_clk_source_name(dispc_clk_src),
3359 dss_feat_get_clk_source_name(dispc_clk_src));
3360
3361 seq_printf(s, "fck\t\t%-16lu\n", dispc_fclk_rate());
3362
3363 if (dss_has_feature(FEAT_CORE_CLK_DIV)) {
3364 seq_printf(s, "- DISPC-CORE-CLK -\n");
3365 l = dispc_read_reg(DISPC_DIVISOR);
3366 lcd = FLD_GET(l, 23, 16);
3367
3368 seq_printf(s, "lck\t\t%-16lulck div\t%u\n",
3369 (dispc_fclk_rate()/lcd), lcd);
3370 }
3371
3372 dispc_dump_clocks_channel(s, OMAP_DSS_CHANNEL_LCD);
3373
3374 if (dss_has_feature(FEAT_MGR_LCD2))
3375 dispc_dump_clocks_channel(s, OMAP_DSS_CHANNEL_LCD2);
3376 if (dss_has_feature(FEAT_MGR_LCD3))
3377 dispc_dump_clocks_channel(s, OMAP_DSS_CHANNEL_LCD3);
3378
3379 dispc_runtime_put();
3380 }
3381
3382 static void dispc_dump_regs(struct seq_file *s)
3383 {
3384 int i, j;
3385 const char *mgr_names[] = {
3386 [OMAP_DSS_CHANNEL_LCD] = "LCD",
3387 [OMAP_DSS_CHANNEL_DIGIT] = "TV",
3388 [OMAP_DSS_CHANNEL_LCD2] = "LCD2",
3389 [OMAP_DSS_CHANNEL_LCD3] = "LCD3",
3390 };
3391 const char *ovl_names[] = {
3392 [OMAP_DSS_GFX] = "GFX",
3393 [OMAP_DSS_VIDEO1] = "VID1",
3394 [OMAP_DSS_VIDEO2] = "VID2",
3395 [OMAP_DSS_VIDEO3] = "VID3",
3396 [OMAP_DSS_WB] = "WB",
3397 };
3398 const char **p_names;
3399
3400 #define DUMPREG(r) seq_printf(s, "%-50s %08x\n", #r, dispc_read_reg(r))
3401
3402 if (dispc_runtime_get())
3403 return;
3404
3405 /* DISPC common registers */
3406 DUMPREG(DISPC_REVISION);
3407 DUMPREG(DISPC_SYSCONFIG);
3408 DUMPREG(DISPC_SYSSTATUS);
3409 DUMPREG(DISPC_IRQSTATUS);
3410 DUMPREG(DISPC_IRQENABLE);
3411 DUMPREG(DISPC_CONTROL);
3412 DUMPREG(DISPC_CONFIG);
3413 DUMPREG(DISPC_CAPABLE);
3414 DUMPREG(DISPC_LINE_STATUS);
3415 DUMPREG(DISPC_LINE_NUMBER);
3416 if (dss_has_feature(FEAT_ALPHA_FIXED_ZORDER) ||
3417 dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
3418 DUMPREG(DISPC_GLOBAL_ALPHA);
3419 if (dss_has_feature(FEAT_MGR_LCD2)) {
3420 DUMPREG(DISPC_CONTROL2);
3421 DUMPREG(DISPC_CONFIG2);
3422 }
3423 if (dss_has_feature(FEAT_MGR_LCD3)) {
3424 DUMPREG(DISPC_CONTROL3);
3425 DUMPREG(DISPC_CONFIG3);
3426 }
3427 if (dss_has_feature(FEAT_MFLAG))
3428 DUMPREG(DISPC_GLOBAL_MFLAG_ATTRIBUTE);
3429
3430 #undef DUMPREG
3431
3432 #define DISPC_REG(i, name) name(i)
3433 #define DUMPREG(i, r) seq_printf(s, "%s(%s)%*s %08x\n", #r, p_names[i], \
3434 (int)(48 - strlen(#r) - strlen(p_names[i])), " ", \
3435 dispc_read_reg(DISPC_REG(i, r)))
3436
3437 p_names = mgr_names;
3438
3439 /* DISPC channel specific registers */
3440 for (i = 0; i < dss_feat_get_num_mgrs(); i++) {
3441 DUMPREG(i, DISPC_DEFAULT_COLOR);
3442 DUMPREG(i, DISPC_TRANS_COLOR);
3443 DUMPREG(i, DISPC_SIZE_MGR);
3444
3445 if (i == OMAP_DSS_CHANNEL_DIGIT)
3446 continue;
3447
3448 DUMPREG(i, DISPC_TIMING_H);
3449 DUMPREG(i, DISPC_TIMING_V);
3450 DUMPREG(i, DISPC_POL_FREQ);
3451 DUMPREG(i, DISPC_DIVISORo);
3452
3453 DUMPREG(i, DISPC_DATA_CYCLE1);
3454 DUMPREG(i, DISPC_DATA_CYCLE2);
3455 DUMPREG(i, DISPC_DATA_CYCLE3);
3456
3457 if (dss_has_feature(FEAT_CPR)) {
3458 DUMPREG(i, DISPC_CPR_COEF_R);
3459 DUMPREG(i, DISPC_CPR_COEF_G);
3460 DUMPREG(i, DISPC_CPR_COEF_B);
3461 }
3462 }
3463
3464 p_names = ovl_names;
3465
3466 for (i = 0; i < dss_feat_get_num_ovls(); i++) {
3467 DUMPREG(i, DISPC_OVL_BA0);
3468 DUMPREG(i, DISPC_OVL_BA1);
3469 DUMPREG(i, DISPC_OVL_POSITION);
3470 DUMPREG(i, DISPC_OVL_SIZE);
3471 DUMPREG(i, DISPC_OVL_ATTRIBUTES);
3472 DUMPREG(i, DISPC_OVL_FIFO_THRESHOLD);
3473 DUMPREG(i, DISPC_OVL_FIFO_SIZE_STATUS);
3474 DUMPREG(i, DISPC_OVL_ROW_INC);
3475 DUMPREG(i, DISPC_OVL_PIXEL_INC);
3476
3477 if (dss_has_feature(FEAT_PRELOAD))
3478 DUMPREG(i, DISPC_OVL_PRELOAD);
3479 if (dss_has_feature(FEAT_MFLAG))
3480 DUMPREG(i, DISPC_OVL_MFLAG_THRESHOLD);
3481
3482 if (i == OMAP_DSS_GFX) {
3483 DUMPREG(i, DISPC_OVL_WINDOW_SKIP);
3484 DUMPREG(i, DISPC_OVL_TABLE_BA);
3485 continue;
3486 }
3487
3488 DUMPREG(i, DISPC_OVL_FIR);
3489 DUMPREG(i, DISPC_OVL_PICTURE_SIZE);
3490 DUMPREG(i, DISPC_OVL_ACCU0);
3491 DUMPREG(i, DISPC_OVL_ACCU1);
3492 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
3493 DUMPREG(i, DISPC_OVL_BA0_UV);
3494 DUMPREG(i, DISPC_OVL_BA1_UV);
3495 DUMPREG(i, DISPC_OVL_FIR2);
3496 DUMPREG(i, DISPC_OVL_ACCU2_0);
3497 DUMPREG(i, DISPC_OVL_ACCU2_1);
3498 }
3499 if (dss_has_feature(FEAT_ATTR2))
3500 DUMPREG(i, DISPC_OVL_ATTRIBUTES2);
3501 }
3502
3503 if (dispc.feat->has_writeback) {
3504 i = OMAP_DSS_WB;
3505 DUMPREG(i, DISPC_OVL_BA0);
3506 DUMPREG(i, DISPC_OVL_BA1);
3507 DUMPREG(i, DISPC_OVL_SIZE);
3508 DUMPREG(i, DISPC_OVL_ATTRIBUTES);
3509 DUMPREG(i, DISPC_OVL_FIFO_THRESHOLD);
3510 DUMPREG(i, DISPC_OVL_FIFO_SIZE_STATUS);
3511 DUMPREG(i, DISPC_OVL_ROW_INC);
3512 DUMPREG(i, DISPC_OVL_PIXEL_INC);
3513
3514 if (dss_has_feature(FEAT_MFLAG))
3515 DUMPREG(i, DISPC_OVL_MFLAG_THRESHOLD);
3516
3517 DUMPREG(i, DISPC_OVL_FIR);
3518 DUMPREG(i, DISPC_OVL_PICTURE_SIZE);
3519 DUMPREG(i, DISPC_OVL_ACCU0);
3520 DUMPREG(i, DISPC_OVL_ACCU1);
3521 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
3522 DUMPREG(i, DISPC_OVL_BA0_UV);
3523 DUMPREG(i, DISPC_OVL_BA1_UV);
3524 DUMPREG(i, DISPC_OVL_FIR2);
3525 DUMPREG(i, DISPC_OVL_ACCU2_0);
3526 DUMPREG(i, DISPC_OVL_ACCU2_1);
3527 }
3528 if (dss_has_feature(FEAT_ATTR2))
3529 DUMPREG(i, DISPC_OVL_ATTRIBUTES2);
3530 }
3531
3532 #undef DISPC_REG
3533 #undef DUMPREG
3534
3535 #define DISPC_REG(plane, name, i) name(plane, i)
3536 #define DUMPREG(plane, name, i) \
3537 seq_printf(s, "%s_%d(%s)%*s %08x\n", #name, i, p_names[plane], \
3538 (int)(46 - strlen(#name) - strlen(p_names[plane])), " ", \
3539 dispc_read_reg(DISPC_REG(plane, name, i)))
3540
3541 /* Video pipeline coefficient registers */
3542
3543 /* start from OMAP_DSS_VIDEO1 */
3544 for (i = 1; i < dss_feat_get_num_ovls(); i++) {
3545 for (j = 0; j < 8; j++)
3546 DUMPREG(i, DISPC_OVL_FIR_COEF_H, j);
3547
3548 for (j = 0; j < 8; j++)
3549 DUMPREG(i, DISPC_OVL_FIR_COEF_HV, j);
3550
3551 for (j = 0; j < 5; j++)
3552 DUMPREG(i, DISPC_OVL_CONV_COEF, j);
3553
3554 if (dss_has_feature(FEAT_FIR_COEF_V)) {
3555 for (j = 0; j < 8; j++)
3556 DUMPREG(i, DISPC_OVL_FIR_COEF_V, j);
3557 }
3558
3559 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
3560 for (j = 0; j < 8; j++)
3561 DUMPREG(i, DISPC_OVL_FIR_COEF_H2, j);
3562
3563 for (j = 0; j < 8; j++)
3564 DUMPREG(i, DISPC_OVL_FIR_COEF_HV2, j);
3565
3566 for (j = 0; j < 8; j++)
3567 DUMPREG(i, DISPC_OVL_FIR_COEF_V2, j);
3568 }
3569 }
3570
3571 dispc_runtime_put();
3572
3573 #undef DISPC_REG
3574 #undef DUMPREG
3575 }
3576
3577 /* calculate clock rates using dividers in cinfo */
3578 int dispc_calc_clock_rates(unsigned long dispc_fclk_rate,
3579 struct dispc_clock_info *cinfo)
3580 {
3581 if (cinfo->lck_div > 255 || cinfo->lck_div == 0)
3582 return -EINVAL;
3583 if (cinfo->pck_div < 1 || cinfo->pck_div > 255)
3584 return -EINVAL;
3585
3586 cinfo->lck = dispc_fclk_rate / cinfo->lck_div;
3587 cinfo->pck = cinfo->lck / cinfo->pck_div;
3588
3589 return 0;
3590 }
3591
3592 bool dispc_div_calc(unsigned long dispc,
3593 unsigned long pck_min, unsigned long pck_max,
3594 dispc_div_calc_func func, void *data)
3595 {
3596 int lckd, lckd_start, lckd_stop;
3597 int pckd, pckd_start, pckd_stop;
3598 unsigned long pck, lck;
3599 unsigned long lck_max;
3600 unsigned long pckd_hw_min, pckd_hw_max;
3601 unsigned min_fck_per_pck;
3602 unsigned long fck;
3603
3604 #ifdef CONFIG_FB_OMAP2_DSS_MIN_FCK_PER_PCK
3605 min_fck_per_pck = CONFIG_FB_OMAP2_DSS_MIN_FCK_PER_PCK;
3606 #else
3607 min_fck_per_pck = 0;
3608 #endif
3609
3610 pckd_hw_min = dss_feat_get_param_min(FEAT_PARAM_DSS_PCD);
3611 pckd_hw_max = dss_feat_get_param_max(FEAT_PARAM_DSS_PCD);
3612
3613 lck_max = dss_feat_get_param_max(FEAT_PARAM_DSS_FCK);
3614
3615 pck_min = pck_min ? pck_min : 1;
3616 pck_max = pck_max ? pck_max : ULONG_MAX;
3617
3618 lckd_start = max(DIV_ROUND_UP(dispc, lck_max), 1ul);
3619 lckd_stop = min(dispc / pck_min, 255ul);
3620
3621 for (lckd = lckd_start; lckd <= lckd_stop; ++lckd) {
3622 lck = dispc / lckd;
3623
3624 pckd_start = max(DIV_ROUND_UP(lck, pck_max), pckd_hw_min);
3625 pckd_stop = min(lck / pck_min, pckd_hw_max);
3626
3627 for (pckd = pckd_start; pckd <= pckd_stop; ++pckd) {
3628 pck = lck / pckd;
3629
3630 /*
3631 * For OMAP2/3 the DISPC fclk is the same as LCD's logic
3632 * clock, which means we're configuring DISPC fclk here
3633 * also. Thus we need to use the calculated lck. For
3634 * OMAP4+ the DISPC fclk is a separate clock.
3635 */
3636 if (dss_has_feature(FEAT_CORE_CLK_DIV))
3637 fck = dispc_core_clk_rate();
3638 else
3639 fck = lck;
3640
3641 if (fck < pck * min_fck_per_pck)
3642 continue;
3643
3644 if (func(lckd, pckd, lck, pck, data))
3645 return true;
3646 }
3647 }
3648
3649 return false;
3650 }
3651
3652 void dispc_mgr_set_clock_div(enum omap_channel channel,
3653 const struct dispc_clock_info *cinfo)
3654 {
3655 DSSDBG("lck = %lu (%u)\n", cinfo->lck, cinfo->lck_div);
3656 DSSDBG("pck = %lu (%u)\n", cinfo->pck, cinfo->pck_div);
3657
3658 dispc_mgr_set_lcd_divisor(channel, cinfo->lck_div, cinfo->pck_div);
3659 }
3660
3661 int dispc_mgr_get_clock_div(enum omap_channel channel,
3662 struct dispc_clock_info *cinfo)
3663 {
3664 unsigned long fck;
3665
3666 fck = dispc_fclk_rate();
3667
3668 cinfo->lck_div = REG_GET(DISPC_DIVISORo(channel), 23, 16);
3669 cinfo->pck_div = REG_GET(DISPC_DIVISORo(channel), 7, 0);
3670
3671 cinfo->lck = fck / cinfo->lck_div;
3672 cinfo->pck = cinfo->lck / cinfo->pck_div;
3673
3674 return 0;
3675 }
3676
3677 u32 dispc_read_irqstatus(void)
3678 {
3679 return dispc_read_reg(DISPC_IRQSTATUS);
3680 }
3681 EXPORT_SYMBOL(dispc_read_irqstatus);
3682
3683 void dispc_clear_irqstatus(u32 mask)
3684 {
3685 dispc_write_reg(DISPC_IRQSTATUS, mask);
3686 }
3687 EXPORT_SYMBOL(dispc_clear_irqstatus);
3688
3689 u32 dispc_read_irqenable(void)
3690 {
3691 return dispc_read_reg(DISPC_IRQENABLE);
3692 }
3693 EXPORT_SYMBOL(dispc_read_irqenable);
3694
3695 void dispc_write_irqenable(u32 mask)
3696 {
3697 u32 old_mask = dispc_read_reg(DISPC_IRQENABLE);
3698
3699 /* clear the irqstatus for newly enabled irqs */
3700 dispc_clear_irqstatus((mask ^ old_mask) & mask);
3701
3702 dispc_write_reg(DISPC_IRQENABLE, mask);
3703 }
3704 EXPORT_SYMBOL(dispc_write_irqenable);
3705
3706 void dispc_enable_sidle(void)
3707 {
3708 REG_FLD_MOD(DISPC_SYSCONFIG, 2, 4, 3); /* SIDLEMODE: smart idle */
3709 }
3710
3711 void dispc_disable_sidle(void)
3712 {
3713 REG_FLD_MOD(DISPC_SYSCONFIG, 1, 4, 3); /* SIDLEMODE: no idle */
3714 }
3715
3716 static void _omap_dispc_initial_config(void)
3717 {
3718 u32 l;
3719
3720 /* Exclusively enable DISPC_CORE_CLK and set divider to 1 */
3721 if (dss_has_feature(FEAT_CORE_CLK_DIV)) {
3722 l = dispc_read_reg(DISPC_DIVISOR);
3723 /* Use DISPC_DIVISOR.LCD, instead of DISPC_DIVISOR1.LCD */
3724 l = FLD_MOD(l, 1, 0, 0);
3725 l = FLD_MOD(l, 1, 23, 16);
3726 dispc_write_reg(DISPC_DIVISOR, l);
3727
3728 dispc.core_clk_rate = dispc_fclk_rate();
3729 }
3730
3731 /* FUNCGATED */
3732 if (dss_has_feature(FEAT_FUNCGATED))
3733 REG_FLD_MOD(DISPC_CONFIG, 1, 9, 9);
3734
3735 dispc_setup_color_conv_coef();
3736
3737 dispc_set_loadmode(OMAP_DSS_LOAD_FRAME_ONLY);
3738
3739 dispc_init_fifos();
3740
3741 dispc_configure_burst_sizes();
3742
3743 dispc_ovl_enable_zorder_planes();
3744
3745 if (dispc.feat->mstandby_workaround)
3746 REG_FLD_MOD(DISPC_MSTANDBY_CTRL, 1, 0, 0);
3747
3748 if (dss_has_feature(FEAT_MFLAG))
3749 dispc_init_mflag();
3750 }
3751
3752 static const struct dispc_features omap24xx_dispc_feats = {
3753 .sw_start = 5,
3754 .fp_start = 15,
3755 .bp_start = 27,
3756 .sw_max = 64,
3757 .vp_max = 255,
3758 .hp_max = 256,
3759 .mgr_width_start = 10,
3760 .mgr_height_start = 26,
3761 .mgr_width_max = 2048,
3762 .mgr_height_max = 2048,
3763 .max_lcd_pclk = 66500000,
3764 .calc_scaling = dispc_ovl_calc_scaling_24xx,
3765 .calc_core_clk = calc_core_clk_24xx,
3766 .num_fifos = 3,
3767 .no_framedone_tv = true,
3768 .set_max_preload = false,
3769 .last_pixel_inc_missing = true,
3770 };
3771
3772 static const struct dispc_features omap34xx_rev1_0_dispc_feats = {
3773 .sw_start = 5,
3774 .fp_start = 15,
3775 .bp_start = 27,
3776 .sw_max = 64,
3777 .vp_max = 255,
3778 .hp_max = 256,
3779 .mgr_width_start = 10,
3780 .mgr_height_start = 26,
3781 .mgr_width_max = 2048,
3782 .mgr_height_max = 2048,
3783 .max_lcd_pclk = 173000000,
3784 .max_tv_pclk = 59000000,
3785 .calc_scaling = dispc_ovl_calc_scaling_34xx,
3786 .calc_core_clk = calc_core_clk_34xx,
3787 .num_fifos = 3,
3788 .no_framedone_tv = true,
3789 .set_max_preload = false,
3790 .last_pixel_inc_missing = true,
3791 };
3792
3793 static const struct dispc_features omap34xx_rev3_0_dispc_feats = {
3794 .sw_start = 7,
3795 .fp_start = 19,
3796 .bp_start = 31,
3797 .sw_max = 256,
3798 .vp_max = 4095,
3799 .hp_max = 4096,
3800 .mgr_width_start = 10,
3801 .mgr_height_start = 26,
3802 .mgr_width_max = 2048,
3803 .mgr_height_max = 2048,
3804 .max_lcd_pclk = 173000000,
3805 .max_tv_pclk = 59000000,
3806 .calc_scaling = dispc_ovl_calc_scaling_34xx,
3807 .calc_core_clk = calc_core_clk_34xx,
3808 .num_fifos = 3,
3809 .no_framedone_tv = true,
3810 .set_max_preload = false,
3811 .last_pixel_inc_missing = true,
3812 };
3813
3814 static const struct dispc_features omap44xx_dispc_feats = {
3815 .sw_start = 7,
3816 .fp_start = 19,
3817 .bp_start = 31,
3818 .sw_max = 256,
3819 .vp_max = 4095,
3820 .hp_max = 4096,
3821 .mgr_width_start = 10,
3822 .mgr_height_start = 26,
3823 .mgr_width_max = 2048,
3824 .mgr_height_max = 2048,
3825 .max_lcd_pclk = 170000000,
3826 .max_tv_pclk = 185625000,
3827 .calc_scaling = dispc_ovl_calc_scaling_44xx,
3828 .calc_core_clk = calc_core_clk_44xx,
3829 .num_fifos = 5,
3830 .gfx_fifo_workaround = true,
3831 .set_max_preload = true,
3832 .supports_sync_align = true,
3833 .has_writeback = true,
3834 };
3835
3836 static const struct dispc_features omap54xx_dispc_feats = {
3837 .sw_start = 7,
3838 .fp_start = 19,
3839 .bp_start = 31,
3840 .sw_max = 256,
3841 .vp_max = 4095,
3842 .hp_max = 4096,
3843 .mgr_width_start = 11,
3844 .mgr_height_start = 27,
3845 .mgr_width_max = 4096,
3846 .mgr_height_max = 4096,
3847 .max_lcd_pclk = 170000000,
3848 .max_tv_pclk = 186000000,
3849 .calc_scaling = dispc_ovl_calc_scaling_44xx,
3850 .calc_core_clk = calc_core_clk_44xx,
3851 .num_fifos = 5,
3852 .gfx_fifo_workaround = true,
3853 .mstandby_workaround = true,
3854 .set_max_preload = true,
3855 .supports_sync_align = true,
3856 .has_writeback = true,
3857 };
3858
3859 static const struct dispc_features *dispc_get_features(void)
3860 {
3861 switch (omapdss_get_version()) {
3862 case OMAPDSS_VER_OMAP24xx:
3863 return &omap24xx_dispc_feats;
3864
3865 case OMAPDSS_VER_OMAP34xx_ES1:
3866 return &omap34xx_rev1_0_dispc_feats;
3867
3868 case OMAPDSS_VER_OMAP34xx_ES3:
3869 case OMAPDSS_VER_OMAP3630:
3870 case OMAPDSS_VER_AM35xx:
3871 case OMAPDSS_VER_AM43xx:
3872 return &omap34xx_rev3_0_dispc_feats;
3873
3874 case OMAPDSS_VER_OMAP4430_ES1:
3875 case OMAPDSS_VER_OMAP4430_ES2:
3876 case OMAPDSS_VER_OMAP4:
3877 return &omap44xx_dispc_feats;
3878
3879 case OMAPDSS_VER_OMAP5:
3880 case OMAPDSS_VER_DRA7xx:
3881 return &omap54xx_dispc_feats;
3882
3883 default:
3884 return NULL;
3885 }
3886 }
3887
3888 static irqreturn_t dispc_irq_handler(int irq, void *arg)
3889 {
3890 if (!dispc.is_enabled)
3891 return IRQ_NONE;
3892
3893 return dispc.user_handler(irq, dispc.user_data);
3894 }
3895
3896 int dispc_request_irq(irq_handler_t handler, void *dev_id)
3897 {
3898 int r;
3899
3900 if (dispc.user_handler != NULL)
3901 return -EBUSY;
3902
3903 dispc.user_handler = handler;
3904 dispc.user_data = dev_id;
3905
3906 /* ensure the dispc_irq_handler sees the values above */
3907 smp_wmb();
3908
3909 r = devm_request_irq(&dispc.pdev->dev, dispc.irq, dispc_irq_handler,
3910 IRQF_SHARED, "OMAP DISPC", &dispc);
3911 if (r) {
3912 dispc.user_handler = NULL;
3913 dispc.user_data = NULL;
3914 }
3915
3916 return r;
3917 }
3918 EXPORT_SYMBOL(dispc_request_irq);
3919
3920 void dispc_free_irq(void *dev_id)
3921 {
3922 devm_free_irq(&dispc.pdev->dev, dispc.irq, &dispc);
3923
3924 dispc.user_handler = NULL;
3925 dispc.user_data = NULL;
3926 }
3927 EXPORT_SYMBOL(dispc_free_irq);
3928
3929 /* DISPC HW IP initialisation */
3930 static int dispc_bind(struct device *dev, struct device *master, void *data)
3931 {
3932 struct platform_device *pdev = to_platform_device(dev);
3933 u32 rev;
3934 int r = 0;
3935 struct resource *dispc_mem;
3936 struct device_node *np = pdev->dev.of_node;
3937
3938 dispc.pdev = pdev;
3939
3940 spin_lock_init(&dispc.control_lock);
3941
3942 dispc.feat = dispc_get_features();
3943 if (!dispc.feat)
3944 return -ENODEV;
3945
3946 dispc_mem = platform_get_resource(dispc.pdev, IORESOURCE_MEM, 0);
3947 if (!dispc_mem) {
3948 DSSERR("can't get IORESOURCE_MEM DISPC\n");
3949 return -EINVAL;
3950 }
3951
3952 dispc.base = devm_ioremap(&pdev->dev, dispc_mem->start,
3953 resource_size(dispc_mem));
3954 if (!dispc.base) {
3955 DSSERR("can't ioremap DISPC\n");
3956 return -ENOMEM;
3957 }
3958
3959 dispc.irq = platform_get_irq(dispc.pdev, 0);
3960 if (dispc.irq < 0) {
3961 DSSERR("platform_get_irq failed\n");
3962 return -ENODEV;
3963 }
3964
3965 if (np && of_property_read_bool(np, "syscon-pol")) {
3966 dispc.syscon_pol = syscon_regmap_lookup_by_phandle(np, "syscon-pol");
3967 if (IS_ERR(dispc.syscon_pol)) {
3968 dev_err(&pdev->dev, "failed to get syscon-pol regmap\n");
3969 return PTR_ERR(dispc.syscon_pol);
3970 }
3971
3972 if (of_property_read_u32_index(np, "syscon-pol", 1,
3973 &dispc.syscon_pol_offset)) {
3974 dev_err(&pdev->dev, "failed to get syscon-pol offset\n");
3975 return -EINVAL;
3976 }
3977 }
3978
3979 pm_runtime_enable(&pdev->dev);
3980
3981 r = dispc_runtime_get();
3982 if (r)
3983 goto err_runtime_get;
3984
3985 _omap_dispc_initial_config();
3986
3987 rev = dispc_read_reg(DISPC_REVISION);
3988 dev_dbg(&pdev->dev, "OMAP DISPC rev %d.%d\n",
3989 FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
3990
3991 dispc_runtime_put();
3992
3993 dss_init_overlay_managers();
3994
3995 dss_debugfs_create_file("dispc", dispc_dump_regs);
3996
3997 return 0;
3998
3999 err_runtime_get:
4000 pm_runtime_disable(&pdev->dev);
4001 return r;
4002 }
4003
4004 static void dispc_unbind(struct device *dev, struct device *master,
4005 void *data)
4006 {
4007 pm_runtime_disable(dev);
4008
4009 dss_uninit_overlay_managers();
4010 }
4011
4012 static const struct component_ops dispc_component_ops = {
4013 .bind = dispc_bind,
4014 .unbind = dispc_unbind,
4015 };
4016
4017 static int dispc_probe(struct platform_device *pdev)
4018 {
4019 return component_add(&pdev->dev, &dispc_component_ops);
4020 }
4021
4022 static int dispc_remove(struct platform_device *pdev)
4023 {
4024 component_del(&pdev->dev, &dispc_component_ops);
4025 return 0;
4026 }
4027
4028 static int dispc_runtime_suspend(struct device *dev)
4029 {
4030 dispc.is_enabled = false;
4031 /* ensure the dispc_irq_handler sees the is_enabled value */
4032 smp_wmb();
4033 /* wait for current handler to finish before turning the DISPC off */
4034 synchronize_irq(dispc.irq);
4035
4036 dispc_save_context();
4037
4038 return 0;
4039 }
4040
4041 static int dispc_runtime_resume(struct device *dev)
4042 {
4043 /*
4044 * The reset value for load mode is 0 (OMAP_DSS_LOAD_CLUT_AND_FRAME)
4045 * but we always initialize it to 2 (OMAP_DSS_LOAD_FRAME_ONLY) in
4046 * _omap_dispc_initial_config(). We can thus use it to detect if
4047 * we have lost register context.
4048 */
4049 if (REG_GET(DISPC_CONFIG, 2, 1) != OMAP_DSS_LOAD_FRAME_ONLY) {
4050 _omap_dispc_initial_config();
4051
4052 dispc_restore_context();
4053 }
4054
4055 dispc.is_enabled = true;
4056 /* ensure the dispc_irq_handler sees the is_enabled value */
4057 smp_wmb();
4058
4059 return 0;
4060 }
4061
4062 static const struct dev_pm_ops dispc_pm_ops = {
4063 .runtime_suspend = dispc_runtime_suspend,
4064 .runtime_resume = dispc_runtime_resume,
4065 };
4066
4067 static const struct of_device_id dispc_of_match[] = {
4068 { .compatible = "ti,omap2-dispc", },
4069 { .compatible = "ti,omap3-dispc", },
4070 { .compatible = "ti,omap4-dispc", },
4071 { .compatible = "ti,omap5-dispc", },
4072 { .compatible = "ti,dra7-dispc", },
4073 {},
4074 };
4075
4076 static struct platform_driver omap_dispchw_driver = {
4077 .probe = dispc_probe,
4078 .remove = dispc_remove,
4079 .driver = {
4080 .name = "omapdss_dispc",
4081 .pm = &dispc_pm_ops,
4082 .of_match_table = dispc_of_match,
4083 .suppress_bind_attrs = true,
4084 },
4085 };
4086
4087 int __init dispc_init_platform_driver(void)
4088 {
4089 return platform_driver_register(&omap_dispchw_driver);
4090 }
4091
4092 void dispc_uninit_platform_driver(void)
4093 {
4094 platform_driver_unregister(&omap_dispchw_driver);
4095 }
Linux with added FPC-III support