drivers/watchdog/qcom-wdt.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /* Copyright (c) 2014, The Linux Foundation. All rights reserved.
   3  */
   4 #include <linux/bits.h>
   5 #include <linux/clk.h>
   6 #include <linux/delay.h>
   7 #include <linux/interrupt.h>
   8 #include <linux/io.h>
   9 #include <linux/kernel.h>
  10 #include <linux/module.h>
  11 #include <linux/of.h>
  12 #include <linux/platform_device.h>
  13 #include <linux/watchdog.h>
  14 #include <linux/of_device.h>
  15
  16 enum wdt_reg {
  17         WDT_RST,
  18         WDT_EN,
  19         WDT_STS,
  20         WDT_BARK_TIME,
  21         WDT_BITE_TIME,
  22 };
  23
  24 #define QCOM_WDT_ENABLE         BIT(0)
  25 #define QCOM_WDT_ENABLE_IRQ     BIT(1)
  26
  27 static const u32 reg_offset_data_apcs_tmr[] = {
  28         [WDT_RST] = 0x38,
  29         [WDT_EN] = 0x40,
  30         [WDT_STS] = 0x44,
  31         [WDT_BARK_TIME] = 0x4C,
  32         [WDT_BITE_TIME] = 0x5C,
  33 };
  34
  35 static const u32 reg_offset_data_kpss[] = {
  36         [WDT_RST] = 0x4,
  37         [WDT_EN] = 0x8,
  38         [WDT_STS] = 0xC,
  39         [WDT_BARK_TIME] = 0x10,
  40         [WDT_BITE_TIME] = 0x14,
  41 };
  42
  43 struct qcom_wdt_match_data {
  44         const u32 *offset;
  45         bool pretimeout;
  46 };
  47
  48 struct qcom_wdt {
  49         struct watchdog_device  wdd;
  50         unsigned long           rate;
  51         void __iomem            *base;
  52         const u32               *layout;
  53 };
  54
  55 static void __iomem *wdt_addr(struct qcom_wdt *wdt, enum wdt_reg reg)
  56 {
  57         return wdt->base + wdt->layout[reg];
  58 }
  59
  60 static inline
  61 struct qcom_wdt *to_qcom_wdt(struct watchdog_device *wdd)
  62 {
  63         return container_of(wdd, struct qcom_wdt, wdd);
  64 }
  65
  66 static inline int qcom_get_enable(struct watchdog_device *wdd)
  67 {
  68         int enable = QCOM_WDT_ENABLE;
  69
  70         if (wdd->pretimeout)
  71                 enable |= QCOM_WDT_ENABLE_IRQ;
  72
  73         return enable;
  74 }
  75
  76 static irqreturn_t qcom_wdt_isr(int irq, void *arg)
  77 {
  78         struct watchdog_device *wdd = arg;
  79
  80         watchdog_notify_pretimeout(wdd);
  81
  82         return IRQ_HANDLED;
  83 }
  84
  85 static int qcom_wdt_start(struct watchdog_device *wdd)
  86 {
  87         struct qcom_wdt *wdt = to_qcom_wdt(wdd);
  88         unsigned int bark = wdd->timeout - wdd->pretimeout;
  89
  90         writel(0, wdt_addr(wdt, WDT_EN));
  91         writel(1, wdt_addr(wdt, WDT_RST));
  92         writel(bark * wdt->rate, wdt_addr(wdt, WDT_BARK_TIME));
  93         writel(wdd->timeout * wdt->rate, wdt_addr(wdt, WDT_BITE_TIME));
  94         writel(qcom_get_enable(wdd), wdt_addr(wdt, WDT_EN));
  95         return 0;
  96 }
  97
  98 static int qcom_wdt_stop(struct watchdog_device *wdd)
  99 {
 100         struct qcom_wdt *wdt = to_qcom_wdt(wdd);
 101
 102         writel(0, wdt_addr(wdt, WDT_EN));
 103         return 0;
 104 }
 105
 106 static int qcom_wdt_ping(struct watchdog_device *wdd)
 107 {
 108         struct qcom_wdt *wdt = to_qcom_wdt(wdd);
 109
 110         writel(1, wdt_addr(wdt, WDT_RST));
 111         return 0;
 112 }
 113
 114 static int qcom_wdt_set_timeout(struct watchdog_device *wdd,
 115                                 unsigned int timeout)
 116 {
 117         wdd->timeout = timeout;
 118         return qcom_wdt_start(wdd);
 119 }
 120
 121 static int qcom_wdt_set_pretimeout(struct watchdog_device *wdd,
 122                                    unsigned int timeout)
 123 {
 124         wdd->pretimeout = timeout;
 125         return qcom_wdt_start(wdd);
 126 }
 127
 128 static int qcom_wdt_restart(struct watchdog_device *wdd, unsigned long action,
 129                             void *data)
 130 {
 131         struct qcom_wdt *wdt = to_qcom_wdt(wdd);
 132         u32 timeout;
 133
 134         /*
 135          * Trigger watchdog bite:
 136          *    Setup BITE_TIME to be 128ms, and enable WDT.
 137          */
 138         timeout = 128 * wdt->rate / 1000;
 139
 140         writel(0, wdt_addr(wdt, WDT_EN));
 141         writel(1, wdt_addr(wdt, WDT_RST));
 142         writel(timeout, wdt_addr(wdt, WDT_BARK_TIME));
 143         writel(timeout, wdt_addr(wdt, WDT_BITE_TIME));
 144         writel(QCOM_WDT_ENABLE, wdt_addr(wdt, WDT_EN));
 145
 146         /*
 147          * Actually make sure the above sequence hits hardware before sleeping.
 148          */
 149         wmb();
 150
 151         mdelay(150);
 152         return 0;
 153 }
 154
 155 static int qcom_wdt_is_running(struct watchdog_device *wdd)
 156 {
 157         struct qcom_wdt *wdt = to_qcom_wdt(wdd);
 158
 159         return (readl(wdt_addr(wdt, WDT_EN)) & QCOM_WDT_ENABLE);
 160 }
 161
 162 static const struct watchdog_ops qcom_wdt_ops = {
 163         .start          = qcom_wdt_start,
 164         .stop           = qcom_wdt_stop,
 165         .ping           = qcom_wdt_ping,
 166         .set_timeout    = qcom_wdt_set_timeout,
 167         .set_pretimeout = qcom_wdt_set_pretimeout,
 168         .restart        = qcom_wdt_restart,
 169         .owner          = THIS_MODULE,
 170 };
 171
 172 static const struct watchdog_info qcom_wdt_info = {
 173         .options        = WDIOF_KEEPALIVEPING
 174                         | WDIOF_MAGICCLOSE
 175                         | WDIOF_SETTIMEOUT
 176                         | WDIOF_CARDRESET,
 177         .identity       = KBUILD_MODNAME,
 178 };
 179
 180 static const struct watchdog_info qcom_wdt_pt_info = {
 181         .options        = WDIOF_KEEPALIVEPING
 182                         | WDIOF_MAGICCLOSE
 183                         | WDIOF_SETTIMEOUT
 184                         | WDIOF_PRETIMEOUT
 185                         | WDIOF_CARDRESET,
 186         .identity       = KBUILD_MODNAME,
 187 };
 188
 189 static void qcom_clk_disable_unprepare(void *data)
 190 {
 191         clk_disable_unprepare(data);
 192 }
 193
 194 static const struct qcom_wdt_match_data match_data_apcs_tmr = {
 195         .offset = reg_offset_data_apcs_tmr,
 196         .pretimeout = false,
 197 };
 198
 199 static const struct qcom_wdt_match_data match_data_kpss = {
 200         .offset = reg_offset_data_kpss,
 201         .pretimeout = true,
 202 };
 203
 204 static int qcom_wdt_probe(struct platform_device *pdev)
 205 {
 206         struct device *dev = &pdev->dev;
 207         struct qcom_wdt *wdt;
 208         struct resource *res;
 209         struct device_node *np = dev->of_node;
 210         const struct qcom_wdt_match_data *data;
 211         u32 percpu_offset;
 212         int irq, ret;
 213         struct clk *clk;
 214
 215         data = of_device_get_match_data(dev);
 216         if (!data) {
 217                 dev_err(dev, "Unsupported QCOM WDT module\n");
 218                 return -ENODEV;
 219         }
 220
 221         wdt = devm_kzalloc(dev, sizeof(*wdt), GFP_KERNEL);
 222         if (!wdt)
 223                 return -ENOMEM;
 224
 225         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 226         if (!res)
 227                 return -ENOMEM;
 228
 229         /* We use CPU0's DGT for the watchdog */
 230         if (of_property_read_u32(np, "cpu-offset", &percpu_offset))
 231                 percpu_offset = 0;
 232
 233         res->start += percpu_offset;
 234         res->end += percpu_offset;
 235
 236         wdt->base = devm_ioremap_resource(dev, res);
 237         if (IS_ERR(wdt->base))
 238                 return PTR_ERR(wdt->base);
 239
 240         clk = devm_clk_get(dev, NULL);
 241         if (IS_ERR(clk)) {
 242                 dev_err(dev, "failed to get input clock\n");
 243                 return PTR_ERR(clk);
 244         }
 245
 246         ret = clk_prepare_enable(clk);
 247         if (ret) {
 248                 dev_err(dev, "failed to setup clock\n");
 249                 return ret;
 250         }
 251         ret = devm_add_action_or_reset(dev, qcom_clk_disable_unprepare, clk);
 252         if (ret)
 253                 return ret;
 254
 255         /*
 256          * We use the clock rate to calculate the max timeout, so ensure it's
 257          * not zero to avoid a divide-by-zero exception.
 258          *
 259          * WATCHDOG_CORE assumes units of seconds, if the WDT is clocked such
 260          * that it would bite before a second elapses it's usefulness is
 261          * limited.  Bail if this is the case.
 262          */
 263         wdt->rate = clk_get_rate(clk);
 264         if (wdt->rate == 0 ||
 265             wdt->rate > 0x10000000U) {
 266                 dev_err(dev, "invalid clock rate\n");
 267                 return -EINVAL;
 268         }
 269
 270         /* check if there is pretimeout support */
 271         irq = platform_get_irq_optional(pdev, 0);
 272         if (data->pretimeout && irq > 0) {
 273                 ret = devm_request_irq(dev, irq, qcom_wdt_isr, 0,
 274                                        "wdt_bark", &wdt->wdd);
 275                 if (ret)
 276                         return ret;
 277
 278                 wdt->wdd.info = &qcom_wdt_pt_info;
 279                 wdt->wdd.pretimeout = 1;
 280         } else {
 281                 if (irq == -EPROBE_DEFER)
 282                         return -EPROBE_DEFER;
 283
 284                 wdt->wdd.info = &qcom_wdt_info;
 285         }
 286
 287         wdt->wdd.ops = &qcom_wdt_ops;
 288         wdt->wdd.min_timeout = 1;
 289         wdt->wdd.max_timeout = 0x10000000U / wdt->rate;
 290         wdt->wdd.parent = dev;
 291         wdt->layout = data->offset;
 292
 293         if (readl(wdt_addr(wdt, WDT_STS)) & 1)
 294                 wdt->wdd.bootstatus = WDIOF_CARDRESET;
 295
 296         /*
 297          * If 'timeout-sec' unspecified in devicetree, assume a 30 second
 298          * default, unless the max timeout is less than 30 seconds, then use
 299          * the max instead.
 300          */
 301         wdt->wdd.timeout = min(wdt->wdd.max_timeout, 30U);
 302         watchdog_init_timeout(&wdt->wdd, 0, dev);
 303
 304         /*
 305          * If WDT is already running, call WDT start which
 306          * will stop the WDT, set timeouts as bootloader
 307          * might use different ones and set running bit
 308          * to inform the WDT subsystem to ping the WDT
 309          */
 310         if (qcom_wdt_is_running(&wdt->wdd)) {
 311                 qcom_wdt_start(&wdt->wdd);
 312                 set_bit(WDOG_HW_RUNNING, &wdt->wdd.status);
 313         }
 314
 315         ret = devm_watchdog_register_device(dev, &wdt->wdd);
 316         if (ret)
 317                 return ret;
 318
 319         platform_set_drvdata(pdev, wdt);
 320         return 0;
 321 }
 322
 323 static int __maybe_unused qcom_wdt_suspend(struct device *dev)
 324 {
 325         struct qcom_wdt *wdt = dev_get_drvdata(dev);
 326
 327         if (watchdog_active(&wdt->wdd))
 328                 qcom_wdt_stop(&wdt->wdd);
 329
 330         return 0;
 331 }
 332
 333 static int __maybe_unused qcom_wdt_resume(struct device *dev)
 334 {
 335         struct qcom_wdt *wdt = dev_get_drvdata(dev);
 336
 337         if (watchdog_active(&wdt->wdd))
 338                 qcom_wdt_start(&wdt->wdd);
 339
 340         return 0;
 341 }
 342
 343 static SIMPLE_DEV_PM_OPS(qcom_wdt_pm_ops, qcom_wdt_suspend, qcom_wdt_resume);
 344
 345 static const struct of_device_id qcom_wdt_of_table[] = {
 346         { .compatible = "qcom,kpss-timer", .data = &match_data_apcs_tmr },
 347         { .compatible = "qcom,scss-timer", .data = &match_data_apcs_tmr },
 348         { .compatible = "qcom,kpss-wdt", .data = &match_data_kpss },
 349         { },
 350 };
 351 MODULE_DEVICE_TABLE(of, qcom_wdt_of_table);
 352
 353 static struct platform_driver qcom_watchdog_driver = {
 354         .probe  = qcom_wdt_probe,
 355         .driver = {
 356                 .name           = KBUILD_MODNAME,
 357                 .of_match_table = qcom_wdt_of_table,
 358                 .pm             = &qcom_wdt_pm_ops,
 359         },
 360 };
 361 module_platform_driver(qcom_watchdog_driver);
 362
 363 MODULE_DESCRIPTION("QCOM KPSS Watchdog Driver");
 364 MODULE_LICENSE("GPL v2");