2 * Renesas R-Car Gen2 PHY driver
4 * Copyright (C) 2014 Renesas Solutions Corp.
5 * Copyright (C) 2014 Cogent Embedded, Inc.
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
12 #include <linux/clk.h>
13 #include <linux/delay.h>
15 #include <linux/module.h>
17 #include <linux/phy/phy.h>
18 #include <linux/platform_device.h>
19 #include <linux/spinlock.h>
20 #include <linux/atomic.h>
22 #define USBHS_LPSTS 0x02
23 #define USBHS_UGCTRL 0x80
24 #define USBHS_UGCTRL2 0x84
25 #define USBHS_UGSTS 0x88 /* From technical update */
27 /* Low Power Status register (LPSTS) */
28 #define USBHS_LPSTS_SUSPM 0x4000
30 /* USB General control register (UGCTRL) */
31 #define USBHS_UGCTRL_CONNECT 0x00000004
32 #define USBHS_UGCTRL_PLLRESET 0x00000001
34 /* USB General control register 2 (UGCTRL2) */
35 #define USBHS_UGCTRL2_USB2SEL 0x80000000
36 #define USBHS_UGCTRL2_USB2SEL_PCI 0x00000000
37 #define USBHS_UGCTRL2_USB2SEL_USB30 0x80000000
38 #define USBHS_UGCTRL2_USB0SEL 0x00000030
39 #define USBHS_UGCTRL2_USB0SEL_PCI 0x00000010
40 #define USBHS_UGCTRL2_USB0SEL_HS_USB 0x00000030
42 /* USB General status register (UGSTS) */
43 #define USBHS_UGSTS_LOCK 0x00000100 /* From technical update */
45 #define PHYS_PER_CHANNEL 2
47 struct rcar_gen2_phy
{
49 struct rcar_gen2_channel
*channel
;
54 struct rcar_gen2_channel
{
55 struct device_node
*of_node
;
56 struct rcar_gen2_phy_driver
*drv
;
57 struct rcar_gen2_phy phys
[PHYS_PER_CHANNEL
];
62 struct rcar_gen2_phy_driver
{
67 struct rcar_gen2_channel
*channels
;
70 static int rcar_gen2_phy_init(struct phy
*p
)
72 struct rcar_gen2_phy
*phy
= phy_get_drvdata(p
);
73 struct rcar_gen2_channel
*channel
= phy
->channel
;
74 struct rcar_gen2_phy_driver
*drv
= channel
->drv
;
79 * Try to acquire exclusive access to PHY. The first driver calling
80 * phy_init() on a given channel wins, and all attempts to use another
81 * PHY on this channel will fail until phy_exit() is called by the first
82 * driver. Achieving this with cmpxcgh() should be SMP-safe.
84 if (cmpxchg(&channel
->selected_phy
, -1, phy
->number
) != -1)
87 clk_prepare_enable(drv
->clk
);
89 spin_lock_irqsave(&drv
->lock
, flags
);
90 ugctrl2
= readl(drv
->base
+ USBHS_UGCTRL2
);
91 ugctrl2
&= ~channel
->select_mask
;
92 ugctrl2
|= phy
->select_value
;
93 writel(ugctrl2
, drv
->base
+ USBHS_UGCTRL2
);
94 spin_unlock_irqrestore(&drv
->lock
, flags
);
98 static int rcar_gen2_phy_exit(struct phy
*p
)
100 struct rcar_gen2_phy
*phy
= phy_get_drvdata(p
);
101 struct rcar_gen2_channel
*channel
= phy
->channel
;
103 clk_disable_unprepare(channel
->drv
->clk
);
105 channel
->selected_phy
= -1;
110 static int rcar_gen2_phy_power_on(struct phy
*p
)
112 struct rcar_gen2_phy
*phy
= phy_get_drvdata(p
);
113 struct rcar_gen2_phy_driver
*drv
= phy
->channel
->drv
;
114 void __iomem
*base
= drv
->base
;
119 /* Skip if it's not USBHS */
120 if (phy
->select_value
!= USBHS_UGCTRL2_USB0SEL_HS_USB
)
123 spin_lock_irqsave(&drv
->lock
, flags
);
125 /* Power on USBHS PHY */
126 value
= readl(base
+ USBHS_UGCTRL
);
127 value
&= ~USBHS_UGCTRL_PLLRESET
;
128 writel(value
, base
+ USBHS_UGCTRL
);
130 value
= readw(base
+ USBHS_LPSTS
);
131 value
|= USBHS_LPSTS_SUSPM
;
132 writew(value
, base
+ USBHS_LPSTS
);
134 for (i
= 0; i
< 20; i
++) {
135 value
= readl(base
+ USBHS_UGSTS
);
136 if ((value
& USBHS_UGSTS_LOCK
) == USBHS_UGSTS_LOCK
) {
137 value
= readl(base
+ USBHS_UGCTRL
);
138 value
|= USBHS_UGCTRL_CONNECT
;
139 writel(value
, base
+ USBHS_UGCTRL
);
145 /* Timed out waiting for the PLL lock */
149 spin_unlock_irqrestore(&drv
->lock
, flags
);
154 static int rcar_gen2_phy_power_off(struct phy
*p
)
156 struct rcar_gen2_phy
*phy
= phy_get_drvdata(p
);
157 struct rcar_gen2_phy_driver
*drv
= phy
->channel
->drv
;
158 void __iomem
*base
= drv
->base
;
162 /* Skip if it's not USBHS */
163 if (phy
->select_value
!= USBHS_UGCTRL2_USB0SEL_HS_USB
)
166 spin_lock_irqsave(&drv
->lock
, flags
);
168 /* Power off USBHS PHY */
169 value
= readl(base
+ USBHS_UGCTRL
);
170 value
&= ~USBHS_UGCTRL_CONNECT
;
171 writel(value
, base
+ USBHS_UGCTRL
);
173 value
= readw(base
+ USBHS_LPSTS
);
174 value
&= ~USBHS_LPSTS_SUSPM
;
175 writew(value
, base
+ USBHS_LPSTS
);
177 value
= readl(base
+ USBHS_UGCTRL
);
178 value
|= USBHS_UGCTRL_PLLRESET
;
179 writel(value
, base
+ USBHS_UGCTRL
);
181 spin_unlock_irqrestore(&drv
->lock
, flags
);
186 static const struct phy_ops rcar_gen2_phy_ops
= {
187 .init
= rcar_gen2_phy_init
,
188 .exit
= rcar_gen2_phy_exit
,
189 .power_on
= rcar_gen2_phy_power_on
,
190 .power_off
= rcar_gen2_phy_power_off
,
191 .owner
= THIS_MODULE
,
194 static const struct of_device_id rcar_gen2_phy_match_table
[] = {
195 { .compatible
= "renesas,usb-phy-r8a7790" },
196 { .compatible
= "renesas,usb-phy-r8a7791" },
197 { .compatible
= "renesas,usb-phy-r8a7794" },
198 { .compatible
= "renesas,rcar-gen2-usb-phy" },
201 MODULE_DEVICE_TABLE(of
, rcar_gen2_phy_match_table
);
203 static struct phy
*rcar_gen2_phy_xlate(struct device
*dev
,
204 struct of_phandle_args
*args
)
206 struct rcar_gen2_phy_driver
*drv
;
207 struct device_node
*np
= args
->np
;
210 drv
= dev_get_drvdata(dev
);
212 return ERR_PTR(-EINVAL
);
214 for (i
= 0; i
< drv
->num_channels
; i
++) {
215 if (np
== drv
->channels
[i
].of_node
)
219 if (i
>= drv
->num_channels
|| args
->args
[0] >= 2)
220 return ERR_PTR(-ENODEV
);
222 return drv
->channels
[i
].phys
[args
->args
[0]].phy
;
225 static const u32 select_mask
[] = {
226 [0] = USBHS_UGCTRL2_USB0SEL
,
227 [2] = USBHS_UGCTRL2_USB2SEL
,
230 static const u32 select_value
[][PHYS_PER_CHANNEL
] = {
231 [0] = { USBHS_UGCTRL2_USB0SEL_PCI
, USBHS_UGCTRL2_USB0SEL_HS_USB
},
232 [2] = { USBHS_UGCTRL2_USB2SEL_PCI
, USBHS_UGCTRL2_USB2SEL_USB30
},
235 static int rcar_gen2_phy_probe(struct platform_device
*pdev
)
237 struct device
*dev
= &pdev
->dev
;
238 struct rcar_gen2_phy_driver
*drv
;
239 struct phy_provider
*provider
;
240 struct device_node
*np
;
241 struct resource
*res
;
248 "This driver is required to be instantiated from device tree\n");
252 clk
= devm_clk_get(dev
, "usbhs");
254 dev_err(dev
, "Can't get USBHS clock\n");
258 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
259 base
= devm_ioremap_resource(dev
, res
);
261 return PTR_ERR(base
);
263 drv
= devm_kzalloc(dev
, sizeof(*drv
), GFP_KERNEL
);
267 spin_lock_init(&drv
->lock
);
272 drv
->num_channels
= of_get_child_count(dev
->of_node
);
273 drv
->channels
= devm_kcalloc(dev
, drv
->num_channels
,
274 sizeof(struct rcar_gen2_channel
),
279 for_each_child_of_node(dev
->of_node
, np
) {
280 struct rcar_gen2_channel
*channel
= drv
->channels
+ i
;
284 channel
->of_node
= np
;
286 channel
->selected_phy
= -1;
288 error
= of_property_read_u32(np
, "reg", &channel_num
);
289 if (error
|| channel_num
> 2) {
290 dev_err(dev
, "Invalid \"reg\" property\n");
293 channel
->select_mask
= select_mask
[channel_num
];
295 for (n
= 0; n
< PHYS_PER_CHANNEL
; n
++) {
296 struct rcar_gen2_phy
*phy
= &channel
->phys
[n
];
298 phy
->channel
= channel
;
300 phy
->select_value
= select_value
[channel_num
][n
];
302 phy
->phy
= devm_phy_create(dev
, NULL
,
304 if (IS_ERR(phy
->phy
)) {
305 dev_err(dev
, "Failed to create PHY\n");
306 return PTR_ERR(phy
->phy
);
308 phy_set_drvdata(phy
->phy
, phy
);
314 provider
= devm_of_phy_provider_register(dev
, rcar_gen2_phy_xlate
);
315 if (IS_ERR(provider
)) {
316 dev_err(dev
, "Failed to register PHY provider\n");
317 return PTR_ERR(provider
);
320 dev_set_drvdata(dev
, drv
);
325 static struct platform_driver rcar_gen2_phy_driver
= {
327 .name
= "phy_rcar_gen2",
328 .of_match_table
= rcar_gen2_phy_match_table
,
330 .probe
= rcar_gen2_phy_probe
,
333 module_platform_driver(rcar_gen2_phy_driver
);
335 MODULE_LICENSE("GPL v2");
336 MODULE_DESCRIPTION("Renesas R-Car Gen2 PHY");
337 MODULE_AUTHOR("Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>");