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sched: Remove double_rq_lock() from __migrate_task()
[linux/fpc-iii.git] / drivers / gpu / drm / nouveau / nv50_display.c
blob4c534b7b04daf032d29efdfc6365011eba2a74cf
1 /*
2 * Copyright 2011 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs
23 */
24
25 #include <linux/dma-mapping.h>
26
27 #include <drm/drmP.h>
28 #include <drm/drm_crtc_helper.h>
29 #include <drm/drm_dp_helper.h>
30
31 #include "nouveau_drm.h"
32 #include "nouveau_dma.h"
33 #include "nouveau_gem.h"
34 #include "nouveau_connector.h"
35 #include "nouveau_encoder.h"
36 #include "nouveau_crtc.h"
37 #include "nouveau_fence.h"
38 #include "nv50_display.h"
39
40 #include <core/client.h>
41 #include <core/gpuobj.h>
42 #include <core/class.h>
43
44 #include <subdev/timer.h>
45 #include <subdev/bar.h>
46 #include <subdev/fb.h>
47 #include <subdev/i2c.h>
48
49 #define EVO_DMA_NR 9
50
51 #define EVO_MASTER (0x00)
52 #define EVO_FLIP(c) (0x01 + (c))
53 #define EVO_OVLY(c) (0x05 + (c))
54 #define EVO_OIMM(c) (0x09 + (c))
55 #define EVO_CURS(c) (0x0d + (c))
56
57 /* offsets in shared sync bo of various structures */
58 #define EVO_SYNC(c, o) ((c) * 0x0100 + (o))
59 #define EVO_MAST_NTFY EVO_SYNC( 0, 0x00)
60 #define EVO_FLIP_SEM0(c) EVO_SYNC((c) + 1, 0x00)
61 #define EVO_FLIP_SEM1(c) EVO_SYNC((c) + 1, 0x10)
62
63 #define EVO_CORE_HANDLE (0xd1500000)
64 #define EVO_CHAN_HANDLE(t,i) (0xd15c0000 | (((t) & 0x00ff) << 8) | (i))
65 #define EVO_CHAN_OCLASS(t,c) ((nv_hclass(c) & 0xff00) | ((t) & 0x00ff))
66 #define EVO_PUSH_HANDLE(t,i) (0xd15b0000 | (i) | \
67 (((NV50_DISP_##t##_CLASS) & 0x00ff) << 8))
68
69 /******************************************************************************
70 * EVO channel
71 *****************************************************************************/
72
73 struct nv50_chan {
74 struct nouveau_object *user;
75 u32 handle;
76 };
77
78 static int
79 nv50_chan_create(struct nouveau_object *core, u32 bclass, u8 head,
80 void *data, u32 size, struct nv50_chan *chan)
81 {
82 struct nouveau_object *client = nv_pclass(core, NV_CLIENT_CLASS);
83 const u32 oclass = EVO_CHAN_OCLASS(bclass, core);
84 const u32 handle = EVO_CHAN_HANDLE(bclass, head);
85 int ret;
86
87 ret = nouveau_object_new(client, EVO_CORE_HANDLE, handle,
88 oclass, data, size, &chan->user);
89 if (ret)
90 return ret;
91
92 chan->handle = handle;
93 return 0;
94 }
95
96 static void
97 nv50_chan_destroy(struct nouveau_object *core, struct nv50_chan *chan)
98 {
99 struct nouveau_object *client = nv_pclass(core, NV_CLIENT_CLASS);
100 if (chan->handle)
101 nouveau_object_del(client, EVO_CORE_HANDLE, chan->handle);
102 }
103
104 /******************************************************************************
105 * PIO EVO channel
106 *****************************************************************************/
107
108 struct nv50_pioc {
109 struct nv50_chan base;
110 };
111
112 static void
113 nv50_pioc_destroy(struct nouveau_object *core, struct nv50_pioc *pioc)
114 {
115 nv50_chan_destroy(core, &pioc->base);
116 }
117
118 static int
119 nv50_pioc_create(struct nouveau_object *core, u32 bclass, u8 head,
120 void *data, u32 size, struct nv50_pioc *pioc)
121 {
122 return nv50_chan_create(core, bclass, head, data, size, &pioc->base);
123 }
124
125 /******************************************************************************
126 * DMA EVO channel
127 *****************************************************************************/
128
129 struct nv50_dmac {
130 struct nv50_chan base;
131 dma_addr_t handle;
132 u32 *ptr;
133
134 /* Protects against concurrent pushbuf access to this channel, lock is
135 * grabbed by evo_wait (if the pushbuf reservation is successful) and
136 * dropped again by evo_kick. */
137 struct mutex lock;
138 };
139
140 static void
141 nv50_dmac_destroy(struct nouveau_object *core, struct nv50_dmac *dmac)
142 {
143 if (dmac->ptr) {
144 struct pci_dev *pdev = nv_device(core)->pdev;
145 pci_free_consistent(pdev, PAGE_SIZE, dmac->ptr, dmac->handle);
146 }
147
148 nv50_chan_destroy(core, &dmac->base);
149 }
150
151 static int
152 nv50_dmac_create_fbdma(struct nouveau_object *core, u32 parent)
153 {
154 struct nouveau_fb *pfb = nouveau_fb(core);
155 struct nouveau_object *client = nv_pclass(core, NV_CLIENT_CLASS);
156 struct nouveau_object *object;
157 int ret = nouveau_object_new(client, parent, NvEvoVRAM_LP,
158 NV_DMA_IN_MEMORY_CLASS,
159 &(struct nv_dma_class) {
160 .flags = NV_DMA_TARGET_VRAM |
161 NV_DMA_ACCESS_RDWR,
162 .start = 0,
163 .limit = pfb->ram->size - 1,
164 .conf0 = NV50_DMA_CONF0_ENABLE |
165 NV50_DMA_CONF0_PART_256,
166 }, sizeof(struct nv_dma_class), &object);
167 if (ret)
168 return ret;
169
170 ret = nouveau_object_new(client, parent, NvEvoFB16,
171 NV_DMA_IN_MEMORY_CLASS,
172 &(struct nv_dma_class) {
173 .flags = NV_DMA_TARGET_VRAM |
174 NV_DMA_ACCESS_RDWR,
175 .start = 0,
176 .limit = pfb->ram->size - 1,
177 .conf0 = NV50_DMA_CONF0_ENABLE | 0x70 |
178 NV50_DMA_CONF0_PART_256,
179 }, sizeof(struct nv_dma_class), &object);
180 if (ret)
181 return ret;
182
183 ret = nouveau_object_new(client, parent, NvEvoFB32,
184 NV_DMA_IN_MEMORY_CLASS,
185 &(struct nv_dma_class) {
186 .flags = NV_DMA_TARGET_VRAM |
187 NV_DMA_ACCESS_RDWR,
188 .start = 0,
189 .limit = pfb->ram->size - 1,
190 .conf0 = NV50_DMA_CONF0_ENABLE | 0x7a |
191 NV50_DMA_CONF0_PART_256,
192 }, sizeof(struct nv_dma_class), &object);
193 return ret;
194 }
195
196 static int
197 nvc0_dmac_create_fbdma(struct nouveau_object *core, u32 parent)
198 {
199 struct nouveau_fb *pfb = nouveau_fb(core);
200 struct nouveau_object *client = nv_pclass(core, NV_CLIENT_CLASS);
201 struct nouveau_object *object;
202 int ret = nouveau_object_new(client, parent, NvEvoVRAM_LP,
203 NV_DMA_IN_MEMORY_CLASS,
204 &(struct nv_dma_class) {
205 .flags = NV_DMA_TARGET_VRAM |
206 NV_DMA_ACCESS_RDWR,
207 .start = 0,
208 .limit = pfb->ram->size - 1,
209 .conf0 = NVC0_DMA_CONF0_ENABLE,
210 }, sizeof(struct nv_dma_class), &object);
211 if (ret)
212 return ret;
213
214 ret = nouveau_object_new(client, parent, NvEvoFB16,
215 NV_DMA_IN_MEMORY_CLASS,
216 &(struct nv_dma_class) {
217 .flags = NV_DMA_TARGET_VRAM |
218 NV_DMA_ACCESS_RDWR,
219 .start = 0,
220 .limit = pfb->ram->size - 1,
221 .conf0 = NVC0_DMA_CONF0_ENABLE | 0xfe,
222 }, sizeof(struct nv_dma_class), &object);
223 if (ret)
224 return ret;
225
226 ret = nouveau_object_new(client, parent, NvEvoFB32,
227 NV_DMA_IN_MEMORY_CLASS,
228 &(struct nv_dma_class) {
229 .flags = NV_DMA_TARGET_VRAM |
230 NV_DMA_ACCESS_RDWR,
231 .start = 0,
232 .limit = pfb->ram->size - 1,
233 .conf0 = NVC0_DMA_CONF0_ENABLE | 0xfe,
234 }, sizeof(struct nv_dma_class), &object);
235 return ret;
236 }
237
238 static int
239 nvd0_dmac_create_fbdma(struct nouveau_object *core, u32 parent)
240 {
241 struct nouveau_fb *pfb = nouveau_fb(core);
242 struct nouveau_object *client = nv_pclass(core, NV_CLIENT_CLASS);
243 struct nouveau_object *object;
244 int ret = nouveau_object_new(client, parent, NvEvoVRAM_LP,
245 NV_DMA_IN_MEMORY_CLASS,
246 &(struct nv_dma_class) {
247 .flags = NV_DMA_TARGET_VRAM |
248 NV_DMA_ACCESS_RDWR,
249 .start = 0,
250 .limit = pfb->ram->size - 1,
251 .conf0 = NVD0_DMA_CONF0_ENABLE |
252 NVD0_DMA_CONF0_PAGE_LP,
253 }, sizeof(struct nv_dma_class), &object);
254 if (ret)
255 return ret;
256
257 ret = nouveau_object_new(client, parent, NvEvoFB32,
258 NV_DMA_IN_MEMORY_CLASS,
259 &(struct nv_dma_class) {
260 .flags = NV_DMA_TARGET_VRAM |
261 NV_DMA_ACCESS_RDWR,
262 .start = 0,
263 .limit = pfb->ram->size - 1,
264 .conf0 = NVD0_DMA_CONF0_ENABLE | 0xfe |
265 NVD0_DMA_CONF0_PAGE_LP,
266 }, sizeof(struct nv_dma_class), &object);
267 return ret;
268 }
269
270 static int
271 nv50_dmac_create(struct nouveau_object *core, u32 bclass, u8 head,
272 void *data, u32 size, u64 syncbuf,
273 struct nv50_dmac *dmac)
274 {
275 struct nouveau_fb *pfb = nouveau_fb(core);
276 struct nouveau_object *client = nv_pclass(core, NV_CLIENT_CLASS);
277 struct nouveau_object *object;
278 u32 pushbuf = *(u32 *)data;
279 int ret;
280
281 mutex_init(&dmac->lock);
282
283 dmac->ptr = pci_alloc_consistent(nv_device(core)->pdev, PAGE_SIZE,
284 &dmac->handle);
285 if (!dmac->ptr)
286 return -ENOMEM;
287
288 ret = nouveau_object_new(client, NVDRM_DEVICE, pushbuf,
289 NV_DMA_FROM_MEMORY_CLASS,
290 &(struct nv_dma_class) {
291 .flags = NV_DMA_TARGET_PCI_US |
292 NV_DMA_ACCESS_RD,
293 .start = dmac->handle + 0x0000,
294 .limit = dmac->handle + 0x0fff,
295 }, sizeof(struct nv_dma_class), &object);
296 if (ret)
297 return ret;
298
299 ret = nv50_chan_create(core, bclass, head, data, size, &dmac->base);
300 if (ret)
301 return ret;
302
303 ret = nouveau_object_new(client, dmac->base.handle, NvEvoSync,
304 NV_DMA_IN_MEMORY_CLASS,
305 &(struct nv_dma_class) {
306 .flags = NV_DMA_TARGET_VRAM |
307 NV_DMA_ACCESS_RDWR,
308 .start = syncbuf + 0x0000,
309 .limit = syncbuf + 0x0fff,
310 }, sizeof(struct nv_dma_class), &object);
311 if (ret)
312 return ret;
313
314 ret = nouveau_object_new(client, dmac->base.handle, NvEvoVRAM,
315 NV_DMA_IN_MEMORY_CLASS,
316 &(struct nv_dma_class) {
317 .flags = NV_DMA_TARGET_VRAM |
318 NV_DMA_ACCESS_RDWR,
319 .start = 0,
320 .limit = pfb->ram->size - 1,
321 }, sizeof(struct nv_dma_class), &object);
322 if (ret)
323 return ret;
324
325 if (nv_device(core)->card_type < NV_C0)
326 ret = nv50_dmac_create_fbdma(core, dmac->base.handle);
327 else
328 if (nv_device(core)->card_type < NV_D0)
329 ret = nvc0_dmac_create_fbdma(core, dmac->base.handle);
330 else
331 ret = nvd0_dmac_create_fbdma(core, dmac->base.handle);
332 return ret;
333 }
334
335 struct nv50_mast {
336 struct nv50_dmac base;
337 };
338
339 struct nv50_curs {
340 struct nv50_pioc base;
341 };
342
343 struct nv50_sync {
344 struct nv50_dmac base;
345 u32 addr;
346 u32 data;
347 };
348
349 struct nv50_ovly {
350 struct nv50_dmac base;
351 };
352
353 struct nv50_oimm {
354 struct nv50_pioc base;
355 };
356
357 struct nv50_head {
358 struct nouveau_crtc base;
359 struct nouveau_bo *image;
360 struct nv50_curs curs;
361 struct nv50_sync sync;
362 struct nv50_ovly ovly;
363 struct nv50_oimm oimm;
364 };
365
366 #define nv50_head(c) ((struct nv50_head *)nouveau_crtc(c))
367 #define nv50_curs(c) (&nv50_head(c)->curs)
368 #define nv50_sync(c) (&nv50_head(c)->sync)
369 #define nv50_ovly(c) (&nv50_head(c)->ovly)
370 #define nv50_oimm(c) (&nv50_head(c)->oimm)
371 #define nv50_chan(c) (&(c)->base.base)
372 #define nv50_vers(c) nv_mclass(nv50_chan(c)->user)
373
374 struct nv50_disp {
375 struct nouveau_object *core;
376 struct nv50_mast mast;
377
378 u32 modeset;
379
380 struct nouveau_bo *sync;
381 };
382
383 static struct nv50_disp *
384 nv50_disp(struct drm_device *dev)
385 {
386 return nouveau_display(dev)->priv;
387 }
388
389 #define nv50_mast(d) (&nv50_disp(d)->mast)
390
391 static struct drm_crtc *
392 nv50_display_crtc_get(struct drm_encoder *encoder)
393 {
394 return nouveau_encoder(encoder)->crtc;
395 }
396
397 /******************************************************************************
398 * EVO channel helpers
399 *****************************************************************************/
400 static u32 *
401 evo_wait(void *evoc, int nr)
402 {
403 struct nv50_dmac *dmac = evoc;
404 u32 put = nv_ro32(dmac->base.user, 0x0000) / 4;
405
406 mutex_lock(&dmac->lock);
407 if (put + nr >= (PAGE_SIZE / 4) - 8) {
408 dmac->ptr[put] = 0x20000000;
409
410 nv_wo32(dmac->base.user, 0x0000, 0x00000000);
411 if (!nv_wait(dmac->base.user, 0x0004, ~0, 0x00000000)) {
412 mutex_unlock(&dmac->lock);
413 NV_ERROR(dmac->base.user, "channel stalled\n");
414 return NULL;
415 }
416
417 put = 0;
418 }
419
420 return dmac->ptr + put;
421 }
422
423 static void
424 evo_kick(u32 *push, void *evoc)
425 {
426 struct nv50_dmac *dmac = evoc;
427 nv_wo32(dmac->base.user, 0x0000, (push - dmac->ptr) << 2);
428 mutex_unlock(&dmac->lock);
429 }
430
431 #define evo_mthd(p,m,s) *((p)++) = (((s) << 18) | (m))
432 #define evo_data(p,d) *((p)++) = (d)
433
434 static bool
435 evo_sync_wait(void *data)
436 {
437 if (nouveau_bo_rd32(data, EVO_MAST_NTFY) != 0x00000000)
438 return true;
439 usleep_range(1, 2);
440 return false;
441 }
442
443 static int
444 evo_sync(struct drm_device *dev)
445 {
446 struct nouveau_device *device = nouveau_dev(dev);
447 struct nv50_disp *disp = nv50_disp(dev);
448 struct nv50_mast *mast = nv50_mast(dev);
449 u32 *push = evo_wait(mast, 8);
450 if (push) {
451 nouveau_bo_wr32(disp->sync, EVO_MAST_NTFY, 0x00000000);
452 evo_mthd(push, 0x0084, 1);
453 evo_data(push, 0x80000000 | EVO_MAST_NTFY);
454 evo_mthd(push, 0x0080, 2);
455 evo_data(push, 0x00000000);
456 evo_data(push, 0x00000000);
457 evo_kick(push, mast);
458 if (nv_wait_cb(device, evo_sync_wait, disp->sync))
459 return 0;
460 }
461
462 return -EBUSY;
463 }
464
465 /******************************************************************************
466 * Page flipping channel
467 *****************************************************************************/
468 struct nouveau_bo *
469 nv50_display_crtc_sema(struct drm_device *dev, int crtc)
470 {
471 return nv50_disp(dev)->sync;
472 }
473
474 struct nv50_display_flip {
475 struct nv50_disp *disp;
476 struct nv50_sync *chan;
477 };
478
479 static bool
480 nv50_display_flip_wait(void *data)
481 {
482 struct nv50_display_flip *flip = data;
483 if (nouveau_bo_rd32(flip->disp->sync, flip->chan->addr / 4) ==
484 flip->chan->data)
485 return true;
486 usleep_range(1, 2);
487 return false;
488 }
489
490 void
491 nv50_display_flip_stop(struct drm_crtc *crtc)
492 {
493 struct nouveau_device *device = nouveau_dev(crtc->dev);
494 struct nv50_display_flip flip = {
495 .disp = nv50_disp(crtc->dev),
496 .chan = nv50_sync(crtc),
497 };
498 u32 *push;
499
500 push = evo_wait(flip.chan, 8);
501 if (push) {
502 evo_mthd(push, 0x0084, 1);
503 evo_data(push, 0x00000000);
504 evo_mthd(push, 0x0094, 1);
505 evo_data(push, 0x00000000);
506 evo_mthd(push, 0x00c0, 1);
507 evo_data(push, 0x00000000);
508 evo_mthd(push, 0x0080, 1);
509 evo_data(push, 0x00000000);
510 evo_kick(push, flip.chan);
511 }
512
513 nv_wait_cb(device, nv50_display_flip_wait, &flip);
514 }
515
516 int
517 nv50_display_flip_next(struct drm_crtc *crtc, struct drm_framebuffer *fb,
518 struct nouveau_channel *chan, u32 swap_interval)
519 {
520 struct nouveau_framebuffer *nv_fb = nouveau_framebuffer(fb);
521 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
522 struct nv50_head *head = nv50_head(crtc);
523 struct nv50_sync *sync = nv50_sync(crtc);
524 u32 *push;
525 int ret;
526
527 swap_interval <<= 4;
528 if (swap_interval == 0)
529 swap_interval |= 0x100;
530 if (chan == NULL)
531 evo_sync(crtc->dev);
532
533 push = evo_wait(sync, 128);
534 if (unlikely(push == NULL))
535 return -EBUSY;
536
537 if (chan && nv_mclass(chan->object) < NV84_CHANNEL_IND_CLASS) {
538 ret = RING_SPACE(chan, 8);
539 if (ret)
540 return ret;
541
542 BEGIN_NV04(chan, 0, NV11_SUBCHAN_DMA_SEMAPHORE, 2);
543 OUT_RING (chan, NvEvoSema0 + nv_crtc->index);
544 OUT_RING (chan, sync->addr ^ 0x10);
545 BEGIN_NV04(chan, 0, NV11_SUBCHAN_SEMAPHORE_RELEASE, 1);
546 OUT_RING (chan, sync->data + 1);
547 BEGIN_NV04(chan, 0, NV11_SUBCHAN_SEMAPHORE_OFFSET, 2);
548 OUT_RING (chan, sync->addr);
549 OUT_RING (chan, sync->data);
550 } else
551 if (chan && nv_mclass(chan->object) < NVC0_CHANNEL_IND_CLASS) {
552 u64 addr = nv84_fence_crtc(chan, nv_crtc->index) + sync->addr;
553 ret = RING_SPACE(chan, 12);
554 if (ret)
555 return ret;
556
557 BEGIN_NV04(chan, 0, NV11_SUBCHAN_DMA_SEMAPHORE, 1);
558 OUT_RING (chan, chan->vram);
559 BEGIN_NV04(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4);
560 OUT_RING (chan, upper_32_bits(addr ^ 0x10));
561 OUT_RING (chan, lower_32_bits(addr ^ 0x10));
562 OUT_RING (chan, sync->data + 1);
563 OUT_RING (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_WRITE_LONG);
564 BEGIN_NV04(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4);
565 OUT_RING (chan, upper_32_bits(addr));
566 OUT_RING (chan, lower_32_bits(addr));
567 OUT_RING (chan, sync->data);
568 OUT_RING (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_ACQUIRE_EQUAL);
569 } else
570 if (chan) {
571 u64 addr = nv84_fence_crtc(chan, nv_crtc->index) + sync->addr;
572 ret = RING_SPACE(chan, 10);
573 if (ret)
574 return ret;
575
576 BEGIN_NVC0(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4);
577 OUT_RING (chan, upper_32_bits(addr ^ 0x10));
578 OUT_RING (chan, lower_32_bits(addr ^ 0x10));
579 OUT_RING (chan, sync->data + 1);
580 OUT_RING (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_WRITE_LONG |
581 NVC0_SUBCHAN_SEMAPHORE_TRIGGER_YIELD);
582 BEGIN_NVC0(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4);
583 OUT_RING (chan, upper_32_bits(addr));
584 OUT_RING (chan, lower_32_bits(addr));
585 OUT_RING (chan, sync->data);
586 OUT_RING (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_ACQUIRE_EQUAL |
587 NVC0_SUBCHAN_SEMAPHORE_TRIGGER_YIELD);
588 }
589
590 if (chan) {
591 sync->addr ^= 0x10;
592 sync->data++;
593 FIRE_RING (chan);
594 }
595
596 /* queue the flip */
597 evo_mthd(push, 0x0100, 1);
598 evo_data(push, 0xfffe0000);
599 evo_mthd(push, 0x0084, 1);
600 evo_data(push, swap_interval);
601 if (!(swap_interval & 0x00000100)) {
602 evo_mthd(push, 0x00e0, 1);
603 evo_data(push, 0x40000000);
604 }
605 evo_mthd(push, 0x0088, 4);
606 evo_data(push, sync->addr);
607 evo_data(push, sync->data++);
608 evo_data(push, sync->data);
609 evo_data(push, NvEvoSync);
610 evo_mthd(push, 0x00a0, 2);
611 evo_data(push, 0x00000000);
612 evo_data(push, 0x00000000);
613 evo_mthd(push, 0x00c0, 1);
614 evo_data(push, nv_fb->r_dma);
615 evo_mthd(push, 0x0110, 2);
616 evo_data(push, 0x00000000);
617 evo_data(push, 0x00000000);
618 if (nv50_vers(sync) < NVD0_DISP_SYNC_CLASS) {
619 evo_mthd(push, 0x0800, 5);
620 evo_data(push, nv_fb->nvbo->bo.offset >> 8);
621 evo_data(push, 0);
622 evo_data(push, (fb->height << 16) | fb->width);
623 evo_data(push, nv_fb->r_pitch);
624 evo_data(push, nv_fb->r_format);
625 } else {
626 evo_mthd(push, 0x0400, 5);
627 evo_data(push, nv_fb->nvbo->bo.offset >> 8);
628 evo_data(push, 0);
629 evo_data(push, (fb->height << 16) | fb->width);
630 evo_data(push, nv_fb->r_pitch);
631 evo_data(push, nv_fb->r_format);
632 }
633 evo_mthd(push, 0x0080, 1);
634 evo_data(push, 0x00000000);
635 evo_kick(push, sync);
636
637 nouveau_bo_ref(nv_fb->nvbo, &head->image);
638 return 0;
639 }
640
641 /******************************************************************************
642 * CRTC
643 *****************************************************************************/
644 static int
645 nv50_crtc_set_dither(struct nouveau_crtc *nv_crtc, bool update)
646 {
647 struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev);
648 struct nouveau_connector *nv_connector;
649 struct drm_connector *connector;
650 u32 *push, mode = 0x00;
651
652 nv_connector = nouveau_crtc_connector_get(nv_crtc);
653 connector = &nv_connector->base;
654 if (nv_connector->dithering_mode == DITHERING_MODE_AUTO) {
655 if (nv_crtc->base.primary->fb->depth > connector->display_info.bpc * 3)
656 mode = DITHERING_MODE_DYNAMIC2X2;
657 } else {
658 mode = nv_connector->dithering_mode;
659 }
660
661 if (nv_connector->dithering_depth == DITHERING_DEPTH_AUTO) {
662 if (connector->display_info.bpc >= 8)
663 mode |= DITHERING_DEPTH_8BPC;
664 } else {
665 mode |= nv_connector->dithering_depth;
666 }
667
668 push = evo_wait(mast, 4);
669 if (push) {
670 if (nv50_vers(mast) < NVD0_DISP_MAST_CLASS) {
671 evo_mthd(push, 0x08a0 + (nv_crtc->index * 0x0400), 1);
672 evo_data(push, mode);
673 } else
674 if (nv50_vers(mast) < NVE0_DISP_MAST_CLASS) {
675 evo_mthd(push, 0x0490 + (nv_crtc->index * 0x0300), 1);
676 evo_data(push, mode);
677 } else {
678 evo_mthd(push, 0x04a0 + (nv_crtc->index * 0x0300), 1);
679 evo_data(push, mode);
680 }
681
682 if (update) {
683 evo_mthd(push, 0x0080, 1);
684 evo_data(push, 0x00000000);
685 }
686 evo_kick(push, mast);
687 }
688
689 return 0;
690 }
691
692 static int
693 nv50_crtc_set_scale(struct nouveau_crtc *nv_crtc, bool update)
694 {
695 struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev);
696 struct drm_display_mode *omode, *umode = &nv_crtc->base.mode;
697 struct drm_crtc *crtc = &nv_crtc->base;
698 struct nouveau_connector *nv_connector;
699 int mode = DRM_MODE_SCALE_NONE;
700 u32 oX, oY, *push;
701
702 /* start off at the resolution we programmed the crtc for, this
703 * effectively handles NONE/FULL scaling
704 */
705 nv_connector = nouveau_crtc_connector_get(nv_crtc);
706 if (nv_connector && nv_connector->native_mode)
707 mode = nv_connector->scaling_mode;
708
709 if (mode != DRM_MODE_SCALE_NONE)
710 omode = nv_connector->native_mode;
711 else
712 omode = umode;
713
714 oX = omode->hdisplay;
715 oY = omode->vdisplay;
716 if (omode->flags & DRM_MODE_FLAG_DBLSCAN)
717 oY *= 2;
718
719 /* add overscan compensation if necessary, will keep the aspect
720 * ratio the same as the backend mode unless overridden by the
721 * user setting both hborder and vborder properties.
722 */
723 if (nv_connector && ( nv_connector->underscan == UNDERSCAN_ON ||
724 (nv_connector->underscan == UNDERSCAN_AUTO &&
725 nv_connector->edid &&
726 drm_detect_hdmi_monitor(nv_connector->edid)))) {
727 u32 bX = nv_connector->underscan_hborder;
728 u32 bY = nv_connector->underscan_vborder;
729 u32 aspect = (oY << 19) / oX;
730
731 if (bX) {
732 oX -= (bX * 2);
733 if (bY) oY -= (bY * 2);
734 else oY = ((oX * aspect) + (aspect / 2)) >> 19;
735 } else {
736 oX -= (oX >> 4) + 32;
737 if (bY) oY -= (bY * 2);
738 else oY = ((oX * aspect) + (aspect / 2)) >> 19;
739 }
740 }
741
742 /* handle CENTER/ASPECT scaling, taking into account the areas
743 * removed already for overscan compensation
744 */
745 switch (mode) {
746 case DRM_MODE_SCALE_CENTER:
747 oX = min((u32)umode->hdisplay, oX);
748 oY = min((u32)umode->vdisplay, oY);
749 /* fall-through */
750 case DRM_MODE_SCALE_ASPECT:
751 if (oY < oX) {
752 u32 aspect = (umode->hdisplay << 19) / umode->vdisplay;
753 oX = ((oY * aspect) + (aspect / 2)) >> 19;
754 } else {
755 u32 aspect = (umode->vdisplay << 19) / umode->hdisplay;
756 oY = ((oX * aspect) + (aspect / 2)) >> 19;
757 }
758 break;
759 default:
760 break;
761 }
762
763 push = evo_wait(mast, 8);
764 if (push) {
765 if (nv50_vers(mast) < NVD0_DISP_MAST_CLASS) {
766 /*XXX: SCALE_CTRL_ACTIVE??? */
767 evo_mthd(push, 0x08d8 + (nv_crtc->index * 0x400), 2);
768 evo_data(push, (oY << 16) | oX);
769 evo_data(push, (oY << 16) | oX);
770 evo_mthd(push, 0x08a4 + (nv_crtc->index * 0x400), 1);
771 evo_data(push, 0x00000000);
772 evo_mthd(push, 0x08c8 + (nv_crtc->index * 0x400), 1);
773 evo_data(push, umode->vdisplay << 16 | umode->hdisplay);
774 } else {
775 evo_mthd(push, 0x04c0 + (nv_crtc->index * 0x300), 3);
776 evo_data(push, (oY << 16) | oX);
777 evo_data(push, (oY << 16) | oX);
778 evo_data(push, (oY << 16) | oX);
779 evo_mthd(push, 0x0494 + (nv_crtc->index * 0x300), 1);
780 evo_data(push, 0x00000000);
781 evo_mthd(push, 0x04b8 + (nv_crtc->index * 0x300), 1);
782 evo_data(push, umode->vdisplay << 16 | umode->hdisplay);
783 }
784
785 evo_kick(push, mast);
786
787 if (update) {
788 nv50_display_flip_stop(crtc);
789 nv50_display_flip_next(crtc, crtc->primary->fb,
790 NULL, 1);
791 }
792 }
793
794 return 0;
795 }
796
797 static int
798 nv50_crtc_set_color_vibrance(struct nouveau_crtc *nv_crtc, bool update)
799 {
800 struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev);
801 u32 *push, hue, vib;
802 int adj;
803
804 adj = (nv_crtc->color_vibrance > 0) ? 50 : 0;
805 vib = ((nv_crtc->color_vibrance * 2047 + adj) / 100) & 0xfff;
806 hue = ((nv_crtc->vibrant_hue * 2047) / 100) & 0xfff;
807
808 push = evo_wait(mast, 16);
809 if (push) {
810 if (nv50_vers(mast) < NVD0_DISP_MAST_CLASS) {
811 evo_mthd(push, 0x08a8 + (nv_crtc->index * 0x400), 1);
812 evo_data(push, (hue << 20) | (vib << 8));
813 } else {
814 evo_mthd(push, 0x0498 + (nv_crtc->index * 0x300), 1);
815 evo_data(push, (hue << 20) | (vib << 8));
816 }
817
818 if (update) {
819 evo_mthd(push, 0x0080, 1);
820 evo_data(push, 0x00000000);
821 }
822 evo_kick(push, mast);
823 }
824
825 return 0;
826 }
827
828 static int
829 nv50_crtc_set_image(struct nouveau_crtc *nv_crtc, struct drm_framebuffer *fb,
830 int x, int y, bool update)
831 {
832 struct nouveau_framebuffer *nvfb = nouveau_framebuffer(fb);
833 struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev);
834 u32 *push;
835
836 push = evo_wait(mast, 16);
837 if (push) {
838 if (nv50_vers(mast) < NVD0_DISP_MAST_CLASS) {
839 evo_mthd(push, 0x0860 + (nv_crtc->index * 0x400), 1);
840 evo_data(push, nvfb->nvbo->bo.offset >> 8);
841 evo_mthd(push, 0x0868 + (nv_crtc->index * 0x400), 3);
842 evo_data(push, (fb->height << 16) | fb->width);
843 evo_data(push, nvfb->r_pitch);
844 evo_data(push, nvfb->r_format);
845 evo_mthd(push, 0x08c0 + (nv_crtc->index * 0x400), 1);
846 evo_data(push, (y << 16) | x);
847 if (nv50_vers(mast) > NV50_DISP_MAST_CLASS) {
848 evo_mthd(push, 0x0874 + (nv_crtc->index * 0x400), 1);
849 evo_data(push, nvfb->r_dma);
850 }
851 } else {
852 evo_mthd(push, 0x0460 + (nv_crtc->index * 0x300), 1);
853 evo_data(push, nvfb->nvbo->bo.offset >> 8);
854 evo_mthd(push, 0x0468 + (nv_crtc->index * 0x300), 4);
855 evo_data(push, (fb->height << 16) | fb->width);
856 evo_data(push, nvfb->r_pitch);
857 evo_data(push, nvfb->r_format);
858 evo_data(push, nvfb->r_dma);
859 evo_mthd(push, 0x04b0 + (nv_crtc->index * 0x300), 1);
860 evo_data(push, (y << 16) | x);
861 }
862
863 if (update) {
864 evo_mthd(push, 0x0080, 1);
865 evo_data(push, 0x00000000);
866 }
867 evo_kick(push, mast);
868 }
869
870 nv_crtc->fb.tile_flags = nvfb->r_dma;
871 return 0;
872 }
873
874 static void
875 nv50_crtc_cursor_show(struct nouveau_crtc *nv_crtc)
876 {
877 struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev);
878 u32 *push = evo_wait(mast, 16);
879 if (push) {
880 if (nv50_vers(mast) < NV84_DISP_MAST_CLASS) {
881 evo_mthd(push, 0x0880 + (nv_crtc->index * 0x400), 2);
882 evo_data(push, 0x85000000);
883 evo_data(push, nv_crtc->cursor.nvbo->bo.offset >> 8);
884 } else
885 if (nv50_vers(mast) < NVD0_DISP_MAST_CLASS) {
886 evo_mthd(push, 0x0880 + (nv_crtc->index * 0x400), 2);
887 evo_data(push, 0x85000000);
888 evo_data(push, nv_crtc->cursor.nvbo->bo.offset >> 8);
889 evo_mthd(push, 0x089c + (nv_crtc->index * 0x400), 1);
890 evo_data(push, NvEvoVRAM);
891 } else {
892 evo_mthd(push, 0x0480 + (nv_crtc->index * 0x300), 2);
893 evo_data(push, 0x85000000);
894 evo_data(push, nv_crtc->cursor.nvbo->bo.offset >> 8);
895 evo_mthd(push, 0x048c + (nv_crtc->index * 0x300), 1);
896 evo_data(push, NvEvoVRAM);
897 }
898 evo_kick(push, mast);
899 }
900 }
901
902 static void
903 nv50_crtc_cursor_hide(struct nouveau_crtc *nv_crtc)
904 {
905 struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev);
906 u32 *push = evo_wait(mast, 16);
907 if (push) {
908 if (nv50_vers(mast) < NV84_DISP_MAST_CLASS) {
909 evo_mthd(push, 0x0880 + (nv_crtc->index * 0x400), 1);
910 evo_data(push, 0x05000000);
911 } else
912 if (nv50_vers(mast) < NVD0_DISP_MAST_CLASS) {
913 evo_mthd(push, 0x0880 + (nv_crtc->index * 0x400), 1);
914 evo_data(push, 0x05000000);
915 evo_mthd(push, 0x089c + (nv_crtc->index * 0x400), 1);
916 evo_data(push, 0x00000000);
917 } else {
918 evo_mthd(push, 0x0480 + (nv_crtc->index * 0x300), 1);
919 evo_data(push, 0x05000000);
920 evo_mthd(push, 0x048c + (nv_crtc->index * 0x300), 1);
921 evo_data(push, 0x00000000);
922 }
923 evo_kick(push, mast);
924 }
925 }
926
927 static void
928 nv50_crtc_cursor_show_hide(struct nouveau_crtc *nv_crtc, bool show, bool update)
929 {
930 struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev);
931
932 if (show)
933 nv50_crtc_cursor_show(nv_crtc);
934 else
935 nv50_crtc_cursor_hide(nv_crtc);
936
937 if (update) {
938 u32 *push = evo_wait(mast, 2);
939 if (push) {
940 evo_mthd(push, 0x0080, 1);
941 evo_data(push, 0x00000000);
942 evo_kick(push, mast);
943 }
944 }
945 }
946
947 static void
948 nv50_crtc_dpms(struct drm_crtc *crtc, int mode)
949 {
950 }
951
952 static void
953 nv50_crtc_prepare(struct drm_crtc *crtc)
954 {
955 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
956 struct nv50_mast *mast = nv50_mast(crtc->dev);
957 u32 *push;
958
959 nv50_display_flip_stop(crtc);
960
961 push = evo_wait(mast, 6);
962 if (push) {
963 if (nv50_vers(mast) < NV84_DISP_MAST_CLASS) {
964 evo_mthd(push, 0x0874 + (nv_crtc->index * 0x400), 1);
965 evo_data(push, 0x00000000);
966 evo_mthd(push, 0x0840 + (nv_crtc->index * 0x400), 1);
967 evo_data(push, 0x40000000);
968 } else
969 if (nv50_vers(mast) < NVD0_DISP_MAST_CLASS) {
970 evo_mthd(push, 0x0874 + (nv_crtc->index * 0x400), 1);
971 evo_data(push, 0x00000000);
972 evo_mthd(push, 0x0840 + (nv_crtc->index * 0x400), 1);
973 evo_data(push, 0x40000000);
974 evo_mthd(push, 0x085c + (nv_crtc->index * 0x400), 1);
975 evo_data(push, 0x00000000);
976 } else {
977 evo_mthd(push, 0x0474 + (nv_crtc->index * 0x300), 1);
978 evo_data(push, 0x00000000);
979 evo_mthd(push, 0x0440 + (nv_crtc->index * 0x300), 1);
980 evo_data(push, 0x03000000);
981 evo_mthd(push, 0x045c + (nv_crtc->index * 0x300), 1);
982 evo_data(push, 0x00000000);
983 }
984
985 evo_kick(push, mast);
986 }
987
988 nv50_crtc_cursor_show_hide(nv_crtc, false, false);
989 }
990
991 static void
992 nv50_crtc_commit(struct drm_crtc *crtc)
993 {
994 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
995 struct nv50_mast *mast = nv50_mast(crtc->dev);
996 u32 *push;
997
998 push = evo_wait(mast, 32);
999 if (push) {
1000 if (nv50_vers(mast) < NV84_DISP_MAST_CLASS) {
1001 evo_mthd(push, 0x0874 + (nv_crtc->index * 0x400), 1);
1002 evo_data(push, NvEvoVRAM_LP);
1003 evo_mthd(push, 0x0840 + (nv_crtc->index * 0x400), 2);
1004 evo_data(push, 0xc0000000);
1005 evo_data(push, nv_crtc->lut.nvbo->bo.offset >> 8);
1006 } else
1007 if (nv50_vers(mast) < NVD0_DISP_MAST_CLASS) {
1008 evo_mthd(push, 0x0874 + (nv_crtc->index * 0x400), 1);
1009 evo_data(push, nv_crtc->fb.tile_flags);
1010 evo_mthd(push, 0x0840 + (nv_crtc->index * 0x400), 2);
1011 evo_data(push, 0xc0000000);
1012 evo_data(push, nv_crtc->lut.nvbo->bo.offset >> 8);
1013 evo_mthd(push, 0x085c + (nv_crtc->index * 0x400), 1);
1014 evo_data(push, NvEvoVRAM);
1015 } else {
1016 evo_mthd(push, 0x0474 + (nv_crtc->index * 0x300), 1);
1017 evo_data(push, nv_crtc->fb.tile_flags);
1018 evo_mthd(push, 0x0440 + (nv_crtc->index * 0x300), 4);
1019 evo_data(push, 0x83000000);
1020 evo_data(push, nv_crtc->lut.nvbo->bo.offset >> 8);
1021 evo_data(push, 0x00000000);
1022 evo_data(push, 0x00000000);
1023 evo_mthd(push, 0x045c + (nv_crtc->index * 0x300), 1);
1024 evo_data(push, NvEvoVRAM);
1025 evo_mthd(push, 0x0430 + (nv_crtc->index * 0x300), 1);
1026 evo_data(push, 0xffffff00);
1027 }
1028
1029 evo_kick(push, mast);
1030 }
1031
1032 nv50_crtc_cursor_show_hide(nv_crtc, nv_crtc->cursor.visible, true);
1033 nv50_display_flip_next(crtc, crtc->primary->fb, NULL, 1);
1034 }
1035
1036 static bool
1037 nv50_crtc_mode_fixup(struct drm_crtc *crtc, const struct drm_display_mode *mode,
1038 struct drm_display_mode *adjusted_mode)
1039 {
1040 drm_mode_set_crtcinfo(adjusted_mode, CRTC_INTERLACE_HALVE_V);
1041 return true;
1042 }
1043
1044 static int
1045 nv50_crtc_swap_fbs(struct drm_crtc *crtc, struct drm_framebuffer *old_fb)
1046 {
1047 struct nouveau_framebuffer *nvfb = nouveau_framebuffer(crtc->primary->fb);
1048 struct nv50_head *head = nv50_head(crtc);
1049 int ret;
1050
1051 ret = nouveau_bo_pin(nvfb->nvbo, TTM_PL_FLAG_VRAM);
1052 if (ret == 0) {
1053 if (head->image)
1054 nouveau_bo_unpin(head->image);
1055 nouveau_bo_ref(nvfb->nvbo, &head->image);
1056 }
1057
1058 return ret;
1059 }
1060
1061 static int
1062 nv50_crtc_mode_set(struct drm_crtc *crtc, struct drm_display_mode *umode,
1063 struct drm_display_mode *mode, int x, int y,
1064 struct drm_framebuffer *old_fb)
1065 {
1066 struct nv50_mast *mast = nv50_mast(crtc->dev);
1067 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
1068 struct nouveau_connector *nv_connector;
1069 u32 ilace = (mode->flags & DRM_MODE_FLAG_INTERLACE) ? 2 : 1;
1070 u32 vscan = (mode->flags & DRM_MODE_FLAG_DBLSCAN) ? 2 : 1;
1071 u32 hactive, hsynce, hbackp, hfrontp, hblanke, hblanks;
1072 u32 vactive, vsynce, vbackp, vfrontp, vblanke, vblanks;
1073 u32 vblan2e = 0, vblan2s = 1;
1074 u32 *push;
1075 int ret;
1076
1077 hactive = mode->htotal;
1078 hsynce = mode->hsync_end - mode->hsync_start - 1;
1079 hbackp = mode->htotal - mode->hsync_end;
1080 hblanke = hsynce + hbackp;
1081 hfrontp = mode->hsync_start - mode->hdisplay;
1082 hblanks = mode->htotal - hfrontp - 1;
1083
1084 vactive = mode->vtotal * vscan / ilace;
1085 vsynce = ((mode->vsync_end - mode->vsync_start) * vscan / ilace) - 1;
1086 vbackp = (mode->vtotal - mode->vsync_end) * vscan / ilace;
1087 vblanke = vsynce + vbackp;
1088 vfrontp = (mode->vsync_start - mode->vdisplay) * vscan / ilace;
1089 vblanks = vactive - vfrontp - 1;
1090 if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
1091 vblan2e = vactive + vsynce + vbackp;
1092 vblan2s = vblan2e + (mode->vdisplay * vscan / ilace);
1093 vactive = (vactive * 2) + 1;
1094 }
1095
1096 ret = nv50_crtc_swap_fbs(crtc, old_fb);
1097 if (ret)
1098 return ret;
1099
1100 push = evo_wait(mast, 64);
1101 if (push) {
1102 if (nv50_vers(mast) < NVD0_DISP_MAST_CLASS) {
1103 evo_mthd(push, 0x0804 + (nv_crtc->index * 0x400), 2);
1104 evo_data(push, 0x00800000 | mode->clock);
1105 evo_data(push, (ilace == 2) ? 2 : 0);
1106 evo_mthd(push, 0x0810 + (nv_crtc->index * 0x400), 6);
1107 evo_data(push, 0x00000000);
1108 evo_data(push, (vactive << 16) | hactive);
1109 evo_data(push, ( vsynce << 16) | hsynce);
1110 evo_data(push, (vblanke << 16) | hblanke);
1111 evo_data(push, (vblanks << 16) | hblanks);
1112 evo_data(push, (vblan2e << 16) | vblan2s);
1113 evo_mthd(push, 0x082c + (nv_crtc->index * 0x400), 1);
1114 evo_data(push, 0x00000000);
1115 evo_mthd(push, 0x0900 + (nv_crtc->index * 0x400), 2);
1116 evo_data(push, 0x00000311);
1117 evo_data(push, 0x00000100);
1118 } else {
1119 evo_mthd(push, 0x0410 + (nv_crtc->index * 0x300), 6);
1120 evo_data(push, 0x00000000);
1121 evo_data(push, (vactive << 16) | hactive);
1122 evo_data(push, ( vsynce << 16) | hsynce);
1123 evo_data(push, (vblanke << 16) | hblanke);
1124 evo_data(push, (vblanks << 16) | hblanks);
1125 evo_data(push, (vblan2e << 16) | vblan2s);
1126 evo_mthd(push, 0x042c + (nv_crtc->index * 0x300), 1);
1127 evo_data(push, 0x00000000); /* ??? */
1128 evo_mthd(push, 0x0450 + (nv_crtc->index * 0x300), 3);
1129 evo_data(push, mode->clock * 1000);
1130 evo_data(push, 0x00200000); /* ??? */
1131 evo_data(push, mode->clock * 1000);
1132 evo_mthd(push, 0x04d0 + (nv_crtc->index * 0x300), 2);
1133 evo_data(push, 0x00000311);
1134 evo_data(push, 0x00000100);
1135 }
1136
1137 evo_kick(push, mast);
1138 }
1139
1140 nv_connector = nouveau_crtc_connector_get(nv_crtc);
1141 nv50_crtc_set_dither(nv_crtc, false);
1142 nv50_crtc_set_scale(nv_crtc, false);
1143 nv50_crtc_set_color_vibrance(nv_crtc, false);
1144 nv50_crtc_set_image(nv_crtc, crtc->primary->fb, x, y, false);
1145 return 0;
1146 }
1147
1148 static int
1149 nv50_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y,
1150 struct drm_framebuffer *old_fb)
1151 {
1152 struct nouveau_drm *drm = nouveau_drm(crtc->dev);
1153 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
1154 int ret;
1155
1156 if (!crtc->primary->fb) {
1157 NV_DEBUG(drm, "No FB bound\n");
1158 return 0;
1159 }
1160
1161 ret = nv50_crtc_swap_fbs(crtc, old_fb);
1162 if (ret)
1163 return ret;
1164
1165 nv50_display_flip_stop(crtc);
1166 nv50_crtc_set_image(nv_crtc, crtc->primary->fb, x, y, true);
1167 nv50_display_flip_next(crtc, crtc->primary->fb, NULL, 1);
1168 return 0;
1169 }
1170
1171 static int
1172 nv50_crtc_mode_set_base_atomic(struct drm_crtc *crtc,
1173 struct drm_framebuffer *fb, int x, int y,
1174 enum mode_set_atomic state)
1175 {
1176 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
1177 nv50_display_flip_stop(crtc);
1178 nv50_crtc_set_image(nv_crtc, fb, x, y, true);
1179 return 0;
1180 }
1181
1182 static void
1183 nv50_crtc_lut_load(struct drm_crtc *crtc)
1184 {
1185 struct nv50_disp *disp = nv50_disp(crtc->dev);
1186 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
1187 void __iomem *lut = nvbo_kmap_obj_iovirtual(nv_crtc->lut.nvbo);
1188 int i;
1189
1190 for (i = 0; i < 256; i++) {
1191 u16 r = nv_crtc->lut.r[i] >> 2;
1192 u16 g = nv_crtc->lut.g[i] >> 2;
1193 u16 b = nv_crtc->lut.b[i] >> 2;
1194
1195 if (nv_mclass(disp->core) < NVD0_DISP_CLASS) {
1196 writew(r + 0x0000, lut + (i * 0x08) + 0);
1197 writew(g + 0x0000, lut + (i * 0x08) + 2);
1198 writew(b + 0x0000, lut + (i * 0x08) + 4);
1199 } else {
1200 writew(r + 0x6000, lut + (i * 0x20) + 0);
1201 writew(g + 0x6000, lut + (i * 0x20) + 2);
1202 writew(b + 0x6000, lut + (i * 0x20) + 4);
1203 }
1204 }
1205 }
1206
1207 static void
1208 nv50_crtc_disable(struct drm_crtc *crtc)
1209 {
1210 struct nv50_head *head = nv50_head(crtc);
1211 evo_sync(crtc->dev);
1212 if (head->image)
1213 nouveau_bo_unpin(head->image);
1214 nouveau_bo_ref(NULL, &head->image);
1215 }
1216
1217 static int
1218 nv50_crtc_cursor_set(struct drm_crtc *crtc, struct drm_file *file_priv,
1219 uint32_t handle, uint32_t width, uint32_t height)
1220 {
1221 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
1222 struct drm_device *dev = crtc->dev;
1223 struct drm_gem_object *gem;
1224 struct nouveau_bo *nvbo;
1225 bool visible = (handle != 0);
1226 int i, ret = 0;
1227
1228 if (visible) {
1229 if (width != 64 || height != 64)
1230 return -EINVAL;
1231
1232 gem = drm_gem_object_lookup(dev, file_priv, handle);
1233 if (unlikely(!gem))
1234 return -ENOENT;
1235 nvbo = nouveau_gem_object(gem);
1236
1237 ret = nouveau_bo_map(nvbo);
1238 if (ret == 0) {
1239 for (i = 0; i < 64 * 64; i++) {
1240 u32 v = nouveau_bo_rd32(nvbo, i);
1241 nouveau_bo_wr32(nv_crtc->cursor.nvbo, i, v);
1242 }
1243 nouveau_bo_unmap(nvbo);
1244 }
1245
1246 drm_gem_object_unreference_unlocked(gem);
1247 }
1248
1249 if (visible != nv_crtc->cursor.visible) {
1250 nv50_crtc_cursor_show_hide(nv_crtc, visible, true);
1251 nv_crtc->cursor.visible = visible;
1252 }
1253
1254 return ret;
1255 }
1256
1257 static int
1258 nv50_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
1259 {
1260 struct nv50_curs *curs = nv50_curs(crtc);
1261 struct nv50_chan *chan = nv50_chan(curs);
1262 nv_wo32(chan->user, 0x0084, (y << 16) | (x & 0xffff));
1263 nv_wo32(chan->user, 0x0080, 0x00000000);
1264 return 0;
1265 }
1266
1267 static void
1268 nv50_crtc_gamma_set(struct drm_crtc *crtc, u16 *r, u16 *g, u16 *b,
1269 uint32_t start, uint32_t size)
1270 {
1271 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
1272 u32 end = min_t(u32, start + size, 256);
1273 u32 i;
1274
1275 for (i = start; i < end; i++) {
1276 nv_crtc->lut.r[i] = r[i];
1277 nv_crtc->lut.g[i] = g[i];
1278 nv_crtc->lut.b[i] = b[i];
1279 }
1280
1281 nv50_crtc_lut_load(crtc);
1282 }
1283
1284 static void
1285 nv50_crtc_destroy(struct drm_crtc *crtc)
1286 {
1287 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
1288 struct nv50_disp *disp = nv50_disp(crtc->dev);
1289 struct nv50_head *head = nv50_head(crtc);
1290
1291 nv50_dmac_destroy(disp->core, &head->ovly.base);
1292 nv50_pioc_destroy(disp->core, &head->oimm.base);
1293 nv50_dmac_destroy(disp->core, &head->sync.base);
1294 nv50_pioc_destroy(disp->core, &head->curs.base);
1295
1296 /*XXX: this shouldn't be necessary, but the core doesn't call
1297 * disconnect() during the cleanup paths
1298 */
1299 if (head->image)
1300 nouveau_bo_unpin(head->image);
1301 nouveau_bo_ref(NULL, &head->image);
1302
1303 nouveau_bo_unmap(nv_crtc->cursor.nvbo);
1304 if (nv_crtc->cursor.nvbo)
1305 nouveau_bo_unpin(nv_crtc->cursor.nvbo);
1306 nouveau_bo_ref(NULL, &nv_crtc->cursor.nvbo);
1307
1308 nouveau_bo_unmap(nv_crtc->lut.nvbo);
1309 if (nv_crtc->lut.nvbo)
1310 nouveau_bo_unpin(nv_crtc->lut.nvbo);
1311 nouveau_bo_ref(NULL, &nv_crtc->lut.nvbo);
1312
1313 drm_crtc_cleanup(crtc);
1314 kfree(crtc);
1315 }
1316
1317 static const struct drm_crtc_helper_funcs nv50_crtc_hfunc = {
1318 .dpms = nv50_crtc_dpms,
1319 .prepare = nv50_crtc_prepare,
1320 .commit = nv50_crtc_commit,
1321 .mode_fixup = nv50_crtc_mode_fixup,
1322 .mode_set = nv50_crtc_mode_set,
1323 .mode_set_base = nv50_crtc_mode_set_base,
1324 .mode_set_base_atomic = nv50_crtc_mode_set_base_atomic,
1325 .load_lut = nv50_crtc_lut_load,
1326 .disable = nv50_crtc_disable,
1327 };
1328
1329 static const struct drm_crtc_funcs nv50_crtc_func = {
1330 .cursor_set = nv50_crtc_cursor_set,
1331 .cursor_move = nv50_crtc_cursor_move,
1332 .gamma_set = nv50_crtc_gamma_set,
1333 .set_config = nouveau_crtc_set_config,
1334 .destroy = nv50_crtc_destroy,
1335 .page_flip = nouveau_crtc_page_flip,
1336 };
1337
1338 static void
1339 nv50_cursor_set_pos(struct nouveau_crtc *nv_crtc, int x, int y)
1340 {
1341 }
1342
1343 static void
1344 nv50_cursor_set_offset(struct nouveau_crtc *nv_crtc, uint32_t offset)
1345 {
1346 }
1347
1348 static int
1349 nv50_crtc_create(struct drm_device *dev, struct nouveau_object *core, int index)
1350 {
1351 struct nv50_disp *disp = nv50_disp(dev);
1352 struct nv50_head *head;
1353 struct drm_crtc *crtc;
1354 int ret, i;
1355
1356 head = kzalloc(sizeof(*head), GFP_KERNEL);
1357 if (!head)
1358 return -ENOMEM;
1359
1360 head->base.index = index;
1361 head->base.set_dither = nv50_crtc_set_dither;
1362 head->base.set_scale = nv50_crtc_set_scale;
1363 head->base.set_color_vibrance = nv50_crtc_set_color_vibrance;
1364 head->base.color_vibrance = 50;
1365 head->base.vibrant_hue = 0;
1366 head->base.cursor.set_offset = nv50_cursor_set_offset;
1367 head->base.cursor.set_pos = nv50_cursor_set_pos;
1368 for (i = 0; i < 256; i++) {
1369 head->base.lut.r[i] = i << 8;
1370 head->base.lut.g[i] = i << 8;
1371 head->base.lut.b[i] = i << 8;
1372 }
1373
1374 crtc = &head->base.base;
1375 drm_crtc_init(dev, crtc, &nv50_crtc_func);
1376 drm_crtc_helper_add(crtc, &nv50_crtc_hfunc);
1377 drm_mode_crtc_set_gamma_size(crtc, 256);
1378
1379 ret = nouveau_bo_new(dev, 8192, 0x100, TTM_PL_FLAG_VRAM,
1380 0, 0x0000, NULL, &head->base.lut.nvbo);
1381 if (!ret) {
1382 ret = nouveau_bo_pin(head->base.lut.nvbo, TTM_PL_FLAG_VRAM);
1383 if (!ret) {
1384 ret = nouveau_bo_map(head->base.lut.nvbo);
1385 if (ret)
1386 nouveau_bo_unpin(head->base.lut.nvbo);
1387 }
1388 if (ret)
1389 nouveau_bo_ref(NULL, &head->base.lut.nvbo);
1390 }
1391
1392 if (ret)
1393 goto out;
1394
1395 nv50_crtc_lut_load(crtc);
1396
1397 /* allocate cursor resources */
1398 ret = nv50_pioc_create(disp->core, NV50_DISP_CURS_CLASS, index,
1399 &(struct nv50_display_curs_class) {
1400 .head = index,
1401 }, sizeof(struct nv50_display_curs_class),
1402 &head->curs.base);
1403 if (ret)
1404 goto out;
1405
1406 ret = nouveau_bo_new(dev, 64 * 64 * 4, 0x100, TTM_PL_FLAG_VRAM,
1407 0, 0x0000, NULL, &head->base.cursor.nvbo);
1408 if (!ret) {
1409 ret = nouveau_bo_pin(head->base.cursor.nvbo, TTM_PL_FLAG_VRAM);
1410 if (!ret) {
1411 ret = nouveau_bo_map(head->base.cursor.nvbo);
1412 if (ret)
1413 nouveau_bo_unpin(head->base.lut.nvbo);
1414 }
1415 if (ret)
1416 nouveau_bo_ref(NULL, &head->base.cursor.nvbo);
1417 }
1418
1419 if (ret)
1420 goto out;
1421
1422 /* allocate page flip / sync resources */
1423 ret = nv50_dmac_create(disp->core, NV50_DISP_SYNC_CLASS, index,
1424 &(struct nv50_display_sync_class) {
1425 .pushbuf = EVO_PUSH_HANDLE(SYNC, index),
1426 .head = index,
1427 }, sizeof(struct nv50_display_sync_class),
1428 disp->sync->bo.offset, &head->sync.base);
1429 if (ret)
1430 goto out;
1431
1432 head->sync.addr = EVO_FLIP_SEM0(index);
1433 head->sync.data = 0x00000000;
1434
1435 /* allocate overlay resources */
1436 ret = nv50_pioc_create(disp->core, NV50_DISP_OIMM_CLASS, index,
1437 &(struct nv50_display_oimm_class) {
1438 .head = index,
1439 }, sizeof(struct nv50_display_oimm_class),
1440 &head->oimm.base);
1441 if (ret)
1442 goto out;
1443
1444 ret = nv50_dmac_create(disp->core, NV50_DISP_OVLY_CLASS, index,
1445 &(struct nv50_display_ovly_class) {
1446 .pushbuf = EVO_PUSH_HANDLE(OVLY, index),
1447 .head = index,
1448 }, sizeof(struct nv50_display_ovly_class),
1449 disp->sync->bo.offset, &head->ovly.base);
1450 if (ret)
1451 goto out;
1452
1453 out:
1454 if (ret)
1455 nv50_crtc_destroy(crtc);
1456 return ret;
1457 }
1458
1459 /******************************************************************************
1460 * DAC
1461 *****************************************************************************/
1462 static void
1463 nv50_dac_dpms(struct drm_encoder *encoder, int mode)
1464 {
1465 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1466 struct nv50_disp *disp = nv50_disp(encoder->dev);
1467 int or = nv_encoder->or;
1468 u32 dpms_ctrl;
1469
1470 dpms_ctrl = 0x00000000;
1471 if (mode == DRM_MODE_DPMS_STANDBY || mode == DRM_MODE_DPMS_OFF)
1472 dpms_ctrl |= 0x00000001;
1473 if (mode == DRM_MODE_DPMS_SUSPEND || mode == DRM_MODE_DPMS_OFF)
1474 dpms_ctrl |= 0x00000004;
1475
1476 nv_call(disp->core, NV50_DISP_DAC_PWR + or, dpms_ctrl);
1477 }
1478
1479 static bool
1480 nv50_dac_mode_fixup(struct drm_encoder *encoder,
1481 const struct drm_display_mode *mode,
1482 struct drm_display_mode *adjusted_mode)
1483 {
1484 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1485 struct nouveau_connector *nv_connector;
1486
1487 nv_connector = nouveau_encoder_connector_get(nv_encoder);
1488 if (nv_connector && nv_connector->native_mode) {
1489 if (nv_connector->scaling_mode != DRM_MODE_SCALE_NONE) {
1490 int id = adjusted_mode->base.id;
1491 *adjusted_mode = *nv_connector->native_mode;
1492 adjusted_mode->base.id = id;
1493 }
1494 }
1495
1496 return true;
1497 }
1498
1499 static void
1500 nv50_dac_commit(struct drm_encoder *encoder)
1501 {
1502 }
1503
1504 static void
1505 nv50_dac_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
1506 struct drm_display_mode *adjusted_mode)
1507 {
1508 struct nv50_mast *mast = nv50_mast(encoder->dev);
1509 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1510 struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
1511 u32 *push;
1512
1513 nv50_dac_dpms(encoder, DRM_MODE_DPMS_ON);
1514
1515 push = evo_wait(mast, 8);
1516 if (push) {
1517 if (nv50_vers(mast) < NVD0_DISP_MAST_CLASS) {
1518 u32 syncs = 0x00000000;
1519
1520 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
1521 syncs |= 0x00000001;
1522 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
1523 syncs |= 0x00000002;
1524
1525 evo_mthd(push, 0x0400 + (nv_encoder->or * 0x080), 2);
1526 evo_data(push, 1 << nv_crtc->index);
1527 evo_data(push, syncs);
1528 } else {
1529 u32 magic = 0x31ec6000 | (nv_crtc->index << 25);
1530 u32 syncs = 0x00000001;
1531
1532 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
1533 syncs |= 0x00000008;
1534 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
1535 syncs |= 0x00000010;
1536
1537 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1538 magic |= 0x00000001;
1539
1540 evo_mthd(push, 0x0404 + (nv_crtc->index * 0x300), 2);
1541 evo_data(push, syncs);
1542 evo_data(push, magic);
1543 evo_mthd(push, 0x0180 + (nv_encoder->or * 0x020), 1);
1544 evo_data(push, 1 << nv_crtc->index);
1545 }
1546
1547 evo_kick(push, mast);
1548 }
1549
1550 nv_encoder->crtc = encoder->crtc;
1551 }
1552
1553 static void
1554 nv50_dac_disconnect(struct drm_encoder *encoder)
1555 {
1556 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1557 struct nv50_mast *mast = nv50_mast(encoder->dev);
1558 const int or = nv_encoder->or;
1559 u32 *push;
1560
1561 if (nv_encoder->crtc) {
1562 nv50_crtc_prepare(nv_encoder->crtc);
1563
1564 push = evo_wait(mast, 4);
1565 if (push) {
1566 if (nv50_vers(mast) < NVD0_DISP_MAST_CLASS) {
1567 evo_mthd(push, 0x0400 + (or * 0x080), 1);
1568 evo_data(push, 0x00000000);
1569 } else {
1570 evo_mthd(push, 0x0180 + (or * 0x020), 1);
1571 evo_data(push, 0x00000000);
1572 }
1573 evo_kick(push, mast);
1574 }
1575 }
1576
1577 nv_encoder->crtc = NULL;
1578 }
1579
1580 static enum drm_connector_status
1581 nv50_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector)
1582 {
1583 struct nv50_disp *disp = nv50_disp(encoder->dev);
1584 int ret, or = nouveau_encoder(encoder)->or;
1585 u32 load = nouveau_drm(encoder->dev)->vbios.dactestval;
1586 if (load == 0)
1587 load = 340;
1588
1589 ret = nv_exec(disp->core, NV50_DISP_DAC_LOAD + or, &load, sizeof(load));
1590 if (ret || !load)
1591 return connector_status_disconnected;
1592
1593 return connector_status_connected;
1594 }
1595
1596 static void
1597 nv50_dac_destroy(struct drm_encoder *encoder)
1598 {
1599 drm_encoder_cleanup(encoder);
1600 kfree(encoder);
1601 }
1602
1603 static const struct drm_encoder_helper_funcs nv50_dac_hfunc = {
1604 .dpms = nv50_dac_dpms,
1605 .mode_fixup = nv50_dac_mode_fixup,
1606 .prepare = nv50_dac_disconnect,
1607 .commit = nv50_dac_commit,
1608 .mode_set = nv50_dac_mode_set,
1609 .disable = nv50_dac_disconnect,
1610 .get_crtc = nv50_display_crtc_get,
1611 .detect = nv50_dac_detect
1612 };
1613
1614 static const struct drm_encoder_funcs nv50_dac_func = {
1615 .destroy = nv50_dac_destroy,
1616 };
1617
1618 static int
1619 nv50_dac_create(struct drm_connector *connector, struct dcb_output *dcbe)
1620 {
1621 struct nouveau_drm *drm = nouveau_drm(connector->dev);
1622 struct nouveau_i2c *i2c = nouveau_i2c(drm->device);
1623 struct nouveau_encoder *nv_encoder;
1624 struct drm_encoder *encoder;
1625 int type = DRM_MODE_ENCODER_DAC;
1626
1627 nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL);
1628 if (!nv_encoder)
1629 return -ENOMEM;
1630 nv_encoder->dcb = dcbe;
1631 nv_encoder->or = ffs(dcbe->or) - 1;
1632 nv_encoder->i2c = i2c->find(i2c, dcbe->i2c_index);
1633
1634 encoder = to_drm_encoder(nv_encoder);
1635 encoder->possible_crtcs = dcbe->heads;
1636 encoder->possible_clones = 0;
1637 drm_encoder_init(connector->dev, encoder, &nv50_dac_func, type);
1638 drm_encoder_helper_add(encoder, &nv50_dac_hfunc);
1639
1640 drm_mode_connector_attach_encoder(connector, encoder);
1641 return 0;
1642 }
1643
1644 /******************************************************************************
1645 * Audio
1646 *****************************************************************************/
1647 static void
1648 nv50_audio_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode)
1649 {
1650 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1651 struct nouveau_connector *nv_connector;
1652 struct nv50_disp *disp = nv50_disp(encoder->dev);
1653
1654 nv_connector = nouveau_encoder_connector_get(nv_encoder);
1655 if (!drm_detect_monitor_audio(nv_connector->edid))
1656 return;
1657
1658 drm_edid_to_eld(&nv_connector->base, nv_connector->edid);
1659
1660 nv_exec(disp->core, NVA3_DISP_SOR_HDA_ELD + nv_encoder->or,
1661 nv_connector->base.eld,
1662 nv_connector->base.eld[2] * 4);
1663 }
1664
1665 static void
1666 nv50_audio_disconnect(struct drm_encoder *encoder)
1667 {
1668 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1669 struct nv50_disp *disp = nv50_disp(encoder->dev);
1670
1671 nv_exec(disp->core, NVA3_DISP_SOR_HDA_ELD + nv_encoder->or, NULL, 0);
1672 }
1673
1674 /******************************************************************************
1675 * HDMI
1676 *****************************************************************************/
1677 static void
1678 nv50_hdmi_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode)
1679 {
1680 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1681 struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
1682 struct nouveau_connector *nv_connector;
1683 struct nv50_disp *disp = nv50_disp(encoder->dev);
1684 const u32 moff = (nv_crtc->index << 3) | nv_encoder->or;
1685 u32 rekey = 56; /* binary driver, and tegra constant */
1686 u32 max_ac_packet;
1687
1688 nv_connector = nouveau_encoder_connector_get(nv_encoder);
1689 if (!drm_detect_hdmi_monitor(nv_connector->edid))
1690 return;
1691
1692 max_ac_packet = mode->htotal - mode->hdisplay;
1693 max_ac_packet -= rekey;
1694 max_ac_packet -= 18; /* constant from tegra */
1695 max_ac_packet /= 32;
1696
1697 nv_call(disp->core, NV84_DISP_SOR_HDMI_PWR + moff,
1698 NV84_DISP_SOR_HDMI_PWR_STATE_ON |
1699 (max_ac_packet << 16) | rekey);
1700
1701 nv50_audio_mode_set(encoder, mode);
1702 }
1703
1704 static void
1705 nv50_hdmi_disconnect(struct drm_encoder *encoder, struct nouveau_crtc *nv_crtc)
1706 {
1707 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1708 struct nv50_disp *disp = nv50_disp(encoder->dev);
1709 const u32 moff = (nv_crtc->index << 3) | nv_encoder->or;
1710
1711 nv50_audio_disconnect(encoder);
1712
1713 nv_call(disp->core, NV84_DISP_SOR_HDMI_PWR + moff, 0x00000000);
1714 }
1715
1716 /******************************************************************************
1717 * SOR
1718 *****************************************************************************/
1719 static void
1720 nv50_sor_dpms(struct drm_encoder *encoder, int mode)
1721 {
1722 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1723 struct drm_device *dev = encoder->dev;
1724 struct nv50_disp *disp = nv50_disp(dev);
1725 struct drm_encoder *partner;
1726 u32 mthd;
1727
1728 nv_encoder->last_dpms = mode;
1729
1730 list_for_each_entry(partner, &dev->mode_config.encoder_list, head) {
1731 struct nouveau_encoder *nv_partner = nouveau_encoder(partner);
1732
1733 if (partner->encoder_type != DRM_MODE_ENCODER_TMDS)
1734 continue;
1735
1736 if (nv_partner != nv_encoder &&
1737 nv_partner->dcb->or == nv_encoder->dcb->or) {
1738 if (nv_partner->last_dpms == DRM_MODE_DPMS_ON)
1739 return;
1740 break;
1741 }
1742 }
1743
1744 mthd = (ffs(nv_encoder->dcb->heads) - 1) << 3;
1745 mthd |= (ffs(nv_encoder->dcb->sorconf.link) - 1) << 2;
1746 mthd |= nv_encoder->or;
1747
1748 if (nv_encoder->dcb->type == DCB_OUTPUT_DP) {
1749 nv_call(disp->core, NV50_DISP_SOR_PWR | mthd, 1);
1750 mthd |= NV94_DISP_SOR_DP_PWR;
1751 } else {
1752 mthd |= NV50_DISP_SOR_PWR;
1753 }
1754
1755 nv_call(disp->core, mthd, (mode == DRM_MODE_DPMS_ON));
1756 }
1757
1758 static bool
1759 nv50_sor_mode_fixup(struct drm_encoder *encoder,
1760 const struct drm_display_mode *mode,
1761 struct drm_display_mode *adjusted_mode)
1762 {
1763 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1764 struct nouveau_connector *nv_connector;
1765
1766 nv_connector = nouveau_encoder_connector_get(nv_encoder);
1767 if (nv_connector && nv_connector->native_mode) {
1768 if (nv_connector->scaling_mode != DRM_MODE_SCALE_NONE) {
1769 int id = adjusted_mode->base.id;
1770 *adjusted_mode = *nv_connector->native_mode;
1771 adjusted_mode->base.id = id;
1772 }
1773 }
1774
1775 return true;
1776 }
1777
1778 static void
1779 nv50_sor_ctrl(struct nouveau_encoder *nv_encoder, u32 mask, u32 data)
1780 {
1781 struct nv50_mast *mast = nv50_mast(nv_encoder->base.base.dev);
1782 u32 temp = (nv_encoder->ctrl & ~mask) | (data & mask), *push;
1783 if (temp != nv_encoder->ctrl && (push = evo_wait(mast, 2))) {
1784 if (nv50_vers(mast) < NVD0_DISP_MAST_CLASS) {
1785 evo_mthd(push, 0x0600 + (nv_encoder->or * 0x40), 1);
1786 evo_data(push, (nv_encoder->ctrl = temp));
1787 } else {
1788 evo_mthd(push, 0x0200 + (nv_encoder->or * 0x20), 1);
1789 evo_data(push, (nv_encoder->ctrl = temp));
1790 }
1791 evo_kick(push, mast);
1792 }
1793 }
1794
1795 static void
1796 nv50_sor_disconnect(struct drm_encoder *encoder)
1797 {
1798 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1799 struct nouveau_crtc *nv_crtc = nouveau_crtc(nv_encoder->crtc);
1800
1801 nv_encoder->last_dpms = DRM_MODE_DPMS_OFF;
1802 nv_encoder->crtc = NULL;
1803
1804 if (nv_crtc) {
1805 nv50_crtc_prepare(&nv_crtc->base);
1806 nv50_sor_ctrl(nv_encoder, 1 << nv_crtc->index, 0);
1807 nv50_hdmi_disconnect(&nv_encoder->base.base, nv_crtc);
1808 }
1809 }
1810
1811 static void
1812 nv50_sor_commit(struct drm_encoder *encoder)
1813 {
1814 }
1815
1816 static void
1817 nv50_sor_mode_set(struct drm_encoder *encoder, struct drm_display_mode *umode,
1818 struct drm_display_mode *mode)
1819 {
1820 struct nv50_disp *disp = nv50_disp(encoder->dev);
1821 struct nv50_mast *mast = nv50_mast(encoder->dev);
1822 struct drm_device *dev = encoder->dev;
1823 struct nouveau_drm *drm = nouveau_drm(dev);
1824 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1825 struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
1826 struct nouveau_connector *nv_connector;
1827 struct nvbios *bios = &drm->vbios;
1828 u32 lvds = 0, mask, ctrl;
1829 u8 owner = 1 << nv_crtc->index;
1830 u8 proto = 0xf;
1831 u8 depth = 0x0;
1832
1833 nv_connector = nouveau_encoder_connector_get(nv_encoder);
1834 nv_encoder->crtc = encoder->crtc;
1835
1836 switch (nv_encoder->dcb->type) {
1837 case DCB_OUTPUT_TMDS:
1838 if (nv_encoder->dcb->sorconf.link & 1) {
1839 if (mode->clock < 165000)
1840 proto = 0x1;
1841 else
1842 proto = 0x5;
1843 } else {
1844 proto = 0x2;
1845 }
1846
1847 nv50_hdmi_mode_set(&nv_encoder->base.base, mode);
1848 break;
1849 case DCB_OUTPUT_LVDS:
1850 proto = 0x0;
1851
1852 if (bios->fp_no_ddc) {
1853 if (bios->fp.dual_link)
1854 lvds |= 0x0100;
1855 if (bios->fp.if_is_24bit)
1856 lvds |= 0x0200;
1857 } else {
1858 if (nv_connector->type == DCB_CONNECTOR_LVDS_SPWG) {
1859 if (((u8 *)nv_connector->edid)[121] == 2)
1860 lvds |= 0x0100;
1861 } else
1862 if (mode->clock >= bios->fp.duallink_transition_clk) {
1863 lvds |= 0x0100;
1864 }
1865
1866 if (lvds & 0x0100) {
1867 if (bios->fp.strapless_is_24bit & 2)
1868 lvds |= 0x0200;
1869 } else {
1870 if (bios->fp.strapless_is_24bit & 1)
1871 lvds |= 0x0200;
1872 }
1873
1874 if (nv_connector->base.display_info.bpc == 8)
1875 lvds |= 0x0200;
1876 }
1877
1878 nv_call(disp->core, NV50_DISP_SOR_LVDS_SCRIPT + nv_encoder->or, lvds);
1879 break;
1880 case DCB_OUTPUT_DP:
1881 if (nv_connector->base.display_info.bpc == 6) {
1882 nv_encoder->dp.datarate = mode->clock * 18 / 8;
1883 depth = 0x2;
1884 } else
1885 if (nv_connector->base.display_info.bpc == 8) {
1886 nv_encoder->dp.datarate = mode->clock * 24 / 8;
1887 depth = 0x5;
1888 } else {
1889 nv_encoder->dp.datarate = mode->clock * 30 / 8;
1890 depth = 0x6;
1891 }
1892
1893 if (nv_encoder->dcb->sorconf.link & 1)
1894 proto = 0x8;
1895 else
1896 proto = 0x9;
1897 break;
1898 default:
1899 BUG_ON(1);
1900 break;
1901 }
1902
1903 nv50_sor_dpms(&nv_encoder->base.base, DRM_MODE_DPMS_ON);
1904
1905 if (nv50_vers(mast) >= NVD0_DISP_CLASS) {
1906 u32 *push = evo_wait(mast, 3);
1907 if (push) {
1908 u32 magic = 0x31ec6000 | (nv_crtc->index << 25);
1909 u32 syncs = 0x00000001;
1910
1911 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
1912 syncs |= 0x00000008;
1913 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
1914 syncs |= 0x00000010;
1915
1916 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1917 magic |= 0x00000001;
1918
1919 evo_mthd(push, 0x0404 + (nv_crtc->index * 0x300), 2);
1920 evo_data(push, syncs | (depth << 6));
1921 evo_data(push, magic);
1922 evo_kick(push, mast);
1923 }
1924
1925 ctrl = proto << 8;
1926 mask = 0x00000f00;
1927 } else {
1928 ctrl = (depth << 16) | (proto << 8);
1929 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
1930 ctrl |= 0x00001000;
1931 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
1932 ctrl |= 0x00002000;
1933 mask = 0x000f3f00;
1934 }
1935
1936 nv50_sor_ctrl(nv_encoder, mask | owner, ctrl | owner);
1937 }
1938
1939 static void
1940 nv50_sor_destroy(struct drm_encoder *encoder)
1941 {
1942 drm_encoder_cleanup(encoder);
1943 kfree(encoder);
1944 }
1945
1946 static const struct drm_encoder_helper_funcs nv50_sor_hfunc = {
1947 .dpms = nv50_sor_dpms,
1948 .mode_fixup = nv50_sor_mode_fixup,
1949 .prepare = nv50_sor_disconnect,
1950 .commit = nv50_sor_commit,
1951 .mode_set = nv50_sor_mode_set,
1952 .disable = nv50_sor_disconnect,
1953 .get_crtc = nv50_display_crtc_get,
1954 };
1955
1956 static const struct drm_encoder_funcs nv50_sor_func = {
1957 .destroy = nv50_sor_destroy,
1958 };
1959
1960 static int
1961 nv50_sor_create(struct drm_connector *connector, struct dcb_output *dcbe)
1962 {
1963 struct nouveau_drm *drm = nouveau_drm(connector->dev);
1964 struct nouveau_i2c *i2c = nouveau_i2c(drm->device);
1965 struct nouveau_encoder *nv_encoder;
1966 struct drm_encoder *encoder;
1967 int type;
1968
1969 switch (dcbe->type) {
1970 case DCB_OUTPUT_LVDS: type = DRM_MODE_ENCODER_LVDS; break;
1971 case DCB_OUTPUT_TMDS:
1972 case DCB_OUTPUT_DP:
1973 default:
1974 type = DRM_MODE_ENCODER_TMDS;
1975 break;
1976 }
1977
1978 nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL);
1979 if (!nv_encoder)
1980 return -ENOMEM;
1981 nv_encoder->dcb = dcbe;
1982 nv_encoder->or = ffs(dcbe->or) - 1;
1983 nv_encoder->i2c = i2c->find(i2c, dcbe->i2c_index);
1984 nv_encoder->last_dpms = DRM_MODE_DPMS_OFF;
1985
1986 encoder = to_drm_encoder(nv_encoder);
1987 encoder->possible_crtcs = dcbe->heads;
1988 encoder->possible_clones = 0;
1989 drm_encoder_init(connector->dev, encoder, &nv50_sor_func, type);
1990 drm_encoder_helper_add(encoder, &nv50_sor_hfunc);
1991
1992 drm_mode_connector_attach_encoder(connector, encoder);
1993 return 0;
1994 }
1995
1996 /******************************************************************************
1997 * PIOR
1998 *****************************************************************************/
1999
2000 static void
2001 nv50_pior_dpms(struct drm_encoder *encoder, int mode)
2002 {
2003 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
2004 struct nv50_disp *disp = nv50_disp(encoder->dev);
2005 u32 mthd = (nv_encoder->dcb->type << 12) | nv_encoder->or;
2006 u32 ctrl = (mode == DRM_MODE_DPMS_ON);
2007 nv_call(disp->core, NV50_DISP_PIOR_PWR + mthd, ctrl);
2008 }
2009
2010 static bool
2011 nv50_pior_mode_fixup(struct drm_encoder *encoder,
2012 const struct drm_display_mode *mode,
2013 struct drm_display_mode *adjusted_mode)
2014 {
2015 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
2016 struct nouveau_connector *nv_connector;
2017
2018 nv_connector = nouveau_encoder_connector_get(nv_encoder);
2019 if (nv_connector && nv_connector->native_mode) {
2020 if (nv_connector->scaling_mode != DRM_MODE_SCALE_NONE) {
2021 int id = adjusted_mode->base.id;
2022 *adjusted_mode = *nv_connector->native_mode;
2023 adjusted_mode->base.id = id;
2024 }
2025 }
2026
2027 adjusted_mode->clock *= 2;
2028 return true;
2029 }
2030
2031 static void
2032 nv50_pior_commit(struct drm_encoder *encoder)
2033 {
2034 }
2035
2036 static void
2037 nv50_pior_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
2038 struct drm_display_mode *adjusted_mode)
2039 {
2040 struct nv50_mast *mast = nv50_mast(encoder->dev);
2041 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
2042 struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
2043 struct nouveau_connector *nv_connector;
2044 u8 owner = 1 << nv_crtc->index;
2045 u8 proto, depth;
2046 u32 *push;
2047
2048 nv_connector = nouveau_encoder_connector_get(nv_encoder);
2049 switch (nv_connector->base.display_info.bpc) {
2050 case 10: depth = 0x6; break;
2051 case 8: depth = 0x5; break;
2052 case 6: depth = 0x2; break;
2053 default: depth = 0x0; break;
2054 }
2055
2056 switch (nv_encoder->dcb->type) {
2057 case DCB_OUTPUT_TMDS:
2058 case DCB_OUTPUT_DP:
2059 proto = 0x0;
2060 break;
2061 default:
2062 BUG_ON(1);
2063 break;
2064 }
2065
2066 nv50_pior_dpms(encoder, DRM_MODE_DPMS_ON);
2067
2068 push = evo_wait(mast, 8);
2069 if (push) {
2070 if (nv50_vers(mast) < NVD0_DISP_MAST_CLASS) {
2071 u32 ctrl = (depth << 16) | (proto << 8) | owner;
2072 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
2073 ctrl |= 0x00001000;
2074 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
2075 ctrl |= 0x00002000;
2076 evo_mthd(push, 0x0700 + (nv_encoder->or * 0x040), 1);
2077 evo_data(push, ctrl);
2078 }
2079
2080 evo_kick(push, mast);
2081 }
2082
2083 nv_encoder->crtc = encoder->crtc;
2084 }
2085
2086 static void
2087 nv50_pior_disconnect(struct drm_encoder *encoder)
2088 {
2089 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
2090 struct nv50_mast *mast = nv50_mast(encoder->dev);
2091 const int or = nv_encoder->or;
2092 u32 *push;
2093
2094 if (nv_encoder->crtc) {
2095 nv50_crtc_prepare(nv_encoder->crtc);
2096
2097 push = evo_wait(mast, 4);
2098 if (push) {
2099 if (nv50_vers(mast) < NVD0_DISP_MAST_CLASS) {
2100 evo_mthd(push, 0x0700 + (or * 0x040), 1);
2101 evo_data(push, 0x00000000);
2102 }
2103 evo_kick(push, mast);
2104 }
2105 }
2106
2107 nv_encoder->crtc = NULL;
2108 }
2109
2110 static void
2111 nv50_pior_destroy(struct drm_encoder *encoder)
2112 {
2113 drm_encoder_cleanup(encoder);
2114 kfree(encoder);
2115 }
2116
2117 static const struct drm_encoder_helper_funcs nv50_pior_hfunc = {
2118 .dpms = nv50_pior_dpms,
2119 .mode_fixup = nv50_pior_mode_fixup,
2120 .prepare = nv50_pior_disconnect,
2121 .commit = nv50_pior_commit,
2122 .mode_set = nv50_pior_mode_set,
2123 .disable = nv50_pior_disconnect,
2124 .get_crtc = nv50_display_crtc_get,
2125 };
2126
2127 static const struct drm_encoder_funcs nv50_pior_func = {
2128 .destroy = nv50_pior_destroy,
2129 };
2130
2131 static int
2132 nv50_pior_create(struct drm_connector *connector, struct dcb_output *dcbe)
2133 {
2134 struct nouveau_drm *drm = nouveau_drm(connector->dev);
2135 struct nouveau_i2c *i2c = nouveau_i2c(drm->device);
2136 struct nouveau_i2c_port *ddc = NULL;
2137 struct nouveau_encoder *nv_encoder;
2138 struct drm_encoder *encoder;
2139 int type;
2140
2141 switch (dcbe->type) {
2142 case DCB_OUTPUT_TMDS:
2143 ddc = i2c->find_type(i2c, NV_I2C_TYPE_EXTDDC(dcbe->extdev));
2144 type = DRM_MODE_ENCODER_TMDS;
2145 break;
2146 case DCB_OUTPUT_DP:
2147 ddc = i2c->find_type(i2c, NV_I2C_TYPE_EXTAUX(dcbe->extdev));
2148 type = DRM_MODE_ENCODER_TMDS;
2149 break;
2150 default:
2151 return -ENODEV;
2152 }
2153
2154 nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL);
2155 if (!nv_encoder)
2156 return -ENOMEM;
2157 nv_encoder->dcb = dcbe;
2158 nv_encoder->or = ffs(dcbe->or) - 1;
2159 nv_encoder->i2c = ddc;
2160
2161 encoder = to_drm_encoder(nv_encoder);
2162 encoder->possible_crtcs = dcbe->heads;
2163 encoder->possible_clones = 0;
2164 drm_encoder_init(connector->dev, encoder, &nv50_pior_func, type);
2165 drm_encoder_helper_add(encoder, &nv50_pior_hfunc);
2166
2167 drm_mode_connector_attach_encoder(connector, encoder);
2168 return 0;
2169 }
2170
2171 /******************************************************************************
2172 * Init
2173 *****************************************************************************/
2174 void
2175 nv50_display_fini(struct drm_device *dev)
2176 {
2177 }
2178
2179 int
2180 nv50_display_init(struct drm_device *dev)
2181 {
2182 struct nv50_disp *disp = nv50_disp(dev);
2183 struct drm_crtc *crtc;
2184 u32 *push;
2185
2186 push = evo_wait(nv50_mast(dev), 32);
2187 if (!push)
2188 return -EBUSY;
2189
2190 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2191 struct nv50_sync *sync = nv50_sync(crtc);
2192 nouveau_bo_wr32(disp->sync, sync->addr / 4, sync->data);
2193 }
2194
2195 evo_mthd(push, 0x0088, 1);
2196 evo_data(push, NvEvoSync);
2197 evo_kick(push, nv50_mast(dev));
2198 return 0;
2199 }
2200
2201 void
2202 nv50_display_destroy(struct drm_device *dev)
2203 {
2204 struct nv50_disp *disp = nv50_disp(dev);
2205
2206 nv50_dmac_destroy(disp->core, &disp->mast.base);
2207
2208 nouveau_bo_unmap(disp->sync);
2209 if (disp->sync)
2210 nouveau_bo_unpin(disp->sync);
2211 nouveau_bo_ref(NULL, &disp->sync);
2212
2213 nouveau_display(dev)->priv = NULL;
2214 kfree(disp);
2215 }
2216
2217 int
2218 nv50_display_create(struct drm_device *dev)
2219 {
2220 struct nouveau_device *device = nouveau_dev(dev);
2221 struct nouveau_drm *drm = nouveau_drm(dev);
2222 struct dcb_table *dcb = &drm->vbios.dcb;
2223 struct drm_connector *connector, *tmp;
2224 struct nv50_disp *disp;
2225 struct dcb_output *dcbe;
2226 int crtcs, ret, i;
2227
2228 disp = kzalloc(sizeof(*disp), GFP_KERNEL);
2229 if (!disp)
2230 return -ENOMEM;
2231
2232 nouveau_display(dev)->priv = disp;
2233 nouveau_display(dev)->dtor = nv50_display_destroy;
2234 nouveau_display(dev)->init = nv50_display_init;
2235 nouveau_display(dev)->fini = nv50_display_fini;
2236 disp->core = nouveau_display(dev)->core;
2237
2238 /* small shared memory area we use for notifiers and semaphores */
2239 ret = nouveau_bo_new(dev, 4096, 0x1000, TTM_PL_FLAG_VRAM,
2240 0, 0x0000, NULL, &disp->sync);
2241 if (!ret) {
2242 ret = nouveau_bo_pin(disp->sync, TTM_PL_FLAG_VRAM);
2243 if (!ret) {
2244 ret = nouveau_bo_map(disp->sync);
2245 if (ret)
2246 nouveau_bo_unpin(disp->sync);
2247 }
2248 if (ret)
2249 nouveau_bo_ref(NULL, &disp->sync);
2250 }
2251
2252 if (ret)
2253 goto out;
2254
2255 /* allocate master evo channel */
2256 ret = nv50_dmac_create(disp->core, NV50_DISP_MAST_CLASS, 0,
2257 &(struct nv50_display_mast_class) {
2258 .pushbuf = EVO_PUSH_HANDLE(MAST, 0),
2259 }, sizeof(struct nv50_display_mast_class),
2260 disp->sync->bo.offset, &disp->mast.base);
2261 if (ret)
2262 goto out;
2263
2264 /* create crtc objects to represent the hw heads */
2265 if (nv_mclass(disp->core) >= NVD0_DISP_CLASS)
2266 crtcs = nv_rd32(device, 0x022448);
2267 else
2268 crtcs = 2;
2269
2270 for (i = 0; i < crtcs; i++) {
2271 ret = nv50_crtc_create(dev, disp->core, i);
2272 if (ret)
2273 goto out;
2274 }
2275
2276 /* create encoder/connector objects based on VBIOS DCB table */
2277 for (i = 0, dcbe = &dcb->entry[0]; i < dcb->entries; i++, dcbe++) {
2278 connector = nouveau_connector_create(dev, dcbe->connector);
2279 if (IS_ERR(connector))
2280 continue;
2281
2282 if (dcbe->location == DCB_LOC_ON_CHIP) {
2283 switch (dcbe->type) {
2284 case DCB_OUTPUT_TMDS:
2285 case DCB_OUTPUT_LVDS:
2286 case DCB_OUTPUT_DP:
2287 ret = nv50_sor_create(connector, dcbe);
2288 break;
2289 case DCB_OUTPUT_ANALOG:
2290 ret = nv50_dac_create(connector, dcbe);
2291 break;
2292 default:
2293 ret = -ENODEV;
2294 break;
2295 }
2296 } else {
2297 ret = nv50_pior_create(connector, dcbe);
2298 }
2299
2300 if (ret) {
2301 NV_WARN(drm, "failed to create encoder %d/%d/%d: %d\n",
2302 dcbe->location, dcbe->type,
2303 ffs(dcbe->or) - 1, ret);
2304 ret = 0;
2305 }
2306 }
2307
2308 /* cull any connectors we created that don't have an encoder */
2309 list_for_each_entry_safe(connector, tmp, &dev->mode_config.connector_list, head) {
2310 if (connector->encoder_ids[0])
2311 continue;
2312
2313 NV_WARN(drm, "%s has no encoders, removing\n",
2314 connector->name);
2315 connector->funcs->destroy(connector);
2316 }
2317
2318 out:
2319 if (ret)
2320 nv50_display_destroy(dev);
2321 return ret;
2322 }
Linux with added FPC-III support