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sched: Remove double_rq_lock() from __migrate_task()
[linux/fpc-iii.git] / drivers / gpu / drm / radeon / r100.c
blob1544efcf1c3a655d04b197302737a820b07d1790
1 /*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28 #include <linux/seq_file.h>
29 #include <linux/slab.h>
30 #include <drm/drmP.h>
31 #include <drm/radeon_drm.h>
32 #include "radeon_reg.h"
33 #include "radeon.h"
34 #include "radeon_asic.h"
35 #include "r100d.h"
36 #include "rs100d.h"
37 #include "rv200d.h"
38 #include "rv250d.h"
39 #include "atom.h"
40
41 #include <linux/firmware.h>
42 #include <linux/module.h>
43
44 #include "r100_reg_safe.h"
45 #include "rn50_reg_safe.h"
46
47 /* Firmware Names */
48 #define FIRMWARE_R100 "radeon/R100_cp.bin"
49 #define FIRMWARE_R200 "radeon/R200_cp.bin"
50 #define FIRMWARE_R300 "radeon/R300_cp.bin"
51 #define FIRMWARE_R420 "radeon/R420_cp.bin"
52 #define FIRMWARE_RS690 "radeon/RS690_cp.bin"
53 #define FIRMWARE_RS600 "radeon/RS600_cp.bin"
54 #define FIRMWARE_R520 "radeon/R520_cp.bin"
55
56 MODULE_FIRMWARE(FIRMWARE_R100);
57 MODULE_FIRMWARE(FIRMWARE_R200);
58 MODULE_FIRMWARE(FIRMWARE_R300);
59 MODULE_FIRMWARE(FIRMWARE_R420);
60 MODULE_FIRMWARE(FIRMWARE_RS690);
61 MODULE_FIRMWARE(FIRMWARE_RS600);
62 MODULE_FIRMWARE(FIRMWARE_R520);
63
64 #include "r100_track.h"
65
66 /* This files gather functions specifics to:
67 * r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280
68 * and others in some cases.
69 */
70
71 static bool r100_is_in_vblank(struct radeon_device *rdev, int crtc)
72 {
73 if (crtc == 0) {
74 if (RREG32(RADEON_CRTC_STATUS) & RADEON_CRTC_VBLANK_CUR)
75 return true;
76 else
77 return false;
78 } else {
79 if (RREG32(RADEON_CRTC2_STATUS) & RADEON_CRTC2_VBLANK_CUR)
80 return true;
81 else
82 return false;
83 }
84 }
85
86 static bool r100_is_counter_moving(struct radeon_device *rdev, int crtc)
87 {
88 u32 vline1, vline2;
89
90 if (crtc == 0) {
91 vline1 = (RREG32(RADEON_CRTC_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
92 vline2 = (RREG32(RADEON_CRTC_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
93 } else {
94 vline1 = (RREG32(RADEON_CRTC2_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
95 vline2 = (RREG32(RADEON_CRTC2_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
96 }
97 if (vline1 != vline2)
98 return true;
99 else
100 return false;
101 }
102
103 /**
104 * r100_wait_for_vblank - vblank wait asic callback.
105 *
106 * @rdev: radeon_device pointer
107 * @crtc: crtc to wait for vblank on
108 *
109 * Wait for vblank on the requested crtc (r1xx-r4xx).
110 */
111 void r100_wait_for_vblank(struct radeon_device *rdev, int crtc)
112 {
113 unsigned i = 0;
114
115 if (crtc >= rdev->num_crtc)
116 return;
117
118 if (crtc == 0) {
119 if (!(RREG32(RADEON_CRTC_GEN_CNTL) & RADEON_CRTC_EN))
120 return;
121 } else {
122 if (!(RREG32(RADEON_CRTC2_GEN_CNTL) & RADEON_CRTC2_EN))
123 return;
124 }
125
126 /* depending on when we hit vblank, we may be close to active; if so,
127 * wait for another frame.
128 */
129 while (r100_is_in_vblank(rdev, crtc)) {
130 if (i++ % 100 == 0) {
131 if (!r100_is_counter_moving(rdev, crtc))
132 break;
133 }
134 }
135
136 while (!r100_is_in_vblank(rdev, crtc)) {
137 if (i++ % 100 == 0) {
138 if (!r100_is_counter_moving(rdev, crtc))
139 break;
140 }
141 }
142 }
143
144 /**
145 * r100_page_flip - pageflip callback.
146 *
147 * @rdev: radeon_device pointer
148 * @crtc_id: crtc to cleanup pageflip on
149 * @crtc_base: new address of the crtc (GPU MC address)
150 *
151 * Does the actual pageflip (r1xx-r4xx).
152 * During vblank we take the crtc lock and wait for the update_pending
153 * bit to go high, when it does, we release the lock, and allow the
154 * double buffered update to take place.
155 */
156 void r100_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base)
157 {
158 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
159 u32 tmp = ((u32)crtc_base) | RADEON_CRTC_OFFSET__OFFSET_LOCK;
160 int i;
161
162 /* Lock the graphics update lock */
163 /* update the scanout addresses */
164 WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, tmp);
165
166 /* Wait for update_pending to go high. */
167 for (i = 0; i < rdev->usec_timeout; i++) {
168 if (RREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset) & RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET)
169 break;
170 udelay(1);
171 }
172 DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n");
173
174 /* Unlock the lock, so double-buffering can take place inside vblank */
175 tmp &= ~RADEON_CRTC_OFFSET__OFFSET_LOCK;
176 WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, tmp);
177
178 }
179
180 /**
181 * r100_page_flip_pending - check if page flip is still pending
182 *
183 * @rdev: radeon_device pointer
184 * @crtc_id: crtc to check
185 *
186 * Check if the last pagefilp is still pending (r1xx-r4xx).
187 * Returns the current update pending status.
188 */
189 bool r100_page_flip_pending(struct radeon_device *rdev, int crtc_id)
190 {
191 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
192
193 /* Return current update_pending status: */
194 return !!(RREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset) &
195 RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET);
196 }
197
198 /**
199 * r100_pm_get_dynpm_state - look up dynpm power state callback.
200 *
201 * @rdev: radeon_device pointer
202 *
203 * Look up the optimal power state based on the
204 * current state of the GPU (r1xx-r5xx).
205 * Used for dynpm only.
206 */
207 void r100_pm_get_dynpm_state(struct radeon_device *rdev)
208 {
209 int i;
210 rdev->pm.dynpm_can_upclock = true;
211 rdev->pm.dynpm_can_downclock = true;
212
213 switch (rdev->pm.dynpm_planned_action) {
214 case DYNPM_ACTION_MINIMUM:
215 rdev->pm.requested_power_state_index = 0;
216 rdev->pm.dynpm_can_downclock = false;
217 break;
218 case DYNPM_ACTION_DOWNCLOCK:
219 if (rdev->pm.current_power_state_index == 0) {
220 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
221 rdev->pm.dynpm_can_downclock = false;
222 } else {
223 if (rdev->pm.active_crtc_count > 1) {
224 for (i = 0; i < rdev->pm.num_power_states; i++) {
225 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
226 continue;
227 else if (i >= rdev->pm.current_power_state_index) {
228 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
229 break;
230 } else {
231 rdev->pm.requested_power_state_index = i;
232 break;
233 }
234 }
235 } else
236 rdev->pm.requested_power_state_index =
237 rdev->pm.current_power_state_index - 1;
238 }
239 /* don't use the power state if crtcs are active and no display flag is set */
240 if ((rdev->pm.active_crtc_count > 0) &&
241 (rdev->pm.power_state[rdev->pm.requested_power_state_index].clock_info[0].flags &
242 RADEON_PM_MODE_NO_DISPLAY)) {
243 rdev->pm.requested_power_state_index++;
244 }
245 break;
246 case DYNPM_ACTION_UPCLOCK:
247 if (rdev->pm.current_power_state_index == (rdev->pm.num_power_states - 1)) {
248 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
249 rdev->pm.dynpm_can_upclock = false;
250 } else {
251 if (rdev->pm.active_crtc_count > 1) {
252 for (i = (rdev->pm.num_power_states - 1); i >= 0; i--) {
253 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
254 continue;
255 else if (i <= rdev->pm.current_power_state_index) {
256 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
257 break;
258 } else {
259 rdev->pm.requested_power_state_index = i;
260 break;
261 }
262 }
263 } else
264 rdev->pm.requested_power_state_index =
265 rdev->pm.current_power_state_index + 1;
266 }
267 break;
268 case DYNPM_ACTION_DEFAULT:
269 rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index;
270 rdev->pm.dynpm_can_upclock = false;
271 break;
272 case DYNPM_ACTION_NONE:
273 default:
274 DRM_ERROR("Requested mode for not defined action\n");
275 return;
276 }
277 /* only one clock mode per power state */
278 rdev->pm.requested_clock_mode_index = 0;
279
280 DRM_DEBUG_DRIVER("Requested: e: %d m: %d p: %d\n",
281 rdev->pm.power_state[rdev->pm.requested_power_state_index].
282 clock_info[rdev->pm.requested_clock_mode_index].sclk,
283 rdev->pm.power_state[rdev->pm.requested_power_state_index].
284 clock_info[rdev->pm.requested_clock_mode_index].mclk,
285 rdev->pm.power_state[rdev->pm.requested_power_state_index].
286 pcie_lanes);
287 }
288
289 /**
290 * r100_pm_init_profile - Initialize power profiles callback.
291 *
292 * @rdev: radeon_device pointer
293 *
294 * Initialize the power states used in profile mode
295 * (r1xx-r3xx).
296 * Used for profile mode only.
297 */
298 void r100_pm_init_profile(struct radeon_device *rdev)
299 {
300 /* default */
301 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
302 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
303 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
304 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
305 /* low sh */
306 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 0;
307 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 0;
308 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
309 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
310 /* mid sh */
311 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 0;
312 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 0;
313 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
314 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
315 /* high sh */
316 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 0;
317 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
318 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
319 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
320 /* low mh */
321 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 0;
322 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
323 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
324 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
325 /* mid mh */
326 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 0;
327 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
328 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
329 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
330 /* high mh */
331 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 0;
332 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
333 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
334 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
335 }
336
337 /**
338 * r100_pm_misc - set additional pm hw parameters callback.
339 *
340 * @rdev: radeon_device pointer
341 *
342 * Set non-clock parameters associated with a power state
343 * (voltage, pcie lanes, etc.) (r1xx-r4xx).
344 */
345 void r100_pm_misc(struct radeon_device *rdev)
346 {
347 int requested_index = rdev->pm.requested_power_state_index;
348 struct radeon_power_state *ps = &rdev->pm.power_state[requested_index];
349 struct radeon_voltage *voltage = &ps->clock_info[0].voltage;
350 u32 tmp, sclk_cntl, sclk_cntl2, sclk_more_cntl;
351
352 if ((voltage->type == VOLTAGE_GPIO) && (voltage->gpio.valid)) {
353 if (ps->misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) {
354 tmp = RREG32(voltage->gpio.reg);
355 if (voltage->active_high)
356 tmp |= voltage->gpio.mask;
357 else
358 tmp &= ~(voltage->gpio.mask);
359 WREG32(voltage->gpio.reg, tmp);
360 if (voltage->delay)
361 udelay(voltage->delay);
362 } else {
363 tmp = RREG32(voltage->gpio.reg);
364 if (voltage->active_high)
365 tmp &= ~voltage->gpio.mask;
366 else
367 tmp |= voltage->gpio.mask;
368 WREG32(voltage->gpio.reg, tmp);
369 if (voltage->delay)
370 udelay(voltage->delay);
371 }
372 }
373
374 sclk_cntl = RREG32_PLL(SCLK_CNTL);
375 sclk_cntl2 = RREG32_PLL(SCLK_CNTL2);
376 sclk_cntl2 &= ~REDUCED_SPEED_SCLK_SEL(3);
377 sclk_more_cntl = RREG32_PLL(SCLK_MORE_CNTL);
378 sclk_more_cntl &= ~VOLTAGE_DELAY_SEL(3);
379 if (ps->misc & ATOM_PM_MISCINFO_ASIC_REDUCED_SPEED_SCLK_EN) {
380 sclk_more_cntl |= REDUCED_SPEED_SCLK_EN;
381 if (ps->misc & ATOM_PM_MISCINFO_DYN_CLK_3D_IDLE)
382 sclk_cntl2 |= REDUCED_SPEED_SCLK_MODE;
383 else
384 sclk_cntl2 &= ~REDUCED_SPEED_SCLK_MODE;
385 if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_2)
386 sclk_cntl2 |= REDUCED_SPEED_SCLK_SEL(0);
387 else if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_4)
388 sclk_cntl2 |= REDUCED_SPEED_SCLK_SEL(2);
389 } else
390 sclk_more_cntl &= ~REDUCED_SPEED_SCLK_EN;
391
392 if (ps->misc & ATOM_PM_MISCINFO_ASIC_DYNAMIC_VOLTAGE_EN) {
393 sclk_more_cntl |= IO_CG_VOLTAGE_DROP;
394 if (voltage->delay) {
395 sclk_more_cntl |= VOLTAGE_DROP_SYNC;
396 switch (voltage->delay) {
397 case 33:
398 sclk_more_cntl |= VOLTAGE_DELAY_SEL(0);
399 break;
400 case 66:
401 sclk_more_cntl |= VOLTAGE_DELAY_SEL(1);
402 break;
403 case 99:
404 sclk_more_cntl |= VOLTAGE_DELAY_SEL(2);
405 break;
406 case 132:
407 sclk_more_cntl |= VOLTAGE_DELAY_SEL(3);
408 break;
409 }
410 } else
411 sclk_more_cntl &= ~VOLTAGE_DROP_SYNC;
412 } else
413 sclk_more_cntl &= ~IO_CG_VOLTAGE_DROP;
414
415 if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_HDP_BLOCK_EN)
416 sclk_cntl &= ~FORCE_HDP;
417 else
418 sclk_cntl |= FORCE_HDP;
419
420 WREG32_PLL(SCLK_CNTL, sclk_cntl);
421 WREG32_PLL(SCLK_CNTL2, sclk_cntl2);
422 WREG32_PLL(SCLK_MORE_CNTL, sclk_more_cntl);
423
424 /* set pcie lanes */
425 if ((rdev->flags & RADEON_IS_PCIE) &&
426 !(rdev->flags & RADEON_IS_IGP) &&
427 rdev->asic->pm.set_pcie_lanes &&
428 (ps->pcie_lanes !=
429 rdev->pm.power_state[rdev->pm.current_power_state_index].pcie_lanes)) {
430 radeon_set_pcie_lanes(rdev,
431 ps->pcie_lanes);
432 DRM_DEBUG_DRIVER("Setting: p: %d\n", ps->pcie_lanes);
433 }
434 }
435
436 /**
437 * r100_pm_prepare - pre-power state change callback.
438 *
439 * @rdev: radeon_device pointer
440 *
441 * Prepare for a power state change (r1xx-r4xx).
442 */
443 void r100_pm_prepare(struct radeon_device *rdev)
444 {
445 struct drm_device *ddev = rdev->ddev;
446 struct drm_crtc *crtc;
447 struct radeon_crtc *radeon_crtc;
448 u32 tmp;
449
450 /* disable any active CRTCs */
451 list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
452 radeon_crtc = to_radeon_crtc(crtc);
453 if (radeon_crtc->enabled) {
454 if (radeon_crtc->crtc_id) {
455 tmp = RREG32(RADEON_CRTC2_GEN_CNTL);
456 tmp |= RADEON_CRTC2_DISP_REQ_EN_B;
457 WREG32(RADEON_CRTC2_GEN_CNTL, tmp);
458 } else {
459 tmp = RREG32(RADEON_CRTC_GEN_CNTL);
460 tmp |= RADEON_CRTC_DISP_REQ_EN_B;
461 WREG32(RADEON_CRTC_GEN_CNTL, tmp);
462 }
463 }
464 }
465 }
466
467 /**
468 * r100_pm_finish - post-power state change callback.
469 *
470 * @rdev: radeon_device pointer
471 *
472 * Clean up after a power state change (r1xx-r4xx).
473 */
474 void r100_pm_finish(struct radeon_device *rdev)
475 {
476 struct drm_device *ddev = rdev->ddev;
477 struct drm_crtc *crtc;
478 struct radeon_crtc *radeon_crtc;
479 u32 tmp;
480
481 /* enable any active CRTCs */
482 list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
483 radeon_crtc = to_radeon_crtc(crtc);
484 if (radeon_crtc->enabled) {
485 if (radeon_crtc->crtc_id) {
486 tmp = RREG32(RADEON_CRTC2_GEN_CNTL);
487 tmp &= ~RADEON_CRTC2_DISP_REQ_EN_B;
488 WREG32(RADEON_CRTC2_GEN_CNTL, tmp);
489 } else {
490 tmp = RREG32(RADEON_CRTC_GEN_CNTL);
491 tmp &= ~RADEON_CRTC_DISP_REQ_EN_B;
492 WREG32(RADEON_CRTC_GEN_CNTL, tmp);
493 }
494 }
495 }
496 }
497
498 /**
499 * r100_gui_idle - gui idle callback.
500 *
501 * @rdev: radeon_device pointer
502 *
503 * Check of the GUI (2D/3D engines) are idle (r1xx-r5xx).
504 * Returns true if idle, false if not.
505 */
506 bool r100_gui_idle(struct radeon_device *rdev)
507 {
508 if (RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_ACTIVE)
509 return false;
510 else
511 return true;
512 }
513
514 /* hpd for digital panel detect/disconnect */
515 /**
516 * r100_hpd_sense - hpd sense callback.
517 *
518 * @rdev: radeon_device pointer
519 * @hpd: hpd (hotplug detect) pin
520 *
521 * Checks if a digital monitor is connected (r1xx-r4xx).
522 * Returns true if connected, false if not connected.
523 */
524 bool r100_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
525 {
526 bool connected = false;
527
528 switch (hpd) {
529 case RADEON_HPD_1:
530 if (RREG32(RADEON_FP_GEN_CNTL) & RADEON_FP_DETECT_SENSE)
531 connected = true;
532 break;
533 case RADEON_HPD_2:
534 if (RREG32(RADEON_FP2_GEN_CNTL) & RADEON_FP2_DETECT_SENSE)
535 connected = true;
536 break;
537 default:
538 break;
539 }
540 return connected;
541 }
542
543 /**
544 * r100_hpd_set_polarity - hpd set polarity callback.
545 *
546 * @rdev: radeon_device pointer
547 * @hpd: hpd (hotplug detect) pin
548 *
549 * Set the polarity of the hpd pin (r1xx-r4xx).
550 */
551 void r100_hpd_set_polarity(struct radeon_device *rdev,
552 enum radeon_hpd_id hpd)
553 {
554 u32 tmp;
555 bool connected = r100_hpd_sense(rdev, hpd);
556
557 switch (hpd) {
558 case RADEON_HPD_1:
559 tmp = RREG32(RADEON_FP_GEN_CNTL);
560 if (connected)
561 tmp &= ~RADEON_FP_DETECT_INT_POL;
562 else
563 tmp |= RADEON_FP_DETECT_INT_POL;
564 WREG32(RADEON_FP_GEN_CNTL, tmp);
565 break;
566 case RADEON_HPD_2:
567 tmp = RREG32(RADEON_FP2_GEN_CNTL);
568 if (connected)
569 tmp &= ~RADEON_FP2_DETECT_INT_POL;
570 else
571 tmp |= RADEON_FP2_DETECT_INT_POL;
572 WREG32(RADEON_FP2_GEN_CNTL, tmp);
573 break;
574 default:
575 break;
576 }
577 }
578
579 /**
580 * r100_hpd_init - hpd setup callback.
581 *
582 * @rdev: radeon_device pointer
583 *
584 * Setup the hpd pins used by the card (r1xx-r4xx).
585 * Set the polarity, and enable the hpd interrupts.
586 */
587 void r100_hpd_init(struct radeon_device *rdev)
588 {
589 struct drm_device *dev = rdev->ddev;
590 struct drm_connector *connector;
591 unsigned enable = 0;
592
593 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
594 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
595 enable |= 1 << radeon_connector->hpd.hpd;
596 radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd);
597 }
598 radeon_irq_kms_enable_hpd(rdev, enable);
599 }
600
601 /**
602 * r100_hpd_fini - hpd tear down callback.
603 *
604 * @rdev: radeon_device pointer
605 *
606 * Tear down the hpd pins used by the card (r1xx-r4xx).
607 * Disable the hpd interrupts.
608 */
609 void r100_hpd_fini(struct radeon_device *rdev)
610 {
611 struct drm_device *dev = rdev->ddev;
612 struct drm_connector *connector;
613 unsigned disable = 0;
614
615 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
616 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
617 disable |= 1 << radeon_connector->hpd.hpd;
618 }
619 radeon_irq_kms_disable_hpd(rdev, disable);
620 }
621
622 /*
623 * PCI GART
624 */
625 void r100_pci_gart_tlb_flush(struct radeon_device *rdev)
626 {
627 /* TODO: can we do somethings here ? */
628 /* It seems hw only cache one entry so we should discard this
629 * entry otherwise if first GPU GART read hit this entry it
630 * could end up in wrong address. */
631 }
632
633 int r100_pci_gart_init(struct radeon_device *rdev)
634 {
635 int r;
636
637 if (rdev->gart.ptr) {
638 WARN(1, "R100 PCI GART already initialized\n");
639 return 0;
640 }
641 /* Initialize common gart structure */
642 r = radeon_gart_init(rdev);
643 if (r)
644 return r;
645 rdev->gart.table_size = rdev->gart.num_gpu_pages * 4;
646 rdev->asic->gart.tlb_flush = &r100_pci_gart_tlb_flush;
647 rdev->asic->gart.set_page = &r100_pci_gart_set_page;
648 return radeon_gart_table_ram_alloc(rdev);
649 }
650
651 int r100_pci_gart_enable(struct radeon_device *rdev)
652 {
653 uint32_t tmp;
654
655 radeon_gart_restore(rdev);
656 /* discard memory request outside of configured range */
657 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS;
658 WREG32(RADEON_AIC_CNTL, tmp);
659 /* set address range for PCI address translate */
660 WREG32(RADEON_AIC_LO_ADDR, rdev->mc.gtt_start);
661 WREG32(RADEON_AIC_HI_ADDR, rdev->mc.gtt_end);
662 /* set PCI GART page-table base address */
663 WREG32(RADEON_AIC_PT_BASE, rdev->gart.table_addr);
664 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_PCIGART_TRANSLATE_EN;
665 WREG32(RADEON_AIC_CNTL, tmp);
666 r100_pci_gart_tlb_flush(rdev);
667 DRM_INFO("PCI GART of %uM enabled (table at 0x%016llX).\n",
668 (unsigned)(rdev->mc.gtt_size >> 20),
669 (unsigned long long)rdev->gart.table_addr);
670 rdev->gart.ready = true;
671 return 0;
672 }
673
674 void r100_pci_gart_disable(struct radeon_device *rdev)
675 {
676 uint32_t tmp;
677
678 /* discard memory request outside of configured range */
679 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS;
680 WREG32(RADEON_AIC_CNTL, tmp & ~RADEON_PCIGART_TRANSLATE_EN);
681 WREG32(RADEON_AIC_LO_ADDR, 0);
682 WREG32(RADEON_AIC_HI_ADDR, 0);
683 }
684
685 void r100_pci_gart_set_page(struct radeon_device *rdev, unsigned i,
686 uint64_t addr)
687 {
688 u32 *gtt = rdev->gart.ptr;
689 gtt[i] = cpu_to_le32(lower_32_bits(addr));
690 }
691
692 void r100_pci_gart_fini(struct radeon_device *rdev)
693 {
694 radeon_gart_fini(rdev);
695 r100_pci_gart_disable(rdev);
696 radeon_gart_table_ram_free(rdev);
697 }
698
699 int r100_irq_set(struct radeon_device *rdev)
700 {
701 uint32_t tmp = 0;
702
703 if (!rdev->irq.installed) {
704 WARN(1, "Can't enable IRQ/MSI because no handler is installed\n");
705 WREG32(R_000040_GEN_INT_CNTL, 0);
706 return -EINVAL;
707 }
708 if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) {
709 tmp |= RADEON_SW_INT_ENABLE;
710 }
711 if (rdev->irq.crtc_vblank_int[0] ||
712 atomic_read(&rdev->irq.pflip[0])) {
713 tmp |= RADEON_CRTC_VBLANK_MASK;
714 }
715 if (rdev->irq.crtc_vblank_int[1] ||
716 atomic_read(&rdev->irq.pflip[1])) {
717 tmp |= RADEON_CRTC2_VBLANK_MASK;
718 }
719 if (rdev->irq.hpd[0]) {
720 tmp |= RADEON_FP_DETECT_MASK;
721 }
722 if (rdev->irq.hpd[1]) {
723 tmp |= RADEON_FP2_DETECT_MASK;
724 }
725 WREG32(RADEON_GEN_INT_CNTL, tmp);
726 return 0;
727 }
728
729 void r100_irq_disable(struct radeon_device *rdev)
730 {
731 u32 tmp;
732
733 WREG32(R_000040_GEN_INT_CNTL, 0);
734 /* Wait and acknowledge irq */
735 mdelay(1);
736 tmp = RREG32(R_000044_GEN_INT_STATUS);
737 WREG32(R_000044_GEN_INT_STATUS, tmp);
738 }
739
740 static uint32_t r100_irq_ack(struct radeon_device *rdev)
741 {
742 uint32_t irqs = RREG32(RADEON_GEN_INT_STATUS);
743 uint32_t irq_mask = RADEON_SW_INT_TEST |
744 RADEON_CRTC_VBLANK_STAT | RADEON_CRTC2_VBLANK_STAT |
745 RADEON_FP_DETECT_STAT | RADEON_FP2_DETECT_STAT;
746
747 if (irqs) {
748 WREG32(RADEON_GEN_INT_STATUS, irqs);
749 }
750 return irqs & irq_mask;
751 }
752
753 int r100_irq_process(struct radeon_device *rdev)
754 {
755 uint32_t status, msi_rearm;
756 bool queue_hotplug = false;
757
758 status = r100_irq_ack(rdev);
759 if (!status) {
760 return IRQ_NONE;
761 }
762 if (rdev->shutdown) {
763 return IRQ_NONE;
764 }
765 while (status) {
766 /* SW interrupt */
767 if (status & RADEON_SW_INT_TEST) {
768 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
769 }
770 /* Vertical blank interrupts */
771 if (status & RADEON_CRTC_VBLANK_STAT) {
772 if (rdev->irq.crtc_vblank_int[0]) {
773 drm_handle_vblank(rdev->ddev, 0);
774 rdev->pm.vblank_sync = true;
775 wake_up(&rdev->irq.vblank_queue);
776 }
777 if (atomic_read(&rdev->irq.pflip[0]))
778 radeon_crtc_handle_vblank(rdev, 0);
779 }
780 if (status & RADEON_CRTC2_VBLANK_STAT) {
781 if (rdev->irq.crtc_vblank_int[1]) {
782 drm_handle_vblank(rdev->ddev, 1);
783 rdev->pm.vblank_sync = true;
784 wake_up(&rdev->irq.vblank_queue);
785 }
786 if (atomic_read(&rdev->irq.pflip[1]))
787 radeon_crtc_handle_vblank(rdev, 1);
788 }
789 if (status & RADEON_FP_DETECT_STAT) {
790 queue_hotplug = true;
791 DRM_DEBUG("HPD1\n");
792 }
793 if (status & RADEON_FP2_DETECT_STAT) {
794 queue_hotplug = true;
795 DRM_DEBUG("HPD2\n");
796 }
797 status = r100_irq_ack(rdev);
798 }
799 if (queue_hotplug)
800 schedule_work(&rdev->hotplug_work);
801 if (rdev->msi_enabled) {
802 switch (rdev->family) {
803 case CHIP_RS400:
804 case CHIP_RS480:
805 msi_rearm = RREG32(RADEON_AIC_CNTL) & ~RS400_MSI_REARM;
806 WREG32(RADEON_AIC_CNTL, msi_rearm);
807 WREG32(RADEON_AIC_CNTL, msi_rearm | RS400_MSI_REARM);
808 break;
809 default:
810 WREG32(RADEON_MSI_REARM_EN, RV370_MSI_REARM_EN);
811 break;
812 }
813 }
814 return IRQ_HANDLED;
815 }
816
817 u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc)
818 {
819 if (crtc == 0)
820 return RREG32(RADEON_CRTC_CRNT_FRAME);
821 else
822 return RREG32(RADEON_CRTC2_CRNT_FRAME);
823 }
824
825 /* Who ever call radeon_fence_emit should call ring_lock and ask
826 * for enough space (today caller are ib schedule and buffer move) */
827 void r100_fence_ring_emit(struct radeon_device *rdev,
828 struct radeon_fence *fence)
829 {
830 struct radeon_ring *ring = &rdev->ring[fence->ring];
831
832 /* We have to make sure that caches are flushed before
833 * CPU might read something from VRAM. */
834 radeon_ring_write(ring, PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0));
835 radeon_ring_write(ring, RADEON_RB3D_DC_FLUSH_ALL);
836 radeon_ring_write(ring, PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0));
837 radeon_ring_write(ring, RADEON_RB3D_ZC_FLUSH_ALL);
838 /* Wait until IDLE & CLEAN */
839 radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0));
840 radeon_ring_write(ring, RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_3D_IDLECLEAN);
841 radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0));
842 radeon_ring_write(ring, rdev->config.r100.hdp_cntl |
843 RADEON_HDP_READ_BUFFER_INVALIDATE);
844 radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0));
845 radeon_ring_write(ring, rdev->config.r100.hdp_cntl);
846 /* Emit fence sequence & fire IRQ */
847 radeon_ring_write(ring, PACKET0(rdev->fence_drv[fence->ring].scratch_reg, 0));
848 radeon_ring_write(ring, fence->seq);
849 radeon_ring_write(ring, PACKET0(RADEON_GEN_INT_STATUS, 0));
850 radeon_ring_write(ring, RADEON_SW_INT_FIRE);
851 }
852
853 bool r100_semaphore_ring_emit(struct radeon_device *rdev,
854 struct radeon_ring *ring,
855 struct radeon_semaphore *semaphore,
856 bool emit_wait)
857 {
858 /* Unused on older asics, since we don't have semaphores or multiple rings */
859 BUG();
860 return false;
861 }
862
863 int r100_copy_blit(struct radeon_device *rdev,
864 uint64_t src_offset,
865 uint64_t dst_offset,
866 unsigned num_gpu_pages,
867 struct radeon_fence **fence)
868 {
869 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
870 uint32_t cur_pages;
871 uint32_t stride_bytes = RADEON_GPU_PAGE_SIZE;
872 uint32_t pitch;
873 uint32_t stride_pixels;
874 unsigned ndw;
875 int num_loops;
876 int r = 0;
877
878 /* radeon limited to 16k stride */
879 stride_bytes &= 0x3fff;
880 /* radeon pitch is /64 */
881 pitch = stride_bytes / 64;
882 stride_pixels = stride_bytes / 4;
883 num_loops = DIV_ROUND_UP(num_gpu_pages, 8191);
884
885 /* Ask for enough room for blit + flush + fence */
886 ndw = 64 + (10 * num_loops);
887 r = radeon_ring_lock(rdev, ring, ndw);
888 if (r) {
889 DRM_ERROR("radeon: moving bo (%d) asking for %u dw.\n", r, ndw);
890 return -EINVAL;
891 }
892 while (num_gpu_pages > 0) {
893 cur_pages = num_gpu_pages;
894 if (cur_pages > 8191) {
895 cur_pages = 8191;
896 }
897 num_gpu_pages -= cur_pages;
898
899 /* pages are in Y direction - height
900 page width in X direction - width */
901 radeon_ring_write(ring, PACKET3(PACKET3_BITBLT_MULTI, 8));
902 radeon_ring_write(ring,
903 RADEON_GMC_SRC_PITCH_OFFSET_CNTL |
904 RADEON_GMC_DST_PITCH_OFFSET_CNTL |
905 RADEON_GMC_SRC_CLIPPING |
906 RADEON_GMC_DST_CLIPPING |
907 RADEON_GMC_BRUSH_NONE |
908 (RADEON_COLOR_FORMAT_ARGB8888 << 8) |
909 RADEON_GMC_SRC_DATATYPE_COLOR |
910 RADEON_ROP3_S |
911 RADEON_DP_SRC_SOURCE_MEMORY |
912 RADEON_GMC_CLR_CMP_CNTL_DIS |
913 RADEON_GMC_WR_MSK_DIS);
914 radeon_ring_write(ring, (pitch << 22) | (src_offset >> 10));
915 radeon_ring_write(ring, (pitch << 22) | (dst_offset >> 10));
916 radeon_ring_write(ring, (0x1fff) | (0x1fff << 16));
917 radeon_ring_write(ring, 0);
918 radeon_ring_write(ring, (0x1fff) | (0x1fff << 16));
919 radeon_ring_write(ring, num_gpu_pages);
920 radeon_ring_write(ring, num_gpu_pages);
921 radeon_ring_write(ring, cur_pages | (stride_pixels << 16));
922 }
923 radeon_ring_write(ring, PACKET0(RADEON_DSTCACHE_CTLSTAT, 0));
924 radeon_ring_write(ring, RADEON_RB2D_DC_FLUSH_ALL);
925 radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0));
926 radeon_ring_write(ring,
927 RADEON_WAIT_2D_IDLECLEAN |
928 RADEON_WAIT_HOST_IDLECLEAN |
929 RADEON_WAIT_DMA_GUI_IDLE);
930 if (fence) {
931 r = radeon_fence_emit(rdev, fence, RADEON_RING_TYPE_GFX_INDEX);
932 }
933 radeon_ring_unlock_commit(rdev, ring);
934 return r;
935 }
936
937 static int r100_cp_wait_for_idle(struct radeon_device *rdev)
938 {
939 unsigned i;
940 u32 tmp;
941
942 for (i = 0; i < rdev->usec_timeout; i++) {
943 tmp = RREG32(R_000E40_RBBM_STATUS);
944 if (!G_000E40_CP_CMDSTRM_BUSY(tmp)) {
945 return 0;
946 }
947 udelay(1);
948 }
949 return -1;
950 }
951
952 void r100_ring_start(struct radeon_device *rdev, struct radeon_ring *ring)
953 {
954 int r;
955
956 r = radeon_ring_lock(rdev, ring, 2);
957 if (r) {
958 return;
959 }
960 radeon_ring_write(ring, PACKET0(RADEON_ISYNC_CNTL, 0));
961 radeon_ring_write(ring,
962 RADEON_ISYNC_ANY2D_IDLE3D |
963 RADEON_ISYNC_ANY3D_IDLE2D |
964 RADEON_ISYNC_WAIT_IDLEGUI |
965 RADEON_ISYNC_CPSCRATCH_IDLEGUI);
966 radeon_ring_unlock_commit(rdev, ring);
967 }
968
969
970 /* Load the microcode for the CP */
971 static int r100_cp_init_microcode(struct radeon_device *rdev)
972 {
973 const char *fw_name = NULL;
974 int err;
975
976 DRM_DEBUG_KMS("\n");
977
978 if ((rdev->family == CHIP_R100) || (rdev->family == CHIP_RV100) ||
979 (rdev->family == CHIP_RV200) || (rdev->family == CHIP_RS100) ||
980 (rdev->family == CHIP_RS200)) {
981 DRM_INFO("Loading R100 Microcode\n");
982 fw_name = FIRMWARE_R100;
983 } else if ((rdev->family == CHIP_R200) ||
984 (rdev->family == CHIP_RV250) ||
985 (rdev->family == CHIP_RV280) ||
986 (rdev->family == CHIP_RS300)) {
987 DRM_INFO("Loading R200 Microcode\n");
988 fw_name = FIRMWARE_R200;
989 } else if ((rdev->family == CHIP_R300) ||
990 (rdev->family == CHIP_R350) ||
991 (rdev->family == CHIP_RV350) ||
992 (rdev->family == CHIP_RV380) ||
993 (rdev->family == CHIP_RS400) ||
994 (rdev->family == CHIP_RS480)) {
995 DRM_INFO("Loading R300 Microcode\n");
996 fw_name = FIRMWARE_R300;
997 } else if ((rdev->family == CHIP_R420) ||
998 (rdev->family == CHIP_R423) ||
999 (rdev->family == CHIP_RV410)) {
1000 DRM_INFO("Loading R400 Microcode\n");
1001 fw_name = FIRMWARE_R420;
1002 } else if ((rdev->family == CHIP_RS690) ||
1003 (rdev->family == CHIP_RS740)) {
1004 DRM_INFO("Loading RS690/RS740 Microcode\n");
1005 fw_name = FIRMWARE_RS690;
1006 } else if (rdev->family == CHIP_RS600) {
1007 DRM_INFO("Loading RS600 Microcode\n");
1008 fw_name = FIRMWARE_RS600;
1009 } else if ((rdev->family == CHIP_RV515) ||
1010 (rdev->family == CHIP_R520) ||
1011 (rdev->family == CHIP_RV530) ||
1012 (rdev->family == CHIP_R580) ||
1013 (rdev->family == CHIP_RV560) ||
1014 (rdev->family == CHIP_RV570)) {
1015 DRM_INFO("Loading R500 Microcode\n");
1016 fw_name = FIRMWARE_R520;
1017 }
1018
1019 err = request_firmware(&rdev->me_fw, fw_name, rdev->dev);
1020 if (err) {
1021 printk(KERN_ERR "radeon_cp: Failed to load firmware \"%s\"\n",
1022 fw_name);
1023 } else if (rdev->me_fw->size % 8) {
1024 printk(KERN_ERR
1025 "radeon_cp: Bogus length %zu in firmware \"%s\"\n",
1026 rdev->me_fw->size, fw_name);
1027 err = -EINVAL;
1028 release_firmware(rdev->me_fw);
1029 rdev->me_fw = NULL;
1030 }
1031 return err;
1032 }
1033
1034 u32 r100_gfx_get_rptr(struct radeon_device *rdev,
1035 struct radeon_ring *ring)
1036 {
1037 u32 rptr;
1038
1039 if (rdev->wb.enabled)
1040 rptr = le32_to_cpu(rdev->wb.wb[ring->rptr_offs/4]);
1041 else
1042 rptr = RREG32(RADEON_CP_RB_RPTR);
1043
1044 return rptr;
1045 }
1046
1047 u32 r100_gfx_get_wptr(struct radeon_device *rdev,
1048 struct radeon_ring *ring)
1049 {
1050 u32 wptr;
1051
1052 wptr = RREG32(RADEON_CP_RB_WPTR);
1053
1054 return wptr;
1055 }
1056
1057 void r100_gfx_set_wptr(struct radeon_device *rdev,
1058 struct radeon_ring *ring)
1059 {
1060 WREG32(RADEON_CP_RB_WPTR, ring->wptr);
1061 (void)RREG32(RADEON_CP_RB_WPTR);
1062 }
1063
1064 static void r100_cp_load_microcode(struct radeon_device *rdev)
1065 {
1066 const __be32 *fw_data;
1067 int i, size;
1068
1069 if (r100_gui_wait_for_idle(rdev)) {
1070 printk(KERN_WARNING "Failed to wait GUI idle while "
1071 "programming pipes. Bad things might happen.\n");
1072 }
1073
1074 if (rdev->me_fw) {
1075 size = rdev->me_fw->size / 4;
1076 fw_data = (const __be32 *)&rdev->me_fw->data[0];
1077 WREG32(RADEON_CP_ME_RAM_ADDR, 0);
1078 for (i = 0; i < size; i += 2) {
1079 WREG32(RADEON_CP_ME_RAM_DATAH,
1080 be32_to_cpup(&fw_data[i]));
1081 WREG32(RADEON_CP_ME_RAM_DATAL,
1082 be32_to_cpup(&fw_data[i + 1]));
1083 }
1084 }
1085 }
1086
1087 int r100_cp_init(struct radeon_device *rdev, unsigned ring_size)
1088 {
1089 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
1090 unsigned rb_bufsz;
1091 unsigned rb_blksz;
1092 unsigned max_fetch;
1093 unsigned pre_write_timer;
1094 unsigned pre_write_limit;
1095 unsigned indirect2_start;
1096 unsigned indirect1_start;
1097 uint32_t tmp;
1098 int r;
1099
1100 if (r100_debugfs_cp_init(rdev)) {
1101 DRM_ERROR("Failed to register debugfs file for CP !\n");
1102 }
1103 if (!rdev->me_fw) {
1104 r = r100_cp_init_microcode(rdev);
1105 if (r) {
1106 DRM_ERROR("Failed to load firmware!\n");
1107 return r;
1108 }
1109 }
1110
1111 /* Align ring size */
1112 rb_bufsz = order_base_2(ring_size / 8);
1113 ring_size = (1 << (rb_bufsz + 1)) * 4;
1114 r100_cp_load_microcode(rdev);
1115 r = radeon_ring_init(rdev, ring, ring_size, RADEON_WB_CP_RPTR_OFFSET,
1116 RADEON_CP_PACKET2);
1117 if (r) {
1118 return r;
1119 }
1120 /* Each time the cp read 1024 bytes (16 dword/quadword) update
1121 * the rptr copy in system ram */
1122 rb_blksz = 9;
1123 /* cp will read 128bytes at a time (4 dwords) */
1124 max_fetch = 1;
1125 ring->align_mask = 16 - 1;
1126 /* Write to CP_RB_WPTR will be delayed for pre_write_timer clocks */
1127 pre_write_timer = 64;
1128 /* Force CP_RB_WPTR write if written more than one time before the
1129 * delay expire
1130 */
1131 pre_write_limit = 0;
1132 /* Setup the cp cache like this (cache size is 96 dwords) :
1133 * RING 0 to 15
1134 * INDIRECT1 16 to 79
1135 * INDIRECT2 80 to 95
1136 * So ring cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords))
1137 * indirect1 cache size is 64dwords (> (2 * max_fetch = 2 * 4dwords))
1138 * indirect2 cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords))
1139 * Idea being that most of the gpu cmd will be through indirect1 buffer
1140 * so it gets the bigger cache.
1141 */
1142 indirect2_start = 80;
1143 indirect1_start = 16;
1144 /* cp setup */
1145 WREG32(0x718, pre_write_timer | (pre_write_limit << 28));
1146 tmp = (REG_SET(RADEON_RB_BUFSZ, rb_bufsz) |
1147 REG_SET(RADEON_RB_BLKSZ, rb_blksz) |
1148 REG_SET(RADEON_MAX_FETCH, max_fetch));
1149 #ifdef __BIG_ENDIAN
1150 tmp |= RADEON_BUF_SWAP_32BIT;
1151 #endif
1152 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_NO_UPDATE);
1153
1154 /* Set ring address */
1155 DRM_INFO("radeon: ring at 0x%016lX\n", (unsigned long)ring->gpu_addr);
1156 WREG32(RADEON_CP_RB_BASE, ring->gpu_addr);
1157 /* Force read & write ptr to 0 */
1158 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA | RADEON_RB_NO_UPDATE);
1159 WREG32(RADEON_CP_RB_RPTR_WR, 0);
1160 ring->wptr = 0;
1161 WREG32(RADEON_CP_RB_WPTR, ring->wptr);
1162
1163 /* set the wb address whether it's enabled or not */
1164 WREG32(R_00070C_CP_RB_RPTR_ADDR,
1165 S_00070C_RB_RPTR_ADDR((rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) >> 2));
1166 WREG32(R_000774_SCRATCH_ADDR, rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET);
1167
1168 if (rdev->wb.enabled)
1169 WREG32(R_000770_SCRATCH_UMSK, 0xff);
1170 else {
1171 tmp |= RADEON_RB_NO_UPDATE;
1172 WREG32(R_000770_SCRATCH_UMSK, 0);
1173 }
1174
1175 WREG32(RADEON_CP_RB_CNTL, tmp);
1176 udelay(10);
1177 /* Set cp mode to bus mastering & enable cp*/
1178 WREG32(RADEON_CP_CSQ_MODE,
1179 REG_SET(RADEON_INDIRECT2_START, indirect2_start) |
1180 REG_SET(RADEON_INDIRECT1_START, indirect1_start));
1181 WREG32(RADEON_CP_RB_WPTR_DELAY, 0);
1182 WREG32(RADEON_CP_CSQ_MODE, 0x00004D4D);
1183 WREG32(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIBM_INDBM);
1184
1185 /* at this point everything should be setup correctly to enable master */
1186 pci_set_master(rdev->pdev);
1187
1188 radeon_ring_start(rdev, RADEON_RING_TYPE_GFX_INDEX, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]);
1189 r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, ring);
1190 if (r) {
1191 DRM_ERROR("radeon: cp isn't working (%d).\n", r);
1192 return r;
1193 }
1194 ring->ready = true;
1195 radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size);
1196
1197 if (!ring->rptr_save_reg /* not resuming from suspend */
1198 && radeon_ring_supports_scratch_reg(rdev, ring)) {
1199 r = radeon_scratch_get(rdev, &ring->rptr_save_reg);
1200 if (r) {
1201 DRM_ERROR("failed to get scratch reg for rptr save (%d).\n", r);
1202 ring->rptr_save_reg = 0;
1203 }
1204 }
1205 return 0;
1206 }
1207
1208 void r100_cp_fini(struct radeon_device *rdev)
1209 {
1210 if (r100_cp_wait_for_idle(rdev)) {
1211 DRM_ERROR("Wait for CP idle timeout, shutting down CP.\n");
1212 }
1213 /* Disable ring */
1214 r100_cp_disable(rdev);
1215 radeon_scratch_free(rdev, rdev->ring[RADEON_RING_TYPE_GFX_INDEX].rptr_save_reg);
1216 radeon_ring_fini(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]);
1217 DRM_INFO("radeon: cp finalized\n");
1218 }
1219
1220 void r100_cp_disable(struct radeon_device *rdev)
1221 {
1222 /* Disable ring */
1223 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
1224 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
1225 WREG32(RADEON_CP_CSQ_MODE, 0);
1226 WREG32(RADEON_CP_CSQ_CNTL, 0);
1227 WREG32(R_000770_SCRATCH_UMSK, 0);
1228 if (r100_gui_wait_for_idle(rdev)) {
1229 printk(KERN_WARNING "Failed to wait GUI idle while "
1230 "programming pipes. Bad things might happen.\n");
1231 }
1232 }
1233
1234 /*
1235 * CS functions
1236 */
1237 int r100_reloc_pitch_offset(struct radeon_cs_parser *p,
1238 struct radeon_cs_packet *pkt,
1239 unsigned idx,
1240 unsigned reg)
1241 {
1242 int r;
1243 u32 tile_flags = 0;
1244 u32 tmp;
1245 struct radeon_cs_reloc *reloc;
1246 u32 value;
1247
1248 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1249 if (r) {
1250 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1251 idx, reg);
1252 radeon_cs_dump_packet(p, pkt);
1253 return r;
1254 }
1255
1256 value = radeon_get_ib_value(p, idx);
1257 tmp = value & 0x003fffff;
1258 tmp += (((u32)reloc->gpu_offset) >> 10);
1259
1260 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
1261 if (reloc->tiling_flags & RADEON_TILING_MACRO)
1262 tile_flags |= RADEON_DST_TILE_MACRO;
1263 if (reloc->tiling_flags & RADEON_TILING_MICRO) {
1264 if (reg == RADEON_SRC_PITCH_OFFSET) {
1265 DRM_ERROR("Cannot src blit from microtiled surface\n");
1266 radeon_cs_dump_packet(p, pkt);
1267 return -EINVAL;
1268 }
1269 tile_flags |= RADEON_DST_TILE_MICRO;
1270 }
1271
1272 tmp |= tile_flags;
1273 p->ib.ptr[idx] = (value & 0x3fc00000) | tmp;
1274 } else
1275 p->ib.ptr[idx] = (value & 0xffc00000) | tmp;
1276 return 0;
1277 }
1278
1279 int r100_packet3_load_vbpntr(struct radeon_cs_parser *p,
1280 struct radeon_cs_packet *pkt,
1281 int idx)
1282 {
1283 unsigned c, i;
1284 struct radeon_cs_reloc *reloc;
1285 struct r100_cs_track *track;
1286 int r = 0;
1287 volatile uint32_t *ib;
1288 u32 idx_value;
1289
1290 ib = p->ib.ptr;
1291 track = (struct r100_cs_track *)p->track;
1292 c = radeon_get_ib_value(p, idx++) & 0x1F;
1293 if (c > 16) {
1294 DRM_ERROR("Only 16 vertex buffers are allowed %d\n",
1295 pkt->opcode);
1296 radeon_cs_dump_packet(p, pkt);
1297 return -EINVAL;
1298 }
1299 track->num_arrays = c;
1300 for (i = 0; i < (c - 1); i+=2, idx+=3) {
1301 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1302 if (r) {
1303 DRM_ERROR("No reloc for packet3 %d\n",
1304 pkt->opcode);
1305 radeon_cs_dump_packet(p, pkt);
1306 return r;
1307 }
1308 idx_value = radeon_get_ib_value(p, idx);
1309 ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->gpu_offset);
1310
1311 track->arrays[i + 0].esize = idx_value >> 8;
1312 track->arrays[i + 0].robj = reloc->robj;
1313 track->arrays[i + 0].esize &= 0x7F;
1314 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1315 if (r) {
1316 DRM_ERROR("No reloc for packet3 %d\n",
1317 pkt->opcode);
1318 radeon_cs_dump_packet(p, pkt);
1319 return r;
1320 }
1321 ib[idx+2] = radeon_get_ib_value(p, idx + 2) + ((u32)reloc->gpu_offset);
1322 track->arrays[i + 1].robj = reloc->robj;
1323 track->arrays[i + 1].esize = idx_value >> 24;
1324 track->arrays[i + 1].esize &= 0x7F;
1325 }
1326 if (c & 1) {
1327 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1328 if (r) {
1329 DRM_ERROR("No reloc for packet3 %d\n",
1330 pkt->opcode);
1331 radeon_cs_dump_packet(p, pkt);
1332 return r;
1333 }
1334 idx_value = radeon_get_ib_value(p, idx);
1335 ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->gpu_offset);
1336 track->arrays[i + 0].robj = reloc->robj;
1337 track->arrays[i + 0].esize = idx_value >> 8;
1338 track->arrays[i + 0].esize &= 0x7F;
1339 }
1340 return r;
1341 }
1342
1343 int r100_cs_parse_packet0(struct radeon_cs_parser *p,
1344 struct radeon_cs_packet *pkt,
1345 const unsigned *auth, unsigned n,
1346 radeon_packet0_check_t check)
1347 {
1348 unsigned reg;
1349 unsigned i, j, m;
1350 unsigned idx;
1351 int r;
1352
1353 idx = pkt->idx + 1;
1354 reg = pkt->reg;
1355 /* Check that register fall into register range
1356 * determined by the number of entry (n) in the
1357 * safe register bitmap.
1358 */
1359 if (pkt->one_reg_wr) {
1360 if ((reg >> 7) > n) {
1361 return -EINVAL;
1362 }
1363 } else {
1364 if (((reg + (pkt->count << 2)) >> 7) > n) {
1365 return -EINVAL;
1366 }
1367 }
1368 for (i = 0; i <= pkt->count; i++, idx++) {
1369 j = (reg >> 7);
1370 m = 1 << ((reg >> 2) & 31);
1371 if (auth[j] & m) {
1372 r = check(p, pkt, idx, reg);
1373 if (r) {
1374 return r;
1375 }
1376 }
1377 if (pkt->one_reg_wr) {
1378 if (!(auth[j] & m)) {
1379 break;
1380 }
1381 } else {
1382 reg += 4;
1383 }
1384 }
1385 return 0;
1386 }
1387
1388 /**
1389 * r100_cs_packet_next_vline() - parse userspace VLINE packet
1390 * @parser: parser structure holding parsing context.
1391 *
1392 * Userspace sends a special sequence for VLINE waits.
1393 * PACKET0 - VLINE_START_END + value
1394 * PACKET0 - WAIT_UNTIL +_value
1395 * RELOC (P3) - crtc_id in reloc.
1396 *
1397 * This function parses this and relocates the VLINE START END
1398 * and WAIT UNTIL packets to the correct crtc.
1399 * It also detects a switched off crtc and nulls out the
1400 * wait in that case.
1401 */
1402 int r100_cs_packet_parse_vline(struct radeon_cs_parser *p)
1403 {
1404 struct drm_mode_object *obj;
1405 struct drm_crtc *crtc;
1406 struct radeon_crtc *radeon_crtc;
1407 struct radeon_cs_packet p3reloc, waitreloc;
1408 int crtc_id;
1409 int r;
1410 uint32_t header, h_idx, reg;
1411 volatile uint32_t *ib;
1412
1413 ib = p->ib.ptr;
1414
1415 /* parse the wait until */
1416 r = radeon_cs_packet_parse(p, &waitreloc, p->idx);
1417 if (r)
1418 return r;
1419
1420 /* check its a wait until and only 1 count */
1421 if (waitreloc.reg != RADEON_WAIT_UNTIL ||
1422 waitreloc.count != 0) {
1423 DRM_ERROR("vline wait had illegal wait until segment\n");
1424 return -EINVAL;
1425 }
1426
1427 if (radeon_get_ib_value(p, waitreloc.idx + 1) != RADEON_WAIT_CRTC_VLINE) {
1428 DRM_ERROR("vline wait had illegal wait until\n");
1429 return -EINVAL;
1430 }
1431
1432 /* jump over the NOP */
1433 r = radeon_cs_packet_parse(p, &p3reloc, p->idx + waitreloc.count + 2);
1434 if (r)
1435 return r;
1436
1437 h_idx = p->idx - 2;
1438 p->idx += waitreloc.count + 2;
1439 p->idx += p3reloc.count + 2;
1440
1441 header = radeon_get_ib_value(p, h_idx);
1442 crtc_id = radeon_get_ib_value(p, h_idx + 5);
1443 reg = R100_CP_PACKET0_GET_REG(header);
1444 obj = drm_mode_object_find(p->rdev->ddev, crtc_id, DRM_MODE_OBJECT_CRTC);
1445 if (!obj) {
1446 DRM_ERROR("cannot find crtc %d\n", crtc_id);
1447 return -ENOENT;
1448 }
1449 crtc = obj_to_crtc(obj);
1450 radeon_crtc = to_radeon_crtc(crtc);
1451 crtc_id = radeon_crtc->crtc_id;
1452
1453 if (!crtc->enabled) {
1454 /* if the CRTC isn't enabled - we need to nop out the wait until */
1455 ib[h_idx + 2] = PACKET2(0);
1456 ib[h_idx + 3] = PACKET2(0);
1457 } else if (crtc_id == 1) {
1458 switch (reg) {
1459 case AVIVO_D1MODE_VLINE_START_END:
1460 header &= ~R300_CP_PACKET0_REG_MASK;
1461 header |= AVIVO_D2MODE_VLINE_START_END >> 2;
1462 break;
1463 case RADEON_CRTC_GUI_TRIG_VLINE:
1464 header &= ~R300_CP_PACKET0_REG_MASK;
1465 header |= RADEON_CRTC2_GUI_TRIG_VLINE >> 2;
1466 break;
1467 default:
1468 DRM_ERROR("unknown crtc reloc\n");
1469 return -EINVAL;
1470 }
1471 ib[h_idx] = header;
1472 ib[h_idx + 3] |= RADEON_ENG_DISPLAY_SELECT_CRTC1;
1473 }
1474
1475 return 0;
1476 }
1477
1478 static int r100_get_vtx_size(uint32_t vtx_fmt)
1479 {
1480 int vtx_size;
1481 vtx_size = 2;
1482 /* ordered according to bits in spec */
1483 if (vtx_fmt & RADEON_SE_VTX_FMT_W0)
1484 vtx_size++;
1485 if (vtx_fmt & RADEON_SE_VTX_FMT_FPCOLOR)
1486 vtx_size += 3;
1487 if (vtx_fmt & RADEON_SE_VTX_FMT_FPALPHA)
1488 vtx_size++;
1489 if (vtx_fmt & RADEON_SE_VTX_FMT_PKCOLOR)
1490 vtx_size++;
1491 if (vtx_fmt & RADEON_SE_VTX_FMT_FPSPEC)
1492 vtx_size += 3;
1493 if (vtx_fmt & RADEON_SE_VTX_FMT_FPFOG)
1494 vtx_size++;
1495 if (vtx_fmt & RADEON_SE_VTX_FMT_PKSPEC)
1496 vtx_size++;
1497 if (vtx_fmt & RADEON_SE_VTX_FMT_ST0)
1498 vtx_size += 2;
1499 if (vtx_fmt & RADEON_SE_VTX_FMT_ST1)
1500 vtx_size += 2;
1501 if (vtx_fmt & RADEON_SE_VTX_FMT_Q1)
1502 vtx_size++;
1503 if (vtx_fmt & RADEON_SE_VTX_FMT_ST2)
1504 vtx_size += 2;
1505 if (vtx_fmt & RADEON_SE_VTX_FMT_Q2)
1506 vtx_size++;
1507 if (vtx_fmt & RADEON_SE_VTX_FMT_ST3)
1508 vtx_size += 2;
1509 if (vtx_fmt & RADEON_SE_VTX_FMT_Q3)
1510 vtx_size++;
1511 if (vtx_fmt & RADEON_SE_VTX_FMT_Q0)
1512 vtx_size++;
1513 /* blend weight */
1514 if (vtx_fmt & (0x7 << 15))
1515 vtx_size += (vtx_fmt >> 15) & 0x7;
1516 if (vtx_fmt & RADEON_SE_VTX_FMT_N0)
1517 vtx_size += 3;
1518 if (vtx_fmt & RADEON_SE_VTX_FMT_XY1)
1519 vtx_size += 2;
1520 if (vtx_fmt & RADEON_SE_VTX_FMT_Z1)
1521 vtx_size++;
1522 if (vtx_fmt & RADEON_SE_VTX_FMT_W1)
1523 vtx_size++;
1524 if (vtx_fmt & RADEON_SE_VTX_FMT_N1)
1525 vtx_size++;
1526 if (vtx_fmt & RADEON_SE_VTX_FMT_Z)
1527 vtx_size++;
1528 return vtx_size;
1529 }
1530
1531 static int r100_packet0_check(struct radeon_cs_parser *p,
1532 struct radeon_cs_packet *pkt,
1533 unsigned idx, unsigned reg)
1534 {
1535 struct radeon_cs_reloc *reloc;
1536 struct r100_cs_track *track;
1537 volatile uint32_t *ib;
1538 uint32_t tmp;
1539 int r;
1540 int i, face;
1541 u32 tile_flags = 0;
1542 u32 idx_value;
1543
1544 ib = p->ib.ptr;
1545 track = (struct r100_cs_track *)p->track;
1546
1547 idx_value = radeon_get_ib_value(p, idx);
1548
1549 switch (reg) {
1550 case RADEON_CRTC_GUI_TRIG_VLINE:
1551 r = r100_cs_packet_parse_vline(p);
1552 if (r) {
1553 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1554 idx, reg);
1555 radeon_cs_dump_packet(p, pkt);
1556 return r;
1557 }
1558 break;
1559 /* FIXME: only allow PACKET3 blit? easier to check for out of
1560 * range access */
1561 case RADEON_DST_PITCH_OFFSET:
1562 case RADEON_SRC_PITCH_OFFSET:
1563 r = r100_reloc_pitch_offset(p, pkt, idx, reg);
1564 if (r)
1565 return r;
1566 break;
1567 case RADEON_RB3D_DEPTHOFFSET:
1568 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1569 if (r) {
1570 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1571 idx, reg);
1572 radeon_cs_dump_packet(p, pkt);
1573 return r;
1574 }
1575 track->zb.robj = reloc->robj;
1576 track->zb.offset = idx_value;
1577 track->zb_dirty = true;
1578 ib[idx] = idx_value + ((u32)reloc->gpu_offset);
1579 break;
1580 case RADEON_RB3D_COLOROFFSET:
1581 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1582 if (r) {
1583 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1584 idx, reg);
1585 radeon_cs_dump_packet(p, pkt);
1586 return r;
1587 }
1588 track->cb[0].robj = reloc->robj;
1589 track->cb[0].offset = idx_value;
1590 track->cb_dirty = true;
1591 ib[idx] = idx_value + ((u32)reloc->gpu_offset);
1592 break;
1593 case RADEON_PP_TXOFFSET_0:
1594 case RADEON_PP_TXOFFSET_1:
1595 case RADEON_PP_TXOFFSET_2:
1596 i = (reg - RADEON_PP_TXOFFSET_0) / 24;
1597 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1598 if (r) {
1599 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1600 idx, reg);
1601 radeon_cs_dump_packet(p, pkt);
1602 return r;
1603 }
1604 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
1605 if (reloc->tiling_flags & RADEON_TILING_MACRO)
1606 tile_flags |= RADEON_TXO_MACRO_TILE;
1607 if (reloc->tiling_flags & RADEON_TILING_MICRO)
1608 tile_flags |= RADEON_TXO_MICRO_TILE_X2;
1609
1610 tmp = idx_value & ~(0x7 << 2);
1611 tmp |= tile_flags;
1612 ib[idx] = tmp + ((u32)reloc->gpu_offset);
1613 } else
1614 ib[idx] = idx_value + ((u32)reloc->gpu_offset);
1615 track->textures[i].robj = reloc->robj;
1616 track->tex_dirty = true;
1617 break;
1618 case RADEON_PP_CUBIC_OFFSET_T0_0:
1619 case RADEON_PP_CUBIC_OFFSET_T0_1:
1620 case RADEON_PP_CUBIC_OFFSET_T0_2:
1621 case RADEON_PP_CUBIC_OFFSET_T0_3:
1622 case RADEON_PP_CUBIC_OFFSET_T0_4:
1623 i = (reg - RADEON_PP_CUBIC_OFFSET_T0_0) / 4;
1624 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1625 if (r) {
1626 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1627 idx, reg);
1628 radeon_cs_dump_packet(p, pkt);
1629 return r;
1630 }
1631 track->textures[0].cube_info[i].offset = idx_value;
1632 ib[idx] = idx_value + ((u32)reloc->gpu_offset);
1633 track->textures[0].cube_info[i].robj = reloc->robj;
1634 track->tex_dirty = true;
1635 break;
1636 case RADEON_PP_CUBIC_OFFSET_T1_0:
1637 case RADEON_PP_CUBIC_OFFSET_T1_1:
1638 case RADEON_PP_CUBIC_OFFSET_T1_2:
1639 case RADEON_PP_CUBIC_OFFSET_T1_3:
1640 case RADEON_PP_CUBIC_OFFSET_T1_4:
1641 i = (reg - RADEON_PP_CUBIC_OFFSET_T1_0) / 4;
1642 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1643 if (r) {
1644 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1645 idx, reg);
1646 radeon_cs_dump_packet(p, pkt);
1647 return r;
1648 }
1649 track->textures[1].cube_info[i].offset = idx_value;
1650 ib[idx] = idx_value + ((u32)reloc->gpu_offset);
1651 track->textures[1].cube_info[i].robj = reloc->robj;
1652 track->tex_dirty = true;
1653 break;
1654 case RADEON_PP_CUBIC_OFFSET_T2_0:
1655 case RADEON_PP_CUBIC_OFFSET_T2_1:
1656 case RADEON_PP_CUBIC_OFFSET_T2_2:
1657 case RADEON_PP_CUBIC_OFFSET_T2_3:
1658 case RADEON_PP_CUBIC_OFFSET_T2_4:
1659 i = (reg - RADEON_PP_CUBIC_OFFSET_T2_0) / 4;
1660 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1661 if (r) {
1662 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1663 idx, reg);
1664 radeon_cs_dump_packet(p, pkt);
1665 return r;
1666 }
1667 track->textures[2].cube_info[i].offset = idx_value;
1668 ib[idx] = idx_value + ((u32)reloc->gpu_offset);
1669 track->textures[2].cube_info[i].robj = reloc->robj;
1670 track->tex_dirty = true;
1671 break;
1672 case RADEON_RE_WIDTH_HEIGHT:
1673 track->maxy = ((idx_value >> 16) & 0x7FF);
1674 track->cb_dirty = true;
1675 track->zb_dirty = true;
1676 break;
1677 case RADEON_RB3D_COLORPITCH:
1678 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1679 if (r) {
1680 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1681 idx, reg);
1682 radeon_cs_dump_packet(p, pkt);
1683 return r;
1684 }
1685 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
1686 if (reloc->tiling_flags & RADEON_TILING_MACRO)
1687 tile_flags |= RADEON_COLOR_TILE_ENABLE;
1688 if (reloc->tiling_flags & RADEON_TILING_MICRO)
1689 tile_flags |= RADEON_COLOR_MICROTILE_ENABLE;
1690
1691 tmp = idx_value & ~(0x7 << 16);
1692 tmp |= tile_flags;
1693 ib[idx] = tmp;
1694 } else
1695 ib[idx] = idx_value;
1696
1697 track->cb[0].pitch = idx_value & RADEON_COLORPITCH_MASK;
1698 track->cb_dirty = true;
1699 break;
1700 case RADEON_RB3D_DEPTHPITCH:
1701 track->zb.pitch = idx_value & RADEON_DEPTHPITCH_MASK;
1702 track->zb_dirty = true;
1703 break;
1704 case RADEON_RB3D_CNTL:
1705 switch ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f) {
1706 case 7:
1707 case 8:
1708 case 9:
1709 case 11:
1710 case 12:
1711 track->cb[0].cpp = 1;
1712 break;
1713 case 3:
1714 case 4:
1715 case 15:
1716 track->cb[0].cpp = 2;
1717 break;
1718 case 6:
1719 track->cb[0].cpp = 4;
1720 break;
1721 default:
1722 DRM_ERROR("Invalid color buffer format (%d) !\n",
1723 ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f));
1724 return -EINVAL;
1725 }
1726 track->z_enabled = !!(idx_value & RADEON_Z_ENABLE);
1727 track->cb_dirty = true;
1728 track->zb_dirty = true;
1729 break;
1730 case RADEON_RB3D_ZSTENCILCNTL:
1731 switch (idx_value & 0xf) {
1732 case 0:
1733 track->zb.cpp = 2;
1734 break;
1735 case 2:
1736 case 3:
1737 case 4:
1738 case 5:
1739 case 9:
1740 case 11:
1741 track->zb.cpp = 4;
1742 break;
1743 default:
1744 break;
1745 }
1746 track->zb_dirty = true;
1747 break;
1748 case RADEON_RB3D_ZPASS_ADDR:
1749 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1750 if (r) {
1751 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1752 idx, reg);
1753 radeon_cs_dump_packet(p, pkt);
1754 return r;
1755 }
1756 ib[idx] = idx_value + ((u32)reloc->gpu_offset);
1757 break;
1758 case RADEON_PP_CNTL:
1759 {
1760 uint32_t temp = idx_value >> 4;
1761 for (i = 0; i < track->num_texture; i++)
1762 track->textures[i].enabled = !!(temp & (1 << i));
1763 track->tex_dirty = true;
1764 }
1765 break;
1766 case RADEON_SE_VF_CNTL:
1767 track->vap_vf_cntl = idx_value;
1768 break;
1769 case RADEON_SE_VTX_FMT:
1770 track->vtx_size = r100_get_vtx_size(idx_value);
1771 break;
1772 case RADEON_PP_TEX_SIZE_0:
1773 case RADEON_PP_TEX_SIZE_1:
1774 case RADEON_PP_TEX_SIZE_2:
1775 i = (reg - RADEON_PP_TEX_SIZE_0) / 8;
1776 track->textures[i].width = (idx_value & RADEON_TEX_USIZE_MASK) + 1;
1777 track->textures[i].height = ((idx_value & RADEON_TEX_VSIZE_MASK) >> RADEON_TEX_VSIZE_SHIFT) + 1;
1778 track->tex_dirty = true;
1779 break;
1780 case RADEON_PP_TEX_PITCH_0:
1781 case RADEON_PP_TEX_PITCH_1:
1782 case RADEON_PP_TEX_PITCH_2:
1783 i = (reg - RADEON_PP_TEX_PITCH_0) / 8;
1784 track->textures[i].pitch = idx_value + 32;
1785 track->tex_dirty = true;
1786 break;
1787 case RADEON_PP_TXFILTER_0:
1788 case RADEON_PP_TXFILTER_1:
1789 case RADEON_PP_TXFILTER_2:
1790 i = (reg - RADEON_PP_TXFILTER_0) / 24;
1791 track->textures[i].num_levels = ((idx_value & RADEON_MAX_MIP_LEVEL_MASK)
1792 >> RADEON_MAX_MIP_LEVEL_SHIFT);
1793 tmp = (idx_value >> 23) & 0x7;
1794 if (tmp == 2 || tmp == 6)
1795 track->textures[i].roundup_w = false;
1796 tmp = (idx_value >> 27) & 0x7;
1797 if (tmp == 2 || tmp == 6)
1798 track->textures[i].roundup_h = false;
1799 track->tex_dirty = true;
1800 break;
1801 case RADEON_PP_TXFORMAT_0:
1802 case RADEON_PP_TXFORMAT_1:
1803 case RADEON_PP_TXFORMAT_2:
1804 i = (reg - RADEON_PP_TXFORMAT_0) / 24;
1805 if (idx_value & RADEON_TXFORMAT_NON_POWER2) {
1806 track->textures[i].use_pitch = 1;
1807 } else {
1808 track->textures[i].use_pitch = 0;
1809 track->textures[i].width = 1 << ((idx_value >> RADEON_TXFORMAT_WIDTH_SHIFT) & RADEON_TXFORMAT_WIDTH_MASK);
1810 track->textures[i].height = 1 << ((idx_value >> RADEON_TXFORMAT_HEIGHT_SHIFT) & RADEON_TXFORMAT_HEIGHT_MASK);
1811 }
1812 if (idx_value & RADEON_TXFORMAT_CUBIC_MAP_ENABLE)
1813 track->textures[i].tex_coord_type = 2;
1814 switch ((idx_value & RADEON_TXFORMAT_FORMAT_MASK)) {
1815 case RADEON_TXFORMAT_I8:
1816 case RADEON_TXFORMAT_RGB332:
1817 case RADEON_TXFORMAT_Y8:
1818 track->textures[i].cpp = 1;
1819 track->textures[i].compress_format = R100_TRACK_COMP_NONE;
1820 break;
1821 case RADEON_TXFORMAT_AI88:
1822 case RADEON_TXFORMAT_ARGB1555:
1823 case RADEON_TXFORMAT_RGB565:
1824 case RADEON_TXFORMAT_ARGB4444:
1825 case RADEON_TXFORMAT_VYUY422:
1826 case RADEON_TXFORMAT_YVYU422:
1827 case RADEON_TXFORMAT_SHADOW16:
1828 case RADEON_TXFORMAT_LDUDV655:
1829 case RADEON_TXFORMAT_DUDV88:
1830 track->textures[i].cpp = 2;
1831 track->textures[i].compress_format = R100_TRACK_COMP_NONE;
1832 break;
1833 case RADEON_TXFORMAT_ARGB8888:
1834 case RADEON_TXFORMAT_RGBA8888:
1835 case RADEON_TXFORMAT_SHADOW32:
1836 case RADEON_TXFORMAT_LDUDUV8888:
1837 track->textures[i].cpp = 4;
1838 track->textures[i].compress_format = R100_TRACK_COMP_NONE;
1839 break;
1840 case RADEON_TXFORMAT_DXT1:
1841 track->textures[i].cpp = 1;
1842 track->textures[i].compress_format = R100_TRACK_COMP_DXT1;
1843 break;
1844 case RADEON_TXFORMAT_DXT23:
1845 case RADEON_TXFORMAT_DXT45:
1846 track->textures[i].cpp = 1;
1847 track->textures[i].compress_format = R100_TRACK_COMP_DXT35;
1848 break;
1849 }
1850 track->textures[i].cube_info[4].width = 1 << ((idx_value >> 16) & 0xf);
1851 track->textures[i].cube_info[4].height = 1 << ((idx_value >> 20) & 0xf);
1852 track->tex_dirty = true;
1853 break;
1854 case RADEON_PP_CUBIC_FACES_0:
1855 case RADEON_PP_CUBIC_FACES_1:
1856 case RADEON_PP_CUBIC_FACES_2:
1857 tmp = idx_value;
1858 i = (reg - RADEON_PP_CUBIC_FACES_0) / 4;
1859 for (face = 0; face < 4; face++) {
1860 track->textures[i].cube_info[face].width = 1 << ((tmp >> (face * 8)) & 0xf);
1861 track->textures[i].cube_info[face].height = 1 << ((tmp >> ((face * 8) + 4)) & 0xf);
1862 }
1863 track->tex_dirty = true;
1864 break;
1865 default:
1866 printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n",
1867 reg, idx);
1868 return -EINVAL;
1869 }
1870 return 0;
1871 }
1872
1873 int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p,
1874 struct radeon_cs_packet *pkt,
1875 struct radeon_bo *robj)
1876 {
1877 unsigned idx;
1878 u32 value;
1879 idx = pkt->idx + 1;
1880 value = radeon_get_ib_value(p, idx + 2);
1881 if ((value + 1) > radeon_bo_size(robj)) {
1882 DRM_ERROR("[drm] Buffer too small for PACKET3 INDX_BUFFER "
1883 "(need %u have %lu) !\n",
1884 value + 1,
1885 radeon_bo_size(robj));
1886 return -EINVAL;
1887 }
1888 return 0;
1889 }
1890
1891 static int r100_packet3_check(struct radeon_cs_parser *p,
1892 struct radeon_cs_packet *pkt)
1893 {
1894 struct radeon_cs_reloc *reloc;
1895 struct r100_cs_track *track;
1896 unsigned idx;
1897 volatile uint32_t *ib;
1898 int r;
1899
1900 ib = p->ib.ptr;
1901 idx = pkt->idx + 1;
1902 track = (struct r100_cs_track *)p->track;
1903 switch (pkt->opcode) {
1904 case PACKET3_3D_LOAD_VBPNTR:
1905 r = r100_packet3_load_vbpntr(p, pkt, idx);
1906 if (r)
1907 return r;
1908 break;
1909 case PACKET3_INDX_BUFFER:
1910 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1911 if (r) {
1912 DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
1913 radeon_cs_dump_packet(p, pkt);
1914 return r;
1915 }
1916 ib[idx+1] = radeon_get_ib_value(p, idx+1) + ((u32)reloc->gpu_offset);
1917 r = r100_cs_track_check_pkt3_indx_buffer(p, pkt, reloc->robj);
1918 if (r) {
1919 return r;
1920 }
1921 break;
1922 case 0x23:
1923 /* 3D_RNDR_GEN_INDX_PRIM on r100/r200 */
1924 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1925 if (r) {
1926 DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
1927 radeon_cs_dump_packet(p, pkt);
1928 return r;
1929 }
1930 ib[idx] = radeon_get_ib_value(p, idx) + ((u32)reloc->gpu_offset);
1931 track->num_arrays = 1;
1932 track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 2));
1933
1934 track->arrays[0].robj = reloc->robj;
1935 track->arrays[0].esize = track->vtx_size;
1936
1937 track->max_indx = radeon_get_ib_value(p, idx+1);
1938
1939 track->vap_vf_cntl = radeon_get_ib_value(p, idx+3);
1940 track->immd_dwords = pkt->count - 1;
1941 r = r100_cs_track_check(p->rdev, track);
1942 if (r)
1943 return r;
1944 break;
1945 case PACKET3_3D_DRAW_IMMD:
1946 if (((radeon_get_ib_value(p, idx + 1) >> 4) & 0x3) != 3) {
1947 DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1948 return -EINVAL;
1949 }
1950 track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 0));
1951 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1952 track->immd_dwords = pkt->count - 1;
1953 r = r100_cs_track_check(p->rdev, track);
1954 if (r)
1955 return r;
1956 break;
1957 /* triggers drawing using in-packet vertex data */
1958 case PACKET3_3D_DRAW_IMMD_2:
1959 if (((radeon_get_ib_value(p, idx) >> 4) & 0x3) != 3) {
1960 DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1961 return -EINVAL;
1962 }
1963 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1964 track->immd_dwords = pkt->count;
1965 r = r100_cs_track_check(p->rdev, track);
1966 if (r)
1967 return r;
1968 break;
1969 /* triggers drawing using in-packet vertex data */
1970 case PACKET3_3D_DRAW_VBUF_2:
1971 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1972 r = r100_cs_track_check(p->rdev, track);
1973 if (r)
1974 return r;
1975 break;
1976 /* triggers drawing of vertex buffers setup elsewhere */
1977 case PACKET3_3D_DRAW_INDX_2:
1978 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1979 r = r100_cs_track_check(p->rdev, track);
1980 if (r)
1981 return r;
1982 break;
1983 /* triggers drawing using indices to vertex buffer */
1984 case PACKET3_3D_DRAW_VBUF:
1985 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1986 r = r100_cs_track_check(p->rdev, track);
1987 if (r)
1988 return r;
1989 break;
1990 /* triggers drawing of vertex buffers setup elsewhere */
1991 case PACKET3_3D_DRAW_INDX:
1992 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1993 r = r100_cs_track_check(p->rdev, track);
1994 if (r)
1995 return r;
1996 break;
1997 /* triggers drawing using indices to vertex buffer */
1998 case PACKET3_3D_CLEAR_HIZ:
1999 case PACKET3_3D_CLEAR_ZMASK:
2000 if (p->rdev->hyperz_filp != p->filp)
2001 return -EINVAL;
2002 break;
2003 case PACKET3_NOP:
2004 break;
2005 default:
2006 DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode);
2007 return -EINVAL;
2008 }
2009 return 0;
2010 }
2011
2012 int r100_cs_parse(struct radeon_cs_parser *p)
2013 {
2014 struct radeon_cs_packet pkt;
2015 struct r100_cs_track *track;
2016 int r;
2017
2018 track = kzalloc(sizeof(*track), GFP_KERNEL);
2019 if (!track)
2020 return -ENOMEM;
2021 r100_cs_track_clear(p->rdev, track);
2022 p->track = track;
2023 do {
2024 r = radeon_cs_packet_parse(p, &pkt, p->idx);
2025 if (r) {
2026 return r;
2027 }
2028 p->idx += pkt.count + 2;
2029 switch (pkt.type) {
2030 case RADEON_PACKET_TYPE0:
2031 if (p->rdev->family >= CHIP_R200)
2032 r = r100_cs_parse_packet0(p, &pkt,
2033 p->rdev->config.r100.reg_safe_bm,
2034 p->rdev->config.r100.reg_safe_bm_size,
2035 &r200_packet0_check);
2036 else
2037 r = r100_cs_parse_packet0(p, &pkt,
2038 p->rdev->config.r100.reg_safe_bm,
2039 p->rdev->config.r100.reg_safe_bm_size,
2040 &r100_packet0_check);
2041 break;
2042 case RADEON_PACKET_TYPE2:
2043 break;
2044 case RADEON_PACKET_TYPE3:
2045 r = r100_packet3_check(p, &pkt);
2046 break;
2047 default:
2048 DRM_ERROR("Unknown packet type %d !\n",
2049 pkt.type);
2050 return -EINVAL;
2051 }
2052 if (r)
2053 return r;
2054 } while (p->idx < p->chunks[p->chunk_ib_idx].length_dw);
2055 return 0;
2056 }
2057
2058 static void r100_cs_track_texture_print(struct r100_cs_track_texture *t)
2059 {
2060 DRM_ERROR("pitch %d\n", t->pitch);
2061 DRM_ERROR("use_pitch %d\n", t->use_pitch);
2062 DRM_ERROR("width %d\n", t->width);
2063 DRM_ERROR("width_11 %d\n", t->width_11);
2064 DRM_ERROR("height %d\n", t->height);
2065 DRM_ERROR("height_11 %d\n", t->height_11);
2066 DRM_ERROR("num levels %d\n", t->num_levels);
2067 DRM_ERROR("depth %d\n", t->txdepth);
2068 DRM_ERROR("bpp %d\n", t->cpp);
2069 DRM_ERROR("coordinate type %d\n", t->tex_coord_type);
2070 DRM_ERROR("width round to power of 2 %d\n", t->roundup_w);
2071 DRM_ERROR("height round to power of 2 %d\n", t->roundup_h);
2072 DRM_ERROR("compress format %d\n", t->compress_format);
2073 }
2074
2075 static int r100_track_compress_size(int compress_format, int w, int h)
2076 {
2077 int block_width, block_height, block_bytes;
2078 int wblocks, hblocks;
2079 int min_wblocks;
2080 int sz;
2081
2082 block_width = 4;
2083 block_height = 4;
2084
2085 switch (compress_format) {
2086 case R100_TRACK_COMP_DXT1:
2087 block_bytes = 8;
2088 min_wblocks = 4;
2089 break;
2090 default:
2091 case R100_TRACK_COMP_DXT35:
2092 block_bytes = 16;
2093 min_wblocks = 2;
2094 break;
2095 }
2096
2097 hblocks = (h + block_height - 1) / block_height;
2098 wblocks = (w + block_width - 1) / block_width;
2099 if (wblocks < min_wblocks)
2100 wblocks = min_wblocks;
2101 sz = wblocks * hblocks * block_bytes;
2102 return sz;
2103 }
2104
2105 static int r100_cs_track_cube(struct radeon_device *rdev,
2106 struct r100_cs_track *track, unsigned idx)
2107 {
2108 unsigned face, w, h;
2109 struct radeon_bo *cube_robj;
2110 unsigned long size;
2111 unsigned compress_format = track->textures[idx].compress_format;
2112
2113 for (face = 0; face < 5; face++) {
2114 cube_robj = track->textures[idx].cube_info[face].robj;
2115 w = track->textures[idx].cube_info[face].width;
2116 h = track->textures[idx].cube_info[face].height;
2117
2118 if (compress_format) {
2119 size = r100_track_compress_size(compress_format, w, h);
2120 } else
2121 size = w * h;
2122 size *= track->textures[idx].cpp;
2123
2124 size += track->textures[idx].cube_info[face].offset;
2125
2126 if (size > radeon_bo_size(cube_robj)) {
2127 DRM_ERROR("Cube texture offset greater than object size %lu %lu\n",
2128 size, radeon_bo_size(cube_robj));
2129 r100_cs_track_texture_print(&track->textures[idx]);
2130 return -1;
2131 }
2132 }
2133 return 0;
2134 }
2135
2136 static int r100_cs_track_texture_check(struct radeon_device *rdev,
2137 struct r100_cs_track *track)
2138 {
2139 struct radeon_bo *robj;
2140 unsigned long size;
2141 unsigned u, i, w, h, d;
2142 int ret;
2143
2144 for (u = 0; u < track->num_texture; u++) {
2145 if (!track->textures[u].enabled)
2146 continue;
2147 if (track->textures[u].lookup_disable)
2148 continue;
2149 robj = track->textures[u].robj;
2150 if (robj == NULL) {
2151 DRM_ERROR("No texture bound to unit %u\n", u);
2152 return -EINVAL;
2153 }
2154 size = 0;
2155 for (i = 0; i <= track->textures[u].num_levels; i++) {
2156 if (track->textures[u].use_pitch) {
2157 if (rdev->family < CHIP_R300)
2158 w = (track->textures[u].pitch / track->textures[u].cpp) / (1 << i);
2159 else
2160 w = track->textures[u].pitch / (1 << i);
2161 } else {
2162 w = track->textures[u].width;
2163 if (rdev->family >= CHIP_RV515)
2164 w |= track->textures[u].width_11;
2165 w = w / (1 << i);
2166 if (track->textures[u].roundup_w)
2167 w = roundup_pow_of_two(w);
2168 }
2169 h = track->textures[u].height;
2170 if (rdev->family >= CHIP_RV515)
2171 h |= track->textures[u].height_11;
2172 h = h / (1 << i);
2173 if (track->textures[u].roundup_h)
2174 h = roundup_pow_of_two(h);
2175 if (track->textures[u].tex_coord_type == 1) {
2176 d = (1 << track->textures[u].txdepth) / (1 << i);
2177 if (!d)
2178 d = 1;
2179 } else {
2180 d = 1;
2181 }
2182 if (track->textures[u].compress_format) {
2183
2184 size += r100_track_compress_size(track->textures[u].compress_format, w, h) * d;
2185 /* compressed textures are block based */
2186 } else
2187 size += w * h * d;
2188 }
2189 size *= track->textures[u].cpp;
2190
2191 switch (track->textures[u].tex_coord_type) {
2192 case 0:
2193 case 1:
2194 break;
2195 case 2:
2196 if (track->separate_cube) {
2197 ret = r100_cs_track_cube(rdev, track, u);
2198 if (ret)
2199 return ret;
2200 } else
2201 size *= 6;
2202 break;
2203 default:
2204 DRM_ERROR("Invalid texture coordinate type %u for unit "
2205 "%u\n", track->textures[u].tex_coord_type, u);
2206 return -EINVAL;
2207 }
2208 if (size > radeon_bo_size(robj)) {
2209 DRM_ERROR("Texture of unit %u needs %lu bytes but is "
2210 "%lu\n", u, size, radeon_bo_size(robj));
2211 r100_cs_track_texture_print(&track->textures[u]);
2212 return -EINVAL;
2213 }
2214 }
2215 return 0;
2216 }
2217
2218 int r100_cs_track_check(struct radeon_device *rdev, struct r100_cs_track *track)
2219 {
2220 unsigned i;
2221 unsigned long size;
2222 unsigned prim_walk;
2223 unsigned nverts;
2224 unsigned num_cb = track->cb_dirty ? track->num_cb : 0;
2225
2226 if (num_cb && !track->zb_cb_clear && !track->color_channel_mask &&
2227 !track->blend_read_enable)
2228 num_cb = 0;
2229
2230 for (i = 0; i < num_cb; i++) {
2231 if (track->cb[i].robj == NULL) {
2232 DRM_ERROR("[drm] No buffer for color buffer %d !\n", i);
2233 return -EINVAL;
2234 }
2235 size = track->cb[i].pitch * track->cb[i].cpp * track->maxy;
2236 size += track->cb[i].offset;
2237 if (size > radeon_bo_size(track->cb[i].robj)) {
2238 DRM_ERROR("[drm] Buffer too small for color buffer %d "
2239 "(need %lu have %lu) !\n", i, size,
2240 radeon_bo_size(track->cb[i].robj));
2241 DRM_ERROR("[drm] color buffer %d (%u %u %u %u)\n",
2242 i, track->cb[i].pitch, track->cb[i].cpp,
2243 track->cb[i].offset, track->maxy);
2244 return -EINVAL;
2245 }
2246 }
2247 track->cb_dirty = false;
2248
2249 if (track->zb_dirty && track->z_enabled) {
2250 if (track->zb.robj == NULL) {
2251 DRM_ERROR("[drm] No buffer for z buffer !\n");
2252 return -EINVAL;
2253 }
2254 size = track->zb.pitch * track->zb.cpp * track->maxy;
2255 size += track->zb.offset;
2256 if (size > radeon_bo_size(track->zb.robj)) {
2257 DRM_ERROR("[drm] Buffer too small for z buffer "
2258 "(need %lu have %lu) !\n", size,
2259 radeon_bo_size(track->zb.robj));
2260 DRM_ERROR("[drm] zbuffer (%u %u %u %u)\n",
2261 track->zb.pitch, track->zb.cpp,
2262 track->zb.offset, track->maxy);
2263 return -EINVAL;
2264 }
2265 }
2266 track->zb_dirty = false;
2267
2268 if (track->aa_dirty && track->aaresolve) {
2269 if (track->aa.robj == NULL) {
2270 DRM_ERROR("[drm] No buffer for AA resolve buffer %d !\n", i);
2271 return -EINVAL;
2272 }
2273 /* I believe the format comes from colorbuffer0. */
2274 size = track->aa.pitch * track->cb[0].cpp * track->maxy;
2275 size += track->aa.offset;
2276 if (size > radeon_bo_size(track->aa.robj)) {
2277 DRM_ERROR("[drm] Buffer too small for AA resolve buffer %d "
2278 "(need %lu have %lu) !\n", i, size,
2279 radeon_bo_size(track->aa.robj));
2280 DRM_ERROR("[drm] AA resolve buffer %d (%u %u %u %u)\n",
2281 i, track->aa.pitch, track->cb[0].cpp,
2282 track->aa.offset, track->maxy);
2283 return -EINVAL;
2284 }
2285 }
2286 track->aa_dirty = false;
2287
2288 prim_walk = (track->vap_vf_cntl >> 4) & 0x3;
2289 if (track->vap_vf_cntl & (1 << 14)) {
2290 nverts = track->vap_alt_nverts;
2291 } else {
2292 nverts = (track->vap_vf_cntl >> 16) & 0xFFFF;
2293 }
2294 switch (prim_walk) {
2295 case 1:
2296 for (i = 0; i < track->num_arrays; i++) {
2297 size = track->arrays[i].esize * track->max_indx * 4;
2298 if (track->arrays[i].robj == NULL) {
2299 DRM_ERROR("(PW %u) Vertex array %u no buffer "
2300 "bound\n", prim_walk, i);
2301 return -EINVAL;
2302 }
2303 if (size > radeon_bo_size(track->arrays[i].robj)) {
2304 dev_err(rdev->dev, "(PW %u) Vertex array %u "
2305 "need %lu dwords have %lu dwords\n",
2306 prim_walk, i, size >> 2,
2307 radeon_bo_size(track->arrays[i].robj)
2308 >> 2);
2309 DRM_ERROR("Max indices %u\n", track->max_indx);
2310 return -EINVAL;
2311 }
2312 }
2313 break;
2314 case 2:
2315 for (i = 0; i < track->num_arrays; i++) {
2316 size = track->arrays[i].esize * (nverts - 1) * 4;
2317 if (track->arrays[i].robj == NULL) {
2318 DRM_ERROR("(PW %u) Vertex array %u no buffer "
2319 "bound\n", prim_walk, i);
2320 return -EINVAL;
2321 }
2322 if (size > radeon_bo_size(track->arrays[i].robj)) {
2323 dev_err(rdev->dev, "(PW %u) Vertex array %u "
2324 "need %lu dwords have %lu dwords\n",
2325 prim_walk, i, size >> 2,
2326 radeon_bo_size(track->arrays[i].robj)
2327 >> 2);
2328 return -EINVAL;
2329 }
2330 }
2331 break;
2332 case 3:
2333 size = track->vtx_size * nverts;
2334 if (size != track->immd_dwords) {
2335 DRM_ERROR("IMMD draw %u dwors but needs %lu dwords\n",
2336 track->immd_dwords, size);
2337 DRM_ERROR("VAP_VF_CNTL.NUM_VERTICES %u, VTX_SIZE %u\n",
2338 nverts, track->vtx_size);
2339 return -EINVAL;
2340 }
2341 break;
2342 default:
2343 DRM_ERROR("[drm] Invalid primitive walk %d for VAP_VF_CNTL\n",
2344 prim_walk);
2345 return -EINVAL;
2346 }
2347
2348 if (track->tex_dirty) {
2349 track->tex_dirty = false;
2350 return r100_cs_track_texture_check(rdev, track);
2351 }
2352 return 0;
2353 }
2354
2355 void r100_cs_track_clear(struct radeon_device *rdev, struct r100_cs_track *track)
2356 {
2357 unsigned i, face;
2358
2359 track->cb_dirty = true;
2360 track->zb_dirty = true;
2361 track->tex_dirty = true;
2362 track->aa_dirty = true;
2363
2364 if (rdev->family < CHIP_R300) {
2365 track->num_cb = 1;
2366 if (rdev->family <= CHIP_RS200)
2367 track->num_texture = 3;
2368 else
2369 track->num_texture = 6;
2370 track->maxy = 2048;
2371 track->separate_cube = 1;
2372 } else {
2373 track->num_cb = 4;
2374 track->num_texture = 16;
2375 track->maxy = 4096;
2376 track->separate_cube = 0;
2377 track->aaresolve = false;
2378 track->aa.robj = NULL;
2379 }
2380
2381 for (i = 0; i < track->num_cb; i++) {
2382 track->cb[i].robj = NULL;
2383 track->cb[i].pitch = 8192;
2384 track->cb[i].cpp = 16;
2385 track->cb[i].offset = 0;
2386 }
2387 track->z_enabled = true;
2388 track->zb.robj = NULL;
2389 track->zb.pitch = 8192;
2390 track->zb.cpp = 4;
2391 track->zb.offset = 0;
2392 track->vtx_size = 0x7F;
2393 track->immd_dwords = 0xFFFFFFFFUL;
2394 track->num_arrays = 11;
2395 track->max_indx = 0x00FFFFFFUL;
2396 for (i = 0; i < track->num_arrays; i++) {
2397 track->arrays[i].robj = NULL;
2398 track->arrays[i].esize = 0x7F;
2399 }
2400 for (i = 0; i < track->num_texture; i++) {
2401 track->textures[i].compress_format = R100_TRACK_COMP_NONE;
2402 track->textures[i].pitch = 16536;
2403 track->textures[i].width = 16536;
2404 track->textures[i].height = 16536;
2405 track->textures[i].width_11 = 1 << 11;
2406 track->textures[i].height_11 = 1 << 11;
2407 track->textures[i].num_levels = 12;
2408 if (rdev->family <= CHIP_RS200) {
2409 track->textures[i].tex_coord_type = 0;
2410 track->textures[i].txdepth = 0;
2411 } else {
2412 track->textures[i].txdepth = 16;
2413 track->textures[i].tex_coord_type = 1;
2414 }
2415 track->textures[i].cpp = 64;
2416 track->textures[i].robj = NULL;
2417 /* CS IB emission code makes sure texture unit are disabled */
2418 track->textures[i].enabled = false;
2419 track->textures[i].lookup_disable = false;
2420 track->textures[i].roundup_w = true;
2421 track->textures[i].roundup_h = true;
2422 if (track->separate_cube)
2423 for (face = 0; face < 5; face++) {
2424 track->textures[i].cube_info[face].robj = NULL;
2425 track->textures[i].cube_info[face].width = 16536;
2426 track->textures[i].cube_info[face].height = 16536;
2427 track->textures[i].cube_info[face].offset = 0;
2428 }
2429 }
2430 }
2431
2432 /*
2433 * Global GPU functions
2434 */
2435 static void r100_errata(struct radeon_device *rdev)
2436 {
2437 rdev->pll_errata = 0;
2438
2439 if (rdev->family == CHIP_RV200 || rdev->family == CHIP_RS200) {
2440 rdev->pll_errata |= CHIP_ERRATA_PLL_DUMMYREADS;
2441 }
2442
2443 if (rdev->family == CHIP_RV100 ||
2444 rdev->family == CHIP_RS100 ||
2445 rdev->family == CHIP_RS200) {
2446 rdev->pll_errata |= CHIP_ERRATA_PLL_DELAY;
2447 }
2448 }
2449
2450 static int r100_rbbm_fifo_wait_for_entry(struct radeon_device *rdev, unsigned n)
2451 {
2452 unsigned i;
2453 uint32_t tmp;
2454
2455 for (i = 0; i < rdev->usec_timeout; i++) {
2456 tmp = RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_FIFOCNT_MASK;
2457 if (tmp >= n) {
2458 return 0;
2459 }
2460 DRM_UDELAY(1);
2461 }
2462 return -1;
2463 }
2464
2465 int r100_gui_wait_for_idle(struct radeon_device *rdev)
2466 {
2467 unsigned i;
2468 uint32_t tmp;
2469
2470 if (r100_rbbm_fifo_wait_for_entry(rdev, 64)) {
2471 printk(KERN_WARNING "radeon: wait for empty RBBM fifo failed !"
2472 " Bad things might happen.\n");
2473 }
2474 for (i = 0; i < rdev->usec_timeout; i++) {
2475 tmp = RREG32(RADEON_RBBM_STATUS);
2476 if (!(tmp & RADEON_RBBM_ACTIVE)) {
2477 return 0;
2478 }
2479 DRM_UDELAY(1);
2480 }
2481 return -1;
2482 }
2483
2484 int r100_mc_wait_for_idle(struct radeon_device *rdev)
2485 {
2486 unsigned i;
2487 uint32_t tmp;
2488
2489 for (i = 0; i < rdev->usec_timeout; i++) {
2490 /* read MC_STATUS */
2491 tmp = RREG32(RADEON_MC_STATUS);
2492 if (tmp & RADEON_MC_IDLE) {
2493 return 0;
2494 }
2495 DRM_UDELAY(1);
2496 }
2497 return -1;
2498 }
2499
2500 bool r100_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
2501 {
2502 u32 rbbm_status;
2503
2504 rbbm_status = RREG32(R_000E40_RBBM_STATUS);
2505 if (!G_000E40_GUI_ACTIVE(rbbm_status)) {
2506 radeon_ring_lockup_update(rdev, ring);
2507 return false;
2508 }
2509 return radeon_ring_test_lockup(rdev, ring);
2510 }
2511
2512 /* required on r1xx, r2xx, r300, r(v)350, r420/r481, rs400/rs480 */
2513 void r100_enable_bm(struct radeon_device *rdev)
2514 {
2515 uint32_t tmp;
2516 /* Enable bus mastering */
2517 tmp = RREG32(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
2518 WREG32(RADEON_BUS_CNTL, tmp);
2519 }
2520
2521 void r100_bm_disable(struct radeon_device *rdev)
2522 {
2523 u32 tmp;
2524
2525 /* disable bus mastering */
2526 tmp = RREG32(R_000030_BUS_CNTL);
2527 WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000044);
2528 mdelay(1);
2529 WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000042);
2530 mdelay(1);
2531 WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000040);
2532 tmp = RREG32(RADEON_BUS_CNTL);
2533 mdelay(1);
2534 pci_clear_master(rdev->pdev);
2535 mdelay(1);
2536 }
2537
2538 int r100_asic_reset(struct radeon_device *rdev)
2539 {
2540 struct r100_mc_save save;
2541 u32 status, tmp;
2542 int ret = 0;
2543
2544 status = RREG32(R_000E40_RBBM_STATUS);
2545 if (!G_000E40_GUI_ACTIVE(status)) {
2546 return 0;
2547 }
2548 r100_mc_stop(rdev, &save);
2549 status = RREG32(R_000E40_RBBM_STATUS);
2550 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
2551 /* stop CP */
2552 WREG32(RADEON_CP_CSQ_CNTL, 0);
2553 tmp = RREG32(RADEON_CP_RB_CNTL);
2554 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA);
2555 WREG32(RADEON_CP_RB_RPTR_WR, 0);
2556 WREG32(RADEON_CP_RB_WPTR, 0);
2557 WREG32(RADEON_CP_RB_CNTL, tmp);
2558 /* save PCI state */
2559 pci_save_state(rdev->pdev);
2560 /* disable bus mastering */
2561 r100_bm_disable(rdev);
2562 WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_SE(1) |
2563 S_0000F0_SOFT_RESET_RE(1) |
2564 S_0000F0_SOFT_RESET_PP(1) |
2565 S_0000F0_SOFT_RESET_RB(1));
2566 RREG32(R_0000F0_RBBM_SOFT_RESET);
2567 mdelay(500);
2568 WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
2569 mdelay(1);
2570 status = RREG32(R_000E40_RBBM_STATUS);
2571 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
2572 /* reset CP */
2573 WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_CP(1));
2574 RREG32(R_0000F0_RBBM_SOFT_RESET);
2575 mdelay(500);
2576 WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
2577 mdelay(1);
2578 status = RREG32(R_000E40_RBBM_STATUS);
2579 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
2580 /* restore PCI & busmastering */
2581 pci_restore_state(rdev->pdev);
2582 r100_enable_bm(rdev);
2583 /* Check if GPU is idle */
2584 if (G_000E40_SE_BUSY(status) || G_000E40_RE_BUSY(status) ||
2585 G_000E40_TAM_BUSY(status) || G_000E40_PB_BUSY(status)) {
2586 dev_err(rdev->dev, "failed to reset GPU\n");
2587 ret = -1;
2588 } else
2589 dev_info(rdev->dev, "GPU reset succeed\n");
2590 r100_mc_resume(rdev, &save);
2591 return ret;
2592 }
2593
2594 void r100_set_common_regs(struct radeon_device *rdev)
2595 {
2596 struct drm_device *dev = rdev->ddev;
2597 bool force_dac2 = false;
2598 u32 tmp;
2599
2600 /* set these so they don't interfere with anything */
2601 WREG32(RADEON_OV0_SCALE_CNTL, 0);
2602 WREG32(RADEON_SUBPIC_CNTL, 0);
2603 WREG32(RADEON_VIPH_CONTROL, 0);
2604 WREG32(RADEON_I2C_CNTL_1, 0);
2605 WREG32(RADEON_DVI_I2C_CNTL_1, 0);
2606 WREG32(RADEON_CAP0_TRIG_CNTL, 0);
2607 WREG32(RADEON_CAP1_TRIG_CNTL, 0);
2608
2609 /* always set up dac2 on rn50 and some rv100 as lots
2610 * of servers seem to wire it up to a VGA port but
2611 * don't report it in the bios connector
2612 * table.
2613 */
2614 switch (dev->pdev->device) {
2615 /* RN50 */
2616 case 0x515e:
2617 case 0x5969:
2618 force_dac2 = true;
2619 break;
2620 /* RV100*/
2621 case 0x5159:
2622 case 0x515a:
2623 /* DELL triple head servers */
2624 if ((dev->pdev->subsystem_vendor == 0x1028 /* DELL */) &&
2625 ((dev->pdev->subsystem_device == 0x016c) ||
2626 (dev->pdev->subsystem_device == 0x016d) ||
2627 (dev->pdev->subsystem_device == 0x016e) ||
2628 (dev->pdev->subsystem_device == 0x016f) ||
2629 (dev->pdev->subsystem_device == 0x0170) ||
2630 (dev->pdev->subsystem_device == 0x017d) ||
2631 (dev->pdev->subsystem_device == 0x017e) ||
2632 (dev->pdev->subsystem_device == 0x0183) ||
2633 (dev->pdev->subsystem_device == 0x018a) ||
2634 (dev->pdev->subsystem_device == 0x019a)))
2635 force_dac2 = true;
2636 break;
2637 }
2638
2639 if (force_dac2) {
2640 u32 disp_hw_debug = RREG32(RADEON_DISP_HW_DEBUG);
2641 u32 tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
2642 u32 dac2_cntl = RREG32(RADEON_DAC_CNTL2);
2643
2644 /* For CRT on DAC2, don't turn it on if BIOS didn't
2645 enable it, even it's detected.
2646 */
2647
2648 /* force it to crtc0 */
2649 dac2_cntl &= ~RADEON_DAC2_DAC_CLK_SEL;
2650 dac2_cntl |= RADEON_DAC2_DAC2_CLK_SEL;
2651 disp_hw_debug |= RADEON_CRT2_DISP1_SEL;
2652
2653 /* set up the TV DAC */
2654 tv_dac_cntl &= ~(RADEON_TV_DAC_PEDESTAL |
2655 RADEON_TV_DAC_STD_MASK |
2656 RADEON_TV_DAC_RDACPD |
2657 RADEON_TV_DAC_GDACPD |
2658 RADEON_TV_DAC_BDACPD |
2659 RADEON_TV_DAC_BGADJ_MASK |
2660 RADEON_TV_DAC_DACADJ_MASK);
2661 tv_dac_cntl |= (RADEON_TV_DAC_NBLANK |
2662 RADEON_TV_DAC_NHOLD |
2663 RADEON_TV_DAC_STD_PS2 |
2664 (0x58 << 16));
2665
2666 WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
2667 WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug);
2668 WREG32(RADEON_DAC_CNTL2, dac2_cntl);
2669 }
2670
2671 /* switch PM block to ACPI mode */
2672 tmp = RREG32_PLL(RADEON_PLL_PWRMGT_CNTL);
2673 tmp &= ~RADEON_PM_MODE_SEL;
2674 WREG32_PLL(RADEON_PLL_PWRMGT_CNTL, tmp);
2675
2676 }
2677
2678 /*
2679 * VRAM info
2680 */
2681 static void r100_vram_get_type(struct radeon_device *rdev)
2682 {
2683 uint32_t tmp;
2684
2685 rdev->mc.vram_is_ddr = false;
2686 if (rdev->flags & RADEON_IS_IGP)
2687 rdev->mc.vram_is_ddr = true;
2688 else if (RREG32(RADEON_MEM_SDRAM_MODE_REG) & RADEON_MEM_CFG_TYPE_DDR)
2689 rdev->mc.vram_is_ddr = true;
2690 if ((rdev->family == CHIP_RV100) ||
2691 (rdev->family == CHIP_RS100) ||
2692 (rdev->family == CHIP_RS200)) {
2693 tmp = RREG32(RADEON_MEM_CNTL);
2694 if (tmp & RV100_HALF_MODE) {
2695 rdev->mc.vram_width = 32;
2696 } else {
2697 rdev->mc.vram_width = 64;
2698 }
2699 if (rdev->flags & RADEON_SINGLE_CRTC) {
2700 rdev->mc.vram_width /= 4;
2701 rdev->mc.vram_is_ddr = true;
2702 }
2703 } else if (rdev->family <= CHIP_RV280) {
2704 tmp = RREG32(RADEON_MEM_CNTL);
2705 if (tmp & RADEON_MEM_NUM_CHANNELS_MASK) {
2706 rdev->mc.vram_width = 128;
2707 } else {
2708 rdev->mc.vram_width = 64;
2709 }
2710 } else {
2711 /* newer IGPs */
2712 rdev->mc.vram_width = 128;
2713 }
2714 }
2715
2716 static u32 r100_get_accessible_vram(struct radeon_device *rdev)
2717 {
2718 u32 aper_size;
2719 u8 byte;
2720
2721 aper_size = RREG32(RADEON_CONFIG_APER_SIZE);
2722
2723 /* Set HDP_APER_CNTL only on cards that are known not to be broken,
2724 * that is has the 2nd generation multifunction PCI interface
2725 */
2726 if (rdev->family == CHIP_RV280 ||
2727 rdev->family >= CHIP_RV350) {
2728 WREG32_P(RADEON_HOST_PATH_CNTL, RADEON_HDP_APER_CNTL,
2729 ~RADEON_HDP_APER_CNTL);
2730 DRM_INFO("Generation 2 PCI interface, using max accessible memory\n");
2731 return aper_size * 2;
2732 }
2733
2734 /* Older cards have all sorts of funny issues to deal with. First
2735 * check if it's a multifunction card by reading the PCI config
2736 * header type... Limit those to one aperture size
2737 */
2738 pci_read_config_byte(rdev->pdev, 0xe, &byte);
2739 if (byte & 0x80) {
2740 DRM_INFO("Generation 1 PCI interface in multifunction mode\n");
2741 DRM_INFO("Limiting VRAM to one aperture\n");
2742 return aper_size;
2743 }
2744
2745 /* Single function older card. We read HDP_APER_CNTL to see how the BIOS
2746 * have set it up. We don't write this as it's broken on some ASICs but
2747 * we expect the BIOS to have done the right thing (might be too optimistic...)
2748 */
2749 if (RREG32(RADEON_HOST_PATH_CNTL) & RADEON_HDP_APER_CNTL)
2750 return aper_size * 2;
2751 return aper_size;
2752 }
2753
2754 void r100_vram_init_sizes(struct radeon_device *rdev)
2755 {
2756 u64 config_aper_size;
2757
2758 /* work out accessible VRAM */
2759 rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
2760 rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
2761 rdev->mc.visible_vram_size = r100_get_accessible_vram(rdev);
2762 /* FIXME we don't use the second aperture yet when we could use it */
2763 if (rdev->mc.visible_vram_size > rdev->mc.aper_size)
2764 rdev->mc.visible_vram_size = rdev->mc.aper_size;
2765 config_aper_size = RREG32(RADEON_CONFIG_APER_SIZE);
2766 if (rdev->flags & RADEON_IS_IGP) {
2767 uint32_t tom;
2768 /* read NB_TOM to get the amount of ram stolen for the GPU */
2769 tom = RREG32(RADEON_NB_TOM);
2770 rdev->mc.real_vram_size = (((tom >> 16) - (tom & 0xffff) + 1) << 16);
2771 WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
2772 rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
2773 } else {
2774 rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE);
2775 /* Some production boards of m6 will report 0
2776 * if it's 8 MB
2777 */
2778 if (rdev->mc.real_vram_size == 0) {
2779 rdev->mc.real_vram_size = 8192 * 1024;
2780 WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
2781 }
2782 /* Fix for RN50, M6, M7 with 8/16/32(??) MBs of VRAM -
2783 * Novell bug 204882 + along with lots of ubuntu ones
2784 */
2785 if (rdev->mc.aper_size > config_aper_size)
2786 config_aper_size = rdev->mc.aper_size;
2787
2788 if (config_aper_size > rdev->mc.real_vram_size)
2789 rdev->mc.mc_vram_size = config_aper_size;
2790 else
2791 rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
2792 }
2793 }
2794
2795 void r100_vga_set_state(struct radeon_device *rdev, bool state)
2796 {
2797 uint32_t temp;
2798
2799 temp = RREG32(RADEON_CONFIG_CNTL);
2800 if (state == false) {
2801 temp &= ~RADEON_CFG_VGA_RAM_EN;
2802 temp |= RADEON_CFG_VGA_IO_DIS;
2803 } else {
2804 temp &= ~RADEON_CFG_VGA_IO_DIS;
2805 }
2806 WREG32(RADEON_CONFIG_CNTL, temp);
2807 }
2808
2809 static void r100_mc_init(struct radeon_device *rdev)
2810 {
2811 u64 base;
2812
2813 r100_vram_get_type(rdev);
2814 r100_vram_init_sizes(rdev);
2815 base = rdev->mc.aper_base;
2816 if (rdev->flags & RADEON_IS_IGP)
2817 base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16;
2818 radeon_vram_location(rdev, &rdev->mc, base);
2819 rdev->mc.gtt_base_align = 0;
2820 if (!(rdev->flags & RADEON_IS_AGP))
2821 radeon_gtt_location(rdev, &rdev->mc);
2822 radeon_update_bandwidth_info(rdev);
2823 }
2824
2825
2826 /*
2827 * Indirect registers accessor
2828 */
2829 void r100_pll_errata_after_index(struct radeon_device *rdev)
2830 {
2831 if (rdev->pll_errata & CHIP_ERRATA_PLL_DUMMYREADS) {
2832 (void)RREG32(RADEON_CLOCK_CNTL_DATA);
2833 (void)RREG32(RADEON_CRTC_GEN_CNTL);
2834 }
2835 }
2836
2837 static void r100_pll_errata_after_data(struct radeon_device *rdev)
2838 {
2839 /* This workarounds is necessary on RV100, RS100 and RS200 chips
2840 * or the chip could hang on a subsequent access
2841 */
2842 if (rdev->pll_errata & CHIP_ERRATA_PLL_DELAY) {
2843 mdelay(5);
2844 }
2845
2846 /* This function is required to workaround a hardware bug in some (all?)
2847 * revisions of the R300. This workaround should be called after every
2848 * CLOCK_CNTL_INDEX register access. If not, register reads afterward
2849 * may not be correct.
2850 */
2851 if (rdev->pll_errata & CHIP_ERRATA_R300_CG) {
2852 uint32_t save, tmp;
2853
2854 save = RREG32(RADEON_CLOCK_CNTL_INDEX);
2855 tmp = save & ~(0x3f | RADEON_PLL_WR_EN);
2856 WREG32(RADEON_CLOCK_CNTL_INDEX, tmp);
2857 tmp = RREG32(RADEON_CLOCK_CNTL_DATA);
2858 WREG32(RADEON_CLOCK_CNTL_INDEX, save);
2859 }
2860 }
2861
2862 uint32_t r100_pll_rreg(struct radeon_device *rdev, uint32_t reg)
2863 {
2864 unsigned long flags;
2865 uint32_t data;
2866
2867 spin_lock_irqsave(&rdev->pll_idx_lock, flags);
2868 WREG8(RADEON_CLOCK_CNTL_INDEX, reg & 0x3f);
2869 r100_pll_errata_after_index(rdev);
2870 data = RREG32(RADEON_CLOCK_CNTL_DATA);
2871 r100_pll_errata_after_data(rdev);
2872 spin_unlock_irqrestore(&rdev->pll_idx_lock, flags);
2873 return data;
2874 }
2875
2876 void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
2877 {
2878 unsigned long flags;
2879
2880 spin_lock_irqsave(&rdev->pll_idx_lock, flags);
2881 WREG8(RADEON_CLOCK_CNTL_INDEX, ((reg & 0x3f) | RADEON_PLL_WR_EN));
2882 r100_pll_errata_after_index(rdev);
2883 WREG32(RADEON_CLOCK_CNTL_DATA, v);
2884 r100_pll_errata_after_data(rdev);
2885 spin_unlock_irqrestore(&rdev->pll_idx_lock, flags);
2886 }
2887
2888 static void r100_set_safe_registers(struct radeon_device *rdev)
2889 {
2890 if (ASIC_IS_RN50(rdev)) {
2891 rdev->config.r100.reg_safe_bm = rn50_reg_safe_bm;
2892 rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(rn50_reg_safe_bm);
2893 } else if (rdev->family < CHIP_R200) {
2894 rdev->config.r100.reg_safe_bm = r100_reg_safe_bm;
2895 rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(r100_reg_safe_bm);
2896 } else {
2897 r200_set_safe_registers(rdev);
2898 }
2899 }
2900
2901 /*
2902 * Debugfs info
2903 */
2904 #if defined(CONFIG_DEBUG_FS)
2905 static int r100_debugfs_rbbm_info(struct seq_file *m, void *data)
2906 {
2907 struct drm_info_node *node = (struct drm_info_node *) m->private;
2908 struct drm_device *dev = node->minor->dev;
2909 struct radeon_device *rdev = dev->dev_private;
2910 uint32_t reg, value;
2911 unsigned i;
2912
2913 seq_printf(m, "RBBM_STATUS 0x%08x\n", RREG32(RADEON_RBBM_STATUS));
2914 seq_printf(m, "RBBM_CMDFIFO_STAT 0x%08x\n", RREG32(0xE7C));
2915 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
2916 for (i = 0; i < 64; i++) {
2917 WREG32(RADEON_RBBM_CMDFIFO_ADDR, i | 0x100);
2918 reg = (RREG32(RADEON_RBBM_CMDFIFO_DATA) - 1) >> 2;
2919 WREG32(RADEON_RBBM_CMDFIFO_ADDR, i);
2920 value = RREG32(RADEON_RBBM_CMDFIFO_DATA);
2921 seq_printf(m, "[0x%03X] 0x%04X=0x%08X\n", i, reg, value);
2922 }
2923 return 0;
2924 }
2925
2926 static int r100_debugfs_cp_ring_info(struct seq_file *m, void *data)
2927 {
2928 struct drm_info_node *node = (struct drm_info_node *) m->private;
2929 struct drm_device *dev = node->minor->dev;
2930 struct radeon_device *rdev = dev->dev_private;
2931 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
2932 uint32_t rdp, wdp;
2933 unsigned count, i, j;
2934
2935 radeon_ring_free_size(rdev, ring);
2936 rdp = RREG32(RADEON_CP_RB_RPTR);
2937 wdp = RREG32(RADEON_CP_RB_WPTR);
2938 count = (rdp + ring->ring_size - wdp) & ring->ptr_mask;
2939 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
2940 seq_printf(m, "CP_RB_WPTR 0x%08x\n", wdp);
2941 seq_printf(m, "CP_RB_RPTR 0x%08x\n", rdp);
2942 seq_printf(m, "%u free dwords in ring\n", ring->ring_free_dw);
2943 seq_printf(m, "%u dwords in ring\n", count);
2944 if (ring->ready) {
2945 for (j = 0; j <= count; j++) {
2946 i = (rdp + j) & ring->ptr_mask;
2947 seq_printf(m, "r[%04d]=0x%08x\n", i, ring->ring[i]);
2948 }
2949 }
2950 return 0;
2951 }
2952
2953
2954 static int r100_debugfs_cp_csq_fifo(struct seq_file *m, void *data)
2955 {
2956 struct drm_info_node *node = (struct drm_info_node *) m->private;
2957 struct drm_device *dev = node->minor->dev;
2958 struct radeon_device *rdev = dev->dev_private;
2959 uint32_t csq_stat, csq2_stat, tmp;
2960 unsigned r_rptr, r_wptr, ib1_rptr, ib1_wptr, ib2_rptr, ib2_wptr;
2961 unsigned i;
2962
2963 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
2964 seq_printf(m, "CP_CSQ_MODE 0x%08x\n", RREG32(RADEON_CP_CSQ_MODE));
2965 csq_stat = RREG32(RADEON_CP_CSQ_STAT);
2966 csq2_stat = RREG32(RADEON_CP_CSQ2_STAT);
2967 r_rptr = (csq_stat >> 0) & 0x3ff;
2968 r_wptr = (csq_stat >> 10) & 0x3ff;
2969 ib1_rptr = (csq_stat >> 20) & 0x3ff;
2970 ib1_wptr = (csq2_stat >> 0) & 0x3ff;
2971 ib2_rptr = (csq2_stat >> 10) & 0x3ff;
2972 ib2_wptr = (csq2_stat >> 20) & 0x3ff;
2973 seq_printf(m, "CP_CSQ_STAT 0x%08x\n", csq_stat);
2974 seq_printf(m, "CP_CSQ2_STAT 0x%08x\n", csq2_stat);
2975 seq_printf(m, "Ring rptr %u\n", r_rptr);
2976 seq_printf(m, "Ring wptr %u\n", r_wptr);
2977 seq_printf(m, "Indirect1 rptr %u\n", ib1_rptr);
2978 seq_printf(m, "Indirect1 wptr %u\n", ib1_wptr);
2979 seq_printf(m, "Indirect2 rptr %u\n", ib2_rptr);
2980 seq_printf(m, "Indirect2 wptr %u\n", ib2_wptr);
2981 /* FIXME: 0, 128, 640 depends on fifo setup see cp_init_kms
2982 * 128 = indirect1_start * 8 & 640 = indirect2_start * 8 */
2983 seq_printf(m, "Ring fifo:\n");
2984 for (i = 0; i < 256; i++) {
2985 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
2986 tmp = RREG32(RADEON_CP_CSQ_DATA);
2987 seq_printf(m, "rfifo[%04d]=0x%08X\n", i, tmp);
2988 }
2989 seq_printf(m, "Indirect1 fifo:\n");
2990 for (i = 256; i <= 512; i++) {
2991 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
2992 tmp = RREG32(RADEON_CP_CSQ_DATA);
2993 seq_printf(m, "ib1fifo[%04d]=0x%08X\n", i, tmp);
2994 }
2995 seq_printf(m, "Indirect2 fifo:\n");
2996 for (i = 640; i < ib1_wptr; i++) {
2997 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
2998 tmp = RREG32(RADEON_CP_CSQ_DATA);
2999 seq_printf(m, "ib2fifo[%04d]=0x%08X\n", i, tmp);
3000 }
3001 return 0;
3002 }
3003
3004 static int r100_debugfs_mc_info(struct seq_file *m, void *data)
3005 {
3006 struct drm_info_node *node = (struct drm_info_node *) m->private;
3007 struct drm_device *dev = node->minor->dev;
3008 struct radeon_device *rdev = dev->dev_private;
3009 uint32_t tmp;
3010
3011 tmp = RREG32(RADEON_CONFIG_MEMSIZE);
3012 seq_printf(m, "CONFIG_MEMSIZE 0x%08x\n", tmp);
3013 tmp = RREG32(RADEON_MC_FB_LOCATION);
3014 seq_printf(m, "MC_FB_LOCATION 0x%08x\n", tmp);
3015 tmp = RREG32(RADEON_BUS_CNTL);
3016 seq_printf(m, "BUS_CNTL 0x%08x\n", tmp);
3017 tmp = RREG32(RADEON_MC_AGP_LOCATION);
3018 seq_printf(m, "MC_AGP_LOCATION 0x%08x\n", tmp);
3019 tmp = RREG32(RADEON_AGP_BASE);
3020 seq_printf(m, "AGP_BASE 0x%08x\n", tmp);
3021 tmp = RREG32(RADEON_HOST_PATH_CNTL);
3022 seq_printf(m, "HOST_PATH_CNTL 0x%08x\n", tmp);
3023 tmp = RREG32(0x01D0);
3024 seq_printf(m, "AIC_CTRL 0x%08x\n", tmp);
3025 tmp = RREG32(RADEON_AIC_LO_ADDR);
3026 seq_printf(m, "AIC_LO_ADDR 0x%08x\n", tmp);
3027 tmp = RREG32(RADEON_AIC_HI_ADDR);
3028 seq_printf(m, "AIC_HI_ADDR 0x%08x\n", tmp);
3029 tmp = RREG32(0x01E4);
3030 seq_printf(m, "AIC_TLB_ADDR 0x%08x\n", tmp);
3031 return 0;
3032 }
3033
3034 static struct drm_info_list r100_debugfs_rbbm_list[] = {
3035 {"r100_rbbm_info", r100_debugfs_rbbm_info, 0, NULL},
3036 };
3037
3038 static struct drm_info_list r100_debugfs_cp_list[] = {
3039 {"r100_cp_ring_info", r100_debugfs_cp_ring_info, 0, NULL},
3040 {"r100_cp_csq_fifo", r100_debugfs_cp_csq_fifo, 0, NULL},
3041 };
3042
3043 static struct drm_info_list r100_debugfs_mc_info_list[] = {
3044 {"r100_mc_info", r100_debugfs_mc_info, 0, NULL},
3045 };
3046 #endif
3047
3048 int r100_debugfs_rbbm_init(struct radeon_device *rdev)
3049 {
3050 #if defined(CONFIG_DEBUG_FS)
3051 return radeon_debugfs_add_files(rdev, r100_debugfs_rbbm_list, 1);
3052 #else
3053 return 0;
3054 #endif
3055 }
3056
3057 int r100_debugfs_cp_init(struct radeon_device *rdev)
3058 {
3059 #if defined(CONFIG_DEBUG_FS)
3060 return radeon_debugfs_add_files(rdev, r100_debugfs_cp_list, 2);
3061 #else
3062 return 0;
3063 #endif
3064 }
3065
3066 int r100_debugfs_mc_info_init(struct radeon_device *rdev)
3067 {
3068 #if defined(CONFIG_DEBUG_FS)
3069 return radeon_debugfs_add_files(rdev, r100_debugfs_mc_info_list, 1);
3070 #else
3071 return 0;
3072 #endif
3073 }
3074
3075 int r100_set_surface_reg(struct radeon_device *rdev, int reg,
3076 uint32_t tiling_flags, uint32_t pitch,
3077 uint32_t offset, uint32_t obj_size)
3078 {
3079 int surf_index = reg * 16;
3080 int flags = 0;
3081
3082 if (rdev->family <= CHIP_RS200) {
3083 if ((tiling_flags & (RADEON_TILING_MACRO|RADEON_TILING_MICRO))
3084 == (RADEON_TILING_MACRO|RADEON_TILING_MICRO))
3085 flags |= RADEON_SURF_TILE_COLOR_BOTH;
3086 if (tiling_flags & RADEON_TILING_MACRO)
3087 flags |= RADEON_SURF_TILE_COLOR_MACRO;
3088 /* setting pitch to 0 disables tiling */
3089 if ((tiling_flags & (RADEON_TILING_MACRO|RADEON_TILING_MICRO))
3090 == 0)
3091 pitch = 0;
3092 } else if (rdev->family <= CHIP_RV280) {
3093 if (tiling_flags & (RADEON_TILING_MACRO))
3094 flags |= R200_SURF_TILE_COLOR_MACRO;
3095 if (tiling_flags & RADEON_TILING_MICRO)
3096 flags |= R200_SURF_TILE_COLOR_MICRO;
3097 } else {
3098 if (tiling_flags & RADEON_TILING_MACRO)
3099 flags |= R300_SURF_TILE_MACRO;
3100 if (tiling_flags & RADEON_TILING_MICRO)
3101 flags |= R300_SURF_TILE_MICRO;
3102 }
3103
3104 if (tiling_flags & RADEON_TILING_SWAP_16BIT)
3105 flags |= RADEON_SURF_AP0_SWP_16BPP | RADEON_SURF_AP1_SWP_16BPP;
3106 if (tiling_flags & RADEON_TILING_SWAP_32BIT)
3107 flags |= RADEON_SURF_AP0_SWP_32BPP | RADEON_SURF_AP1_SWP_32BPP;
3108
3109 /* r100/r200 divide by 16 */
3110 if (rdev->family < CHIP_R300)
3111 flags |= pitch / 16;
3112 else
3113 flags |= pitch / 8;
3114
3115
3116 DRM_DEBUG_KMS("writing surface %d %d %x %x\n", reg, flags, offset, offset+obj_size-1);
3117 WREG32(RADEON_SURFACE0_INFO + surf_index, flags);
3118 WREG32(RADEON_SURFACE0_LOWER_BOUND + surf_index, offset);
3119 WREG32(RADEON_SURFACE0_UPPER_BOUND + surf_index, offset + obj_size - 1);
3120 return 0;
3121 }
3122
3123 void r100_clear_surface_reg(struct radeon_device *rdev, int reg)
3124 {
3125 int surf_index = reg * 16;
3126 WREG32(RADEON_SURFACE0_INFO + surf_index, 0);
3127 }
3128
3129 void r100_bandwidth_update(struct radeon_device *rdev)
3130 {
3131 fixed20_12 trcd_ff, trp_ff, tras_ff, trbs_ff, tcas_ff;
3132 fixed20_12 sclk_ff, mclk_ff, sclk_eff_ff, sclk_delay_ff;
3133 fixed20_12 peak_disp_bw, mem_bw, pix_clk, pix_clk2, temp_ff, crit_point_ff;
3134 uint32_t temp, data, mem_trcd, mem_trp, mem_tras;
3135 fixed20_12 memtcas_ff[8] = {
3136 dfixed_init(1),
3137 dfixed_init(2),
3138 dfixed_init(3),
3139 dfixed_init(0),
3140 dfixed_init_half(1),
3141 dfixed_init_half(2),
3142 dfixed_init(0),
3143 };
3144 fixed20_12 memtcas_rs480_ff[8] = {
3145 dfixed_init(0),
3146 dfixed_init(1),
3147 dfixed_init(2),
3148 dfixed_init(3),
3149 dfixed_init(0),
3150 dfixed_init_half(1),
3151 dfixed_init_half(2),
3152 dfixed_init_half(3),
3153 };
3154 fixed20_12 memtcas2_ff[8] = {
3155 dfixed_init(0),
3156 dfixed_init(1),
3157 dfixed_init(2),
3158 dfixed_init(3),
3159 dfixed_init(4),
3160 dfixed_init(5),
3161 dfixed_init(6),
3162 dfixed_init(7),
3163 };
3164 fixed20_12 memtrbs[8] = {
3165 dfixed_init(1),
3166 dfixed_init_half(1),
3167 dfixed_init(2),
3168 dfixed_init_half(2),
3169 dfixed_init(3),
3170 dfixed_init_half(3),
3171 dfixed_init(4),
3172 dfixed_init_half(4)
3173 };
3174 fixed20_12 memtrbs_r4xx[8] = {
3175 dfixed_init(4),
3176 dfixed_init(5),
3177 dfixed_init(6),
3178 dfixed_init(7),
3179 dfixed_init(8),
3180 dfixed_init(9),
3181 dfixed_init(10),
3182 dfixed_init(11)
3183 };
3184 fixed20_12 min_mem_eff;
3185 fixed20_12 mc_latency_sclk, mc_latency_mclk, k1;
3186 fixed20_12 cur_latency_mclk, cur_latency_sclk;
3187 fixed20_12 disp_latency, disp_latency_overhead, disp_drain_rate,
3188 disp_drain_rate2, read_return_rate;
3189 fixed20_12 time_disp1_drop_priority;
3190 int c;
3191 int cur_size = 16; /* in octawords */
3192 int critical_point = 0, critical_point2;
3193 /* uint32_t read_return_rate, time_disp1_drop_priority; */
3194 int stop_req, max_stop_req;
3195 struct drm_display_mode *mode1 = NULL;
3196 struct drm_display_mode *mode2 = NULL;
3197 uint32_t pixel_bytes1 = 0;
3198 uint32_t pixel_bytes2 = 0;
3199
3200 radeon_update_display_priority(rdev);
3201
3202 if (rdev->mode_info.crtcs[0]->base.enabled) {
3203 mode1 = &rdev->mode_info.crtcs[0]->base.mode;
3204 pixel_bytes1 = rdev->mode_info.crtcs[0]->base.primary->fb->bits_per_pixel / 8;
3205 }
3206 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3207 if (rdev->mode_info.crtcs[1]->base.enabled) {
3208 mode2 = &rdev->mode_info.crtcs[1]->base.mode;
3209 pixel_bytes2 = rdev->mode_info.crtcs[1]->base.primary->fb->bits_per_pixel / 8;
3210 }
3211 }
3212
3213 min_mem_eff.full = dfixed_const_8(0);
3214 /* get modes */
3215 if ((rdev->disp_priority == 2) && ASIC_IS_R300(rdev)) {
3216 uint32_t mc_init_misc_lat_timer = RREG32(R300_MC_INIT_MISC_LAT_TIMER);
3217 mc_init_misc_lat_timer &= ~(R300_MC_DISP1R_INIT_LAT_MASK << R300_MC_DISP1R_INIT_LAT_SHIFT);
3218 mc_init_misc_lat_timer &= ~(R300_MC_DISP0R_INIT_LAT_MASK << R300_MC_DISP0R_INIT_LAT_SHIFT);
3219 /* check crtc enables */
3220 if (mode2)
3221 mc_init_misc_lat_timer |= (1 << R300_MC_DISP1R_INIT_LAT_SHIFT);
3222 if (mode1)
3223 mc_init_misc_lat_timer |= (1 << R300_MC_DISP0R_INIT_LAT_SHIFT);
3224 WREG32(R300_MC_INIT_MISC_LAT_TIMER, mc_init_misc_lat_timer);
3225 }
3226
3227 /*
3228 * determine is there is enough bw for current mode
3229 */
3230 sclk_ff = rdev->pm.sclk;
3231 mclk_ff = rdev->pm.mclk;
3232
3233 temp = (rdev->mc.vram_width / 8) * (rdev->mc.vram_is_ddr ? 2 : 1);
3234 temp_ff.full = dfixed_const(temp);
3235 mem_bw.full = dfixed_mul(mclk_ff, temp_ff);
3236
3237 pix_clk.full = 0;
3238 pix_clk2.full = 0;
3239 peak_disp_bw.full = 0;
3240 if (mode1) {
3241 temp_ff.full = dfixed_const(1000);
3242 pix_clk.full = dfixed_const(mode1->clock); /* convert to fixed point */
3243 pix_clk.full = dfixed_div(pix_clk, temp_ff);
3244 temp_ff.full = dfixed_const(pixel_bytes1);
3245 peak_disp_bw.full += dfixed_mul(pix_clk, temp_ff);
3246 }
3247 if (mode2) {
3248 temp_ff.full = dfixed_const(1000);
3249 pix_clk2.full = dfixed_const(mode2->clock); /* convert to fixed point */
3250 pix_clk2.full = dfixed_div(pix_clk2, temp_ff);
3251 temp_ff.full = dfixed_const(pixel_bytes2);
3252 peak_disp_bw.full += dfixed_mul(pix_clk2, temp_ff);
3253 }
3254
3255 mem_bw.full = dfixed_mul(mem_bw, min_mem_eff);
3256 if (peak_disp_bw.full >= mem_bw.full) {
3257 DRM_ERROR("You may not have enough display bandwidth for current mode\n"
3258 "If you have flickering problem, try to lower resolution, refresh rate, or color depth\n");
3259 }
3260
3261 /* Get values from the EXT_MEM_CNTL register...converting its contents. */
3262 temp = RREG32(RADEON_MEM_TIMING_CNTL);
3263 if ((rdev->family == CHIP_RV100) || (rdev->flags & RADEON_IS_IGP)) { /* RV100, M6, IGPs */
3264 mem_trcd = ((temp >> 2) & 0x3) + 1;
3265 mem_trp = ((temp & 0x3)) + 1;
3266 mem_tras = ((temp & 0x70) >> 4) + 1;
3267 } else if (rdev->family == CHIP_R300 ||
3268 rdev->family == CHIP_R350) { /* r300, r350 */
3269 mem_trcd = (temp & 0x7) + 1;
3270 mem_trp = ((temp >> 8) & 0x7) + 1;
3271 mem_tras = ((temp >> 11) & 0xf) + 4;
3272 } else if (rdev->family == CHIP_RV350 ||
3273 rdev->family <= CHIP_RV380) {
3274 /* rv3x0 */
3275 mem_trcd = (temp & 0x7) + 3;
3276 mem_trp = ((temp >> 8) & 0x7) + 3;
3277 mem_tras = ((temp >> 11) & 0xf) + 6;
3278 } else if (rdev->family == CHIP_R420 ||
3279 rdev->family == CHIP_R423 ||
3280 rdev->family == CHIP_RV410) {
3281 /* r4xx */
3282 mem_trcd = (temp & 0xf) + 3;
3283 if (mem_trcd > 15)
3284 mem_trcd = 15;
3285 mem_trp = ((temp >> 8) & 0xf) + 3;
3286 if (mem_trp > 15)
3287 mem_trp = 15;
3288 mem_tras = ((temp >> 12) & 0x1f) + 6;
3289 if (mem_tras > 31)
3290 mem_tras = 31;
3291 } else { /* RV200, R200 */
3292 mem_trcd = (temp & 0x7) + 1;
3293 mem_trp = ((temp >> 8) & 0x7) + 1;
3294 mem_tras = ((temp >> 12) & 0xf) + 4;
3295 }
3296 /* convert to FF */
3297 trcd_ff.full = dfixed_const(mem_trcd);
3298 trp_ff.full = dfixed_const(mem_trp);
3299 tras_ff.full = dfixed_const(mem_tras);
3300
3301 /* Get values from the MEM_SDRAM_MODE_REG register...converting its */
3302 temp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
3303 data = (temp & (7 << 20)) >> 20;
3304 if ((rdev->family == CHIP_RV100) || rdev->flags & RADEON_IS_IGP) {
3305 if (rdev->family == CHIP_RS480) /* don't think rs400 */
3306 tcas_ff = memtcas_rs480_ff[data];
3307 else
3308 tcas_ff = memtcas_ff[data];
3309 } else
3310 tcas_ff = memtcas2_ff[data];
3311
3312 if (rdev->family == CHIP_RS400 ||
3313 rdev->family == CHIP_RS480) {
3314 /* extra cas latency stored in bits 23-25 0-4 clocks */
3315 data = (temp >> 23) & 0x7;
3316 if (data < 5)
3317 tcas_ff.full += dfixed_const(data);
3318 }
3319
3320 if (ASIC_IS_R300(rdev) && !(rdev->flags & RADEON_IS_IGP)) {
3321 /* on the R300, Tcas is included in Trbs.
3322 */
3323 temp = RREG32(RADEON_MEM_CNTL);
3324 data = (R300_MEM_NUM_CHANNELS_MASK & temp);
3325 if (data == 1) {
3326 if (R300_MEM_USE_CD_CH_ONLY & temp) {
3327 temp = RREG32(R300_MC_IND_INDEX);
3328 temp &= ~R300_MC_IND_ADDR_MASK;
3329 temp |= R300_MC_READ_CNTL_CD_mcind;
3330 WREG32(R300_MC_IND_INDEX, temp);
3331 temp = RREG32(R300_MC_IND_DATA);
3332 data = (R300_MEM_RBS_POSITION_C_MASK & temp);
3333 } else {
3334 temp = RREG32(R300_MC_READ_CNTL_AB);
3335 data = (R300_MEM_RBS_POSITION_A_MASK & temp);
3336 }
3337 } else {
3338 temp = RREG32(R300_MC_READ_CNTL_AB);
3339 data = (R300_MEM_RBS_POSITION_A_MASK & temp);
3340 }
3341 if (rdev->family == CHIP_RV410 ||
3342 rdev->family == CHIP_R420 ||
3343 rdev->family == CHIP_R423)
3344 trbs_ff = memtrbs_r4xx[data];
3345 else
3346 trbs_ff = memtrbs[data];
3347 tcas_ff.full += trbs_ff.full;
3348 }
3349
3350 sclk_eff_ff.full = sclk_ff.full;
3351
3352 if (rdev->flags & RADEON_IS_AGP) {
3353 fixed20_12 agpmode_ff;
3354 agpmode_ff.full = dfixed_const(radeon_agpmode);
3355 temp_ff.full = dfixed_const_666(16);
3356 sclk_eff_ff.full -= dfixed_mul(agpmode_ff, temp_ff);
3357 }
3358 /* TODO PCIE lanes may affect this - agpmode == 16?? */
3359
3360 if (ASIC_IS_R300(rdev)) {
3361 sclk_delay_ff.full = dfixed_const(250);
3362 } else {
3363 if ((rdev->family == CHIP_RV100) ||
3364 rdev->flags & RADEON_IS_IGP) {
3365 if (rdev->mc.vram_is_ddr)
3366 sclk_delay_ff.full = dfixed_const(41);
3367 else
3368 sclk_delay_ff.full = dfixed_const(33);
3369 } else {
3370 if (rdev->mc.vram_width == 128)
3371 sclk_delay_ff.full = dfixed_const(57);
3372 else
3373 sclk_delay_ff.full = dfixed_const(41);
3374 }
3375 }
3376
3377 mc_latency_sclk.full = dfixed_div(sclk_delay_ff, sclk_eff_ff);
3378
3379 if (rdev->mc.vram_is_ddr) {
3380 if (rdev->mc.vram_width == 32) {
3381 k1.full = dfixed_const(40);
3382 c = 3;
3383 } else {
3384 k1.full = dfixed_const(20);
3385 c = 1;
3386 }
3387 } else {
3388 k1.full = dfixed_const(40);
3389 c = 3;
3390 }
3391
3392 temp_ff.full = dfixed_const(2);
3393 mc_latency_mclk.full = dfixed_mul(trcd_ff, temp_ff);
3394 temp_ff.full = dfixed_const(c);
3395 mc_latency_mclk.full += dfixed_mul(tcas_ff, temp_ff);
3396 temp_ff.full = dfixed_const(4);
3397 mc_latency_mclk.full += dfixed_mul(tras_ff, temp_ff);
3398 mc_latency_mclk.full += dfixed_mul(trp_ff, temp_ff);
3399 mc_latency_mclk.full += k1.full;
3400
3401 mc_latency_mclk.full = dfixed_div(mc_latency_mclk, mclk_ff);
3402 mc_latency_mclk.full += dfixed_div(temp_ff, sclk_eff_ff);
3403
3404 /*
3405 HW cursor time assuming worst case of full size colour cursor.
3406 */
3407 temp_ff.full = dfixed_const((2 * (cur_size - (rdev->mc.vram_is_ddr + 1))));
3408 temp_ff.full += trcd_ff.full;
3409 if (temp_ff.full < tras_ff.full)
3410 temp_ff.full = tras_ff.full;
3411 cur_latency_mclk.full = dfixed_div(temp_ff, mclk_ff);
3412
3413 temp_ff.full = dfixed_const(cur_size);
3414 cur_latency_sclk.full = dfixed_div(temp_ff, sclk_eff_ff);
3415 /*
3416 Find the total latency for the display data.
3417 */
3418 disp_latency_overhead.full = dfixed_const(8);
3419 disp_latency_overhead.full = dfixed_div(disp_latency_overhead, sclk_ff);
3420 mc_latency_mclk.full += disp_latency_overhead.full + cur_latency_mclk.full;
3421 mc_latency_sclk.full += disp_latency_overhead.full + cur_latency_sclk.full;
3422
3423 if (mc_latency_mclk.full > mc_latency_sclk.full)
3424 disp_latency.full = mc_latency_mclk.full;
3425 else
3426 disp_latency.full = mc_latency_sclk.full;
3427
3428 /* setup Max GRPH_STOP_REQ default value */
3429 if (ASIC_IS_RV100(rdev))
3430 max_stop_req = 0x5c;
3431 else
3432 max_stop_req = 0x7c;
3433
3434 if (mode1) {
3435 /* CRTC1
3436 Set GRPH_BUFFER_CNTL register using h/w defined optimal values.
3437 GRPH_STOP_REQ <= MIN[ 0x7C, (CRTC_H_DISP + 1) * (bit depth) / 0x10 ]
3438 */
3439 stop_req = mode1->hdisplay * pixel_bytes1 / 16;
3440
3441 if (stop_req > max_stop_req)
3442 stop_req = max_stop_req;
3443
3444 /*
3445 Find the drain rate of the display buffer.
3446 */
3447 temp_ff.full = dfixed_const((16/pixel_bytes1));
3448 disp_drain_rate.full = dfixed_div(pix_clk, temp_ff);
3449
3450 /*
3451 Find the critical point of the display buffer.
3452 */
3453 crit_point_ff.full = dfixed_mul(disp_drain_rate, disp_latency);
3454 crit_point_ff.full += dfixed_const_half(0);
3455
3456 critical_point = dfixed_trunc(crit_point_ff);
3457
3458 if (rdev->disp_priority == 2) {
3459 critical_point = 0;
3460 }
3461
3462 /*
3463 The critical point should never be above max_stop_req-4. Setting
3464 GRPH_CRITICAL_CNTL = 0 will thus force high priority all the time.
3465 */
3466 if (max_stop_req - critical_point < 4)
3467 critical_point = 0;
3468
3469 if (critical_point == 0 && mode2 && rdev->family == CHIP_R300) {
3470 /* some R300 cards have problem with this set to 0, when CRTC2 is enabled.*/
3471 critical_point = 0x10;
3472 }
3473
3474 temp = RREG32(RADEON_GRPH_BUFFER_CNTL);
3475 temp &= ~(RADEON_GRPH_STOP_REQ_MASK);
3476 temp |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT);
3477 temp &= ~(RADEON_GRPH_START_REQ_MASK);
3478 if ((rdev->family == CHIP_R350) &&
3479 (stop_req > 0x15)) {
3480 stop_req -= 0x10;
3481 }
3482 temp |= (stop_req << RADEON_GRPH_START_REQ_SHIFT);
3483 temp |= RADEON_GRPH_BUFFER_SIZE;
3484 temp &= ~(RADEON_GRPH_CRITICAL_CNTL |
3485 RADEON_GRPH_CRITICAL_AT_SOF |
3486 RADEON_GRPH_STOP_CNTL);
3487 /*
3488 Write the result into the register.
3489 */
3490 WREG32(RADEON_GRPH_BUFFER_CNTL, ((temp & ~RADEON_GRPH_CRITICAL_POINT_MASK) |
3491 (critical_point << RADEON_GRPH_CRITICAL_POINT_SHIFT)));
3492
3493 #if 0
3494 if ((rdev->family == CHIP_RS400) ||
3495 (rdev->family == CHIP_RS480)) {
3496 /* attempt to program RS400 disp regs correctly ??? */
3497 temp = RREG32(RS400_DISP1_REG_CNTL);
3498 temp &= ~(RS400_DISP1_START_REQ_LEVEL_MASK |
3499 RS400_DISP1_STOP_REQ_LEVEL_MASK);
3500 WREG32(RS400_DISP1_REQ_CNTL1, (temp |
3501 (critical_point << RS400_DISP1_START_REQ_LEVEL_SHIFT) |
3502 (critical_point << RS400_DISP1_STOP_REQ_LEVEL_SHIFT)));
3503 temp = RREG32(RS400_DMIF_MEM_CNTL1);
3504 temp &= ~(RS400_DISP1_CRITICAL_POINT_START_MASK |
3505 RS400_DISP1_CRITICAL_POINT_STOP_MASK);
3506 WREG32(RS400_DMIF_MEM_CNTL1, (temp |
3507 (critical_point << RS400_DISP1_CRITICAL_POINT_START_SHIFT) |
3508 (critical_point << RS400_DISP1_CRITICAL_POINT_STOP_SHIFT)));
3509 }
3510 #endif
3511
3512 DRM_DEBUG_KMS("GRPH_BUFFER_CNTL from to %x\n",
3513 /* (unsigned int)info->SavedReg->grph_buffer_cntl, */
3514 (unsigned int)RREG32(RADEON_GRPH_BUFFER_CNTL));
3515 }
3516
3517 if (mode2) {
3518 u32 grph2_cntl;
3519 stop_req = mode2->hdisplay * pixel_bytes2 / 16;
3520
3521 if (stop_req > max_stop_req)
3522 stop_req = max_stop_req;
3523
3524 /*
3525 Find the drain rate of the display buffer.
3526 */
3527 temp_ff.full = dfixed_const((16/pixel_bytes2));
3528 disp_drain_rate2.full = dfixed_div(pix_clk2, temp_ff);
3529
3530 grph2_cntl = RREG32(RADEON_GRPH2_BUFFER_CNTL);
3531 grph2_cntl &= ~(RADEON_GRPH_STOP_REQ_MASK);
3532 grph2_cntl |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT);
3533 grph2_cntl &= ~(RADEON_GRPH_START_REQ_MASK);
3534 if ((rdev->family == CHIP_R350) &&
3535 (stop_req > 0x15)) {
3536 stop_req -= 0x10;
3537 }
3538 grph2_cntl |= (stop_req << RADEON_GRPH_START_REQ_SHIFT);
3539 grph2_cntl |= RADEON_GRPH_BUFFER_SIZE;
3540 grph2_cntl &= ~(RADEON_GRPH_CRITICAL_CNTL |
3541 RADEON_GRPH_CRITICAL_AT_SOF |
3542 RADEON_GRPH_STOP_CNTL);
3543
3544 if ((rdev->family == CHIP_RS100) ||
3545 (rdev->family == CHIP_RS200))
3546 critical_point2 = 0;
3547 else {
3548 temp = (rdev->mc.vram_width * rdev->mc.vram_is_ddr + 1)/128;
3549 temp_ff.full = dfixed_const(temp);
3550 temp_ff.full = dfixed_mul(mclk_ff, temp_ff);
3551 if (sclk_ff.full < temp_ff.full)
3552 temp_ff.full = sclk_ff.full;
3553
3554 read_return_rate.full = temp_ff.full;
3555
3556 if (mode1) {
3557 temp_ff.full = read_return_rate.full - disp_drain_rate.full;
3558 time_disp1_drop_priority.full = dfixed_div(crit_point_ff, temp_ff);
3559 } else {
3560 time_disp1_drop_priority.full = 0;
3561 }
3562 crit_point_ff.full = disp_latency.full + time_disp1_drop_priority.full + disp_latency.full;
3563 crit_point_ff.full = dfixed_mul(crit_point_ff, disp_drain_rate2);
3564 crit_point_ff.full += dfixed_const_half(0);
3565
3566 critical_point2 = dfixed_trunc(crit_point_ff);
3567
3568 if (rdev->disp_priority == 2) {
3569 critical_point2 = 0;
3570 }
3571
3572 if (max_stop_req - critical_point2 < 4)
3573 critical_point2 = 0;
3574
3575 }
3576
3577 if (critical_point2 == 0 && rdev->family == CHIP_R300) {
3578 /* some R300 cards have problem with this set to 0 */
3579 critical_point2 = 0x10;
3580 }
3581
3582 WREG32(RADEON_GRPH2_BUFFER_CNTL, ((grph2_cntl & ~RADEON_GRPH_CRITICAL_POINT_MASK) |
3583 (critical_point2 << RADEON_GRPH_CRITICAL_POINT_SHIFT)));
3584
3585 if ((rdev->family == CHIP_RS400) ||
3586 (rdev->family == CHIP_RS480)) {
3587 #if 0
3588 /* attempt to program RS400 disp2 regs correctly ??? */
3589 temp = RREG32(RS400_DISP2_REQ_CNTL1);
3590 temp &= ~(RS400_DISP2_START_REQ_LEVEL_MASK |
3591 RS400_DISP2_STOP_REQ_LEVEL_MASK);
3592 WREG32(RS400_DISP2_REQ_CNTL1, (temp |
3593 (critical_point2 << RS400_DISP1_START_REQ_LEVEL_SHIFT) |
3594 (critical_point2 << RS400_DISP1_STOP_REQ_LEVEL_SHIFT)));
3595 temp = RREG32(RS400_DISP2_REQ_CNTL2);
3596 temp &= ~(RS400_DISP2_CRITICAL_POINT_START_MASK |
3597 RS400_DISP2_CRITICAL_POINT_STOP_MASK);
3598 WREG32(RS400_DISP2_REQ_CNTL2, (temp |
3599 (critical_point2 << RS400_DISP2_CRITICAL_POINT_START_SHIFT) |
3600 (critical_point2 << RS400_DISP2_CRITICAL_POINT_STOP_SHIFT)));
3601 #endif
3602 WREG32(RS400_DISP2_REQ_CNTL1, 0x105DC1CC);
3603 WREG32(RS400_DISP2_REQ_CNTL2, 0x2749D000);
3604 WREG32(RS400_DMIF_MEM_CNTL1, 0x29CA71DC);
3605 WREG32(RS400_DISP1_REQ_CNTL1, 0x28FBC3AC);
3606 }
3607
3608 DRM_DEBUG_KMS("GRPH2_BUFFER_CNTL from to %x\n",
3609 (unsigned int)RREG32(RADEON_GRPH2_BUFFER_CNTL));
3610 }
3611 }
3612
3613 int r100_ring_test(struct radeon_device *rdev, struct radeon_ring *ring)
3614 {
3615 uint32_t scratch;
3616 uint32_t tmp = 0;
3617 unsigned i;
3618 int r;
3619
3620 r = radeon_scratch_get(rdev, &scratch);
3621 if (r) {
3622 DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r);
3623 return r;
3624 }
3625 WREG32(scratch, 0xCAFEDEAD);
3626 r = radeon_ring_lock(rdev, ring, 2);
3627 if (r) {
3628 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
3629 radeon_scratch_free(rdev, scratch);
3630 return r;
3631 }
3632 radeon_ring_write(ring, PACKET0(scratch, 0));
3633 radeon_ring_write(ring, 0xDEADBEEF);
3634 radeon_ring_unlock_commit(rdev, ring);
3635 for (i = 0; i < rdev->usec_timeout; i++) {
3636 tmp = RREG32(scratch);
3637 if (tmp == 0xDEADBEEF) {
3638 break;
3639 }
3640 DRM_UDELAY(1);
3641 }
3642 if (i < rdev->usec_timeout) {
3643 DRM_INFO("ring test succeeded in %d usecs\n", i);
3644 } else {
3645 DRM_ERROR("radeon: ring test failed (scratch(0x%04X)=0x%08X)\n",
3646 scratch, tmp);
3647 r = -EINVAL;
3648 }
3649 radeon_scratch_free(rdev, scratch);
3650 return r;
3651 }
3652
3653 void r100_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
3654 {
3655 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
3656
3657 if (ring->rptr_save_reg) {
3658 u32 next_rptr = ring->wptr + 2 + 3;
3659 radeon_ring_write(ring, PACKET0(ring->rptr_save_reg, 0));
3660 radeon_ring_write(ring, next_rptr);
3661 }
3662
3663 radeon_ring_write(ring, PACKET0(RADEON_CP_IB_BASE, 1));
3664 radeon_ring_write(ring, ib->gpu_addr);
3665 radeon_ring_write(ring, ib->length_dw);
3666 }
3667
3668 int r100_ib_test(struct radeon_device *rdev, struct radeon_ring *ring)
3669 {
3670 struct radeon_ib ib;
3671 uint32_t scratch;
3672 uint32_t tmp = 0;
3673 unsigned i;
3674 int r;
3675
3676 r = radeon_scratch_get(rdev, &scratch);
3677 if (r) {
3678 DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r);
3679 return r;
3680 }
3681 WREG32(scratch, 0xCAFEDEAD);
3682 r = radeon_ib_get(rdev, RADEON_RING_TYPE_GFX_INDEX, &ib, NULL, 256);
3683 if (r) {
3684 DRM_ERROR("radeon: failed to get ib (%d).\n", r);
3685 goto free_scratch;
3686 }
3687 ib.ptr[0] = PACKET0(scratch, 0);
3688 ib.ptr[1] = 0xDEADBEEF;
3689 ib.ptr[2] = PACKET2(0);
3690 ib.ptr[3] = PACKET2(0);
3691 ib.ptr[4] = PACKET2(0);
3692 ib.ptr[5] = PACKET2(0);
3693 ib.ptr[6] = PACKET2(0);
3694 ib.ptr[7] = PACKET2(0);
3695 ib.length_dw = 8;
3696 r = radeon_ib_schedule(rdev, &ib, NULL);
3697 if (r) {
3698 DRM_ERROR("radeon: failed to schedule ib (%d).\n", r);
3699 goto free_ib;
3700 }
3701 r = radeon_fence_wait(ib.fence, false);
3702 if (r) {
3703 DRM_ERROR("radeon: fence wait failed (%d).\n", r);
3704 goto free_ib;
3705 }
3706 for (i = 0; i < rdev->usec_timeout; i++) {
3707 tmp = RREG32(scratch);
3708 if (tmp == 0xDEADBEEF) {
3709 break;
3710 }
3711 DRM_UDELAY(1);
3712 }
3713 if (i < rdev->usec_timeout) {
3714 DRM_INFO("ib test succeeded in %u usecs\n", i);
3715 } else {
3716 DRM_ERROR("radeon: ib test failed (scratch(0x%04X)=0x%08X)\n",
3717 scratch, tmp);
3718 r = -EINVAL;
3719 }
3720 free_ib:
3721 radeon_ib_free(rdev, &ib);
3722 free_scratch:
3723 radeon_scratch_free(rdev, scratch);
3724 return r;
3725 }
3726
3727 void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save)
3728 {
3729 /* Shutdown CP we shouldn't need to do that but better be safe than
3730 * sorry
3731 */
3732 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
3733 WREG32(R_000740_CP_CSQ_CNTL, 0);
3734
3735 /* Save few CRTC registers */
3736 save->GENMO_WT = RREG8(R_0003C2_GENMO_WT);
3737 save->CRTC_EXT_CNTL = RREG32(R_000054_CRTC_EXT_CNTL);
3738 save->CRTC_GEN_CNTL = RREG32(R_000050_CRTC_GEN_CNTL);
3739 save->CUR_OFFSET = RREG32(R_000260_CUR_OFFSET);
3740 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3741 save->CRTC2_GEN_CNTL = RREG32(R_0003F8_CRTC2_GEN_CNTL);
3742 save->CUR2_OFFSET = RREG32(R_000360_CUR2_OFFSET);
3743 }
3744
3745 /* Disable VGA aperture access */
3746 WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & save->GENMO_WT);
3747 /* Disable cursor, overlay, crtc */
3748 WREG32(R_000260_CUR_OFFSET, save->CUR_OFFSET | S_000260_CUR_LOCK(1));
3749 WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL |
3750 S_000054_CRTC_DISPLAY_DIS(1));
3751 WREG32(R_000050_CRTC_GEN_CNTL,
3752 (C_000050_CRTC_CUR_EN & save->CRTC_GEN_CNTL) |
3753 S_000050_CRTC_DISP_REQ_EN_B(1));
3754 WREG32(R_000420_OV0_SCALE_CNTL,
3755 C_000420_OV0_OVERLAY_EN & RREG32(R_000420_OV0_SCALE_CNTL));
3756 WREG32(R_000260_CUR_OFFSET, C_000260_CUR_LOCK & save->CUR_OFFSET);
3757 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3758 WREG32(R_000360_CUR2_OFFSET, save->CUR2_OFFSET |
3759 S_000360_CUR2_LOCK(1));
3760 WREG32(R_0003F8_CRTC2_GEN_CNTL,
3761 (C_0003F8_CRTC2_CUR_EN & save->CRTC2_GEN_CNTL) |
3762 S_0003F8_CRTC2_DISPLAY_DIS(1) |
3763 S_0003F8_CRTC2_DISP_REQ_EN_B(1));
3764 WREG32(R_000360_CUR2_OFFSET,
3765 C_000360_CUR2_LOCK & save->CUR2_OFFSET);
3766 }
3767 }
3768
3769 void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save)
3770 {
3771 /* Update base address for crtc */
3772 WREG32(R_00023C_DISPLAY_BASE_ADDR, rdev->mc.vram_start);
3773 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3774 WREG32(R_00033C_CRTC2_DISPLAY_BASE_ADDR, rdev->mc.vram_start);
3775 }
3776 /* Restore CRTC registers */
3777 WREG8(R_0003C2_GENMO_WT, save->GENMO_WT);
3778 WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL);
3779 WREG32(R_000050_CRTC_GEN_CNTL, save->CRTC_GEN_CNTL);
3780 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3781 WREG32(R_0003F8_CRTC2_GEN_CNTL, save->CRTC2_GEN_CNTL);
3782 }
3783 }
3784
3785 void r100_vga_render_disable(struct radeon_device *rdev)
3786 {
3787 u32 tmp;
3788
3789 tmp = RREG8(R_0003C2_GENMO_WT);
3790 WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & tmp);
3791 }
3792
3793 static void r100_debugfs(struct radeon_device *rdev)
3794 {
3795 int r;
3796
3797 r = r100_debugfs_mc_info_init(rdev);
3798 if (r)
3799 dev_warn(rdev->dev, "Failed to create r100_mc debugfs file.\n");
3800 }
3801
3802 static void r100_mc_program(struct radeon_device *rdev)
3803 {
3804 struct r100_mc_save save;
3805
3806 /* Stops all mc clients */
3807 r100_mc_stop(rdev, &save);
3808 if (rdev->flags & RADEON_IS_AGP) {
3809 WREG32(R_00014C_MC_AGP_LOCATION,
3810 S_00014C_MC_AGP_START(rdev->mc.gtt_start >> 16) |
3811 S_00014C_MC_AGP_TOP(rdev->mc.gtt_end >> 16));
3812 WREG32(R_000170_AGP_BASE, lower_32_bits(rdev->mc.agp_base));
3813 if (rdev->family > CHIP_RV200)
3814 WREG32(R_00015C_AGP_BASE_2,
3815 upper_32_bits(rdev->mc.agp_base) & 0xff);
3816 } else {
3817 WREG32(R_00014C_MC_AGP_LOCATION, 0x0FFFFFFF);
3818 WREG32(R_000170_AGP_BASE, 0);
3819 if (rdev->family > CHIP_RV200)
3820 WREG32(R_00015C_AGP_BASE_2, 0);
3821 }
3822 /* Wait for mc idle */
3823 if (r100_mc_wait_for_idle(rdev))
3824 dev_warn(rdev->dev, "Wait for MC idle timeout.\n");
3825 /* Program MC, should be a 32bits limited address space */
3826 WREG32(R_000148_MC_FB_LOCATION,
3827 S_000148_MC_FB_START(rdev->mc.vram_start >> 16) |
3828 S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16));
3829 r100_mc_resume(rdev, &save);
3830 }
3831
3832 static void r100_clock_startup(struct radeon_device *rdev)
3833 {
3834 u32 tmp;
3835
3836 if (radeon_dynclks != -1 && radeon_dynclks)
3837 radeon_legacy_set_clock_gating(rdev, 1);
3838 /* We need to force on some of the block */
3839 tmp = RREG32_PLL(R_00000D_SCLK_CNTL);
3840 tmp |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1);
3841 if ((rdev->family == CHIP_RV250) || (rdev->family == CHIP_RV280))
3842 tmp |= S_00000D_FORCE_DISP1(1) | S_00000D_FORCE_DISP2(1);
3843 WREG32_PLL(R_00000D_SCLK_CNTL, tmp);
3844 }
3845
3846 static int r100_startup(struct radeon_device *rdev)
3847 {
3848 int r;
3849
3850 /* set common regs */
3851 r100_set_common_regs(rdev);
3852 /* program mc */
3853 r100_mc_program(rdev);
3854 /* Resume clock */
3855 r100_clock_startup(rdev);
3856 /* Initialize GART (initialize after TTM so we can allocate
3857 * memory through TTM but finalize after TTM) */
3858 r100_enable_bm(rdev);
3859 if (rdev->flags & RADEON_IS_PCI) {
3860 r = r100_pci_gart_enable(rdev);
3861 if (r)
3862 return r;
3863 }
3864
3865 /* allocate wb buffer */
3866 r = radeon_wb_init(rdev);
3867 if (r)
3868 return r;
3869
3870 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
3871 if (r) {
3872 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
3873 return r;
3874 }
3875
3876 /* Enable IRQ */
3877 if (!rdev->irq.installed) {
3878 r = radeon_irq_kms_init(rdev);
3879 if (r)
3880 return r;
3881 }
3882
3883 r100_irq_set(rdev);
3884 rdev->config.r100.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
3885 /* 1M ring buffer */
3886 r = r100_cp_init(rdev, 1024 * 1024);
3887 if (r) {
3888 dev_err(rdev->dev, "failed initializing CP (%d).\n", r);
3889 return r;
3890 }
3891
3892 r = radeon_ib_pool_init(rdev);
3893 if (r) {
3894 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
3895 return r;
3896 }
3897
3898 return 0;
3899 }
3900
3901 int r100_resume(struct radeon_device *rdev)
3902 {
3903 int r;
3904
3905 /* Make sur GART are not working */
3906 if (rdev->flags & RADEON_IS_PCI)
3907 r100_pci_gart_disable(rdev);
3908 /* Resume clock before doing reset */
3909 r100_clock_startup(rdev);
3910 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
3911 if (radeon_asic_reset(rdev)) {
3912 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
3913 RREG32(R_000E40_RBBM_STATUS),
3914 RREG32(R_0007C0_CP_STAT));
3915 }
3916 /* post */
3917 radeon_combios_asic_init(rdev->ddev);
3918 /* Resume clock after posting */
3919 r100_clock_startup(rdev);
3920 /* Initialize surface registers */
3921 radeon_surface_init(rdev);
3922
3923 rdev->accel_working = true;
3924 r = r100_startup(rdev);
3925 if (r) {
3926 rdev->accel_working = false;
3927 }
3928 return r;
3929 }
3930
3931 int r100_suspend(struct radeon_device *rdev)
3932 {
3933 radeon_pm_suspend(rdev);
3934 r100_cp_disable(rdev);
3935 radeon_wb_disable(rdev);
3936 r100_irq_disable(rdev);
3937 if (rdev->flags & RADEON_IS_PCI)
3938 r100_pci_gart_disable(rdev);
3939 return 0;
3940 }
3941
3942 void r100_fini(struct radeon_device *rdev)
3943 {
3944 radeon_pm_fini(rdev);
3945 r100_cp_fini(rdev);
3946 radeon_wb_fini(rdev);
3947 radeon_ib_pool_fini(rdev);
3948 radeon_gem_fini(rdev);
3949 if (rdev->flags & RADEON_IS_PCI)
3950 r100_pci_gart_fini(rdev);
3951 radeon_agp_fini(rdev);
3952 radeon_irq_kms_fini(rdev);
3953 radeon_fence_driver_fini(rdev);
3954 radeon_bo_fini(rdev);
3955 radeon_atombios_fini(rdev);
3956 kfree(rdev->bios);
3957 rdev->bios = NULL;
3958 }
3959
3960 /*
3961 * Due to how kexec works, it can leave the hw fully initialised when it
3962 * boots the new kernel. However doing our init sequence with the CP and
3963 * WB stuff setup causes GPU hangs on the RN50 at least. So at startup
3964 * do some quick sanity checks and restore sane values to avoid this
3965 * problem.
3966 */
3967 void r100_restore_sanity(struct radeon_device *rdev)
3968 {
3969 u32 tmp;
3970
3971 tmp = RREG32(RADEON_CP_CSQ_CNTL);
3972 if (tmp) {
3973 WREG32(RADEON_CP_CSQ_CNTL, 0);
3974 }
3975 tmp = RREG32(RADEON_CP_RB_CNTL);
3976 if (tmp) {
3977 WREG32(RADEON_CP_RB_CNTL, 0);
3978 }
3979 tmp = RREG32(RADEON_SCRATCH_UMSK);
3980 if (tmp) {
3981 WREG32(RADEON_SCRATCH_UMSK, 0);
3982 }
3983 }
3984
3985 int r100_init(struct radeon_device *rdev)
3986 {
3987 int r;
3988
3989 /* Register debugfs file specific to this group of asics */
3990 r100_debugfs(rdev);
3991 /* Disable VGA */
3992 r100_vga_render_disable(rdev);
3993 /* Initialize scratch registers */
3994 radeon_scratch_init(rdev);
3995 /* Initialize surface registers */
3996 radeon_surface_init(rdev);
3997 /* sanity check some register to avoid hangs like after kexec */
3998 r100_restore_sanity(rdev);
3999 /* TODO: disable VGA need to use VGA request */
4000 /* BIOS*/
4001 if (!radeon_get_bios(rdev)) {
4002 if (ASIC_IS_AVIVO(rdev))
4003 return -EINVAL;
4004 }
4005 if (rdev->is_atom_bios) {
4006 dev_err(rdev->dev, "Expecting combios for RS400/RS480 GPU\n");
4007 return -EINVAL;
4008 } else {
4009 r = radeon_combios_init(rdev);
4010 if (r)
4011 return r;
4012 }
4013 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
4014 if (radeon_asic_reset(rdev)) {
4015 dev_warn(rdev->dev,
4016 "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
4017 RREG32(R_000E40_RBBM_STATUS),
4018 RREG32(R_0007C0_CP_STAT));
4019 }
4020 /* check if cards are posted or not */
4021 if (radeon_boot_test_post_card(rdev) == false)
4022 return -EINVAL;
4023 /* Set asic errata */
4024 r100_errata(rdev);
4025 /* Initialize clocks */
4026 radeon_get_clock_info(rdev->ddev);
4027 /* initialize AGP */
4028 if (rdev->flags & RADEON_IS_AGP) {
4029 r = radeon_agp_init(rdev);
4030 if (r) {
4031 radeon_agp_disable(rdev);
4032 }
4033 }
4034 /* initialize VRAM */
4035 r100_mc_init(rdev);
4036 /* Fence driver */
4037 r = radeon_fence_driver_init(rdev);
4038 if (r)
4039 return r;
4040 /* Memory manager */
4041 r = radeon_bo_init(rdev);
4042 if (r)
4043 return r;
4044 if (rdev->flags & RADEON_IS_PCI) {
4045 r = r100_pci_gart_init(rdev);
4046 if (r)
4047 return r;
4048 }
4049 r100_set_safe_registers(rdev);
4050
4051 /* Initialize power management */
4052 radeon_pm_init(rdev);
4053
4054 rdev->accel_working = true;
4055 r = r100_startup(rdev);
4056 if (r) {
4057 /* Somethings want wront with the accel init stop accel */
4058 dev_err(rdev->dev, "Disabling GPU acceleration\n");
4059 r100_cp_fini(rdev);
4060 radeon_wb_fini(rdev);
4061 radeon_ib_pool_fini(rdev);
4062 radeon_irq_kms_fini(rdev);
4063 if (rdev->flags & RADEON_IS_PCI)
4064 r100_pci_gart_fini(rdev);
4065 rdev->accel_working = false;
4066 }
4067 return 0;
4068 }
4069
4070 uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg,
4071 bool always_indirect)
4072 {
4073 if (reg < rdev->rmmio_size && !always_indirect)
4074 return readl(((void __iomem *)rdev->rmmio) + reg);
4075 else {
4076 unsigned long flags;
4077 uint32_t ret;
4078
4079 spin_lock_irqsave(&rdev->mmio_idx_lock, flags);
4080 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
4081 ret = readl(((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
4082 spin_unlock_irqrestore(&rdev->mmio_idx_lock, flags);
4083
4084 return ret;
4085 }
4086 }
4087
4088 void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v,
4089 bool always_indirect)
4090 {
4091 if (reg < rdev->rmmio_size && !always_indirect)
4092 writel(v, ((void __iomem *)rdev->rmmio) + reg);
4093 else {
4094 unsigned long flags;
4095
4096 spin_lock_irqsave(&rdev->mmio_idx_lock, flags);
4097 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
4098 writel(v, ((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
4099 spin_unlock_irqrestore(&rdev->mmio_idx_lock, flags);
4100 }
4101 }
4102
4103 u32 r100_io_rreg(struct radeon_device *rdev, u32 reg)
4104 {
4105 if (reg < rdev->rio_mem_size)
4106 return ioread32(rdev->rio_mem + reg);
4107 else {
4108 iowrite32(reg, rdev->rio_mem + RADEON_MM_INDEX);
4109 return ioread32(rdev->rio_mem + RADEON_MM_DATA);
4110 }
4111 }
4112
4113 void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v)
4114 {
4115 if (reg < rdev->rio_mem_size)
4116 iowrite32(v, rdev->rio_mem + reg);
4117 else {
4118 iowrite32(reg, rdev->rio_mem + RADEON_MM_INDEX);
4119 iowrite32(v, rdev->rio_mem + RADEON_MM_DATA);
4120 }
4121 }
Linux with added FPC-III support