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sched: Remove double_rq_lock() from __migrate_task()
[linux/fpc-iii.git] / drivers / gpu / drm / radeon / r600_hdmi.c
blob26ef8ced6f89fd5388f80d2eb408c1a064af3b0e
1 /*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Christian König.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Christian König
25 */
26 #include <linux/hdmi.h>
27 #include <linux/gcd.h>
28 #include <drm/drmP.h>
29 #include <drm/radeon_drm.h>
30 #include "radeon.h"
31 #include "radeon_asic.h"
32 #include "r600d.h"
33 #include "atom.h"
34
35 /*
36 * HDMI color format
37 */
38 enum r600_hdmi_color_format {
39 RGB = 0,
40 YCC_422 = 1,
41 YCC_444 = 2
42 };
43
44 /*
45 * IEC60958 status bits
46 */
47 enum r600_hdmi_iec_status_bits {
48 AUDIO_STATUS_DIG_ENABLE = 0x01,
49 AUDIO_STATUS_V = 0x02,
50 AUDIO_STATUS_VCFG = 0x04,
51 AUDIO_STATUS_EMPHASIS = 0x08,
52 AUDIO_STATUS_COPYRIGHT = 0x10,
53 AUDIO_STATUS_NONAUDIO = 0x20,
54 AUDIO_STATUS_PROFESSIONAL = 0x40,
55 AUDIO_STATUS_LEVEL = 0x80
56 };
57
58 static const struct radeon_hdmi_acr r600_hdmi_predefined_acr[] = {
59 /* 32kHz 44.1kHz 48kHz */
60 /* Clock N CTS N CTS N CTS */
61 { 25175, 4096, 25175, 28224, 125875, 6144, 25175 }, /* 25,20/1.001 MHz */
62 { 25200, 4096, 25200, 6272, 28000, 6144, 25200 }, /* 25.20 MHz */
63 { 27000, 4096, 27000, 6272, 30000, 6144, 27000 }, /* 27.00 MHz */
64 { 27027, 4096, 27027, 6272, 30030, 6144, 27027 }, /* 27.00*1.001 MHz */
65 { 54000, 4096, 54000, 6272, 60000, 6144, 54000 }, /* 54.00 MHz */
66 { 54054, 4096, 54054, 6272, 60060, 6144, 54054 }, /* 54.00*1.001 MHz */
67 { 74176, 4096, 74176, 5733, 75335, 6144, 74176 }, /* 74.25/1.001 MHz */
68 { 74250, 4096, 74250, 6272, 82500, 6144, 74250 }, /* 74.25 MHz */
69 { 148352, 4096, 148352, 5733, 150670, 6144, 148352 }, /* 148.50/1.001 MHz */
70 { 148500, 4096, 148500, 6272, 165000, 6144, 148500 }, /* 148.50 MHz */
71 };
72
73
74 /*
75 * calculate CTS and N values if they are not found in the table
76 */
77 static void r600_hdmi_calc_cts(uint32_t clock, int *CTS, int *N, int freq)
78 {
79 int n, cts;
80 unsigned long div, mul;
81
82 /* Safe, but overly large values */
83 n = 128 * freq;
84 cts = clock * 1000;
85
86 /* Smallest valid fraction */
87 div = gcd(n, cts);
88
89 n /= div;
90 cts /= div;
91
92 /*
93 * The optimal N is 128*freq/1000. Calculate the closest larger
94 * value that doesn't truncate any bits.
95 */
96 mul = ((128*freq/1000) + (n-1))/n;
97
98 n *= mul;
99 cts *= mul;
100
101 /* Check that we are in spec (not always possible) */
102 if (n < (128*freq/1500))
103 printk(KERN_WARNING "Calculated ACR N value is too small. You may experience audio problems.\n");
104 if (n > (128*freq/300))
105 printk(KERN_WARNING "Calculated ACR N value is too large. You may experience audio problems.\n");
106
107 *N = n;
108 *CTS = cts;
109
110 DRM_DEBUG("Calculated ACR timing N=%d CTS=%d for frequency %d\n",
111 *N, *CTS, freq);
112 }
113
114 struct radeon_hdmi_acr r600_hdmi_acr(uint32_t clock)
115 {
116 struct radeon_hdmi_acr res;
117 u8 i;
118
119 /* Precalculated values for common clocks */
120 for (i = 0; i < ARRAY_SIZE(r600_hdmi_predefined_acr); i++) {
121 if (r600_hdmi_predefined_acr[i].clock == clock)
122 return r600_hdmi_predefined_acr[i];
123 }
124
125 /* And odd clocks get manually calculated */
126 r600_hdmi_calc_cts(clock, &res.cts_32khz, &res.n_32khz, 32000);
127 r600_hdmi_calc_cts(clock, &res.cts_44_1khz, &res.n_44_1khz, 44100);
128 r600_hdmi_calc_cts(clock, &res.cts_48khz, &res.n_48khz, 48000);
129
130 return res;
131 }
132
133 /*
134 * update the N and CTS parameters for a given pixel clock rate
135 */
136 void r600_hdmi_update_ACR(struct drm_encoder *encoder, uint32_t clock)
137 {
138 struct drm_device *dev = encoder->dev;
139 struct radeon_device *rdev = dev->dev_private;
140 struct radeon_hdmi_acr acr = r600_hdmi_acr(clock);
141 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
142 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
143 uint32_t offset = dig->afmt->offset;
144
145 WREG32_P(HDMI0_ACR_32_0 + offset,
146 HDMI0_ACR_CTS_32(acr.cts_32khz),
147 ~HDMI0_ACR_CTS_32_MASK);
148 WREG32_P(HDMI0_ACR_32_1 + offset,
149 HDMI0_ACR_N_32(acr.n_32khz),
150 ~HDMI0_ACR_N_32_MASK);
151
152 WREG32_P(HDMI0_ACR_44_0 + offset,
153 HDMI0_ACR_CTS_44(acr.cts_44_1khz),
154 ~HDMI0_ACR_CTS_44_MASK);
155 WREG32_P(HDMI0_ACR_44_1 + offset,
156 HDMI0_ACR_N_44(acr.n_44_1khz),
157 ~HDMI0_ACR_N_44_MASK);
158
159 WREG32_P(HDMI0_ACR_48_0 + offset,
160 HDMI0_ACR_CTS_48(acr.cts_48khz),
161 ~HDMI0_ACR_CTS_48_MASK);
162 WREG32_P(HDMI0_ACR_48_1 + offset,
163 HDMI0_ACR_N_48(acr.n_48khz),
164 ~HDMI0_ACR_N_48_MASK);
165 }
166
167 /*
168 * build a HDMI Video Info Frame
169 */
170 void r600_hdmi_update_avi_infoframe(struct drm_encoder *encoder, void *buffer,
171 size_t size)
172 {
173 struct drm_device *dev = encoder->dev;
174 struct radeon_device *rdev = dev->dev_private;
175 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
176 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
177 uint32_t offset = dig->afmt->offset;
178 uint8_t *frame = buffer + 3;
179 uint8_t *header = buffer;
180
181 WREG32(HDMI0_AVI_INFO0 + offset,
182 frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24));
183 WREG32(HDMI0_AVI_INFO1 + offset,
184 frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x7] << 24));
185 WREG32(HDMI0_AVI_INFO2 + offset,
186 frame[0x8] | (frame[0x9] << 8) | (frame[0xA] << 16) | (frame[0xB] << 24));
187 WREG32(HDMI0_AVI_INFO3 + offset,
188 frame[0xC] | (frame[0xD] << 8) | (header[1] << 24));
189 }
190
191 /*
192 * build a Audio Info Frame
193 */
194 static void r600_hdmi_update_audio_infoframe(struct drm_encoder *encoder,
195 const void *buffer, size_t size)
196 {
197 struct drm_device *dev = encoder->dev;
198 struct radeon_device *rdev = dev->dev_private;
199 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
200 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
201 uint32_t offset = dig->afmt->offset;
202 const u8 *frame = buffer + 3;
203
204 WREG32(HDMI0_AUDIO_INFO0 + offset,
205 frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24));
206 WREG32(HDMI0_AUDIO_INFO1 + offset,
207 frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x8] << 24));
208 }
209
210 /*
211 * test if audio buffer is filled enough to start playing
212 */
213 static bool r600_hdmi_is_audio_buffer_filled(struct drm_encoder *encoder)
214 {
215 struct drm_device *dev = encoder->dev;
216 struct radeon_device *rdev = dev->dev_private;
217 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
218 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
219 uint32_t offset = dig->afmt->offset;
220
221 return (RREG32(HDMI0_STATUS + offset) & 0x10) != 0;
222 }
223
224 /*
225 * have buffer status changed since last call?
226 */
227 int r600_hdmi_buffer_status_changed(struct drm_encoder *encoder)
228 {
229 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
230 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
231 int status, result;
232
233 if (!dig->afmt || !dig->afmt->enabled)
234 return 0;
235
236 status = r600_hdmi_is_audio_buffer_filled(encoder);
237 result = dig->afmt->last_buffer_filled_status != status;
238 dig->afmt->last_buffer_filled_status = status;
239
240 return result;
241 }
242
243 /*
244 * write the audio workaround status to the hardware
245 */
246 void r600_hdmi_audio_workaround(struct drm_encoder *encoder)
247 {
248 struct drm_device *dev = encoder->dev;
249 struct radeon_device *rdev = dev->dev_private;
250 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
251 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
252 uint32_t offset = dig->afmt->offset;
253 bool hdmi_audio_workaround = false; /* FIXME */
254 u32 value;
255
256 if (!hdmi_audio_workaround ||
257 r600_hdmi_is_audio_buffer_filled(encoder))
258 value = 0; /* disable workaround */
259 else
260 value = HDMI0_AUDIO_TEST_EN; /* enable workaround */
261 WREG32_P(HDMI0_AUDIO_PACKET_CONTROL + offset,
262 value, ~HDMI0_AUDIO_TEST_EN);
263 }
264
265 void r600_audio_set_dto(struct drm_encoder *encoder, u32 clock)
266 {
267 struct drm_device *dev = encoder->dev;
268 struct radeon_device *rdev = dev->dev_private;
269 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
270 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
271 u32 base_rate = 24000;
272 u32 max_ratio = clock / base_rate;
273 u32 dto_phase;
274 u32 dto_modulo = clock;
275 u32 wallclock_ratio;
276 u32 dto_cntl;
277
278 if (!dig || !dig->afmt)
279 return;
280
281 if (max_ratio >= 8) {
282 dto_phase = 192 * 1000;
283 wallclock_ratio = 3;
284 } else if (max_ratio >= 4) {
285 dto_phase = 96 * 1000;
286 wallclock_ratio = 2;
287 } else if (max_ratio >= 2) {
288 dto_phase = 48 * 1000;
289 wallclock_ratio = 1;
290 } else {
291 dto_phase = 24 * 1000;
292 wallclock_ratio = 0;
293 }
294
295 /* there are two DTOs selected by DCCG_AUDIO_DTO_SELECT.
296 * doesn't matter which one you use. Just use the first one.
297 */
298 /* XXX two dtos; generally use dto0 for hdmi */
299 /* Express [24MHz / target pixel clock] as an exact rational
300 * number (coefficient of two integer numbers. DCCG_AUDIO_DTOx_PHASE
301 * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator
302 */
303 if (ASIC_IS_DCE32(rdev)) {
304 if (dig->dig_encoder == 0) {
305 dto_cntl = RREG32(DCCG_AUDIO_DTO0_CNTL) & ~DCCG_AUDIO_DTO_WALLCLOCK_RATIO_MASK;
306 dto_cntl |= DCCG_AUDIO_DTO_WALLCLOCK_RATIO(wallclock_ratio);
307 WREG32(DCCG_AUDIO_DTO0_CNTL, dto_cntl);
308 WREG32(DCCG_AUDIO_DTO0_PHASE, dto_phase);
309 WREG32(DCCG_AUDIO_DTO0_MODULE, dto_modulo);
310 WREG32(DCCG_AUDIO_DTO_SELECT, 0); /* select DTO0 */
311 } else {
312 dto_cntl = RREG32(DCCG_AUDIO_DTO1_CNTL) & ~DCCG_AUDIO_DTO_WALLCLOCK_RATIO_MASK;
313 dto_cntl |= DCCG_AUDIO_DTO_WALLCLOCK_RATIO(wallclock_ratio);
314 WREG32(DCCG_AUDIO_DTO1_CNTL, dto_cntl);
315 WREG32(DCCG_AUDIO_DTO1_PHASE, dto_phase);
316 WREG32(DCCG_AUDIO_DTO1_MODULE, dto_modulo);
317 WREG32(DCCG_AUDIO_DTO_SELECT, 1); /* select DTO1 */
318 }
319 } else {
320 /* according to the reg specs, this should DCE3.2 only, but in
321 * practice it seems to cover DCE2.0/3.0/3.1 as well.
322 */
323 if (dig->dig_encoder == 0) {
324 WREG32(DCCG_AUDIO_DTO0_PHASE, base_rate * 100);
325 WREG32(DCCG_AUDIO_DTO0_MODULE, clock * 100);
326 WREG32(DCCG_AUDIO_DTO_SELECT, 0); /* select DTO0 */
327 } else {
328 WREG32(DCCG_AUDIO_DTO1_PHASE, base_rate * 100);
329 WREG32(DCCG_AUDIO_DTO1_MODULE, clock * 100);
330 WREG32(DCCG_AUDIO_DTO_SELECT, 1); /* select DTO1 */
331 }
332 }
333 }
334
335 /*
336 * update the info frames with the data from the current display mode
337 */
338 void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode)
339 {
340 struct drm_device *dev = encoder->dev;
341 struct radeon_device *rdev = dev->dev_private;
342 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
343 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
344 u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE];
345 struct hdmi_avi_infoframe frame;
346 uint32_t offset;
347 uint32_t acr_ctl;
348 ssize_t err;
349
350 if (!dig || !dig->afmt)
351 return;
352
353 /* Silent, r600_hdmi_enable will raise WARN for us */
354 if (!dig->afmt->enabled)
355 return;
356 offset = dig->afmt->offset;
357
358 /* disable audio prior to setting up hw */
359 dig->afmt->pin = r600_audio_get_pin(rdev);
360 r600_audio_enable(rdev, dig->afmt->pin, false);
361
362 r600_audio_set_dto(encoder, mode->clock);
363
364 WREG32_P(HDMI0_AUDIO_PACKET_CONTROL + offset,
365 HDMI0_AUDIO_SAMPLE_SEND | /* send audio packets */
366 HDMI0_AUDIO_DELAY_EN(1) | /* default audio delay */
367 HDMI0_AUDIO_PACKETS_PER_LINE(3) | /* should be suffient for all audio modes and small enough for all hblanks */
368 HDMI0_60958_CS_UPDATE, /* allow 60958 channel status fields to be updated */
369 ~(HDMI0_AUDIO_SAMPLE_SEND |
370 HDMI0_AUDIO_DELAY_EN_MASK |
371 HDMI0_AUDIO_PACKETS_PER_LINE_MASK |
372 HDMI0_60958_CS_UPDATE));
373
374 /* DCE 3.0 uses register that's normally for CRC_CONTROL */
375 acr_ctl = ASIC_IS_DCE3(rdev) ? DCE3_HDMI0_ACR_PACKET_CONTROL :
376 HDMI0_ACR_PACKET_CONTROL;
377 WREG32_P(acr_ctl + offset,
378 HDMI0_ACR_SOURCE | /* select SW CTS value - XXX verify that hw CTS works on all families */
379 HDMI0_ACR_AUTO_SEND, /* allow hw to sent ACR packets when required */
380 ~(HDMI0_ACR_SOURCE |
381 HDMI0_ACR_AUTO_SEND));
382
383 WREG32_OR(HDMI0_VBI_PACKET_CONTROL + offset,
384 HDMI0_NULL_SEND | /* send null packets when required */
385 HDMI0_GC_SEND | /* send general control packets */
386 HDMI0_GC_CONT); /* send general control packets every frame */
387
388 WREG32_OR(HDMI0_INFOFRAME_CONTROL0 + offset,
389 HDMI0_AVI_INFO_SEND | /* enable AVI info frames */
390 HDMI0_AVI_INFO_CONT | /* send AVI info frames every frame/field */
391 HDMI0_AUDIO_INFO_SEND | /* enable audio info frames (frames won't be set until audio is enabled) */
392 HDMI0_AUDIO_INFO_UPDATE); /* required for audio info values to be updated */
393
394 WREG32_P(HDMI0_INFOFRAME_CONTROL1 + offset,
395 HDMI0_AVI_INFO_LINE(2) | /* anything other than 0 */
396 HDMI0_AUDIO_INFO_LINE(2), /* anything other than 0 */
397 ~(HDMI0_AVI_INFO_LINE_MASK |
398 HDMI0_AUDIO_INFO_LINE_MASK));
399
400 WREG32_AND(HDMI0_GC + offset,
401 ~HDMI0_GC_AVMUTE); /* unset HDMI0_GC_AVMUTE */
402
403 err = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode);
404 if (err < 0) {
405 DRM_ERROR("failed to setup AVI infoframe: %zd\n", err);
406 return;
407 }
408
409 err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer));
410 if (err < 0) {
411 DRM_ERROR("failed to pack AVI infoframe: %zd\n", err);
412 return;
413 }
414
415 r600_hdmi_update_avi_infoframe(encoder, buffer, sizeof(buffer));
416
417 /* fglrx duplicates INFOFRAME_CONTROL0 & INFOFRAME_CONTROL1 ops here */
418
419 WREG32_AND(HDMI0_GENERIC_PACKET_CONTROL + offset,
420 ~(HDMI0_GENERIC0_SEND |
421 HDMI0_GENERIC0_CONT |
422 HDMI0_GENERIC0_UPDATE |
423 HDMI0_GENERIC1_SEND |
424 HDMI0_GENERIC1_CONT |
425 HDMI0_GENERIC0_LINE_MASK |
426 HDMI0_GENERIC1_LINE_MASK));
427
428 r600_hdmi_update_ACR(encoder, mode->clock);
429
430 WREG32_P(HDMI0_60958_0 + offset,
431 HDMI0_60958_CS_CHANNEL_NUMBER_L(1),
432 ~(HDMI0_60958_CS_CHANNEL_NUMBER_L_MASK |
433 HDMI0_60958_CS_CLOCK_ACCURACY_MASK));
434
435 WREG32_P(HDMI0_60958_1 + offset,
436 HDMI0_60958_CS_CHANNEL_NUMBER_R(2),
437 ~HDMI0_60958_CS_CHANNEL_NUMBER_R_MASK);
438
439 /* it's unknown what these bits do excatly, but it's indeed quite useful for debugging */
440 WREG32(HDMI0_RAMP_CONTROL0 + offset, 0x00FFFFFF);
441 WREG32(HDMI0_RAMP_CONTROL1 + offset, 0x007FFFFF);
442 WREG32(HDMI0_RAMP_CONTROL2 + offset, 0x00000001);
443 WREG32(HDMI0_RAMP_CONTROL3 + offset, 0x00000001);
444
445 /* enable audio after to setting up hw */
446 r600_audio_enable(rdev, dig->afmt->pin, true);
447 }
448
449 /**
450 * r600_hdmi_update_audio_settings - Update audio infoframe
451 *
452 * @encoder: drm encoder
453 *
454 * Gets info about current audio stream and updates audio infoframe.
455 */
456 void r600_hdmi_update_audio_settings(struct drm_encoder *encoder)
457 {
458 struct drm_device *dev = encoder->dev;
459 struct radeon_device *rdev = dev->dev_private;
460 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
461 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
462 struct r600_audio_pin audio = r600_audio_status(rdev);
463 uint8_t buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AUDIO_INFOFRAME_SIZE];
464 struct hdmi_audio_infoframe frame;
465 uint32_t offset;
466 uint32_t value;
467 ssize_t err;
468
469 if (!dig->afmt || !dig->afmt->enabled)
470 return;
471 offset = dig->afmt->offset;
472
473 DRM_DEBUG("%s with %d channels, %d Hz sampling rate, %d bits per sample,\n",
474 r600_hdmi_is_audio_buffer_filled(encoder) ? "playing" : "stopped",
475 audio.channels, audio.rate, audio.bits_per_sample);
476 DRM_DEBUG("0x%02X IEC60958 status bits and 0x%02X category code\n",
477 (int)audio.status_bits, (int)audio.category_code);
478
479 err = hdmi_audio_infoframe_init(&frame);
480 if (err < 0) {
481 DRM_ERROR("failed to setup audio infoframe\n");
482 return;
483 }
484
485 frame.channels = audio.channels;
486
487 err = hdmi_audio_infoframe_pack(&frame, buffer, sizeof(buffer));
488 if (err < 0) {
489 DRM_ERROR("failed to pack audio infoframe\n");
490 return;
491 }
492
493 value = RREG32(HDMI0_AUDIO_PACKET_CONTROL + offset);
494 if (value & HDMI0_AUDIO_TEST_EN)
495 WREG32(HDMI0_AUDIO_PACKET_CONTROL + offset,
496 value & ~HDMI0_AUDIO_TEST_EN);
497
498 WREG32_OR(HDMI0_CONTROL + offset,
499 HDMI0_ERROR_ACK);
500
501 WREG32_AND(HDMI0_INFOFRAME_CONTROL0 + offset,
502 ~HDMI0_AUDIO_INFO_SOURCE);
503
504 r600_hdmi_update_audio_infoframe(encoder, buffer, sizeof(buffer));
505
506 WREG32_OR(HDMI0_INFOFRAME_CONTROL0 + offset,
507 HDMI0_AUDIO_INFO_CONT |
508 HDMI0_AUDIO_INFO_UPDATE);
509 }
510
511 /*
512 * enable the HDMI engine
513 */
514 void r600_hdmi_enable(struct drm_encoder *encoder, bool enable)
515 {
516 struct drm_device *dev = encoder->dev;
517 struct radeon_device *rdev = dev->dev_private;
518 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
519 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
520 u32 hdmi = HDMI0_ERROR_ACK;
521
522 if (!dig || !dig->afmt)
523 return;
524
525 /* Silent, r600_hdmi_enable will raise WARN for us */
526 if (enable && dig->afmt->enabled)
527 return;
528 if (!enable && !dig->afmt->enabled)
529 return;
530
531 /* Older chipsets require setting HDMI and routing manually */
532 if (!ASIC_IS_DCE3(rdev)) {
533 if (enable)
534 hdmi |= HDMI0_ENABLE;
535 switch (radeon_encoder->encoder_id) {
536 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
537 if (enable) {
538 WREG32_OR(AVIVO_TMDSA_CNTL, AVIVO_TMDSA_CNTL_HDMI_EN);
539 hdmi |= HDMI0_STREAM(HDMI0_STREAM_TMDSA);
540 } else {
541 WREG32_AND(AVIVO_TMDSA_CNTL, ~AVIVO_TMDSA_CNTL_HDMI_EN);
542 }
543 break;
544 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
545 if (enable) {
546 WREG32_OR(AVIVO_LVTMA_CNTL, AVIVO_LVTMA_CNTL_HDMI_EN);
547 hdmi |= HDMI0_STREAM(HDMI0_STREAM_LVTMA);
548 } else {
549 WREG32_AND(AVIVO_LVTMA_CNTL, ~AVIVO_LVTMA_CNTL_HDMI_EN);
550 }
551 break;
552 case ENCODER_OBJECT_ID_INTERNAL_DDI:
553 if (enable) {
554 WREG32_OR(DDIA_CNTL, DDIA_HDMI_EN);
555 hdmi |= HDMI0_STREAM(HDMI0_STREAM_DDIA);
556 } else {
557 WREG32_AND(DDIA_CNTL, ~DDIA_HDMI_EN);
558 }
559 break;
560 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
561 if (enable)
562 hdmi |= HDMI0_STREAM(HDMI0_STREAM_DVOA);
563 break;
564 default:
565 dev_err(rdev->dev, "Invalid encoder for HDMI: 0x%X\n",
566 radeon_encoder->encoder_id);
567 break;
568 }
569 WREG32(HDMI0_CONTROL + dig->afmt->offset, hdmi);
570 }
571
572 if (rdev->irq.installed) {
573 /* if irq is available use it */
574 /* XXX: shouldn't need this on any asics. Double check DCE2/3 */
575 if (enable)
576 radeon_irq_kms_enable_afmt(rdev, dig->afmt->id);
577 else
578 radeon_irq_kms_disable_afmt(rdev, dig->afmt->id);
579 }
580
581 dig->afmt->enabled = enable;
582
583 DRM_DEBUG("%sabling HDMI interface @ 0x%04X for encoder 0x%x\n",
584 enable ? "En" : "Dis", dig->afmt->offset, radeon_encoder->encoder_id);
585 }
586
Linux with added FPC-III support