drivers/gpu/drm/radeon/radeon.h

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28 #ifndef __RADEON_H__
  29 #define __RADEON_H__
  30
  31 /* TODO: Here are things that needs to be done :
  32  *      - surface allocator & initializer : (bit like scratch reg) should
  33  *        initialize HDP_ stuff on RS600, R600, R700 hw, well anythings
  34  *        related to surface
  35  *      - WB : write back stuff (do it bit like scratch reg things)
  36  *      - Vblank : look at Jesse's rework and what we should do
  37  *      - r600/r700: gart & cp
  38  *      - cs : clean cs ioctl use bitmap & things like that.
  39  *      - power management stuff
  40  *      - Barrier in gart code
  41  *      - Unmappabled vram ?
  42  *      - TESTING, TESTING, TESTING
  43  */
  44
  45 /* Initialization path:
  46  *  We expect that acceleration initialization might fail for various
  47  *  reasons even thought we work hard to make it works on most
  48  *  configurations. In order to still have a working userspace in such
  49  *  situation the init path must succeed up to the memory controller
  50  *  initialization point. Failure before this point are considered as
  51  *  fatal error. Here is the init callchain :
  52  *      radeon_device_init  perform common structure, mutex initialization
  53  *      asic_init           setup the GPU memory layout and perform all
  54  *                          one time initialization (failure in this
  55  *                          function are considered fatal)
  56  *      asic_startup        setup the GPU acceleration, in order to
  57  *                          follow guideline the first thing this
  58  *                          function should do is setting the GPU
  59  *                          memory controller (only MC setup failure
  60  *                          are considered as fatal)
  61  */
  62
  63 #include <linux/atomic.h>
  64 #include <linux/wait.h>
  65 #include <linux/list.h>
  66 #include <linux/kref.h>
  67
  68 #include <ttm/ttm_bo_api.h>
  69 #include <ttm/ttm_bo_driver.h>
  70 #include <ttm/ttm_placement.h>
  71 #include <ttm/ttm_module.h>
  72 #include <ttm/ttm_execbuf_util.h>
  73
  74 #include "radeon_family.h"
  75 #include "radeon_mode.h"
  76 #include "radeon_reg.h"
  77
  78 /*
  79  * Modules parameters.
  80  */
  81 extern int radeon_no_wb;
  82 extern int radeon_modeset;
  83 extern int radeon_dynclks;
  84 extern int radeon_r4xx_atom;
  85 extern int radeon_agpmode;
  86 extern int radeon_vram_limit;
  87 extern int radeon_gart_size;
  88 extern int radeon_benchmarking;
  89 extern int radeon_testing;
  90 extern int radeon_connector_table;
  91 extern int radeon_tv;
  92 extern int radeon_audio;
  93 extern int radeon_disp_priority;
  94 extern int radeon_hw_i2c;
  95 extern int radeon_pcie_gen2;
  96 extern int radeon_msi;
  97 extern int radeon_lockup_timeout;
  98 extern int radeon_fastfb;
  99 extern int radeon_dpm;
 100 extern int radeon_aspm;
 101 extern int radeon_runtime_pm;
 102 extern int radeon_hard_reset;
 103 extern int radeon_vm_size;
 104 extern int radeon_vm_block_size;
 105 extern int radeon_deep_color;
 106
 107 /*
 108  * Copy from radeon_drv.h so we don't have to include both and have conflicting
 109  * symbol;
 110  */
 111 #define RADEON_MAX_USEC_TIMEOUT                 100000  /* 100 ms */
 112 #define RADEON_FENCE_JIFFIES_TIMEOUT            (HZ / 2)
 113 /* RADEON_IB_POOL_SIZE must be a power of 2 */
 114 #define RADEON_IB_POOL_SIZE                     16
 115 #define RADEON_DEBUGFS_MAX_COMPONENTS           32
 116 #define RADEONFB_CONN_LIMIT                     4
 117 #define RADEON_BIOS_NUM_SCRATCH                 8
 118
 119 /* fence seq are set to this number when signaled */
 120 #define RADEON_FENCE_SIGNALED_SEQ               0LL
 121
 122 /* internal ring indices */
 123 /* r1xx+ has gfx CP ring */
 124 #define RADEON_RING_TYPE_GFX_INDEX              0
 125
 126 /* cayman has 2 compute CP rings */
 127 #define CAYMAN_RING_TYPE_CP1_INDEX              1
 128 #define CAYMAN_RING_TYPE_CP2_INDEX              2
 129
 130 /* R600+ has an async dma ring */
 131 #define R600_RING_TYPE_DMA_INDEX                3
 132 /* cayman add a second async dma ring */
 133 #define CAYMAN_RING_TYPE_DMA1_INDEX             4
 134
 135 /* R600+ */
 136 #define R600_RING_TYPE_UVD_INDEX                5
 137
 138 /* TN+ */
 139 #define TN_RING_TYPE_VCE1_INDEX                 6
 140 #define TN_RING_TYPE_VCE2_INDEX                 7
 141
 142 /* max number of rings */
 143 #define RADEON_NUM_RINGS                        8
 144
 145 /* number of hw syncs before falling back on blocking */
 146 #define RADEON_NUM_SYNCS                        4
 147
 148 /* number of hw syncs before falling back on blocking */
 149 #define RADEON_NUM_SYNCS                        4
 150
 151 /* hardcode those limit for now */
 152 #define RADEON_VA_IB_OFFSET                     (1 << 20)
 153 #define RADEON_VA_RESERVED_SIZE                 (8 << 20)
 154 #define RADEON_IB_VM_MAX_SIZE                   (64 << 10)
 155
 156 /* hard reset data */
 157 #define RADEON_ASIC_RESET_DATA                  0x39d5e86b
 158
 159 /* reset flags */
 160 #define RADEON_RESET_GFX                        (1 << 0)
 161 #define RADEON_RESET_COMPUTE                    (1 << 1)
 162 #define RADEON_RESET_DMA                        (1 << 2)
 163 #define RADEON_RESET_CP                         (1 << 3)
 164 #define RADEON_RESET_GRBM                       (1 << 4)
 165 #define RADEON_RESET_DMA1                       (1 << 5)
 166 #define RADEON_RESET_RLC                        (1 << 6)
 167 #define RADEON_RESET_SEM                        (1 << 7)
 168 #define RADEON_RESET_IH                         (1 << 8)
 169 #define RADEON_RESET_VMC                        (1 << 9)
 170 #define RADEON_RESET_MC                         (1 << 10)
 171 #define RADEON_RESET_DISPLAY                    (1 << 11)
 172
 173 /* CG block flags */
 174 #define RADEON_CG_BLOCK_GFX                     (1 << 0)
 175 #define RADEON_CG_BLOCK_MC                      (1 << 1)
 176 #define RADEON_CG_BLOCK_SDMA                    (1 << 2)
 177 #define RADEON_CG_BLOCK_UVD                     (1 << 3)
 178 #define RADEON_CG_BLOCK_VCE                     (1 << 4)
 179 #define RADEON_CG_BLOCK_HDP                     (1 << 5)
 180 #define RADEON_CG_BLOCK_BIF                     (1 << 6)
 181
 182 /* CG flags */
 183 #define RADEON_CG_SUPPORT_GFX_MGCG              (1 << 0)
 184 #define RADEON_CG_SUPPORT_GFX_MGLS              (1 << 1)
 185 #define RADEON_CG_SUPPORT_GFX_CGCG              (1 << 2)
 186 #define RADEON_CG_SUPPORT_GFX_CGLS              (1 << 3)
 187 #define RADEON_CG_SUPPORT_GFX_CGTS              (1 << 4)
 188 #define RADEON_CG_SUPPORT_GFX_CGTS_LS           (1 << 5)
 189 #define RADEON_CG_SUPPORT_GFX_CP_LS             (1 << 6)
 190 #define RADEON_CG_SUPPORT_GFX_RLC_LS            (1 << 7)
 191 #define RADEON_CG_SUPPORT_MC_LS                 (1 << 8)
 192 #define RADEON_CG_SUPPORT_MC_MGCG               (1 << 9)
 193 #define RADEON_CG_SUPPORT_SDMA_LS               (1 << 10)
 194 #define RADEON_CG_SUPPORT_SDMA_MGCG             (1 << 11)
 195 #define RADEON_CG_SUPPORT_BIF_LS                (1 << 12)
 196 #define RADEON_CG_SUPPORT_UVD_MGCG              (1 << 13)
 197 #define RADEON_CG_SUPPORT_VCE_MGCG              (1 << 14)
 198 #define RADEON_CG_SUPPORT_HDP_LS                (1 << 15)
 199 #define RADEON_CG_SUPPORT_HDP_MGCG              (1 << 16)
 200
 201 /* PG flags */
 202 #define RADEON_PG_SUPPORT_GFX_PG                (1 << 0)
 203 #define RADEON_PG_SUPPORT_GFX_SMG               (1 << 1)
 204 #define RADEON_PG_SUPPORT_GFX_DMG               (1 << 2)
 205 #define RADEON_PG_SUPPORT_UVD                   (1 << 3)
 206 #define RADEON_PG_SUPPORT_VCE                   (1 << 4)
 207 #define RADEON_PG_SUPPORT_CP                    (1 << 5)
 208 #define RADEON_PG_SUPPORT_GDS                   (1 << 6)
 209 #define RADEON_PG_SUPPORT_RLC_SMU_HS            (1 << 7)
 210 #define RADEON_PG_SUPPORT_SDMA                  (1 << 8)
 211 #define RADEON_PG_SUPPORT_ACP                   (1 << 9)
 212 #define RADEON_PG_SUPPORT_SAMU                  (1 << 10)
 213
 214 /* max cursor sizes (in pixels) */
 215 #define CURSOR_WIDTH 64
 216 #define CURSOR_HEIGHT 64
 217
 218 #define CIK_CURSOR_WIDTH 128
 219 #define CIK_CURSOR_HEIGHT 128
 220
 221 /*
 222  * Errata workarounds.
 223  */
 224 enum radeon_pll_errata {
 225         CHIP_ERRATA_R300_CG             = 0x00000001,
 226         CHIP_ERRATA_PLL_DUMMYREADS      = 0x00000002,
 227         CHIP_ERRATA_PLL_DELAY           = 0x00000004
 228 };
 229
 230
 231 struct radeon_device;
 232
 233
 234 /*
 235  * BIOS.
 236  */
 237 bool radeon_get_bios(struct radeon_device *rdev);
 238
 239 /*
 240  * Dummy page
 241  */
 242 struct radeon_dummy_page {
 243         struct page     *page;
 244         dma_addr_t      addr;
 245 };
 246 int radeon_dummy_page_init(struct radeon_device *rdev);
 247 void radeon_dummy_page_fini(struct radeon_device *rdev);
 248
 249
 250 /*
 251  * Clocks
 252  */
 253 struct radeon_clock {
 254         struct radeon_pll p1pll;
 255         struct radeon_pll p2pll;
 256         struct radeon_pll dcpll;
 257         struct radeon_pll spll;
 258         struct radeon_pll mpll;
 259         /* 10 Khz units */
 260         uint32_t default_mclk;
 261         uint32_t default_sclk;
 262         uint32_t default_dispclk;
 263         uint32_t current_dispclk;
 264         uint32_t dp_extclk;
 265         uint32_t max_pixel_clock;
 266 };
 267
 268 /*
 269  * Power management
 270  */
 271 int radeon_pm_init(struct radeon_device *rdev);
 272 int radeon_pm_late_init(struct radeon_device *rdev);
 273 void radeon_pm_fini(struct radeon_device *rdev);
 274 void radeon_pm_compute_clocks(struct radeon_device *rdev);
 275 void radeon_pm_suspend(struct radeon_device *rdev);
 276 void radeon_pm_resume(struct radeon_device *rdev);
 277 void radeon_combios_get_power_modes(struct radeon_device *rdev);
 278 void radeon_atombios_get_power_modes(struct radeon_device *rdev);
 279 int radeon_atom_get_clock_dividers(struct radeon_device *rdev,
 280                                    u8 clock_type,
 281                                    u32 clock,
 282                                    bool strobe_mode,
 283                                    struct atom_clock_dividers *dividers);
 284 int radeon_atom_get_memory_pll_dividers(struct radeon_device *rdev,
 285                                         u32 clock,
 286                                         bool strobe_mode,
 287                                         struct atom_mpll_param *mpll_param);
 288 void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type);
 289 int radeon_atom_get_voltage_gpio_settings(struct radeon_device *rdev,
 290                                           u16 voltage_level, u8 voltage_type,
 291                                           u32 *gpio_value, u32 *gpio_mask);
 292 void radeon_atom_set_engine_dram_timings(struct radeon_device *rdev,
 293                                          u32 eng_clock, u32 mem_clock);
 294 int radeon_atom_get_voltage_step(struct radeon_device *rdev,
 295                                  u8 voltage_type, u16 *voltage_step);
 296 int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type,
 297                              u16 voltage_id, u16 *voltage);
 298 int radeon_atom_get_leakage_vddc_based_on_leakage_idx(struct radeon_device *rdev,
 299                                                       u16 *voltage,
 300                                                       u16 leakage_idx);
 301 int radeon_atom_get_leakage_id_from_vbios(struct radeon_device *rdev,
 302                                           u16 *leakage_id);
 303 int radeon_atom_get_leakage_vddc_based_on_leakage_params(struct radeon_device *rdev,
 304                                                          u16 *vddc, u16 *vddci,
 305                                                          u16 virtual_voltage_id,
 306                                                          u16 vbios_voltage_id);
 307 int radeon_atom_round_to_true_voltage(struct radeon_device *rdev,
 308                                       u8 voltage_type,
 309                                       u16 nominal_voltage,
 310                                       u16 *true_voltage);
 311 int radeon_atom_get_min_voltage(struct radeon_device *rdev,
 312                                 u8 voltage_type, u16 *min_voltage);
 313 int radeon_atom_get_max_voltage(struct radeon_device *rdev,
 314                                 u8 voltage_type, u16 *max_voltage);
 315 int radeon_atom_get_voltage_table(struct radeon_device *rdev,
 316                                   u8 voltage_type, u8 voltage_mode,
 317                                   struct atom_voltage_table *voltage_table);
 318 bool radeon_atom_is_voltage_gpio(struct radeon_device *rdev,
 319                                  u8 voltage_type, u8 voltage_mode);
 320 void radeon_atom_update_memory_dll(struct radeon_device *rdev,
 321                                    u32 mem_clock);
 322 void radeon_atom_set_ac_timing(struct radeon_device *rdev,
 323                                u32 mem_clock);
 324 int radeon_atom_init_mc_reg_table(struct radeon_device *rdev,
 325                                   u8 module_index,
 326                                   struct atom_mc_reg_table *reg_table);
 327 int radeon_atom_get_memory_info(struct radeon_device *rdev,
 328                                 u8 module_index, struct atom_memory_info *mem_info);
 329 int radeon_atom_get_mclk_range_table(struct radeon_device *rdev,
 330                                      bool gddr5, u8 module_index,
 331                                      struct atom_memory_clock_range_table *mclk_range_table);
 332 int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type,
 333                              u16 voltage_id, u16 *voltage);
 334 void rs690_pm_info(struct radeon_device *rdev);
 335 extern void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw,
 336                                     unsigned *bankh, unsigned *mtaspect,
 337                                     unsigned *tile_split);
 338
 339 /*
 340  * Fences.
 341  */
 342 struct radeon_fence_driver {
 343         uint32_t                        scratch_reg;
 344         uint64_t                        gpu_addr;
 345         volatile uint32_t               *cpu_addr;
 346         /* sync_seq is protected by ring emission lock */
 347         uint64_t                        sync_seq[RADEON_NUM_RINGS];
 348         atomic64_t                      last_seq;
 349         bool                            initialized;
 350 };
 351
 352 struct radeon_fence {
 353         struct radeon_device            *rdev;
 354         struct kref                     kref;
 355         /* protected by radeon_fence.lock */
 356         uint64_t                        seq;
 357         /* RB, DMA, etc. */
 358         unsigned                        ring;
 359 };
 360
 361 int radeon_fence_driver_start_ring(struct radeon_device *rdev, int ring);
 362 int radeon_fence_driver_init(struct radeon_device *rdev);
 363 void radeon_fence_driver_fini(struct radeon_device *rdev);
 364 void radeon_fence_driver_force_completion(struct radeon_device *rdev);
 365 int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence **fence, int ring);
 366 void radeon_fence_process(struct radeon_device *rdev, int ring);
 367 bool radeon_fence_signaled(struct radeon_fence *fence);
 368 int radeon_fence_wait(struct radeon_fence *fence, bool interruptible);
 369 int radeon_fence_wait_next(struct radeon_device *rdev, int ring);
 370 int radeon_fence_wait_empty(struct radeon_device *rdev, int ring);
 371 int radeon_fence_wait_any(struct radeon_device *rdev,
 372                           struct radeon_fence **fences,
 373                           bool intr);
 374 struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence);
 375 void radeon_fence_unref(struct radeon_fence **fence);
 376 unsigned radeon_fence_count_emitted(struct radeon_device *rdev, int ring);
 377 bool radeon_fence_need_sync(struct radeon_fence *fence, int ring);
 378 void radeon_fence_note_sync(struct radeon_fence *fence, int ring);
 379 static inline struct radeon_fence *radeon_fence_later(struct radeon_fence *a,
 380                                                       struct radeon_fence *b)
 381 {
 382         if (!a) {
 383                 return b;
 384         }
 385
 386         if (!b) {
 387                 return a;
 388         }
 389
 390         BUG_ON(a->ring != b->ring);
 391
 392         if (a->seq > b->seq) {
 393                 return a;
 394         } else {
 395                 return b;
 396         }
 397 }
 398
 399 static inline bool radeon_fence_is_earlier(struct radeon_fence *a,
 400                                            struct radeon_fence *b)
 401 {
 402         if (!a) {
 403                 return false;
 404         }
 405
 406         if (!b) {
 407                 return true;
 408         }
 409
 410         BUG_ON(a->ring != b->ring);
 411
 412         return a->seq < b->seq;
 413 }
 414
 415 /*
 416  * Tiling registers
 417  */
 418 struct radeon_surface_reg {
 419         struct radeon_bo *bo;
 420 };
 421
 422 #define RADEON_GEM_MAX_SURFACES 8
 423
 424 /*
 425  * TTM.
 426  */
 427 struct radeon_mman {
 428         struct ttm_bo_global_ref        bo_global_ref;
 429         struct drm_global_reference     mem_global_ref;
 430         struct ttm_bo_device            bdev;
 431         bool                            mem_global_referenced;
 432         bool                            initialized;
 433
 434 #if defined(CONFIG_DEBUG_FS)
 435         struct dentry                   *vram;
 436         struct dentry                   *gtt;
 437 #endif
 438 };
 439
 440 /* bo virtual address in a specific vm */
 441 struct radeon_bo_va {
 442         /* protected by bo being reserved */
 443         struct list_head                bo_list;
 444         uint64_t                        soffset;
 445         uint64_t                        eoffset;
 446         uint32_t                        flags;
 447         bool                            valid;
 448         unsigned                        ref_count;
 449
 450         /* protected by vm mutex */
 451         struct list_head                vm_list;
 452         struct list_head                vm_status;
 453
 454         /* constant after initialization */
 455         struct radeon_vm                *vm;
 456         struct radeon_bo                *bo;
 457 };
 458
 459 struct radeon_bo {
 460         /* Protected by gem.mutex */
 461         struct list_head                list;
 462         /* Protected by tbo.reserved */
 463         u32                             initial_domain;
 464         u32                             placements[3];
 465         struct ttm_placement            placement;
 466         struct ttm_buffer_object        tbo;
 467         struct ttm_bo_kmap_obj          kmap;
 468         unsigned                        pin_count;
 469         void                            *kptr;
 470         u32                             tiling_flags;
 471         u32                             pitch;
 472         int                             surface_reg;
 473         /* list of all virtual address to which this bo
 474          * is associated to
 475          */
 476         struct list_head                va;
 477         /* Constant after initialization */
 478         struct radeon_device            *rdev;
 479         struct drm_gem_object           gem_base;
 480
 481         struct ttm_bo_kmap_obj          dma_buf_vmap;
 482         pid_t                           pid;
 483 };
 484 #define gem_to_radeon_bo(gobj) container_of((gobj), struct radeon_bo, gem_base)
 485
 486 int radeon_gem_debugfs_init(struct radeon_device *rdev);
 487
 488 /* sub-allocation manager, it has to be protected by another lock.
 489  * By conception this is an helper for other part of the driver
 490  * like the indirect buffer or semaphore, which both have their
 491  * locking.
 492  *
 493  * Principe is simple, we keep a list of sub allocation in offset
 494  * order (first entry has offset == 0, last entry has the highest
 495  * offset).
 496  *
 497  * When allocating new object we first check if there is room at
 498  * the end total_size - (last_object_offset + last_object_size) >=
 499  * alloc_size. If so we allocate new object there.
 500  *
 501  * When there is not enough room at the end, we start waiting for
 502  * each sub object until we reach object_offset+object_size >=
 503  * alloc_size, this object then become the sub object we return.
 504  *
 505  * Alignment can't be bigger than page size.
 506  *
 507  * Hole are not considered for allocation to keep things simple.
 508  * Assumption is that there won't be hole (all object on same
 509  * alignment).
 510  */
 511 struct radeon_sa_manager {
 512         wait_queue_head_t       wq;
 513         struct radeon_bo        *bo;
 514         struct list_head        *hole;
 515         struct list_head        flist[RADEON_NUM_RINGS];
 516         struct list_head        olist;
 517         unsigned                size;
 518         uint64_t                gpu_addr;
 519         void                    *cpu_ptr;
 520         uint32_t                domain;
 521         uint32_t                align;
 522 };
 523
 524 struct radeon_sa_bo;
 525
 526 /* sub-allocation buffer */
 527 struct radeon_sa_bo {
 528         struct list_head                olist;
 529         struct list_head                flist;
 530         struct radeon_sa_manager        *manager;
 531         unsigned                        soffset;
 532         unsigned                        eoffset;
 533         struct radeon_fence             *fence;
 534 };
 535
 536 /*
 537  * GEM objects.
 538  */
 539 struct radeon_gem {
 540         struct mutex            mutex;
 541         struct list_head        objects;
 542 };
 543
 544 int radeon_gem_init(struct radeon_device *rdev);
 545 void radeon_gem_fini(struct radeon_device *rdev);
 546 int radeon_gem_object_create(struct radeon_device *rdev, int size,
 547                                 int alignment, int initial_domain,
 548                                 bool discardable, bool kernel,
 549                                 struct drm_gem_object **obj);
 550
 551 int radeon_mode_dumb_create(struct drm_file *file_priv,
 552                             struct drm_device *dev,
 553                             struct drm_mode_create_dumb *args);
 554 int radeon_mode_dumb_mmap(struct drm_file *filp,
 555                           struct drm_device *dev,
 556                           uint32_t handle, uint64_t *offset_p);
 557
 558 /*
 559  * Semaphores.
 560  */
 561 struct radeon_semaphore {
 562         struct radeon_sa_bo             *sa_bo;
 563         signed                          waiters;
 564         uint64_t                        gpu_addr;
 565         struct radeon_fence             *sync_to[RADEON_NUM_RINGS];
 566 };
 567
 568 int radeon_semaphore_create(struct radeon_device *rdev,
 569                             struct radeon_semaphore **semaphore);
 570 bool radeon_semaphore_emit_signal(struct radeon_device *rdev, int ring,
 571                                   struct radeon_semaphore *semaphore);
 572 bool radeon_semaphore_emit_wait(struct radeon_device *rdev, int ring,
 573                                 struct radeon_semaphore *semaphore);
 574 void radeon_semaphore_sync_to(struct radeon_semaphore *semaphore,
 575                               struct radeon_fence *fence);
 576 int radeon_semaphore_sync_rings(struct radeon_device *rdev,
 577                                 struct radeon_semaphore *semaphore,
 578                                 int waiting_ring);
 579 void radeon_semaphore_free(struct radeon_device *rdev,
 580                            struct radeon_semaphore **semaphore,
 581                            struct radeon_fence *fence);
 582
 583 /*
 584  * GART structures, functions & helpers
 585  */
 586 struct radeon_mc;
 587
 588 #define RADEON_GPU_PAGE_SIZE 4096
 589 #define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1)
 590 #define RADEON_GPU_PAGE_SHIFT 12
 591 #define RADEON_GPU_PAGE_ALIGN(a) (((a) + RADEON_GPU_PAGE_MASK) & ~RADEON_GPU_PAGE_MASK)
 592
 593 struct radeon_gart {
 594         dma_addr_t                      table_addr;
 595         struct radeon_bo                *robj;
 596         void                            *ptr;
 597         unsigned                        num_gpu_pages;
 598         unsigned                        num_cpu_pages;
 599         unsigned                        table_size;
 600         struct page                     **pages;
 601         dma_addr_t                      *pages_addr;
 602         bool                            ready;
 603 };
 604
 605 int radeon_gart_table_ram_alloc(struct radeon_device *rdev);
 606 void radeon_gart_table_ram_free(struct radeon_device *rdev);
 607 int radeon_gart_table_vram_alloc(struct radeon_device *rdev);
 608 void radeon_gart_table_vram_free(struct radeon_device *rdev);
 609 int radeon_gart_table_vram_pin(struct radeon_device *rdev);
 610 void radeon_gart_table_vram_unpin(struct radeon_device *rdev);
 611 int radeon_gart_init(struct radeon_device *rdev);
 612 void radeon_gart_fini(struct radeon_device *rdev);
 613 void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset,
 614                         int pages);
 615 int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,
 616                      int pages, struct page **pagelist,
 617                      dma_addr_t *dma_addr);
 618 void radeon_gart_restore(struct radeon_device *rdev);
 619
 620
 621 /*
 622  * GPU MC structures, functions & helpers
 623  */
 624 struct radeon_mc {
 625         resource_size_t         aper_size;
 626         resource_size_t         aper_base;
 627         resource_size_t         agp_base;
 628         /* for some chips with <= 32MB we need to lie
 629          * about vram size near mc fb location */
 630         u64                     mc_vram_size;
 631         u64                     visible_vram_size;
 632         u64                     gtt_size;
 633         u64                     gtt_start;
 634         u64                     gtt_end;
 635         u64                     vram_start;
 636         u64                     vram_end;
 637         unsigned                vram_width;
 638         u64                     real_vram_size;
 639         int                     vram_mtrr;
 640         bool                    vram_is_ddr;
 641         bool                    igp_sideport_enabled;
 642         u64                     gtt_base_align;
 643         u64                     mc_mask;
 644 };
 645
 646 bool radeon_combios_sideport_present(struct radeon_device *rdev);
 647 bool radeon_atombios_sideport_present(struct radeon_device *rdev);
 648
 649 /*
 650  * GPU scratch registers structures, functions & helpers
 651  */
 652 struct radeon_scratch {
 653         unsigned                num_reg;
 654         uint32_t                reg_base;
 655         bool                    free[32];
 656         uint32_t                reg[32];
 657 };
 658
 659 int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg);
 660 void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg);
 661
 662 /*
 663  * GPU doorbell structures, functions & helpers
 664  */
 665 #define RADEON_MAX_DOORBELLS 1024       /* Reserve at most 1024 doorbell slots for radeon-owned rings. */
 666
 667 struct radeon_doorbell {
 668         /* doorbell mmio */
 669         resource_size_t         base;
 670         resource_size_t         size;
 671         u32 __iomem             *ptr;
 672         u32                     num_doorbells;  /* Number of doorbells actually reserved for radeon. */
 673         unsigned long           used[DIV_ROUND_UP(RADEON_MAX_DOORBELLS, BITS_PER_LONG)];
 674 };
 675
 676 int radeon_doorbell_get(struct radeon_device *rdev, u32 *page);
 677 void radeon_doorbell_free(struct radeon_device *rdev, u32 doorbell);
 678
 679 /*
 680  * IRQS.
 681  */
 682
 683 struct radeon_flip_work {
 684         struct work_struct              flip_work;
 685         struct work_struct              unpin_work;
 686         struct radeon_device            *rdev;
 687         int                             crtc_id;
 688         uint64_t                        base;
 689         struct drm_pending_vblank_event *event;
 690         struct radeon_bo                *old_rbo;
 691         struct radeon_fence             *fence;
 692 };
 693
 694 struct r500_irq_stat_regs {
 695         u32 disp_int;
 696         u32 hdmi0_status;
 697 };
 698
 699 struct r600_irq_stat_regs {
 700         u32 disp_int;
 701         u32 disp_int_cont;
 702         u32 disp_int_cont2;
 703         u32 d1grph_int;
 704         u32 d2grph_int;
 705         u32 hdmi0_status;
 706         u32 hdmi1_status;
 707 };
 708
 709 struct evergreen_irq_stat_regs {
 710         u32 disp_int;
 711         u32 disp_int_cont;
 712         u32 disp_int_cont2;
 713         u32 disp_int_cont3;
 714         u32 disp_int_cont4;
 715         u32 disp_int_cont5;
 716         u32 d1grph_int;
 717         u32 d2grph_int;
 718         u32 d3grph_int;
 719         u32 d4grph_int;
 720         u32 d5grph_int;
 721         u32 d6grph_int;
 722         u32 afmt_status1;
 723         u32 afmt_status2;
 724         u32 afmt_status3;
 725         u32 afmt_status4;
 726         u32 afmt_status5;
 727         u32 afmt_status6;
 728 };
 729
 730 struct cik_irq_stat_regs {
 731         u32 disp_int;
 732         u32 disp_int_cont;
 733         u32 disp_int_cont2;
 734         u32 disp_int_cont3;
 735         u32 disp_int_cont4;
 736         u32 disp_int_cont5;
 737         u32 disp_int_cont6;
 738         u32 d1grph_int;
 739         u32 d2grph_int;
 740         u32 d3grph_int;
 741         u32 d4grph_int;
 742         u32 d5grph_int;
 743         u32 d6grph_int;
 744 };
 745
 746 union radeon_irq_stat_regs {
 747         struct r500_irq_stat_regs r500;
 748         struct r600_irq_stat_regs r600;
 749         struct evergreen_irq_stat_regs evergreen;
 750         struct cik_irq_stat_regs cik;
 751 };
 752
 753 struct radeon_irq {
 754         bool                            installed;
 755         spinlock_t                      lock;
 756         atomic_t                        ring_int[RADEON_NUM_RINGS];
 757         bool                            crtc_vblank_int[RADEON_MAX_CRTCS];
 758         atomic_t                        pflip[RADEON_MAX_CRTCS];
 759         wait_queue_head_t               vblank_queue;
 760         bool                            hpd[RADEON_MAX_HPD_PINS];
 761         bool                            afmt[RADEON_MAX_AFMT_BLOCKS];
 762         union radeon_irq_stat_regs      stat_regs;
 763         bool                            dpm_thermal;
 764 };
 765
 766 int radeon_irq_kms_init(struct radeon_device *rdev);
 767 void radeon_irq_kms_fini(struct radeon_device *rdev);
 768 void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev, int ring);
 769 void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev, int ring);
 770 void radeon_irq_kms_pflip_irq_get(struct radeon_device *rdev, int crtc);
 771 void radeon_irq_kms_pflip_irq_put(struct radeon_device *rdev, int crtc);
 772 void radeon_irq_kms_enable_afmt(struct radeon_device *rdev, int block);
 773 void radeon_irq_kms_disable_afmt(struct radeon_device *rdev, int block);
 774 void radeon_irq_kms_enable_hpd(struct radeon_device *rdev, unsigned hpd_mask);
 775 void radeon_irq_kms_disable_hpd(struct radeon_device *rdev, unsigned hpd_mask);
 776
 777 /*
 778  * CP & rings.
 779  */
 780
 781 struct radeon_ib {
 782         struct radeon_sa_bo             *sa_bo;
 783         uint32_t                        length_dw;
 784         uint64_t                        gpu_addr;
 785         uint32_t                        *ptr;
 786         int                             ring;
 787         struct radeon_fence             *fence;
 788         struct radeon_vm                *vm;
 789         bool                            is_const_ib;
 790         struct radeon_semaphore         *semaphore;
 791 };
 792
 793 struct radeon_ring {
 794         struct radeon_bo        *ring_obj;
 795         volatile uint32_t       *ring;
 796         unsigned                rptr_offs;
 797         unsigned                rptr_save_reg;
 798         u64                     next_rptr_gpu_addr;
 799         volatile u32            *next_rptr_cpu_addr;
 800         unsigned                wptr;
 801         unsigned                wptr_old;
 802         unsigned                ring_size;
 803         unsigned                ring_free_dw;
 804         int                     count_dw;
 805         atomic_t                last_rptr;
 806         atomic64_t              last_activity;
 807         uint64_t                gpu_addr;
 808         uint32_t                align_mask;
 809         uint32_t                ptr_mask;
 810         bool                    ready;
 811         u32                     nop;
 812         u32                     idx;
 813         u64                     last_semaphore_signal_addr;
 814         u64                     last_semaphore_wait_addr;
 815         /* for CIK queues */
 816         u32 me;
 817         u32 pipe;
 818         u32 queue;
 819         struct radeon_bo        *mqd_obj;
 820         u32 doorbell_index;
 821         unsigned                wptr_offs;
 822 };
 823
 824 struct radeon_mec {
 825         struct radeon_bo        *hpd_eop_obj;
 826         u64                     hpd_eop_gpu_addr;
 827         u32 num_pipe;
 828         u32 num_mec;
 829         u32 num_queue;
 830 };
 831
 832 /*
 833  * VM
 834  */
 835
 836 /* maximum number of VMIDs */
 837 #define RADEON_NUM_VM   16
 838
 839 /* number of entries in page table */
 840 #define RADEON_VM_PTE_COUNT (1 << radeon_vm_block_size)
 841
 842 /* PTBs (Page Table Blocks) need to be aligned to 32K */
 843 #define RADEON_VM_PTB_ALIGN_SIZE   32768
 844 #define RADEON_VM_PTB_ALIGN_MASK (RADEON_VM_PTB_ALIGN_SIZE - 1)
 845 #define RADEON_VM_PTB_ALIGN(a) (((a) + RADEON_VM_PTB_ALIGN_MASK) & ~RADEON_VM_PTB_ALIGN_MASK)
 846
 847 #define R600_PTE_VALID          (1 << 0)
 848 #define R600_PTE_SYSTEM         (1 << 1)
 849 #define R600_PTE_SNOOPED        (1 << 2)
 850 #define R600_PTE_READABLE       (1 << 5)
 851 #define R600_PTE_WRITEABLE      (1 << 6)
 852
 853 /* PTE (Page Table Entry) fragment field for different page sizes */
 854 #define R600_PTE_FRAG_4KB       (0 << 7)
 855 #define R600_PTE_FRAG_64KB      (4 << 7)
 856 #define R600_PTE_FRAG_256KB     (6 << 7)
 857
 858 /* flags used for GART page table entries on R600+ */
 859 #define R600_PTE_GART   ( R600_PTE_VALID | R600_PTE_SYSTEM | R600_PTE_SNOOPED \
 860                         | R600_PTE_READABLE | R600_PTE_WRITEABLE)
 861
 862 struct radeon_vm_pt {
 863         struct radeon_bo                *bo;
 864         uint64_t                        addr;
 865 };
 866
 867 struct radeon_vm {
 868         struct list_head                va;
 869         unsigned                        id;
 870
 871         /* BOs freed, but not yet updated in the PT */
 872         struct list_head                freed;
 873
 874         /* contains the page directory */
 875         struct radeon_bo                *page_directory;
 876         uint64_t                        pd_gpu_addr;
 877         unsigned                        max_pde_used;
 878
 879         /* array of page tables, one for each page directory entry */
 880         struct radeon_vm_pt             *page_tables;
 881
 882         struct radeon_bo_va             *ib_bo_va;
 883
 884         struct mutex                    mutex;
 885         /* last fence for cs using this vm */
 886         struct radeon_fence             *fence;
 887         /* last flush or NULL if we still need to flush */
 888         struct radeon_fence             *last_flush;
 889         /* last use of vmid */
 890         struct radeon_fence             *last_id_use;
 891 };
 892
 893 struct radeon_vm_manager {
 894         struct radeon_fence             *active[RADEON_NUM_VM];
 895         uint32_t                        max_pfn;
 896         /* number of VMIDs */
 897         unsigned                        nvm;
 898         /* vram base address for page table entry  */
 899         u64                             vram_base_offset;
 900         /* is vm enabled? */
 901         bool                            enabled;
 902 };
 903
 904 /*
 905  * file private structure
 906  */
 907 struct radeon_fpriv {
 908         struct radeon_vm                vm;
 909 };
 910
 911 /*
 912  * R6xx+ IH ring
 913  */
 914 struct r600_ih {
 915         struct radeon_bo        *ring_obj;
 916         volatile uint32_t       *ring;
 917         unsigned                rptr;
 918         unsigned                ring_size;
 919         uint64_t                gpu_addr;
 920         uint32_t                ptr_mask;
 921         atomic_t                lock;
 922         bool                    enabled;
 923 };
 924
 925 /*
 926  * RLC stuff
 927  */
 928 #include "clearstate_defs.h"
 929
 930 struct radeon_rlc {
 931         /* for power gating */
 932         struct radeon_bo        *save_restore_obj;
 933         uint64_t                save_restore_gpu_addr;
 934         volatile uint32_t       *sr_ptr;
 935         const u32               *reg_list;
 936         u32                     reg_list_size;
 937         /* for clear state */
 938         struct radeon_bo        *clear_state_obj;
 939         uint64_t                clear_state_gpu_addr;
 940         volatile uint32_t       *cs_ptr;
 941         const struct cs_section_def   *cs_data;
 942         u32                     clear_state_size;
 943         /* for cp tables */
 944         struct radeon_bo        *cp_table_obj;
 945         uint64_t                cp_table_gpu_addr;
 946         volatile uint32_t       *cp_table_ptr;
 947         u32                     cp_table_size;
 948 };
 949
 950 int radeon_ib_get(struct radeon_device *rdev, int ring,
 951                   struct radeon_ib *ib, struct radeon_vm *vm,
 952                   unsigned size);
 953 void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib *ib);
 954 int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib,
 955                        struct radeon_ib *const_ib);
 956 int radeon_ib_pool_init(struct radeon_device *rdev);
 957 void radeon_ib_pool_fini(struct radeon_device *rdev);
 958 int radeon_ib_ring_tests(struct radeon_device *rdev);
 959 /* Ring access between begin & end cannot sleep */
 960 bool radeon_ring_supports_scratch_reg(struct radeon_device *rdev,
 961                                       struct radeon_ring *ring);
 962 void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_ring *cp);
 963 int radeon_ring_alloc(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
 964 int radeon_ring_lock(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
 965 void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *cp);
 966 void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_ring *cp);
 967 void radeon_ring_undo(struct radeon_ring *ring);
 968 void radeon_ring_unlock_undo(struct radeon_device *rdev, struct radeon_ring *cp);
 969 int radeon_ring_test(struct radeon_device *rdev, struct radeon_ring *cp);
 970 void radeon_ring_lockup_update(struct radeon_device *rdev,
 971                                struct radeon_ring *ring);
 972 bool radeon_ring_test_lockup(struct radeon_device *rdev, struct radeon_ring *ring);
 973 unsigned radeon_ring_backup(struct radeon_device *rdev, struct radeon_ring *ring,
 974                             uint32_t **data);
 975 int radeon_ring_restore(struct radeon_device *rdev, struct radeon_ring *ring,
 976                         unsigned size, uint32_t *data);
 977 int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ring_size,
 978                      unsigned rptr_offs, u32 nop);
 979 void radeon_ring_fini(struct radeon_device *rdev, struct radeon_ring *cp);
 980
 981
 982 /* r600 async dma */
 983 void r600_dma_stop(struct radeon_device *rdev);
 984 int r600_dma_resume(struct radeon_device *rdev);
 985 void r600_dma_fini(struct radeon_device *rdev);
 986
 987 void cayman_dma_stop(struct radeon_device *rdev);
 988 int cayman_dma_resume(struct radeon_device *rdev);
 989 void cayman_dma_fini(struct radeon_device *rdev);
 990
 991 /*
 992  * CS.
 993  */
 994 struct radeon_cs_reloc {
 995         struct drm_gem_object           *gobj;
 996         struct radeon_bo                *robj;
 997         struct ttm_validate_buffer      tv;
 998         uint64_t                        gpu_offset;
 999         unsigned                        prefered_domains;
1000         unsigned                        allowed_domains;
1001         uint32_t                        tiling_flags;
1002         uint32_t                        handle;
1003 };
1004
1005 struct radeon_cs_chunk {
1006         uint32_t                chunk_id;
1007         uint32_t                length_dw;
1008         uint32_t                *kdata;
1009         void __user             *user_ptr;
1010 };
1011
1012 struct radeon_cs_parser {
1013         struct device           *dev;
1014         struct radeon_device    *rdev;
1015         struct drm_file         *filp;
1016         /* chunks */
1017         unsigned                nchunks;
1018         struct radeon_cs_chunk  *chunks;
1019         uint64_t                *chunks_array;
1020         /* IB */
1021         unsigned                idx;
1022         /* relocations */
1023         unsigned                nrelocs;
1024         struct radeon_cs_reloc  *relocs;
1025         struct radeon_cs_reloc  **relocs_ptr;
1026         struct radeon_cs_reloc  *vm_bos;
1027         struct list_head        validated;
1028         unsigned                dma_reloc_idx;
1029         /* indices of various chunks */
1030         int                     chunk_ib_idx;
1031         int                     chunk_relocs_idx;
1032         int                     chunk_flags_idx;
1033         int                     chunk_const_ib_idx;
1034         struct radeon_ib        ib;
1035         struct radeon_ib        const_ib;
1036         void                    *track;
1037         unsigned                family;
1038         int                     parser_error;
1039         u32                     cs_flags;
1040         u32                     ring;
1041         s32                     priority;
1042         struct ww_acquire_ctx   ticket;
1043 };
1044
1045 static inline u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx)
1046 {
1047         struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx];
1048
1049         if (ibc->kdata)
1050                 return ibc->kdata[idx];
1051         return p->ib.ptr[idx];
1052 }
1053
1054
1055 struct radeon_cs_packet {
1056         unsigned        idx;
1057         unsigned        type;
1058         unsigned        reg;
1059         unsigned        opcode;
1060         int             count;
1061         unsigned        one_reg_wr;
1062 };
1063
1064 typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p,
1065                                       struct radeon_cs_packet *pkt,
1066                                       unsigned idx, unsigned reg);
1067 typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p,
1068                                       struct radeon_cs_packet *pkt);
1069
1070
1071 /*
1072  * AGP
1073  */
1074 int radeon_agp_init(struct radeon_device *rdev);
1075 void radeon_agp_resume(struct radeon_device *rdev);
1076 void radeon_agp_suspend(struct radeon_device *rdev);
1077 void radeon_agp_fini(struct radeon_device *rdev);
1078
1079
1080 /*
1081  * Writeback
1082  */
1083 struct radeon_wb {
1084         struct radeon_bo        *wb_obj;
1085         volatile uint32_t       *wb;
1086         uint64_t                gpu_addr;
1087         bool                    enabled;
1088         bool                    use_event;
1089 };
1090
1091 #define RADEON_WB_SCRATCH_OFFSET 0
1092 #define RADEON_WB_RING0_NEXT_RPTR 256
1093 #define RADEON_WB_CP_RPTR_OFFSET 1024
1094 #define RADEON_WB_CP1_RPTR_OFFSET 1280
1095 #define RADEON_WB_CP2_RPTR_OFFSET 1536
1096 #define R600_WB_DMA_RPTR_OFFSET   1792
1097 #define R600_WB_IH_WPTR_OFFSET   2048
1098 #define CAYMAN_WB_DMA1_RPTR_OFFSET   2304
1099 #define R600_WB_EVENT_OFFSET     3072
1100 #define CIK_WB_CP1_WPTR_OFFSET     3328
1101 #define CIK_WB_CP2_WPTR_OFFSET     3584
1102
1103 /**
1104  * struct radeon_pm - power management datas
1105  * @max_bandwidth:      maximum bandwidth the gpu has (MByte/s)
1106  * @igp_sideport_mclk:  sideport memory clock Mhz (rs690,rs740,rs780,rs880)
1107  * @igp_system_mclk:    system clock Mhz (rs690,rs740,rs780,rs880)
1108  * @igp_ht_link_clk:    ht link clock Mhz (rs690,rs740,rs780,rs880)
1109  * @igp_ht_link_width:  ht link width in bits (rs690,rs740,rs780,rs880)
1110  * @k8_bandwidth:       k8 bandwidth the gpu has (MByte/s) (IGP)
1111  * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP)
1112  * @ht_bandwidth:       ht bandwidth the gpu has (MByte/s) (IGP)
1113  * @core_bandwidth:     core GPU bandwidth the gpu has (MByte/s) (IGP)
1114  * @sclk:               GPU clock Mhz (core bandwidth depends of this clock)
1115  * @needed_bandwidth:   current bandwidth needs
1116  *
1117  * It keeps track of various data needed to take powermanagement decision.
1118  * Bandwidth need is used to determine minimun clock of the GPU and memory.
1119  * Equation between gpu/memory clock and available bandwidth is hw dependent
1120  * (type of memory, bus size, efficiency, ...)
1121  */
1122
1123 enum radeon_pm_method {
1124         PM_METHOD_PROFILE,
1125         PM_METHOD_DYNPM,
1126         PM_METHOD_DPM,
1127 };
1128
1129 enum radeon_dynpm_state {
1130         DYNPM_STATE_DISABLED,
1131         DYNPM_STATE_MINIMUM,
1132         DYNPM_STATE_PAUSED,
1133         DYNPM_STATE_ACTIVE,
1134         DYNPM_STATE_SUSPENDED,
1135 };
1136 enum radeon_dynpm_action {
1137         DYNPM_ACTION_NONE,
1138         DYNPM_ACTION_MINIMUM,
1139         DYNPM_ACTION_DOWNCLOCK,
1140         DYNPM_ACTION_UPCLOCK,
1141         DYNPM_ACTION_DEFAULT
1142 };
1143
1144 enum radeon_voltage_type {
1145         VOLTAGE_NONE = 0,
1146         VOLTAGE_GPIO,
1147         VOLTAGE_VDDC,
1148         VOLTAGE_SW
1149 };
1150
1151 enum radeon_pm_state_type {
1152         /* not used for dpm */
1153         POWER_STATE_TYPE_DEFAULT,
1154         POWER_STATE_TYPE_POWERSAVE,
1155         /* user selectable states */
1156         POWER_STATE_TYPE_BATTERY,
1157         POWER_STATE_TYPE_BALANCED,
1158         POWER_STATE_TYPE_PERFORMANCE,
1159         /* internal states */
1160         POWER_STATE_TYPE_INTERNAL_UVD,
1161         POWER_STATE_TYPE_INTERNAL_UVD_SD,
1162         POWER_STATE_TYPE_INTERNAL_UVD_HD,
1163         POWER_STATE_TYPE_INTERNAL_UVD_HD2,
1164         POWER_STATE_TYPE_INTERNAL_UVD_MVC,
1165         POWER_STATE_TYPE_INTERNAL_BOOT,
1166         POWER_STATE_TYPE_INTERNAL_THERMAL,
1167         POWER_STATE_TYPE_INTERNAL_ACPI,
1168         POWER_STATE_TYPE_INTERNAL_ULV,
1169         POWER_STATE_TYPE_INTERNAL_3DPERF,
1170 };
1171
1172 enum radeon_pm_profile_type {
1173         PM_PROFILE_DEFAULT,
1174         PM_PROFILE_AUTO,
1175         PM_PROFILE_LOW,
1176         PM_PROFILE_MID,
1177         PM_PROFILE_HIGH,
1178 };
1179
1180 #define PM_PROFILE_DEFAULT_IDX 0
1181 #define PM_PROFILE_LOW_SH_IDX  1
1182 #define PM_PROFILE_MID_SH_IDX  2
1183 #define PM_PROFILE_HIGH_SH_IDX 3
1184 #define PM_PROFILE_LOW_MH_IDX  4
1185 #define PM_PROFILE_MID_MH_IDX  5
1186 #define PM_PROFILE_HIGH_MH_IDX 6
1187 #define PM_PROFILE_MAX         7
1188
1189 struct radeon_pm_profile {
1190         int dpms_off_ps_idx;
1191         int dpms_on_ps_idx;
1192         int dpms_off_cm_idx;
1193         int dpms_on_cm_idx;
1194 };
1195
1196 enum radeon_int_thermal_type {
1197         THERMAL_TYPE_NONE,
1198         THERMAL_TYPE_EXTERNAL,
1199         THERMAL_TYPE_EXTERNAL_GPIO,
1200         THERMAL_TYPE_RV6XX,
1201         THERMAL_TYPE_RV770,
1202         THERMAL_TYPE_ADT7473_WITH_INTERNAL,
1203         THERMAL_TYPE_EVERGREEN,
1204         THERMAL_TYPE_SUMO,
1205         THERMAL_TYPE_NI,
1206         THERMAL_TYPE_SI,
1207         THERMAL_TYPE_EMC2103_WITH_INTERNAL,
1208         THERMAL_TYPE_CI,
1209         THERMAL_TYPE_KV,
1210 };
1211
1212 struct radeon_voltage {
1213         enum radeon_voltage_type type;
1214         /* gpio voltage */
1215         struct radeon_gpio_rec gpio;
1216         u32 delay; /* delay in usec from voltage drop to sclk change */
1217         bool active_high; /* voltage drop is active when bit is high */
1218         /* VDDC voltage */
1219         u8 vddc_id; /* index into vddc voltage table */
1220         u8 vddci_id; /* index into vddci voltage table */
1221         bool vddci_enabled;
1222         /* r6xx+ sw */
1223         u16 voltage;
1224         /* evergreen+ vddci */
1225         u16 vddci;
1226 };
1227
1228 /* clock mode flags */
1229 #define RADEON_PM_MODE_NO_DISPLAY          (1 << 0)
1230
1231 struct radeon_pm_clock_info {
1232         /* memory clock */
1233         u32 mclk;
1234         /* engine clock */
1235         u32 sclk;
1236         /* voltage info */
1237         struct radeon_voltage voltage;
1238         /* standardized clock flags */
1239         u32 flags;
1240 };
1241
1242 /* state flags */
1243 #define RADEON_PM_STATE_SINGLE_DISPLAY_ONLY (1 << 0)
1244
1245 struct radeon_power_state {
1246         enum radeon_pm_state_type type;
1247         struct radeon_pm_clock_info *clock_info;
1248         /* number of valid clock modes in this power state */
1249         int num_clock_modes;
1250         struct radeon_pm_clock_info *default_clock_mode;
1251         /* standardized state flags */
1252         u32 flags;
1253         u32 misc; /* vbios specific flags */
1254         u32 misc2; /* vbios specific flags */
1255         int pcie_lanes; /* pcie lanes */
1256 };
1257
1258 /*
1259  * Some modes are overclocked by very low value, accept them
1260  */
1261 #define RADEON_MODE_OVERCLOCK_MARGIN 500 /* 5 MHz */
1262
1263 enum radeon_dpm_auto_throttle_src {
1264         RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL,
1265         RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL
1266 };
1267
1268 enum radeon_dpm_event_src {
1269         RADEON_DPM_EVENT_SRC_ANALOG = 0,
1270         RADEON_DPM_EVENT_SRC_EXTERNAL = 1,
1271         RADEON_DPM_EVENT_SRC_DIGITAL = 2,
1272         RADEON_DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3,
1273         RADEON_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL = 4
1274 };
1275
1276 #define RADEON_MAX_VCE_LEVELS 6
1277
1278 enum radeon_vce_level {
1279         RADEON_VCE_LEVEL_AC_ALL = 0,     /* AC, All cases */
1280         RADEON_VCE_LEVEL_DC_EE = 1,      /* DC, entropy encoding */
1281         RADEON_VCE_LEVEL_DC_LL_LOW = 2,  /* DC, low latency queue, res <= 720 */
1282         RADEON_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */
1283         RADEON_VCE_LEVEL_DC_GP_LOW = 4,  /* DC, general purpose queue, res <= 720 */
1284         RADEON_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */
1285 };
1286
1287 struct radeon_ps {
1288         u32 caps; /* vbios flags */
1289         u32 class; /* vbios flags */
1290         u32 class2; /* vbios flags */
1291         /* UVD clocks */
1292         u32 vclk;
1293         u32 dclk;
1294         /* VCE clocks */
1295         u32 evclk;
1296         u32 ecclk;
1297         bool vce_active;
1298         enum radeon_vce_level vce_level;
1299         /* asic priv */
1300         void *ps_priv;
1301 };
1302
1303 struct radeon_dpm_thermal {
1304         /* thermal interrupt work */
1305         struct work_struct work;
1306         /* low temperature threshold */
1307         int                min_temp;
1308         /* high temperature threshold */
1309         int                max_temp;
1310         /* was interrupt low to high or high to low */
1311         bool               high_to_low;
1312 };
1313
1314 enum radeon_clk_action
1315 {
1316         RADEON_SCLK_UP = 1,
1317         RADEON_SCLK_DOWN
1318 };
1319
1320 struct radeon_blacklist_clocks
1321 {
1322         u32 sclk;
1323         u32 mclk;
1324         enum radeon_clk_action action;
1325 };
1326
1327 struct radeon_clock_and_voltage_limits {
1328         u32 sclk;
1329         u32 mclk;
1330         u16 vddc;
1331         u16 vddci;
1332 };
1333
1334 struct radeon_clock_array {
1335         u32 count;
1336         u32 *values;
1337 };
1338
1339 struct radeon_clock_voltage_dependency_entry {
1340         u32 clk;
1341         u16 v;
1342 };
1343
1344 struct radeon_clock_voltage_dependency_table {
1345         u32 count;
1346         struct radeon_clock_voltage_dependency_entry *entries;
1347 };
1348
1349 union radeon_cac_leakage_entry {
1350         struct {
1351                 u16 vddc;
1352                 u32 leakage;
1353         };
1354         struct {
1355                 u16 vddc1;
1356                 u16 vddc2;
1357                 u16 vddc3;
1358         };
1359 };
1360
1361 struct radeon_cac_leakage_table {
1362         u32 count;
1363         union radeon_cac_leakage_entry *entries;
1364 };
1365
1366 struct radeon_phase_shedding_limits_entry {
1367         u16 voltage;
1368         u32 sclk;
1369         u32 mclk;
1370 };
1371
1372 struct radeon_phase_shedding_limits_table {
1373         u32 count;
1374         struct radeon_phase_shedding_limits_entry *entries;
1375 };
1376
1377 struct radeon_uvd_clock_voltage_dependency_entry {
1378         u32 vclk;
1379         u32 dclk;
1380         u16 v;
1381 };
1382
1383 struct radeon_uvd_clock_voltage_dependency_table {
1384         u8 count;
1385         struct radeon_uvd_clock_voltage_dependency_entry *entries;
1386 };
1387
1388 struct radeon_vce_clock_voltage_dependency_entry {
1389         u32 ecclk;
1390         u32 evclk;
1391         u16 v;
1392 };
1393
1394 struct radeon_vce_clock_voltage_dependency_table {
1395         u8 count;
1396         struct radeon_vce_clock_voltage_dependency_entry *entries;
1397 };
1398
1399 struct radeon_ppm_table {
1400         u8 ppm_design;
1401         u16 cpu_core_number;
1402         u32 platform_tdp;
1403         u32 small_ac_platform_tdp;
1404         u32 platform_tdc;
1405         u32 small_ac_platform_tdc;
1406         u32 apu_tdp;
1407         u32 dgpu_tdp;
1408         u32 dgpu_ulv_power;
1409         u32 tj_max;
1410 };
1411
1412 struct radeon_cac_tdp_table {
1413         u16 tdp;
1414         u16 configurable_tdp;
1415         u16 tdc;
1416         u16 battery_power_limit;
1417         u16 small_power_limit;
1418         u16 low_cac_leakage;
1419         u16 high_cac_leakage;
1420         u16 maximum_power_delivery_limit;
1421 };
1422
1423 struct radeon_dpm_dynamic_state {
1424         struct radeon_clock_voltage_dependency_table vddc_dependency_on_sclk;
1425         struct radeon_clock_voltage_dependency_table vddci_dependency_on_mclk;
1426         struct radeon_clock_voltage_dependency_table vddc_dependency_on_mclk;
1427         struct radeon_clock_voltage_dependency_table mvdd_dependency_on_mclk;
1428         struct radeon_clock_voltage_dependency_table vddc_dependency_on_dispclk;
1429         struct radeon_uvd_clock_voltage_dependency_table uvd_clock_voltage_dependency_table;
1430         struct radeon_vce_clock_voltage_dependency_table vce_clock_voltage_dependency_table;
1431         struct radeon_clock_voltage_dependency_table samu_clock_voltage_dependency_table;
1432         struct radeon_clock_voltage_dependency_table acp_clock_voltage_dependency_table;
1433         struct radeon_clock_array valid_sclk_values;
1434         struct radeon_clock_array valid_mclk_values;
1435         struct radeon_clock_and_voltage_limits max_clock_voltage_on_dc;
1436         struct radeon_clock_and_voltage_limits max_clock_voltage_on_ac;
1437         u32 mclk_sclk_ratio;
1438         u32 sclk_mclk_delta;
1439         u16 vddc_vddci_delta;
1440         u16 min_vddc_for_pcie_gen2;
1441         struct radeon_cac_leakage_table cac_leakage_table;
1442         struct radeon_phase_shedding_limits_table phase_shedding_limits_table;
1443         struct radeon_ppm_table *ppm_table;
1444         struct radeon_cac_tdp_table *cac_tdp_table;
1445 };
1446
1447 struct radeon_dpm_fan {
1448         u16 t_min;
1449         u16 t_med;
1450         u16 t_high;
1451         u16 pwm_min;
1452         u16 pwm_med;
1453         u16 pwm_high;
1454         u8 t_hyst;
1455         u32 cycle_delay;
1456         u16 t_max;
1457         bool ucode_fan_control;
1458 };
1459
1460 enum radeon_pcie_gen {
1461         RADEON_PCIE_GEN1 = 0,
1462         RADEON_PCIE_GEN2 = 1,
1463         RADEON_PCIE_GEN3 = 2,
1464         RADEON_PCIE_GEN_INVALID = 0xffff
1465 };
1466
1467 enum radeon_dpm_forced_level {
1468         RADEON_DPM_FORCED_LEVEL_AUTO = 0,
1469         RADEON_DPM_FORCED_LEVEL_LOW = 1,
1470         RADEON_DPM_FORCED_LEVEL_HIGH = 2,
1471 };
1472
1473 struct radeon_vce_state {
1474         /* vce clocks */
1475         u32 evclk;
1476         u32 ecclk;
1477         /* gpu clocks */
1478         u32 sclk;
1479         u32 mclk;
1480         u8 clk_idx;
1481         u8 pstate;
1482 };
1483
1484 struct radeon_dpm {
1485         struct radeon_ps        *ps;
1486         /* number of valid power states */
1487         int                     num_ps;
1488         /* current power state that is active */
1489         struct radeon_ps        *current_ps;
1490         /* requested power state */
1491         struct radeon_ps        *requested_ps;
1492         /* boot up power state */
1493         struct radeon_ps        *boot_ps;
1494         /* default uvd power state */
1495         struct radeon_ps        *uvd_ps;
1496         /* vce requirements */
1497         struct radeon_vce_state vce_states[RADEON_MAX_VCE_LEVELS];
1498         enum radeon_vce_level vce_level;
1499         enum radeon_pm_state_type state;
1500         enum radeon_pm_state_type user_state;
1501         u32                     platform_caps;
1502         u32                     voltage_response_time;
1503         u32                     backbias_response_time;
1504         void                    *priv;
1505         u32                     new_active_crtcs;
1506         int                     new_active_crtc_count;
1507         u32                     current_active_crtcs;
1508         int                     current_active_crtc_count;
1509         struct radeon_dpm_dynamic_state dyn_state;
1510         struct radeon_dpm_fan fan;
1511         u32 tdp_limit;
1512         u32 near_tdp_limit;
1513         u32 near_tdp_limit_adjusted;
1514         u32 sq_ramping_threshold;
1515         u32 cac_leakage;
1516         u16 tdp_od_limit;
1517         u32 tdp_adjustment;
1518         u16 load_line_slope;
1519         bool power_control;
1520         bool ac_power;
1521         /* special states active */
1522         bool                    thermal_active;
1523         bool                    uvd_active;
1524         bool                    vce_active;
1525         /* thermal handling */
1526         struct radeon_dpm_thermal thermal;
1527         /* forced levels */
1528         enum radeon_dpm_forced_level forced_level;
1529         /* track UVD streams */
1530         unsigned sd;
1531         unsigned hd;
1532 };
1533
1534 void radeon_dpm_enable_uvd(struct radeon_device *rdev, bool enable);
1535 void radeon_dpm_enable_vce(struct radeon_device *rdev, bool enable);
1536
1537 struct radeon_pm {
1538         struct mutex            mutex;
1539         /* write locked while reprogramming mclk */
1540         struct rw_semaphore     mclk_lock;
1541         u32                     active_crtcs;
1542         int                     active_crtc_count;
1543         int                     req_vblank;
1544         bool                    vblank_sync;
1545         fixed20_12              max_bandwidth;
1546         fixed20_12              igp_sideport_mclk;
1547         fixed20_12              igp_system_mclk;
1548         fixed20_12              igp_ht_link_clk;
1549         fixed20_12              igp_ht_link_width;
1550         fixed20_12              k8_bandwidth;
1551         fixed20_12              sideport_bandwidth;
1552         fixed20_12              ht_bandwidth;
1553         fixed20_12              core_bandwidth;
1554         fixed20_12              sclk;
1555         fixed20_12              mclk;
1556         fixed20_12              needed_bandwidth;
1557         struct radeon_power_state *power_state;
1558         /* number of valid power states */
1559         int                     num_power_states;
1560         int                     current_power_state_index;
1561         int                     current_clock_mode_index;
1562         int                     requested_power_state_index;
1563         int                     requested_clock_mode_index;
1564         int                     default_power_state_index;
1565         u32                     current_sclk;
1566         u32                     current_mclk;
1567         u16                     current_vddc;
1568         u16                     current_vddci;
1569         u32                     default_sclk;
1570         u32                     default_mclk;
1571         u16                     default_vddc;
1572         u16                     default_vddci;
1573         struct radeon_i2c_chan *i2c_bus;
1574         /* selected pm method */
1575         enum radeon_pm_method     pm_method;
1576         /* dynpm power management */
1577         struct delayed_work     dynpm_idle_work;
1578         enum radeon_dynpm_state dynpm_state;
1579         enum radeon_dynpm_action        dynpm_planned_action;
1580         unsigned long           dynpm_action_timeout;
1581         bool                    dynpm_can_upclock;
1582         bool                    dynpm_can_downclock;
1583         /* profile-based power management */
1584         enum radeon_pm_profile_type profile;
1585         int                     profile_index;
1586         struct radeon_pm_profile profiles[PM_PROFILE_MAX];
1587         /* internal thermal controller on rv6xx+ */
1588         enum radeon_int_thermal_type int_thermal_type;
1589         struct device           *int_hwmon_dev;
1590         /* dpm */
1591         bool                    dpm_enabled;
1592         struct radeon_dpm       dpm;
1593 };
1594
1595 int radeon_pm_get_type_index(struct radeon_device *rdev,
1596                              enum radeon_pm_state_type ps_type,
1597                              int instance);
1598 /*
1599  * UVD
1600  */
1601 #define RADEON_MAX_UVD_HANDLES  10
1602 #define RADEON_UVD_STACK_SIZE   (1024*1024)
1603 #define RADEON_UVD_HEAP_SIZE    (1024*1024)
1604
1605 struct radeon_uvd {
1606         struct radeon_bo        *vcpu_bo;
1607         void                    *cpu_addr;
1608         uint64_t                gpu_addr;
1609         void                    *saved_bo;
1610         atomic_t                handles[RADEON_MAX_UVD_HANDLES];
1611         struct drm_file         *filp[RADEON_MAX_UVD_HANDLES];
1612         unsigned                img_size[RADEON_MAX_UVD_HANDLES];
1613         struct delayed_work     idle_work;
1614 };
1615
1616 int radeon_uvd_init(struct radeon_device *rdev);
1617 void radeon_uvd_fini(struct radeon_device *rdev);
1618 int radeon_uvd_suspend(struct radeon_device *rdev);
1619 int radeon_uvd_resume(struct radeon_device *rdev);
1620 int radeon_uvd_get_create_msg(struct radeon_device *rdev, int ring,
1621                               uint32_t handle, struct radeon_fence **fence);
1622 int radeon_uvd_get_destroy_msg(struct radeon_device *rdev, int ring,
1623                                uint32_t handle, struct radeon_fence **fence);
1624 void radeon_uvd_force_into_uvd_segment(struct radeon_bo *rbo);
1625 void radeon_uvd_free_handles(struct radeon_device *rdev,
1626                              struct drm_file *filp);
1627 int radeon_uvd_cs_parse(struct radeon_cs_parser *parser);
1628 void radeon_uvd_note_usage(struct radeon_device *rdev);
1629 int radeon_uvd_calc_upll_dividers(struct radeon_device *rdev,
1630                                   unsigned vclk, unsigned dclk,
1631                                   unsigned vco_min, unsigned vco_max,
1632                                   unsigned fb_factor, unsigned fb_mask,
1633                                   unsigned pd_min, unsigned pd_max,
1634                                   unsigned pd_even,
1635                                   unsigned *optimal_fb_div,
1636                                   unsigned *optimal_vclk_div,
1637                                   unsigned *optimal_dclk_div);
1638 int radeon_uvd_send_upll_ctlreq(struct radeon_device *rdev,
1639                                 unsigned cg_upll_func_cntl);
1640
1641 /*
1642  * VCE
1643  */
1644 #define RADEON_MAX_VCE_HANDLES  16
1645 #define RADEON_VCE_STACK_SIZE   (1024*1024)
1646 #define RADEON_VCE_HEAP_SIZE    (4*1024*1024)
1647
1648 struct radeon_vce {
1649         struct radeon_bo        *vcpu_bo;
1650         uint64_t                gpu_addr;
1651         unsigned                fw_version;
1652         unsigned                fb_version;
1653         atomic_t                handles[RADEON_MAX_VCE_HANDLES];
1654         struct drm_file         *filp[RADEON_MAX_VCE_HANDLES];
1655         unsigned                img_size[RADEON_MAX_VCE_HANDLES];
1656         struct delayed_work     idle_work;
1657 };
1658
1659 int radeon_vce_init(struct radeon_device *rdev);
1660 void radeon_vce_fini(struct radeon_device *rdev);
1661 int radeon_vce_suspend(struct radeon_device *rdev);
1662 int radeon_vce_resume(struct radeon_device *rdev);
1663 int radeon_vce_get_create_msg(struct radeon_device *rdev, int ring,
1664                               uint32_t handle, struct radeon_fence **fence);
1665 int radeon_vce_get_destroy_msg(struct radeon_device *rdev, int ring,
1666                                uint32_t handle, struct radeon_fence **fence);
1667 void radeon_vce_free_handles(struct radeon_device *rdev, struct drm_file *filp);
1668 void radeon_vce_note_usage(struct radeon_device *rdev);
1669 int radeon_vce_cs_reloc(struct radeon_cs_parser *p, int lo, int hi, unsigned size);
1670 int radeon_vce_cs_parse(struct radeon_cs_parser *p);
1671 bool radeon_vce_semaphore_emit(struct radeon_device *rdev,
1672                                struct radeon_ring *ring,
1673                                struct radeon_semaphore *semaphore,
1674                                bool emit_wait);
1675 void radeon_vce_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
1676 void radeon_vce_fence_emit(struct radeon_device *rdev,
1677                            struct radeon_fence *fence);
1678 int radeon_vce_ring_test(struct radeon_device *rdev, struct radeon_ring *ring);
1679 int radeon_vce_ib_test(struct radeon_device *rdev, struct radeon_ring *ring);
1680
1681 struct r600_audio_pin {
1682         int                     channels;
1683         int                     rate;
1684         int                     bits_per_sample;
1685         u8                      status_bits;
1686         u8                      category_code;
1687         u32                     offset;
1688         bool                    connected;
1689         u32                     id;
1690 };
1691
1692 struct r600_audio {
1693         bool enabled;
1694         struct r600_audio_pin pin[RADEON_MAX_AFMT_BLOCKS];
1695         int num_pins;
1696 };
1697
1698 /*
1699  * Benchmarking
1700  */
1701 void radeon_benchmark(struct radeon_device *rdev, int test_number);
1702
1703
1704 /*
1705  * Testing
1706  */
1707 void radeon_test_moves(struct radeon_device *rdev);
1708 void radeon_test_ring_sync(struct radeon_device *rdev,
1709                            struct radeon_ring *cpA,
1710                            struct radeon_ring *cpB);
1711 void radeon_test_syncing(struct radeon_device *rdev);
1712
1713
1714 /*
1715  * Debugfs
1716  */
1717 struct radeon_debugfs {
1718         struct drm_info_list    *files;
1719         unsigned                num_files;
1720 };
1721
1722 int radeon_debugfs_add_files(struct radeon_device *rdev,
1723                              struct drm_info_list *files,
1724                              unsigned nfiles);
1725 int radeon_debugfs_fence_init(struct radeon_device *rdev);
1726
1727 /*
1728  * ASIC ring specific functions.
1729  */
1730 struct radeon_asic_ring {
1731         /* ring read/write ptr handling */
1732         u32 (*get_rptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1733         u32 (*get_wptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1734         void (*set_wptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1735
1736         /* validating and patching of IBs */
1737         int (*ib_parse)(struct radeon_device *rdev, struct radeon_ib *ib);
1738         int (*cs_parse)(struct radeon_cs_parser *p);
1739
1740         /* command emmit functions */
1741         void (*ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib);
1742         void (*emit_fence)(struct radeon_device *rdev, struct radeon_fence *fence);
1743         bool (*emit_semaphore)(struct radeon_device *rdev, struct radeon_ring *cp,
1744                                struct radeon_semaphore *semaphore, bool emit_wait);
1745         void (*vm_flush)(struct radeon_device *rdev, int ridx, struct radeon_vm *vm);
1746
1747         /* testing functions */
1748         int (*ring_test)(struct radeon_device *rdev, struct radeon_ring *cp);
1749         int (*ib_test)(struct radeon_device *rdev, struct radeon_ring *cp);
1750         bool (*is_lockup)(struct radeon_device *rdev, struct radeon_ring *cp);
1751
1752         /* deprecated */
1753         void (*ring_start)(struct radeon_device *rdev, struct radeon_ring *cp);
1754 };
1755
1756 /*
1757  * ASIC specific functions.
1758  */
1759 struct radeon_asic {
1760         int (*init)(struct radeon_device *rdev);
1761         void (*fini)(struct radeon_device *rdev);
1762         int (*resume)(struct radeon_device *rdev);
1763         int (*suspend)(struct radeon_device *rdev);
1764         void (*vga_set_state)(struct radeon_device *rdev, bool state);
1765         int (*asic_reset)(struct radeon_device *rdev);
1766         /* ioctl hw specific callback. Some hw might want to perform special
1767          * operation on specific ioctl. For instance on wait idle some hw
1768          * might want to perform and HDP flush through MMIO as it seems that
1769          * some R6XX/R7XX hw doesn't take HDP flush into account if programmed
1770          * through ring.
1771          */
1772         void (*ioctl_wait_idle)(struct radeon_device *rdev, struct radeon_bo *bo);
1773         /* check if 3D engine is idle */
1774         bool (*gui_idle)(struct radeon_device *rdev);
1775         /* wait for mc_idle */
1776         int (*mc_wait_for_idle)(struct radeon_device *rdev);
1777         /* get the reference clock */
1778         u32 (*get_xclk)(struct radeon_device *rdev);
1779         /* get the gpu clock counter */
1780         uint64_t (*get_gpu_clock_counter)(struct radeon_device *rdev);
1781         /* gart */
1782         struct {
1783                 void (*tlb_flush)(struct radeon_device *rdev);
1784                 void (*set_page)(struct radeon_device *rdev, unsigned i,
1785                                  uint64_t addr);
1786         } gart;
1787         struct {
1788                 int (*init)(struct radeon_device *rdev);
1789                 void (*fini)(struct radeon_device *rdev);
1790                 void (*set_page)(struct radeon_device *rdev,
1791                                  struct radeon_ib *ib,
1792                                  uint64_t pe,
1793                                  uint64_t addr, unsigned count,
1794                                  uint32_t incr, uint32_t flags);
1795         } vm;
1796         /* ring specific callbacks */
1797         struct radeon_asic_ring *ring[RADEON_NUM_RINGS];
1798         /* irqs */
1799         struct {
1800                 int (*set)(struct radeon_device *rdev);
1801                 int (*process)(struct radeon_device *rdev);
1802         } irq;
1803         /* displays */
1804         struct {
1805                 /* display watermarks */
1806                 void (*bandwidth_update)(struct radeon_device *rdev);
1807                 /* get frame count */
1808                 u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc);
1809                 /* wait for vblank */
1810                 void (*wait_for_vblank)(struct radeon_device *rdev, int crtc);
1811                 /* set backlight level */
1812                 void (*set_backlight_level)(struct radeon_encoder *radeon_encoder, u8 level);
1813                 /* get backlight level */
1814                 u8 (*get_backlight_level)(struct radeon_encoder *radeon_encoder);
1815                 /* audio callbacks */
1816                 void (*hdmi_enable)(struct drm_encoder *encoder, bool enable);
1817                 void (*hdmi_setmode)(struct drm_encoder *encoder, struct drm_display_mode *mode);
1818         } display;
1819         /* copy functions for bo handling */
1820         struct {
1821                 int (*blit)(struct radeon_device *rdev,
1822                             uint64_t src_offset,
1823                             uint64_t dst_offset,
1824                             unsigned num_gpu_pages,
1825                             struct radeon_fence **fence);
1826                 u32 blit_ring_index;
1827                 int (*dma)(struct radeon_device *rdev,
1828                            uint64_t src_offset,
1829                            uint64_t dst_offset,
1830                            unsigned num_gpu_pages,
1831                            struct radeon_fence **fence);
1832                 u32 dma_ring_index;
1833                 /* method used for bo copy */
1834                 int (*copy)(struct radeon_device *rdev,
1835                             uint64_t src_offset,
1836                             uint64_t dst_offset,
1837                             unsigned num_gpu_pages,
1838                             struct radeon_fence **fence);
1839                 /* ring used for bo copies */
1840                 u32 copy_ring_index;
1841         } copy;
1842         /* surfaces */
1843         struct {
1844                 int (*set_reg)(struct radeon_device *rdev, int reg,
1845                                        uint32_t tiling_flags, uint32_t pitch,
1846                                        uint32_t offset, uint32_t obj_size);
1847                 void (*clear_reg)(struct radeon_device *rdev, int reg);
1848         } surface;
1849         /* hotplug detect */
1850         struct {
1851                 void (*init)(struct radeon_device *rdev);
1852                 void (*fini)(struct radeon_device *rdev);
1853                 bool (*sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
1854                 void (*set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
1855         } hpd;
1856         /* static power management */
1857         struct {
1858                 void (*misc)(struct radeon_device *rdev);
1859                 void (*prepare)(struct radeon_device *rdev);
1860                 void (*finish)(struct radeon_device *rdev);
1861                 void (*init_profile)(struct radeon_device *rdev);
1862                 void (*get_dynpm_state)(struct radeon_device *rdev);
1863                 uint32_t (*get_engine_clock)(struct radeon_device *rdev);
1864                 void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock);
1865                 uint32_t (*get_memory_clock)(struct radeon_device *rdev);
1866                 void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock);
1867                 int (*get_pcie_lanes)(struct radeon_device *rdev);
1868                 void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes);
1869                 void (*set_clock_gating)(struct radeon_device *rdev, int enable);
1870                 int (*set_uvd_clocks)(struct radeon_device *rdev, u32 vclk, u32 dclk);
1871                 int (*set_vce_clocks)(struct radeon_device *rdev, u32 evclk, u32 ecclk);
1872                 int (*get_temperature)(struct radeon_device *rdev);
1873         } pm;
1874         /* dynamic power management */
1875         struct {
1876                 int (*init)(struct radeon_device *rdev);
1877                 void (*setup_asic)(struct radeon_device *rdev);
1878                 int (*enable)(struct radeon_device *rdev);
1879                 int (*late_enable)(struct radeon_device *rdev);
1880                 void (*disable)(struct radeon_device *rdev);
1881                 int (*pre_set_power_state)(struct radeon_device *rdev);
1882                 int (*set_power_state)(struct radeon_device *rdev);
1883                 void (*post_set_power_state)(struct radeon_device *rdev);
1884                 void (*display_configuration_changed)(struct radeon_device *rdev);
1885                 void (*fini)(struct radeon_device *rdev);
1886                 u32 (*get_sclk)(struct radeon_device *rdev, bool low);
1887                 u32 (*get_mclk)(struct radeon_device *rdev, bool low);
1888                 void (*print_power_state)(struct radeon_device *rdev, struct radeon_ps *ps);
1889                 void (*debugfs_print_current_performance_level)(struct radeon_device *rdev, struct seq_file *m);
1890                 int (*force_performance_level)(struct radeon_device *rdev, enum radeon_dpm_forced_level level);
1891                 bool (*vblank_too_short)(struct radeon_device *rdev);
1892                 void (*powergate_uvd)(struct radeon_device *rdev, bool gate);
1893                 void (*enable_bapm)(struct radeon_device *rdev, bool enable);
1894         } dpm;
1895         /* pageflipping */
1896         struct {
1897                 void (*page_flip)(struct radeon_device *rdev, int crtc, u64 crtc_base);
1898                 bool (*page_flip_pending)(struct radeon_device *rdev, int crtc);
1899         } pflip;
1900 };
1901
1902 /*
1903  * Asic structures
1904  */
1905 struct r100_asic {
1906         const unsigned          *reg_safe_bm;
1907         unsigned                reg_safe_bm_size;
1908         u32                     hdp_cntl;
1909 };
1910
1911 struct r300_asic {
1912         const unsigned          *reg_safe_bm;
1913         unsigned                reg_safe_bm_size;
1914         u32                     resync_scratch;
1915         u32                     hdp_cntl;
1916 };
1917
1918 struct r600_asic {
1919         unsigned                max_pipes;
1920         unsigned                max_tile_pipes;
1921         unsigned                max_simds;
1922         unsigned                max_backends;
1923         unsigned                max_gprs;
1924         unsigned                max_threads;
1925         unsigned                max_stack_entries;
1926         unsigned                max_hw_contexts;
1927         unsigned                max_gs_threads;
1928         unsigned                sx_max_export_size;
1929         unsigned                sx_max_export_pos_size;
1930         unsigned                sx_max_export_smx_size;
1931         unsigned                sq_num_cf_insts;
1932         unsigned                tiling_nbanks;
1933         unsigned                tiling_npipes;
1934         unsigned                tiling_group_size;
1935         unsigned                tile_config;
1936         unsigned                backend_map;
1937         unsigned                active_simds;
1938 };
1939
1940 struct rv770_asic {
1941         unsigned                max_pipes;
1942         unsigned                max_tile_pipes;
1943         unsigned                max_simds;
1944         unsigned                max_backends;
1945         unsigned                max_gprs;
1946         unsigned                max_threads;
1947         unsigned                max_stack_entries;
1948         unsigned                max_hw_contexts;
1949         unsigned                max_gs_threads;
1950         unsigned                sx_max_export_size;
1951         unsigned                sx_max_export_pos_size;
1952         unsigned                sx_max_export_smx_size;
1953         unsigned                sq_num_cf_insts;
1954         unsigned                sx_num_of_sets;
1955         unsigned                sc_prim_fifo_size;
1956         unsigned                sc_hiz_tile_fifo_size;
1957         unsigned                sc_earlyz_tile_fifo_fize;
1958         unsigned                tiling_nbanks;
1959         unsigned                tiling_npipes;
1960         unsigned                tiling_group_size;
1961         unsigned                tile_config;
1962         unsigned                backend_map;
1963         unsigned                active_simds;
1964 };
1965
1966 struct evergreen_asic {
1967         unsigned num_ses;
1968         unsigned max_pipes;
1969         unsigned max_tile_pipes;
1970         unsigned max_simds;
1971         unsigned max_backends;
1972         unsigned max_gprs;
1973         unsigned max_threads;
1974         unsigned max_stack_entries;
1975         unsigned max_hw_contexts;
1976         unsigned max_gs_threads;
1977         unsigned sx_max_export_size;
1978         unsigned sx_max_export_pos_size;
1979         unsigned sx_max_export_smx_size;
1980         unsigned sq_num_cf_insts;
1981         unsigned sx_num_of_sets;
1982         unsigned sc_prim_fifo_size;
1983         unsigned sc_hiz_tile_fifo_size;
1984         unsigned sc_earlyz_tile_fifo_size;
1985         unsigned tiling_nbanks;
1986         unsigned tiling_npipes;
1987         unsigned tiling_group_size;
1988         unsigned tile_config;
1989         unsigned backend_map;
1990         unsigned active_simds;
1991 };
1992
1993 struct cayman_asic {
1994         unsigned max_shader_engines;
1995         unsigned max_pipes_per_simd;
1996         unsigned max_tile_pipes;
1997         unsigned max_simds_per_se;
1998         unsigned max_backends_per_se;
1999         unsigned max_texture_channel_caches;
2000         unsigned max_gprs;
2001         unsigned max_threads;
2002         unsigned max_gs_threads;
2003         unsigned max_stack_entries;
2004         unsigned sx_num_of_sets;
2005         unsigned sx_max_export_size;
2006         unsigned sx_max_export_pos_size;
2007         unsigned sx_max_export_smx_size;
2008         unsigned max_hw_contexts;
2009         unsigned sq_num_cf_insts;
2010         unsigned sc_prim_fifo_size;
2011         unsigned sc_hiz_tile_fifo_size;
2012         unsigned sc_earlyz_tile_fifo_size;
2013
2014         unsigned num_shader_engines;
2015         unsigned num_shader_pipes_per_simd;
2016         unsigned num_tile_pipes;
2017         unsigned num_simds_per_se;
2018         unsigned num_backends_per_se;
2019         unsigned backend_disable_mask_per_asic;
2020         unsigned backend_map;
2021         unsigned num_texture_channel_caches;
2022         unsigned mem_max_burst_length_bytes;
2023         unsigned mem_row_size_in_kb;
2024         unsigned shader_engine_tile_size;
2025         unsigned num_gpus;
2026         unsigned multi_gpu_tile_size;
2027
2028         unsigned tile_config;
2029         unsigned active_simds;
2030 };
2031
2032 struct si_asic {
2033         unsigned max_shader_engines;
2034         unsigned max_tile_pipes;
2035         unsigned max_cu_per_sh;
2036         unsigned max_sh_per_se;
2037         unsigned max_backends_per_se;
2038         unsigned max_texture_channel_caches;
2039         unsigned max_gprs;
2040         unsigned max_gs_threads;
2041         unsigned max_hw_contexts;
2042         unsigned sc_prim_fifo_size_frontend;
2043         unsigned sc_prim_fifo_size_backend;
2044         unsigned sc_hiz_tile_fifo_size;
2045         unsigned sc_earlyz_tile_fifo_size;
2046
2047         unsigned num_tile_pipes;
2048         unsigned backend_enable_mask;
2049         unsigned backend_disable_mask_per_asic;
2050         unsigned backend_map;
2051         unsigned num_texture_channel_caches;
2052         unsigned mem_max_burst_length_bytes;
2053         unsigned mem_row_size_in_kb;
2054         unsigned shader_engine_tile_size;
2055         unsigned num_gpus;
2056         unsigned multi_gpu_tile_size;
2057
2058         unsigned tile_config;
2059         uint32_t tile_mode_array[32];
2060         uint32_t active_cus;
2061 };
2062
2063 struct cik_asic {
2064         unsigned max_shader_engines;
2065         unsigned max_tile_pipes;
2066         unsigned max_cu_per_sh;
2067         unsigned max_sh_per_se;
2068         unsigned max_backends_per_se;
2069         unsigned max_texture_channel_caches;
2070         unsigned max_gprs;
2071         unsigned max_gs_threads;
2072         unsigned max_hw_contexts;
2073         unsigned sc_prim_fifo_size_frontend;
2074         unsigned sc_prim_fifo_size_backend;
2075         unsigned sc_hiz_tile_fifo_size;
2076         unsigned sc_earlyz_tile_fifo_size;
2077
2078         unsigned num_tile_pipes;
2079         unsigned backend_enable_mask;
2080         unsigned backend_disable_mask_per_asic;
2081         unsigned backend_map;
2082         unsigned num_texture_channel_caches;
2083         unsigned mem_max_burst_length_bytes;
2084         unsigned mem_row_size_in_kb;
2085         unsigned shader_engine_tile_size;
2086         unsigned num_gpus;
2087         unsigned multi_gpu_tile_size;
2088
2089         unsigned tile_config;
2090         uint32_t tile_mode_array[32];
2091         uint32_t macrotile_mode_array[16];
2092         uint32_t active_cus;
2093 };
2094
2095 union radeon_asic_config {
2096         struct r300_asic        r300;
2097         struct r100_asic        r100;
2098         struct r600_asic        r600;
2099         struct rv770_asic       rv770;
2100         struct evergreen_asic   evergreen;
2101         struct cayman_asic      cayman;
2102         struct si_asic          si;
2103         struct cik_asic         cik;
2104 };
2105
2106 /*
2107  * asic initizalization from radeon_asic.c
2108  */
2109 void radeon_agp_disable(struct radeon_device *rdev);
2110 int radeon_asic_init(struct radeon_device *rdev);
2111
2112
2113 /*
2114  * IOCTL.
2115  */
2116 int radeon_gem_info_ioctl(struct drm_device *dev, void *data,
2117                           struct drm_file *filp);
2118 int radeon_gem_create_ioctl(struct drm_device *dev, void *data,
2119                             struct drm_file *filp);
2120 int radeon_gem_pin_ioctl(struct drm_device *dev, void *data,
2121                          struct drm_file *file_priv);
2122 int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data,
2123                            struct drm_file *file_priv);
2124 int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data,
2125                             struct drm_file *file_priv);
2126 int radeon_gem_pread_ioctl(struct drm_device *dev, void *data,
2127                            struct drm_file *file_priv);
2128 int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data,
2129                                 struct drm_file *filp);
2130 int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data,
2131                           struct drm_file *filp);
2132 int radeon_gem_busy_ioctl(struct drm_device *dev, void *data,
2133                           struct drm_file *filp);
2134 int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
2135                               struct drm_file *filp);
2136 int radeon_gem_va_ioctl(struct drm_device *dev, void *data,
2137                           struct drm_file *filp);
2138 int radeon_gem_op_ioctl(struct drm_device *dev, void *data,
2139                         struct drm_file *filp);
2140 int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
2141 int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
2142                                 struct drm_file *filp);
2143 int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
2144                                 struct drm_file *filp);
2145
2146 /* VRAM scratch page for HDP bug, default vram page */
2147 struct r600_vram_scratch {
2148         struct radeon_bo                *robj;
2149         volatile uint32_t               *ptr;
2150         u64                             gpu_addr;
2151 };
2152
2153 /*
2154  * ACPI
2155  */
2156 struct radeon_atif_notification_cfg {
2157         bool enabled;
2158         int command_code;
2159 };
2160
2161 struct radeon_atif_notifications {
2162         bool display_switch;
2163         bool expansion_mode_change;
2164         bool thermal_state;
2165         bool forced_power_state;
2166         bool system_power_state;
2167         bool display_conf_change;
2168         bool px_gfx_switch;
2169         bool brightness_change;
2170         bool dgpu_display_event;
2171 };
2172
2173 struct radeon_atif_functions {
2174         bool system_params;
2175         bool sbios_requests;
2176         bool select_active_disp;
2177         bool lid_state;
2178         bool get_tv_standard;
2179         bool set_tv_standard;
2180         bool get_panel_expansion_mode;
2181         bool set_panel_expansion_mode;
2182         bool temperature_change;
2183         bool graphics_device_types;
2184 };
2185
2186 struct radeon_atif {
2187         struct radeon_atif_notifications notifications;
2188         struct radeon_atif_functions functions;
2189         struct radeon_atif_notification_cfg notification_cfg;
2190         struct radeon_encoder *encoder_for_bl;
2191 };
2192
2193 struct radeon_atcs_functions {
2194         bool get_ext_state;
2195         bool pcie_perf_req;
2196         bool pcie_dev_rdy;
2197         bool pcie_bus_width;
2198 };
2199
2200 struct radeon_atcs {
2201         struct radeon_atcs_functions functions;
2202 };
2203
2204 /*
2205  * Core structure, functions and helpers.
2206  */
2207 typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t);
2208 typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t);
2209
2210 struct radeon_device {
2211         struct device                   *dev;
2212         struct drm_device               *ddev;
2213         struct pci_dev                  *pdev;
2214         struct rw_semaphore             exclusive_lock;
2215         /* ASIC */
2216         union radeon_asic_config        config;
2217         enum radeon_family              family;
2218         unsigned long                   flags;
2219         int                             usec_timeout;
2220         enum radeon_pll_errata          pll_errata;
2221         int                             num_gb_pipes;
2222         int                             num_z_pipes;
2223         int                             disp_priority;
2224         /* BIOS */
2225         uint8_t                         *bios;
2226         bool                            is_atom_bios;
2227         uint16_t                        bios_header_start;
2228         struct radeon_bo                *stollen_vga_memory;
2229         /* Register mmio */
2230         resource_size_t                 rmmio_base;
2231         resource_size_t                 rmmio_size;
2232         /* protects concurrent MM_INDEX/DATA based register access */
2233         spinlock_t mmio_idx_lock;
2234         /* protects concurrent SMC based register access */
2235         spinlock_t smc_idx_lock;
2236         /* protects concurrent PLL register access */
2237         spinlock_t pll_idx_lock;
2238         /* protects concurrent MC register access */
2239         spinlock_t mc_idx_lock;
2240         /* protects concurrent PCIE register access */
2241         spinlock_t pcie_idx_lock;
2242         /* protects concurrent PCIE_PORT register access */
2243         spinlock_t pciep_idx_lock;
2244         /* protects concurrent PIF register access */
2245         spinlock_t pif_idx_lock;
2246         /* protects concurrent CG register access */
2247         spinlock_t cg_idx_lock;
2248         /* protects concurrent UVD register access */
2249         spinlock_t uvd_idx_lock;
2250         /* protects concurrent RCU register access */
2251         spinlock_t rcu_idx_lock;
2252         /* protects concurrent DIDT register access */
2253         spinlock_t didt_idx_lock;
2254         /* protects concurrent ENDPOINT (audio) register access */
2255         spinlock_t end_idx_lock;
2256         void __iomem                    *rmmio;
2257         radeon_rreg_t                   mc_rreg;
2258         radeon_wreg_t                   mc_wreg;
2259         radeon_rreg_t                   pll_rreg;
2260         radeon_wreg_t                   pll_wreg;
2261         uint32_t                        pcie_reg_mask;
2262         radeon_rreg_t                   pciep_rreg;
2263         radeon_wreg_t                   pciep_wreg;
2264         /* io port */
2265         void __iomem                    *rio_mem;
2266         resource_size_t                 rio_mem_size;
2267         struct radeon_clock             clock;
2268         struct radeon_mc                mc;
2269         struct radeon_gart              gart;
2270         struct radeon_mode_info         mode_info;
2271         struct radeon_scratch           scratch;
2272         struct radeon_doorbell          doorbell;
2273         struct radeon_mman              mman;
2274         struct radeon_fence_driver      fence_drv[RADEON_NUM_RINGS];
2275         wait_queue_head_t               fence_queue;
2276         struct mutex                    ring_lock;
2277         struct radeon_ring              ring[RADEON_NUM_RINGS];
2278         bool                            ib_pool_ready;
2279         struct radeon_sa_manager        ring_tmp_bo;
2280         struct radeon_irq               irq;
2281         struct radeon_asic              *asic;
2282         struct radeon_gem               gem;
2283         struct radeon_pm                pm;
2284         struct radeon_uvd               uvd;
2285         struct radeon_vce               vce;
2286         uint32_t                        bios_scratch[RADEON_BIOS_NUM_SCRATCH];
2287         struct radeon_wb                wb;
2288         struct radeon_dummy_page        dummy_page;
2289         bool                            shutdown;
2290         bool                            suspend;
2291         bool                            need_dma32;
2292         bool                            accel_working;
2293         bool                            fastfb_working; /* IGP feature*/
2294         bool                            needs_reset;
2295         struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES];
2296         const struct firmware *me_fw;   /* all family ME firmware */
2297         const struct firmware *pfp_fw;  /* r6/700 PFP firmware */
2298         const struct firmware *rlc_fw;  /* r6/700 RLC firmware */
2299         const struct firmware *mc_fw;   /* NI MC firmware */
2300         const struct firmware *ce_fw;   /* SI CE firmware */
2301         const struct firmware *mec_fw;  /* CIK MEC firmware */
2302         const struct firmware *sdma_fw; /* CIK SDMA firmware */
2303         const struct firmware *smc_fw;  /* SMC firmware */
2304         const struct firmware *uvd_fw;  /* UVD firmware */
2305         const struct firmware *vce_fw;  /* VCE firmware */
2306         struct r600_vram_scratch vram_scratch;
2307         int msi_enabled; /* msi enabled */
2308         struct r600_ih ih; /* r6/700 interrupt ring */
2309         struct radeon_rlc rlc;
2310         struct radeon_mec mec;
2311         struct work_struct hotplug_work;
2312         struct work_struct audio_work;
2313         struct work_struct reset_work;
2314         int num_crtc; /* number of crtcs */
2315         struct mutex dc_hw_i2c_mutex; /* display controller hw i2c mutex */
2316         bool has_uvd;
2317         struct r600_audio audio; /* audio stuff */
2318         struct notifier_block acpi_nb;
2319         /* only one userspace can use Hyperz features or CMASK at a time */
2320         struct drm_file *hyperz_filp;
2321         struct drm_file *cmask_filp;
2322         /* i2c buses */
2323         struct radeon_i2c_chan *i2c_bus[RADEON_MAX_I2C_BUS];
2324         /* debugfs */
2325         struct radeon_debugfs   debugfs[RADEON_DEBUGFS_MAX_COMPONENTS];
2326         unsigned                debugfs_count;
2327         /* virtual memory */
2328         struct radeon_vm_manager        vm_manager;
2329         struct mutex                    gpu_clock_mutex;
2330         /* memory stats */
2331         atomic64_t                      vram_usage;
2332         atomic64_t                      gtt_usage;
2333         atomic64_t                      num_bytes_moved;
2334         /* ACPI interface */
2335         struct radeon_atif              atif;
2336         struct radeon_atcs              atcs;
2337         /* srbm instance registers */
2338         struct mutex                    srbm_mutex;
2339         /* clock, powergating flags */
2340         u32 cg_flags;
2341         u32 pg_flags;
2342
2343         struct dev_pm_domain vga_pm_domain;
2344         bool have_disp_power_ref;
2345 };
2346
2347 bool radeon_is_px(struct drm_device *dev);
2348 int radeon_device_init(struct radeon_device *rdev,
2349                        struct drm_device *ddev,
2350                        struct pci_dev *pdev,
2351                        uint32_t flags);
2352 void radeon_device_fini(struct radeon_device *rdev);
2353 int radeon_gpu_wait_for_idle(struct radeon_device *rdev);
2354
2355 uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg,
2356                       bool always_indirect);
2357 void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v,
2358                   bool always_indirect);
2359 u32 r100_io_rreg(struct radeon_device *rdev, u32 reg);
2360 void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v);
2361
2362 u32 cik_mm_rdoorbell(struct radeon_device *rdev, u32 index);
2363 void cik_mm_wdoorbell(struct radeon_device *rdev, u32 index, u32 v);
2364
2365 /*
2366  * Cast helper
2367  */
2368 #define to_radeon_fence(p) ((struct radeon_fence *)(p))
2369
2370 /*
2371  * Registers read & write functions.
2372  */
2373 #define RREG8(reg) readb((rdev->rmmio) + (reg))
2374 #define WREG8(reg, v) writeb(v, (rdev->rmmio) + (reg))
2375 #define RREG16(reg) readw((rdev->rmmio) + (reg))
2376 #define WREG16(reg, v) writew(v, (rdev->rmmio) + (reg))
2377 #define RREG32(reg) r100_mm_rreg(rdev, (reg), false)
2378 #define RREG32_IDX(reg) r100_mm_rreg(rdev, (reg), true)
2379 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg), false))
2380 #define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v), false)
2381 #define WREG32_IDX(reg, v) r100_mm_wreg(rdev, (reg), (v), true)
2382 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2383 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2384 #define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg))
2385 #define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v))
2386 #define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg))
2387 #define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v))
2388 #define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg))
2389 #define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v))
2390 #define RREG32_PCIE_PORT(reg) rdev->pciep_rreg(rdev, (reg))
2391 #define WREG32_PCIE_PORT(reg, v) rdev->pciep_wreg(rdev, (reg), (v))
2392 #define RREG32_SMC(reg) tn_smc_rreg(rdev, (reg))
2393 #define WREG32_SMC(reg, v) tn_smc_wreg(rdev, (reg), (v))
2394 #define RREG32_RCU(reg) r600_rcu_rreg(rdev, (reg))
2395 #define WREG32_RCU(reg, v) r600_rcu_wreg(rdev, (reg), (v))
2396 #define RREG32_CG(reg) eg_cg_rreg(rdev, (reg))
2397 #define WREG32_CG(reg, v) eg_cg_wreg(rdev, (reg), (v))
2398 #define RREG32_PIF_PHY0(reg) eg_pif_phy0_rreg(rdev, (reg))
2399 #define WREG32_PIF_PHY0(reg, v) eg_pif_phy0_wreg(rdev, (reg), (v))
2400 #define RREG32_PIF_PHY1(reg) eg_pif_phy1_rreg(rdev, (reg))
2401 #define WREG32_PIF_PHY1(reg, v) eg_pif_phy1_wreg(rdev, (reg), (v))
2402 #define RREG32_UVD_CTX(reg) r600_uvd_ctx_rreg(rdev, (reg))
2403 #define WREG32_UVD_CTX(reg, v) r600_uvd_ctx_wreg(rdev, (reg), (v))
2404 #define RREG32_DIDT(reg) cik_didt_rreg(rdev, (reg))
2405 #define WREG32_DIDT(reg, v) cik_didt_wreg(rdev, (reg), (v))
2406 #define WREG32_P(reg, val, mask)                                \
2407         do {                                                    \
2408                 uint32_t tmp_ = RREG32(reg);                    \
2409                 tmp_ &= (mask);                                 \
2410                 tmp_ |= ((val) & ~(mask));                      \
2411                 WREG32(reg, tmp_);                              \
2412         } while (0)
2413 #define WREG32_AND(reg, and) WREG32_P(reg, 0, and)
2414 #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or))
2415 #define WREG32_PLL_P(reg, val, mask)                            \
2416         do {                                                    \
2417                 uint32_t tmp_ = RREG32_PLL(reg);                \
2418                 tmp_ &= (mask);                                 \
2419                 tmp_ |= ((val) & ~(mask));                      \
2420                 WREG32_PLL(reg, tmp_);                          \
2421         } while (0)
2422 #define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg), false))
2423 #define RREG32_IO(reg) r100_io_rreg(rdev, (reg))
2424 #define WREG32_IO(reg, v) r100_io_wreg(rdev, (reg), (v))
2425
2426 #define RDOORBELL32(index) cik_mm_rdoorbell(rdev, (index))
2427 #define WDOORBELL32(index, v) cik_mm_wdoorbell(rdev, (index), (v))
2428
2429 /*
2430  * Indirect registers accessor
2431  */
2432 static inline uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg)
2433 {
2434         unsigned long flags;
2435         uint32_t r;
2436
2437         spin_lock_irqsave(&rdev->pcie_idx_lock, flags);
2438         WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
2439         r = RREG32(RADEON_PCIE_DATA);
2440         spin_unlock_irqrestore(&rdev->pcie_idx_lock, flags);
2441         return r;
2442 }
2443
2444 static inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
2445 {
2446         unsigned long flags;
2447
2448         spin_lock_irqsave(&rdev->pcie_idx_lock, flags);
2449         WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
2450         WREG32(RADEON_PCIE_DATA, (v));
2451         spin_unlock_irqrestore(&rdev->pcie_idx_lock, flags);
2452 }
2453
2454 static inline u32 tn_smc_rreg(struct radeon_device *rdev, u32 reg)
2455 {
2456         unsigned long flags;
2457         u32 r;
2458
2459         spin_lock_irqsave(&rdev->smc_idx_lock, flags);
2460         WREG32(TN_SMC_IND_INDEX_0, (reg));
2461         r = RREG32(TN_SMC_IND_DATA_0);
2462         spin_unlock_irqrestore(&rdev->smc_idx_lock, flags);
2463         return r;
2464 }
2465
2466 static inline void tn_smc_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2467 {
2468         unsigned long flags;
2469
2470         spin_lock_irqsave(&rdev->smc_idx_lock, flags);
2471         WREG32(TN_SMC_IND_INDEX_0, (reg));
2472         WREG32(TN_SMC_IND_DATA_0, (v));
2473         spin_unlock_irqrestore(&rdev->smc_idx_lock, flags);
2474 }
2475
2476 static inline u32 r600_rcu_rreg(struct radeon_device *rdev, u32 reg)
2477 {
2478         unsigned long flags;
2479         u32 r;
2480
2481         spin_lock_irqsave(&rdev->rcu_idx_lock, flags);
2482         WREG32(R600_RCU_INDEX, ((reg) & 0x1fff));
2483         r = RREG32(R600_RCU_DATA);
2484         spin_unlock_irqrestore(&rdev->rcu_idx_lock, flags);
2485         return r;
2486 }
2487
2488 static inline void r600_rcu_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2489 {
2490         unsigned long flags;
2491
2492         spin_lock_irqsave(&rdev->rcu_idx_lock, flags);
2493         WREG32(R600_RCU_INDEX, ((reg) & 0x1fff));
2494         WREG32(R600_RCU_DATA, (v));
2495         spin_unlock_irqrestore(&rdev->rcu_idx_lock, flags);
2496 }
2497
2498 static inline u32 eg_cg_rreg(struct radeon_device *rdev, u32 reg)
2499 {
2500         unsigned long flags;
2501         u32 r;
2502
2503         spin_lock_irqsave(&rdev->cg_idx_lock, flags);
2504         WREG32(EVERGREEN_CG_IND_ADDR, ((reg) & 0xffff));
2505         r = RREG32(EVERGREEN_CG_IND_DATA);
2506         spin_unlock_irqrestore(&rdev->cg_idx_lock, flags);
2507         return r;
2508 }
2509
2510 static inline void eg_cg_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2511 {
2512         unsigned long flags;
2513
2514         spin_lock_irqsave(&rdev->cg_idx_lock, flags);
2515         WREG32(EVERGREEN_CG_IND_ADDR, ((reg) & 0xffff));
2516         WREG32(EVERGREEN_CG_IND_DATA, (v));
2517         spin_unlock_irqrestore(&rdev->cg_idx_lock, flags);
2518 }
2519
2520 static inline u32 eg_pif_phy0_rreg(struct radeon_device *rdev, u32 reg)
2521 {
2522         unsigned long flags;
2523         u32 r;
2524
2525         spin_lock_irqsave(&rdev->pif_idx_lock, flags);
2526         WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff));
2527         r = RREG32(EVERGREEN_PIF_PHY0_DATA);
2528         spin_unlock_irqrestore(&rdev->pif_idx_lock, flags);
2529         return r;
2530 }
2531
2532 static inline void eg_pif_phy0_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2533 {
2534         unsigned long flags;
2535
2536         spin_lock_irqsave(&rdev->pif_idx_lock, flags);
2537         WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff));
2538         WREG32(EVERGREEN_PIF_PHY0_DATA, (v));
2539         spin_unlock_irqrestore(&rdev->pif_idx_lock, flags);
2540 }
2541
2542 static inline u32 eg_pif_phy1_rreg(struct radeon_device *rdev, u32 reg)
2543 {
2544         unsigned long flags;
2545         u32 r;
2546
2547         spin_lock_irqsave(&rdev->pif_idx_lock, flags);
2548         WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff));
2549         r = RREG32(EVERGREEN_PIF_PHY1_DATA);
2550         spin_unlock_irqrestore(&rdev->pif_idx_lock, flags);
2551         return r;
2552 }
2553
2554 static inline void eg_pif_phy1_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2555 {
2556         unsigned long flags;
2557
2558         spin_lock_irqsave(&rdev->pif_idx_lock, flags);
2559         WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff));
2560         WREG32(EVERGREEN_PIF_PHY1_DATA, (v));
2561         spin_unlock_irqrestore(&rdev->pif_idx_lock, flags);
2562 }
2563
2564 static inline u32 r600_uvd_ctx_rreg(struct radeon_device *rdev, u32 reg)
2565 {
2566         unsigned long flags;
2567         u32 r;
2568
2569         spin_lock_irqsave(&rdev->uvd_idx_lock, flags);
2570         WREG32(R600_UVD_CTX_INDEX, ((reg) & 0x1ff));
2571         r = RREG32(R600_UVD_CTX_DATA);
2572         spin_unlock_irqrestore(&rdev->uvd_idx_lock, flags);
2573         return r;
2574 }
2575
2576 static inline void r600_uvd_ctx_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2577 {
2578         unsigned long flags;
2579
2580         spin_lock_irqsave(&rdev->uvd_idx_lock, flags);
2581         WREG32(R600_UVD_CTX_INDEX, ((reg) & 0x1ff));
2582         WREG32(R600_UVD_CTX_DATA, (v));
2583         spin_unlock_irqrestore(&rdev->uvd_idx_lock, flags);
2584 }
2585
2586
2587 static inline u32 cik_didt_rreg(struct radeon_device *rdev, u32 reg)
2588 {
2589         unsigned long flags;
2590         u32 r;
2591
2592         spin_lock_irqsave(&rdev->didt_idx_lock, flags);
2593         WREG32(CIK_DIDT_IND_INDEX, (reg));
2594         r = RREG32(CIK_DIDT_IND_DATA);
2595         spin_unlock_irqrestore(&rdev->didt_idx_lock, flags);
2596         return r;
2597 }
2598
2599 static inline void cik_didt_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2600 {
2601         unsigned long flags;
2602
2603         spin_lock_irqsave(&rdev->didt_idx_lock, flags);
2604         WREG32(CIK_DIDT_IND_INDEX, (reg));
2605         WREG32(CIK_DIDT_IND_DATA, (v));
2606         spin_unlock_irqrestore(&rdev->didt_idx_lock, flags);
2607 }
2608
2609 void r100_pll_errata_after_index(struct radeon_device *rdev);
2610
2611
2612 /*
2613  * ASICs helpers.
2614  */
2615 #define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \
2616                             (rdev->pdev->device == 0x5969))
2617 #define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \
2618                 (rdev->family == CHIP_RV200) || \
2619                 (rdev->family == CHIP_RS100) || \
2620                 (rdev->family == CHIP_RS200) || \
2621                 (rdev->family == CHIP_RV250) || \
2622                 (rdev->family == CHIP_RV280) || \
2623                 (rdev->family == CHIP_RS300))
2624 #define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300)  ||     \
2625                 (rdev->family == CHIP_RV350) ||                 \
2626                 (rdev->family == CHIP_R350)  ||                 \
2627                 (rdev->family == CHIP_RV380) ||                 \
2628                 (rdev->family == CHIP_R420)  ||                 \
2629                 (rdev->family == CHIP_R423)  ||                 \
2630                 (rdev->family == CHIP_RV410) ||                 \
2631                 (rdev->family == CHIP_RS400) ||                 \
2632                 (rdev->family == CHIP_RS480))
2633 #define ASIC_IS_X2(rdev) ((rdev->ddev->pdev->device == 0x9441) || \
2634                 (rdev->ddev->pdev->device == 0x9443) || \
2635                 (rdev->ddev->pdev->device == 0x944B) || \
2636                 (rdev->ddev->pdev->device == 0x9506) || \
2637                 (rdev->ddev->pdev->device == 0x9509) || \
2638                 (rdev->ddev->pdev->device == 0x950F) || \
2639                 (rdev->ddev->pdev->device == 0x689C) || \
2640                 (rdev->ddev->pdev->device == 0x689D))
2641 #define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600))
2642 #define ASIC_IS_DCE2(rdev) ((rdev->family == CHIP_RS600)  ||    \
2643                             (rdev->family == CHIP_RS690)  ||    \
2644                             (rdev->family == CHIP_RS740)  ||    \
2645                             (rdev->family >= CHIP_R600))
2646 #define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620))
2647 #define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730))
2648 #define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR))
2649 #define ASIC_IS_DCE41(rdev) ((rdev->family >= CHIP_PALM) && \
2650                              (rdev->flags & RADEON_IS_IGP))
2651 #define ASIC_IS_DCE5(rdev) ((rdev->family >= CHIP_BARTS))
2652 #define ASIC_IS_DCE6(rdev) ((rdev->family >= CHIP_ARUBA))
2653 #define ASIC_IS_DCE61(rdev) ((rdev->family >= CHIP_ARUBA) && \
2654                              (rdev->flags & RADEON_IS_IGP))
2655 #define ASIC_IS_DCE64(rdev) ((rdev->family == CHIP_OLAND))
2656 #define ASIC_IS_NODCE(rdev) ((rdev->family == CHIP_HAINAN))
2657 #define ASIC_IS_DCE8(rdev) ((rdev->family >= CHIP_BONAIRE))
2658 #define ASIC_IS_DCE81(rdev) ((rdev->family == CHIP_KAVERI))
2659 #define ASIC_IS_DCE82(rdev) ((rdev->family == CHIP_BONAIRE))
2660 #define ASIC_IS_DCE83(rdev) ((rdev->family == CHIP_KABINI) || \
2661                              (rdev->family == CHIP_MULLINS))
2662
2663 #define ASIC_IS_LOMBOK(rdev) ((rdev->ddev->pdev->device == 0x6849) || \
2664                               (rdev->ddev->pdev->device == 0x6850) || \
2665                               (rdev->ddev->pdev->device == 0x6858) || \
2666                               (rdev->ddev->pdev->device == 0x6859) || \
2667                               (rdev->ddev->pdev->device == 0x6840) || \
2668                               (rdev->ddev->pdev->device == 0x6841) || \
2669                               (rdev->ddev->pdev->device == 0x6842) || \
2670                               (rdev->ddev->pdev->device == 0x6843))
2671
2672 /*
2673  * BIOS helpers.
2674  */
2675 #define RBIOS8(i) (rdev->bios[i])
2676 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
2677 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
2678
2679 int radeon_combios_init(struct radeon_device *rdev);
2680 void radeon_combios_fini(struct radeon_device *rdev);
2681 int radeon_atombios_init(struct radeon_device *rdev);
2682 void radeon_atombios_fini(struct radeon_device *rdev);
2683
2684
2685 /*
2686  * RING helpers.
2687  */
2688 #if DRM_DEBUG_CODE == 0
2689 static inline void radeon_ring_write(struct radeon_ring *ring, uint32_t v)
2690 {
2691         ring->ring[ring->wptr++] = v;
2692         ring->wptr &= ring->ptr_mask;
2693         ring->count_dw--;
2694         ring->ring_free_dw--;
2695 }
2696 #else
2697 /* With debugging this is just too big to inline */
2698 void radeon_ring_write(struct radeon_ring *ring, uint32_t v);
2699 #endif
2700
2701 /*
2702  * ASICs macro.
2703  */
2704 #define radeon_init(rdev) (rdev)->asic->init((rdev))
2705 #define radeon_fini(rdev) (rdev)->asic->fini((rdev))
2706 #define radeon_resume(rdev) (rdev)->asic->resume((rdev))
2707 #define radeon_suspend(rdev) (rdev)->asic->suspend((rdev))
2708 #define radeon_cs_parse(rdev, r, p) (rdev)->asic->ring[(r)]->cs_parse((p))
2709 #define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state))
2710 #define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev))
2711 #define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart.tlb_flush((rdev))
2712 #define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart.set_page((rdev), (i), (p))
2713 #define radeon_asic_vm_init(rdev) (rdev)->asic->vm.init((rdev))
2714 #define radeon_asic_vm_fini(rdev) (rdev)->asic->vm.fini((rdev))
2715 #define radeon_asic_vm_set_page(rdev, ib, pe, addr, count, incr, flags) ((rdev)->asic->vm.set_page((rdev), (ib), (pe), (addr), (count), (incr), (flags)))
2716 #define radeon_ring_start(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_start((rdev), (cp))
2717 #define radeon_ring_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_test((rdev), (cp))
2718 #define radeon_ib_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ib_test((rdev), (cp))
2719 #define radeon_ring_ib_execute(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_execute((rdev), (ib))
2720 #define radeon_ring_ib_parse(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_parse((rdev), (ib))
2721 #define radeon_ring_is_lockup(rdev, r, cp) (rdev)->asic->ring[(r)]->is_lockup((rdev), (cp))
2722 #define radeon_ring_vm_flush(rdev, r, vm) (rdev)->asic->ring[(r)]->vm_flush((rdev), (r), (vm))
2723 #define radeon_ring_get_rptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_rptr((rdev), (r))
2724 #define radeon_ring_get_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_wptr((rdev), (r))
2725 #define radeon_ring_set_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->set_wptr((rdev), (r))
2726 #define radeon_irq_set(rdev) (rdev)->asic->irq.set((rdev))
2727 #define radeon_irq_process(rdev) (rdev)->asic->irq.process((rdev))
2728 #define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->display.get_vblank_counter((rdev), (crtc))
2729 #define radeon_set_backlight_level(rdev, e, l) (rdev)->asic->display.set_backlight_level((e), (l))
2730 #define radeon_get_backlight_level(rdev, e) (rdev)->asic->display.get_backlight_level((e))
2731 #define radeon_hdmi_enable(rdev, e, b) (rdev)->asic->display.hdmi_enable((e), (b))
2732 #define radeon_hdmi_setmode(rdev, e, m) (rdev)->asic->display.hdmi_setmode((e), (m))
2733 #define radeon_fence_ring_emit(rdev, r, fence) (rdev)->asic->ring[(r)]->emit_fence((rdev), (fence))
2734 #define radeon_semaphore_ring_emit(rdev, r, cp, semaphore, emit_wait) (rdev)->asic->ring[(r)]->emit_semaphore((rdev), (cp), (semaphore), (emit_wait))
2735 #define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy.blit((rdev), (s), (d), (np), (f))
2736 #define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy.dma((rdev), (s), (d), (np), (f))
2737 #define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy.copy((rdev), (s), (d), (np), (f))
2738 #define radeon_copy_blit_ring_index(rdev) (rdev)->asic->copy.blit_ring_index
2739 #define radeon_copy_dma_ring_index(rdev) (rdev)->asic->copy.dma_ring_index
2740 #define radeon_copy_ring_index(rdev) (rdev)->asic->copy.copy_ring_index
2741 #define radeon_get_engine_clock(rdev) (rdev)->asic->pm.get_engine_clock((rdev))
2742 #define radeon_set_engine_clock(rdev, e) (rdev)->asic->pm.set_engine_clock((rdev), (e))
2743 #define radeon_get_memory_clock(rdev) (rdev)->asic->pm.get_memory_clock((rdev))
2744 #define radeon_set_memory_clock(rdev, e) (rdev)->asic->pm.set_memory_clock((rdev), (e))
2745 #define radeon_get_pcie_lanes(rdev) (rdev)->asic->pm.get_pcie_lanes((rdev))
2746 #define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->pm.set_pcie_lanes((rdev), (l))
2747 #define radeon_set_clock_gating(rdev, e) (rdev)->asic->pm.set_clock_gating((rdev), (e))
2748 #define radeon_set_uvd_clocks(rdev, v, d) (rdev)->asic->pm.set_uvd_clocks((rdev), (v), (d))
2749 #define radeon_set_vce_clocks(rdev, ev, ec) (rdev)->asic->pm.set_vce_clocks((rdev), (ev), (ec))
2750 #define radeon_get_temperature(rdev) (rdev)->asic->pm.get_temperature((rdev))
2751 #define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->surface.set_reg((rdev), (r), (f), (p), (o), (s)))
2752 #define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->surface.clear_reg((rdev), (r)))
2753 #define radeon_bandwidth_update(rdev) (rdev)->asic->display.bandwidth_update((rdev))
2754 #define radeon_hpd_init(rdev) (rdev)->asic->hpd.init((rdev))
2755 #define radeon_hpd_fini(rdev) (rdev)->asic->hpd.fini((rdev))
2756 #define radeon_hpd_sense(rdev, h) (rdev)->asic->hpd.sense((rdev), (h))
2757 #define radeon_hpd_set_polarity(rdev, h) (rdev)->asic->hpd.set_polarity((rdev), (h))
2758 #define radeon_gui_idle(rdev) (rdev)->asic->gui_idle((rdev))
2759 #define radeon_pm_misc(rdev) (rdev)->asic->pm.misc((rdev))
2760 #define radeon_pm_prepare(rdev) (rdev)->asic->pm.prepare((rdev))
2761 #define radeon_pm_finish(rdev) (rdev)->asic->pm.finish((rdev))
2762 #define radeon_pm_init_profile(rdev) (rdev)->asic->pm.init_profile((rdev))
2763 #define radeon_pm_get_dynpm_state(rdev) (rdev)->asic->pm.get_dynpm_state((rdev))
2764 #define radeon_page_flip(rdev, crtc, base) (rdev)->asic->pflip.page_flip((rdev), (crtc), (base))
2765 #define radeon_page_flip_pending(rdev, crtc) (rdev)->asic->pflip.page_flip_pending((rdev), (crtc))
2766 #define radeon_wait_for_vblank(rdev, crtc) (rdev)->asic->display.wait_for_vblank((rdev), (crtc))
2767 #define radeon_mc_wait_for_idle(rdev) (rdev)->asic->mc_wait_for_idle((rdev))
2768 #define radeon_get_xclk(rdev) (rdev)->asic->get_xclk((rdev))
2769 #define radeon_get_gpu_clock_counter(rdev) (rdev)->asic->get_gpu_clock_counter((rdev))
2770 #define radeon_dpm_init(rdev) rdev->asic->dpm.init((rdev))
2771 #define radeon_dpm_setup_asic(rdev) rdev->asic->dpm.setup_asic((rdev))
2772 #define radeon_dpm_enable(rdev) rdev->asic->dpm.enable((rdev))
2773 #define radeon_dpm_late_enable(rdev) rdev->asic->dpm.late_enable((rdev))
2774 #define radeon_dpm_disable(rdev) rdev->asic->dpm.disable((rdev))
2775 #define radeon_dpm_pre_set_power_state(rdev) rdev->asic->dpm.pre_set_power_state((rdev))
2776 #define radeon_dpm_set_power_state(rdev) rdev->asic->dpm.set_power_state((rdev))
2777 #define radeon_dpm_post_set_power_state(rdev) rdev->asic->dpm.post_set_power_state((rdev))
2778 #define radeon_dpm_display_configuration_changed(rdev) rdev->asic->dpm.display_configuration_changed((rdev))
2779 #define radeon_dpm_fini(rdev) rdev->asic->dpm.fini((rdev))
2780 #define radeon_dpm_get_sclk(rdev, l) rdev->asic->dpm.get_sclk((rdev), (l))
2781 #define radeon_dpm_get_mclk(rdev, l) rdev->asic->dpm.get_mclk((rdev), (l))
2782 #define radeon_dpm_print_power_state(rdev, ps) rdev->asic->dpm.print_power_state((rdev), (ps))
2783 #define radeon_dpm_debugfs_print_current_performance_level(rdev, m) rdev->asic->dpm.debugfs_print_current_performance_level((rdev), (m))
2784 #define radeon_dpm_force_performance_level(rdev, l) rdev->asic->dpm.force_performance_level((rdev), (l))
2785 #define radeon_dpm_vblank_too_short(rdev) rdev->asic->dpm.vblank_too_short((rdev))
2786 #define radeon_dpm_powergate_uvd(rdev, g) rdev->asic->dpm.powergate_uvd((rdev), (g))
2787 #define radeon_dpm_enable_bapm(rdev, e) rdev->asic->dpm.enable_bapm((rdev), (e))
2788
2789 /* Common functions */
2790 /* AGP */
2791 extern int radeon_gpu_reset(struct radeon_device *rdev);
2792 extern void radeon_pci_config_reset(struct radeon_device *rdev);
2793 extern void r600_set_bios_scratch_engine_hung(struct radeon_device *rdev, bool hung);
2794 extern void radeon_agp_disable(struct radeon_device *rdev);
2795 extern int radeon_modeset_init(struct radeon_device *rdev);
2796 extern void radeon_modeset_fini(struct radeon_device *rdev);
2797 extern bool radeon_card_posted(struct radeon_device *rdev);
2798 extern void radeon_update_bandwidth_info(struct radeon_device *rdev);
2799 extern void radeon_update_display_priority(struct radeon_device *rdev);
2800 extern bool radeon_boot_test_post_card(struct radeon_device *rdev);
2801 extern void radeon_scratch_init(struct radeon_device *rdev);
2802 extern void radeon_wb_fini(struct radeon_device *rdev);
2803 extern int radeon_wb_init(struct radeon_device *rdev);
2804 extern void radeon_wb_disable(struct radeon_device *rdev);
2805 extern void radeon_surface_init(struct radeon_device *rdev);
2806 extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data);
2807 extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);
2808 extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
2809 extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain);
2810 extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo);
2811 extern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base);
2812 extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc);
2813 extern int radeon_resume_kms(struct drm_device *dev, bool resume, bool fbcon);
2814 extern int radeon_suspend_kms(struct drm_device *dev, bool suspend, bool fbcon);
2815 extern void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size);
2816 extern void radeon_program_register_sequence(struct radeon_device *rdev,
2817                                              const u32 *registers,
2818                                              const u32 array_size);
2819
2820 /*
2821  * vm
2822  */
2823 int radeon_vm_manager_init(struct radeon_device *rdev);
2824 void radeon_vm_manager_fini(struct radeon_device *rdev);
2825 int radeon_vm_init(struct radeon_device *rdev, struct radeon_vm *vm);
2826 void radeon_vm_fini(struct radeon_device *rdev, struct radeon_vm *vm);
2827 struct radeon_cs_reloc *radeon_vm_get_bos(struct radeon_device *rdev,
2828                                           struct radeon_vm *vm,
2829                                           struct list_head *head);
2830 struct radeon_fence *radeon_vm_grab_id(struct radeon_device *rdev,
2831                                        struct radeon_vm *vm, int ring);
2832 void radeon_vm_flush(struct radeon_device *rdev,
2833                      struct radeon_vm *vm,
2834                      int ring);
2835 void radeon_vm_fence(struct radeon_device *rdev,
2836                      struct radeon_vm *vm,
2837                      struct radeon_fence *fence);
2838 uint64_t radeon_vm_map_gart(struct radeon_device *rdev, uint64_t addr);
2839 int radeon_vm_update_page_directory(struct radeon_device *rdev,
2840                                     struct radeon_vm *vm);
2841 int radeon_vm_clear_freed(struct radeon_device *rdev,
2842                           struct radeon_vm *vm);
2843 int radeon_vm_bo_update(struct radeon_device *rdev,
2844                         struct radeon_bo_va *bo_va,
2845                         struct ttm_mem_reg *mem);
2846 void radeon_vm_bo_invalidate(struct radeon_device *rdev,
2847                              struct radeon_bo *bo);
2848 struct radeon_bo_va *radeon_vm_bo_find(struct radeon_vm *vm,
2849                                        struct radeon_bo *bo);
2850 struct radeon_bo_va *radeon_vm_bo_add(struct radeon_device *rdev,
2851                                       struct radeon_vm *vm,
2852                                       struct radeon_bo *bo);
2853 int radeon_vm_bo_set_addr(struct radeon_device *rdev,
2854                           struct radeon_bo_va *bo_va,
2855                           uint64_t offset,
2856                           uint32_t flags);
2857 void radeon_vm_bo_rmv(struct radeon_device *rdev,
2858                       struct radeon_bo_va *bo_va);
2859
2860 /* audio */
2861 void r600_audio_update_hdmi(struct work_struct *work);
2862 struct r600_audio_pin *r600_audio_get_pin(struct radeon_device *rdev);
2863 struct r600_audio_pin *dce6_audio_get_pin(struct radeon_device *rdev);
2864 void r600_audio_enable(struct radeon_device *rdev,
2865                        struct r600_audio_pin *pin,
2866                        bool enable);
2867 void dce6_audio_enable(struct radeon_device *rdev,
2868                        struct r600_audio_pin *pin,
2869                        bool enable);
2870
2871 /*
2872  * R600 vram scratch functions
2873  */
2874 int r600_vram_scratch_init(struct radeon_device *rdev);
2875 void r600_vram_scratch_fini(struct radeon_device *rdev);
2876
2877 /*
2878  * r600 cs checking helper
2879  */
2880 unsigned r600_mip_minify(unsigned size, unsigned level);
2881 bool r600_fmt_is_valid_color(u32 format);
2882 bool r600_fmt_is_valid_texture(u32 format, enum radeon_family family);
2883 int r600_fmt_get_blocksize(u32 format);
2884 int r600_fmt_get_nblocksx(u32 format, u32 w);
2885 int r600_fmt_get_nblocksy(u32 format, u32 h);
2886
2887 /*
2888  * r600 functions used by radeon_encoder.c
2889  */
2890 struct radeon_hdmi_acr {
2891         u32 clock;
2892
2893         int n_32khz;
2894         int cts_32khz;
2895
2896         int n_44_1khz;
2897         int cts_44_1khz;
2898
2899         int n_48khz;
2900         int cts_48khz;
2901
2902 };
2903
2904 extern struct radeon_hdmi_acr r600_hdmi_acr(uint32_t clock);
2905
2906 extern u32 r6xx_remap_render_backend(struct radeon_device *rdev,
2907                                      u32 tiling_pipe_num,
2908                                      u32 max_rb_num,
2909                                      u32 total_max_rb_num,
2910                                      u32 enabled_rb_mask);
2911
2912 /*
2913  * evergreen functions used by radeon_encoder.c
2914  */
2915
2916 extern int ni_init_microcode(struct radeon_device *rdev);
2917 extern int ni_mc_load_microcode(struct radeon_device *rdev);
2918
2919 /* radeon_acpi.c */
2920 #if defined(CONFIG_ACPI)
2921 extern int radeon_acpi_init(struct radeon_device *rdev);
2922 extern void radeon_acpi_fini(struct radeon_device *rdev);
2923 extern bool radeon_acpi_is_pcie_performance_request_supported(struct radeon_device *rdev);
2924 extern int radeon_acpi_pcie_performance_request(struct radeon_device *rdev,
2925                                                 u8 perf_req, bool advertise);
2926 extern int radeon_acpi_pcie_notify_device_ready(struct radeon_device *rdev);
2927 #else
2928 static inline int radeon_acpi_init(struct radeon_device *rdev) { return 0; }
2929 static inline void radeon_acpi_fini(struct radeon_device *rdev) { }
2930 #endif
2931
2932 int radeon_cs_packet_parse(struct radeon_cs_parser *p,
2933                            struct radeon_cs_packet *pkt,
2934                            unsigned idx);
2935 bool radeon_cs_packet_next_is_pkt3_nop(struct radeon_cs_parser *p);
2936 void radeon_cs_dump_packet(struct radeon_cs_parser *p,
2937                            struct radeon_cs_packet *pkt);
2938 int radeon_cs_packet_next_reloc(struct radeon_cs_parser *p,
2939                                 struct radeon_cs_reloc **cs_reloc,
2940                                 int nomm);
2941 int r600_cs_common_vline_parse(struct radeon_cs_parser *p,
2942                                uint32_t *vline_start_end,
2943                                uint32_t *vline_status);
2944
2945 #include "radeon_object.h"
2946
2947 #endif