2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
29 #include <linux/console.h>
31 #include <drm/drm_crtc_helper.h>
32 #include <drm/radeon_drm.h>
33 #include <linux/vgaarb.h>
34 #include <linux/vga_switcheroo.h>
35 #include "radeon_reg.h"
37 #include "radeon_asic.h"
41 * Registers accessors functions.
44 * radeon_invalid_rreg - dummy reg read function
46 * @rdev: radeon device pointer
47 * @reg: offset of register
49 * Dummy register read function. Used for register blocks
50 * that certain asics don't have (all asics).
51 * Returns the value in the register.
53 static uint32_t radeon_invalid_rreg(struct radeon_device
*rdev
, uint32_t reg
)
55 DRM_ERROR("Invalid callback to read register 0x%04X\n", reg
);
61 * radeon_invalid_wreg - dummy reg write function
63 * @rdev: radeon device pointer
64 * @reg: offset of register
65 * @v: value to write to the register
67 * Dummy register read function. Used for register blocks
68 * that certain asics don't have (all asics).
70 static void radeon_invalid_wreg(struct radeon_device
*rdev
, uint32_t reg
, uint32_t v
)
72 DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n",
78 * radeon_register_accessor_init - sets up the register accessor callbacks
80 * @rdev: radeon device pointer
82 * Sets up the register accessor callbacks for various register
83 * apertures. Not all asics have all apertures (all asics).
85 static void radeon_register_accessor_init(struct radeon_device
*rdev
)
87 rdev
->mc_rreg
= &radeon_invalid_rreg
;
88 rdev
->mc_wreg
= &radeon_invalid_wreg
;
89 rdev
->pll_rreg
= &radeon_invalid_rreg
;
90 rdev
->pll_wreg
= &radeon_invalid_wreg
;
91 rdev
->pciep_rreg
= &radeon_invalid_rreg
;
92 rdev
->pciep_wreg
= &radeon_invalid_wreg
;
94 /* Don't change order as we are overridding accessor. */
95 if (rdev
->family
< CHIP_RV515
) {
96 rdev
->pcie_reg_mask
= 0xff;
98 rdev
->pcie_reg_mask
= 0x7ff;
100 /* FIXME: not sure here */
101 if (rdev
->family
<= CHIP_R580
) {
102 rdev
->pll_rreg
= &r100_pll_rreg
;
103 rdev
->pll_wreg
= &r100_pll_wreg
;
105 if (rdev
->family
>= CHIP_R420
) {
106 rdev
->mc_rreg
= &r420_mc_rreg
;
107 rdev
->mc_wreg
= &r420_mc_wreg
;
109 if (rdev
->family
>= CHIP_RV515
) {
110 rdev
->mc_rreg
= &rv515_mc_rreg
;
111 rdev
->mc_wreg
= &rv515_mc_wreg
;
113 if (rdev
->family
== CHIP_RS400
|| rdev
->family
== CHIP_RS480
) {
114 rdev
->mc_rreg
= &rs400_mc_rreg
;
115 rdev
->mc_wreg
= &rs400_mc_wreg
;
117 if (rdev
->family
== CHIP_RS690
|| rdev
->family
== CHIP_RS740
) {
118 rdev
->mc_rreg
= &rs690_mc_rreg
;
119 rdev
->mc_wreg
= &rs690_mc_wreg
;
121 if (rdev
->family
== CHIP_RS600
) {
122 rdev
->mc_rreg
= &rs600_mc_rreg
;
123 rdev
->mc_wreg
= &rs600_mc_wreg
;
125 if (rdev
->family
== CHIP_RS780
|| rdev
->family
== CHIP_RS880
) {
126 rdev
->mc_rreg
= &rs780_mc_rreg
;
127 rdev
->mc_wreg
= &rs780_mc_wreg
;
130 if (rdev
->family
>= CHIP_BONAIRE
) {
131 rdev
->pciep_rreg
= &cik_pciep_rreg
;
132 rdev
->pciep_wreg
= &cik_pciep_wreg
;
133 } else if (rdev
->family
>= CHIP_R600
) {
134 rdev
->pciep_rreg
= &r600_pciep_rreg
;
135 rdev
->pciep_wreg
= &r600_pciep_wreg
;
140 /* helper to disable agp */
142 * radeon_agp_disable - AGP disable helper function
144 * @rdev: radeon device pointer
146 * Removes AGP flags and changes the gart callbacks on AGP
147 * cards when using the internal gart rather than AGP (all asics).
149 void radeon_agp_disable(struct radeon_device
*rdev
)
151 rdev
->flags
&= ~RADEON_IS_AGP
;
152 if (rdev
->family
>= CHIP_R600
) {
153 DRM_INFO("Forcing AGP to PCIE mode\n");
154 rdev
->flags
|= RADEON_IS_PCIE
;
155 } else if (rdev
->family
>= CHIP_RV515
||
156 rdev
->family
== CHIP_RV380
||
157 rdev
->family
== CHIP_RV410
||
158 rdev
->family
== CHIP_R423
) {
159 DRM_INFO("Forcing AGP to PCIE mode\n");
160 rdev
->flags
|= RADEON_IS_PCIE
;
161 rdev
->asic
->gart
.tlb_flush
= &rv370_pcie_gart_tlb_flush
;
162 rdev
->asic
->gart
.set_page
= &rv370_pcie_gart_set_page
;
164 DRM_INFO("Forcing AGP to PCI mode\n");
165 rdev
->flags
|= RADEON_IS_PCI
;
166 rdev
->asic
->gart
.tlb_flush
= &r100_pci_gart_tlb_flush
;
167 rdev
->asic
->gart
.set_page
= &r100_pci_gart_set_page
;
169 rdev
->mc
.gtt_size
= radeon_gart_size
* 1024 * 1024;
176 static struct radeon_asic_ring r100_gfx_ring
= {
177 .ib_execute
= &r100_ring_ib_execute
,
178 .emit_fence
= &r100_fence_ring_emit
,
179 .emit_semaphore
= &r100_semaphore_ring_emit
,
180 .cs_parse
= &r100_cs_parse
,
181 .ring_start
= &r100_ring_start
,
182 .ring_test
= &r100_ring_test
,
183 .ib_test
= &r100_ib_test
,
184 .is_lockup
= &r100_gpu_is_lockup
,
185 .get_rptr
= &r100_gfx_get_rptr
,
186 .get_wptr
= &r100_gfx_get_wptr
,
187 .set_wptr
= &r100_gfx_set_wptr
,
190 static struct radeon_asic r100_asic
= {
193 .suspend
= &r100_suspend
,
194 .resume
= &r100_resume
,
195 .vga_set_state
= &r100_vga_set_state
,
196 .asic_reset
= &r100_asic_reset
,
197 .ioctl_wait_idle
= NULL
,
198 .gui_idle
= &r100_gui_idle
,
199 .mc_wait_for_idle
= &r100_mc_wait_for_idle
,
201 .tlb_flush
= &r100_pci_gart_tlb_flush
,
202 .set_page
= &r100_pci_gart_set_page
,
205 [RADEON_RING_TYPE_GFX_INDEX
] = &r100_gfx_ring
208 .set
= &r100_irq_set
,
209 .process
= &r100_irq_process
,
212 .bandwidth_update
= &r100_bandwidth_update
,
213 .get_vblank_counter
= &r100_get_vblank_counter
,
214 .wait_for_vblank
= &r100_wait_for_vblank
,
215 .set_backlight_level
= &radeon_legacy_set_backlight_level
,
216 .get_backlight_level
= &radeon_legacy_get_backlight_level
,
219 .blit
= &r100_copy_blit
,
220 .blit_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
222 .dma_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
223 .copy
= &r100_copy_blit
,
224 .copy_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
227 .set_reg
= r100_set_surface_reg
,
228 .clear_reg
= r100_clear_surface_reg
,
231 .init
= &r100_hpd_init
,
232 .fini
= &r100_hpd_fini
,
233 .sense
= &r100_hpd_sense
,
234 .set_polarity
= &r100_hpd_set_polarity
,
237 .misc
= &r100_pm_misc
,
238 .prepare
= &r100_pm_prepare
,
239 .finish
= &r100_pm_finish
,
240 .init_profile
= &r100_pm_init_profile
,
241 .get_dynpm_state
= &r100_pm_get_dynpm_state
,
242 .get_engine_clock
= &radeon_legacy_get_engine_clock
,
243 .set_engine_clock
= &radeon_legacy_set_engine_clock
,
244 .get_memory_clock
= &radeon_legacy_get_memory_clock
,
245 .set_memory_clock
= NULL
,
246 .get_pcie_lanes
= NULL
,
247 .set_pcie_lanes
= NULL
,
248 .set_clock_gating
= &radeon_legacy_set_clock_gating
,
251 .page_flip
= &r100_page_flip
,
252 .page_flip_pending
= &r100_page_flip_pending
,
256 static struct radeon_asic r200_asic
= {
259 .suspend
= &r100_suspend
,
260 .resume
= &r100_resume
,
261 .vga_set_state
= &r100_vga_set_state
,
262 .asic_reset
= &r100_asic_reset
,
263 .ioctl_wait_idle
= NULL
,
264 .gui_idle
= &r100_gui_idle
,
265 .mc_wait_for_idle
= &r100_mc_wait_for_idle
,
267 .tlb_flush
= &r100_pci_gart_tlb_flush
,
268 .set_page
= &r100_pci_gart_set_page
,
271 [RADEON_RING_TYPE_GFX_INDEX
] = &r100_gfx_ring
274 .set
= &r100_irq_set
,
275 .process
= &r100_irq_process
,
278 .bandwidth_update
= &r100_bandwidth_update
,
279 .get_vblank_counter
= &r100_get_vblank_counter
,
280 .wait_for_vblank
= &r100_wait_for_vblank
,
281 .set_backlight_level
= &radeon_legacy_set_backlight_level
,
282 .get_backlight_level
= &radeon_legacy_get_backlight_level
,
285 .blit
= &r100_copy_blit
,
286 .blit_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
287 .dma
= &r200_copy_dma
,
288 .dma_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
289 .copy
= &r100_copy_blit
,
290 .copy_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
293 .set_reg
= r100_set_surface_reg
,
294 .clear_reg
= r100_clear_surface_reg
,
297 .init
= &r100_hpd_init
,
298 .fini
= &r100_hpd_fini
,
299 .sense
= &r100_hpd_sense
,
300 .set_polarity
= &r100_hpd_set_polarity
,
303 .misc
= &r100_pm_misc
,
304 .prepare
= &r100_pm_prepare
,
305 .finish
= &r100_pm_finish
,
306 .init_profile
= &r100_pm_init_profile
,
307 .get_dynpm_state
= &r100_pm_get_dynpm_state
,
308 .get_engine_clock
= &radeon_legacy_get_engine_clock
,
309 .set_engine_clock
= &radeon_legacy_set_engine_clock
,
310 .get_memory_clock
= &radeon_legacy_get_memory_clock
,
311 .set_memory_clock
= NULL
,
312 .get_pcie_lanes
= NULL
,
313 .set_pcie_lanes
= NULL
,
314 .set_clock_gating
= &radeon_legacy_set_clock_gating
,
317 .page_flip
= &r100_page_flip
,
318 .page_flip_pending
= &r100_page_flip_pending
,
322 static struct radeon_asic_ring r300_gfx_ring
= {
323 .ib_execute
= &r100_ring_ib_execute
,
324 .emit_fence
= &r300_fence_ring_emit
,
325 .emit_semaphore
= &r100_semaphore_ring_emit
,
326 .cs_parse
= &r300_cs_parse
,
327 .ring_start
= &r300_ring_start
,
328 .ring_test
= &r100_ring_test
,
329 .ib_test
= &r100_ib_test
,
330 .is_lockup
= &r100_gpu_is_lockup
,
331 .get_rptr
= &r100_gfx_get_rptr
,
332 .get_wptr
= &r100_gfx_get_wptr
,
333 .set_wptr
= &r100_gfx_set_wptr
,
336 static struct radeon_asic r300_asic
= {
339 .suspend
= &r300_suspend
,
340 .resume
= &r300_resume
,
341 .vga_set_state
= &r100_vga_set_state
,
342 .asic_reset
= &r300_asic_reset
,
343 .ioctl_wait_idle
= NULL
,
344 .gui_idle
= &r100_gui_idle
,
345 .mc_wait_for_idle
= &r300_mc_wait_for_idle
,
347 .tlb_flush
= &r100_pci_gart_tlb_flush
,
348 .set_page
= &r100_pci_gart_set_page
,
351 [RADEON_RING_TYPE_GFX_INDEX
] = &r300_gfx_ring
354 .set
= &r100_irq_set
,
355 .process
= &r100_irq_process
,
358 .bandwidth_update
= &r100_bandwidth_update
,
359 .get_vblank_counter
= &r100_get_vblank_counter
,
360 .wait_for_vblank
= &r100_wait_for_vblank
,
361 .set_backlight_level
= &radeon_legacy_set_backlight_level
,
362 .get_backlight_level
= &radeon_legacy_get_backlight_level
,
365 .blit
= &r100_copy_blit
,
366 .blit_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
367 .dma
= &r200_copy_dma
,
368 .dma_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
369 .copy
= &r100_copy_blit
,
370 .copy_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
373 .set_reg
= r100_set_surface_reg
,
374 .clear_reg
= r100_clear_surface_reg
,
377 .init
= &r100_hpd_init
,
378 .fini
= &r100_hpd_fini
,
379 .sense
= &r100_hpd_sense
,
380 .set_polarity
= &r100_hpd_set_polarity
,
383 .misc
= &r100_pm_misc
,
384 .prepare
= &r100_pm_prepare
,
385 .finish
= &r100_pm_finish
,
386 .init_profile
= &r100_pm_init_profile
,
387 .get_dynpm_state
= &r100_pm_get_dynpm_state
,
388 .get_engine_clock
= &radeon_legacy_get_engine_clock
,
389 .set_engine_clock
= &radeon_legacy_set_engine_clock
,
390 .get_memory_clock
= &radeon_legacy_get_memory_clock
,
391 .set_memory_clock
= NULL
,
392 .get_pcie_lanes
= &rv370_get_pcie_lanes
,
393 .set_pcie_lanes
= &rv370_set_pcie_lanes
,
394 .set_clock_gating
= &radeon_legacy_set_clock_gating
,
397 .page_flip
= &r100_page_flip
,
398 .page_flip_pending
= &r100_page_flip_pending
,
402 static struct radeon_asic r300_asic_pcie
= {
405 .suspend
= &r300_suspend
,
406 .resume
= &r300_resume
,
407 .vga_set_state
= &r100_vga_set_state
,
408 .asic_reset
= &r300_asic_reset
,
409 .ioctl_wait_idle
= NULL
,
410 .gui_idle
= &r100_gui_idle
,
411 .mc_wait_for_idle
= &r300_mc_wait_for_idle
,
413 .tlb_flush
= &rv370_pcie_gart_tlb_flush
,
414 .set_page
= &rv370_pcie_gart_set_page
,
417 [RADEON_RING_TYPE_GFX_INDEX
] = &r300_gfx_ring
420 .set
= &r100_irq_set
,
421 .process
= &r100_irq_process
,
424 .bandwidth_update
= &r100_bandwidth_update
,
425 .get_vblank_counter
= &r100_get_vblank_counter
,
426 .wait_for_vblank
= &r100_wait_for_vblank
,
427 .set_backlight_level
= &radeon_legacy_set_backlight_level
,
428 .get_backlight_level
= &radeon_legacy_get_backlight_level
,
431 .blit
= &r100_copy_blit
,
432 .blit_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
433 .dma
= &r200_copy_dma
,
434 .dma_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
435 .copy
= &r100_copy_blit
,
436 .copy_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
439 .set_reg
= r100_set_surface_reg
,
440 .clear_reg
= r100_clear_surface_reg
,
443 .init
= &r100_hpd_init
,
444 .fini
= &r100_hpd_fini
,
445 .sense
= &r100_hpd_sense
,
446 .set_polarity
= &r100_hpd_set_polarity
,
449 .misc
= &r100_pm_misc
,
450 .prepare
= &r100_pm_prepare
,
451 .finish
= &r100_pm_finish
,
452 .init_profile
= &r100_pm_init_profile
,
453 .get_dynpm_state
= &r100_pm_get_dynpm_state
,
454 .get_engine_clock
= &radeon_legacy_get_engine_clock
,
455 .set_engine_clock
= &radeon_legacy_set_engine_clock
,
456 .get_memory_clock
= &radeon_legacy_get_memory_clock
,
457 .set_memory_clock
= NULL
,
458 .get_pcie_lanes
= &rv370_get_pcie_lanes
,
459 .set_pcie_lanes
= &rv370_set_pcie_lanes
,
460 .set_clock_gating
= &radeon_legacy_set_clock_gating
,
463 .page_flip
= &r100_page_flip
,
464 .page_flip_pending
= &r100_page_flip_pending
,
468 static struct radeon_asic r420_asic
= {
471 .suspend
= &r420_suspend
,
472 .resume
= &r420_resume
,
473 .vga_set_state
= &r100_vga_set_state
,
474 .asic_reset
= &r300_asic_reset
,
475 .ioctl_wait_idle
= NULL
,
476 .gui_idle
= &r100_gui_idle
,
477 .mc_wait_for_idle
= &r300_mc_wait_for_idle
,
479 .tlb_flush
= &rv370_pcie_gart_tlb_flush
,
480 .set_page
= &rv370_pcie_gart_set_page
,
483 [RADEON_RING_TYPE_GFX_INDEX
] = &r300_gfx_ring
486 .set
= &r100_irq_set
,
487 .process
= &r100_irq_process
,
490 .bandwidth_update
= &r100_bandwidth_update
,
491 .get_vblank_counter
= &r100_get_vblank_counter
,
492 .wait_for_vblank
= &r100_wait_for_vblank
,
493 .set_backlight_level
= &atombios_set_backlight_level
,
494 .get_backlight_level
= &atombios_get_backlight_level
,
497 .blit
= &r100_copy_blit
,
498 .blit_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
499 .dma
= &r200_copy_dma
,
500 .dma_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
501 .copy
= &r100_copy_blit
,
502 .copy_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
505 .set_reg
= r100_set_surface_reg
,
506 .clear_reg
= r100_clear_surface_reg
,
509 .init
= &r100_hpd_init
,
510 .fini
= &r100_hpd_fini
,
511 .sense
= &r100_hpd_sense
,
512 .set_polarity
= &r100_hpd_set_polarity
,
515 .misc
= &r100_pm_misc
,
516 .prepare
= &r100_pm_prepare
,
517 .finish
= &r100_pm_finish
,
518 .init_profile
= &r420_pm_init_profile
,
519 .get_dynpm_state
= &r100_pm_get_dynpm_state
,
520 .get_engine_clock
= &radeon_atom_get_engine_clock
,
521 .set_engine_clock
= &radeon_atom_set_engine_clock
,
522 .get_memory_clock
= &radeon_atom_get_memory_clock
,
523 .set_memory_clock
= &radeon_atom_set_memory_clock
,
524 .get_pcie_lanes
= &rv370_get_pcie_lanes
,
525 .set_pcie_lanes
= &rv370_set_pcie_lanes
,
526 .set_clock_gating
= &radeon_atom_set_clock_gating
,
529 .page_flip
= &r100_page_flip
,
530 .page_flip_pending
= &r100_page_flip_pending
,
534 static struct radeon_asic rs400_asic
= {
537 .suspend
= &rs400_suspend
,
538 .resume
= &rs400_resume
,
539 .vga_set_state
= &r100_vga_set_state
,
540 .asic_reset
= &r300_asic_reset
,
541 .ioctl_wait_idle
= NULL
,
542 .gui_idle
= &r100_gui_idle
,
543 .mc_wait_for_idle
= &rs400_mc_wait_for_idle
,
545 .tlb_flush
= &rs400_gart_tlb_flush
,
546 .set_page
= &rs400_gart_set_page
,
549 [RADEON_RING_TYPE_GFX_INDEX
] = &r300_gfx_ring
552 .set
= &r100_irq_set
,
553 .process
= &r100_irq_process
,
556 .bandwidth_update
= &r100_bandwidth_update
,
557 .get_vblank_counter
= &r100_get_vblank_counter
,
558 .wait_for_vblank
= &r100_wait_for_vblank
,
559 .set_backlight_level
= &radeon_legacy_set_backlight_level
,
560 .get_backlight_level
= &radeon_legacy_get_backlight_level
,
563 .blit
= &r100_copy_blit
,
564 .blit_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
565 .dma
= &r200_copy_dma
,
566 .dma_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
567 .copy
= &r100_copy_blit
,
568 .copy_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
571 .set_reg
= r100_set_surface_reg
,
572 .clear_reg
= r100_clear_surface_reg
,
575 .init
= &r100_hpd_init
,
576 .fini
= &r100_hpd_fini
,
577 .sense
= &r100_hpd_sense
,
578 .set_polarity
= &r100_hpd_set_polarity
,
581 .misc
= &r100_pm_misc
,
582 .prepare
= &r100_pm_prepare
,
583 .finish
= &r100_pm_finish
,
584 .init_profile
= &r100_pm_init_profile
,
585 .get_dynpm_state
= &r100_pm_get_dynpm_state
,
586 .get_engine_clock
= &radeon_legacy_get_engine_clock
,
587 .set_engine_clock
= &radeon_legacy_set_engine_clock
,
588 .get_memory_clock
= &radeon_legacy_get_memory_clock
,
589 .set_memory_clock
= NULL
,
590 .get_pcie_lanes
= NULL
,
591 .set_pcie_lanes
= NULL
,
592 .set_clock_gating
= &radeon_legacy_set_clock_gating
,
595 .page_flip
= &r100_page_flip
,
596 .page_flip_pending
= &r100_page_flip_pending
,
600 static struct radeon_asic rs600_asic
= {
603 .suspend
= &rs600_suspend
,
604 .resume
= &rs600_resume
,
605 .vga_set_state
= &r100_vga_set_state
,
606 .asic_reset
= &rs600_asic_reset
,
607 .ioctl_wait_idle
= NULL
,
608 .gui_idle
= &r100_gui_idle
,
609 .mc_wait_for_idle
= &rs600_mc_wait_for_idle
,
611 .tlb_flush
= &rs600_gart_tlb_flush
,
612 .set_page
= &rs600_gart_set_page
,
615 [RADEON_RING_TYPE_GFX_INDEX
] = &r300_gfx_ring
618 .set
= &rs600_irq_set
,
619 .process
= &rs600_irq_process
,
622 .bandwidth_update
= &rs600_bandwidth_update
,
623 .get_vblank_counter
= &rs600_get_vblank_counter
,
624 .wait_for_vblank
= &avivo_wait_for_vblank
,
625 .set_backlight_level
= &atombios_set_backlight_level
,
626 .get_backlight_level
= &atombios_get_backlight_level
,
627 .hdmi_enable
= &r600_hdmi_enable
,
628 .hdmi_setmode
= &r600_hdmi_setmode
,
631 .blit
= &r100_copy_blit
,
632 .blit_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
633 .dma
= &r200_copy_dma
,
634 .dma_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
635 .copy
= &r100_copy_blit
,
636 .copy_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
639 .set_reg
= r100_set_surface_reg
,
640 .clear_reg
= r100_clear_surface_reg
,
643 .init
= &rs600_hpd_init
,
644 .fini
= &rs600_hpd_fini
,
645 .sense
= &rs600_hpd_sense
,
646 .set_polarity
= &rs600_hpd_set_polarity
,
649 .misc
= &rs600_pm_misc
,
650 .prepare
= &rs600_pm_prepare
,
651 .finish
= &rs600_pm_finish
,
652 .init_profile
= &r420_pm_init_profile
,
653 .get_dynpm_state
= &r100_pm_get_dynpm_state
,
654 .get_engine_clock
= &radeon_atom_get_engine_clock
,
655 .set_engine_clock
= &radeon_atom_set_engine_clock
,
656 .get_memory_clock
= &radeon_atom_get_memory_clock
,
657 .set_memory_clock
= &radeon_atom_set_memory_clock
,
658 .get_pcie_lanes
= NULL
,
659 .set_pcie_lanes
= NULL
,
660 .set_clock_gating
= &radeon_atom_set_clock_gating
,
663 .page_flip
= &rs600_page_flip
,
664 .page_flip_pending
= &rs600_page_flip_pending
,
668 static struct radeon_asic rs690_asic
= {
671 .suspend
= &rs690_suspend
,
672 .resume
= &rs690_resume
,
673 .vga_set_state
= &r100_vga_set_state
,
674 .asic_reset
= &rs600_asic_reset
,
675 .ioctl_wait_idle
= NULL
,
676 .gui_idle
= &r100_gui_idle
,
677 .mc_wait_for_idle
= &rs690_mc_wait_for_idle
,
679 .tlb_flush
= &rs400_gart_tlb_flush
,
680 .set_page
= &rs400_gart_set_page
,
683 [RADEON_RING_TYPE_GFX_INDEX
] = &r300_gfx_ring
686 .set
= &rs600_irq_set
,
687 .process
= &rs600_irq_process
,
690 .get_vblank_counter
= &rs600_get_vblank_counter
,
691 .bandwidth_update
= &rs690_bandwidth_update
,
692 .wait_for_vblank
= &avivo_wait_for_vblank
,
693 .set_backlight_level
= &atombios_set_backlight_level
,
694 .get_backlight_level
= &atombios_get_backlight_level
,
695 .hdmi_enable
= &r600_hdmi_enable
,
696 .hdmi_setmode
= &r600_hdmi_setmode
,
699 .blit
= &r100_copy_blit
,
700 .blit_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
701 .dma
= &r200_copy_dma
,
702 .dma_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
703 .copy
= &r200_copy_dma
,
704 .copy_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
707 .set_reg
= r100_set_surface_reg
,
708 .clear_reg
= r100_clear_surface_reg
,
711 .init
= &rs600_hpd_init
,
712 .fini
= &rs600_hpd_fini
,
713 .sense
= &rs600_hpd_sense
,
714 .set_polarity
= &rs600_hpd_set_polarity
,
717 .misc
= &rs600_pm_misc
,
718 .prepare
= &rs600_pm_prepare
,
719 .finish
= &rs600_pm_finish
,
720 .init_profile
= &r420_pm_init_profile
,
721 .get_dynpm_state
= &r100_pm_get_dynpm_state
,
722 .get_engine_clock
= &radeon_atom_get_engine_clock
,
723 .set_engine_clock
= &radeon_atom_set_engine_clock
,
724 .get_memory_clock
= &radeon_atom_get_memory_clock
,
725 .set_memory_clock
= &radeon_atom_set_memory_clock
,
726 .get_pcie_lanes
= NULL
,
727 .set_pcie_lanes
= NULL
,
728 .set_clock_gating
= &radeon_atom_set_clock_gating
,
731 .page_flip
= &rs600_page_flip
,
732 .page_flip_pending
= &rs600_page_flip_pending
,
736 static struct radeon_asic rv515_asic
= {
739 .suspend
= &rv515_suspend
,
740 .resume
= &rv515_resume
,
741 .vga_set_state
= &r100_vga_set_state
,
742 .asic_reset
= &rs600_asic_reset
,
743 .ioctl_wait_idle
= NULL
,
744 .gui_idle
= &r100_gui_idle
,
745 .mc_wait_for_idle
= &rv515_mc_wait_for_idle
,
747 .tlb_flush
= &rv370_pcie_gart_tlb_flush
,
748 .set_page
= &rv370_pcie_gart_set_page
,
751 [RADEON_RING_TYPE_GFX_INDEX
] = &r300_gfx_ring
754 .set
= &rs600_irq_set
,
755 .process
= &rs600_irq_process
,
758 .get_vblank_counter
= &rs600_get_vblank_counter
,
759 .bandwidth_update
= &rv515_bandwidth_update
,
760 .wait_for_vblank
= &avivo_wait_for_vblank
,
761 .set_backlight_level
= &atombios_set_backlight_level
,
762 .get_backlight_level
= &atombios_get_backlight_level
,
765 .blit
= &r100_copy_blit
,
766 .blit_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
767 .dma
= &r200_copy_dma
,
768 .dma_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
769 .copy
= &r100_copy_blit
,
770 .copy_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
773 .set_reg
= r100_set_surface_reg
,
774 .clear_reg
= r100_clear_surface_reg
,
777 .init
= &rs600_hpd_init
,
778 .fini
= &rs600_hpd_fini
,
779 .sense
= &rs600_hpd_sense
,
780 .set_polarity
= &rs600_hpd_set_polarity
,
783 .misc
= &rs600_pm_misc
,
784 .prepare
= &rs600_pm_prepare
,
785 .finish
= &rs600_pm_finish
,
786 .init_profile
= &r420_pm_init_profile
,
787 .get_dynpm_state
= &r100_pm_get_dynpm_state
,
788 .get_engine_clock
= &radeon_atom_get_engine_clock
,
789 .set_engine_clock
= &radeon_atom_set_engine_clock
,
790 .get_memory_clock
= &radeon_atom_get_memory_clock
,
791 .set_memory_clock
= &radeon_atom_set_memory_clock
,
792 .get_pcie_lanes
= &rv370_get_pcie_lanes
,
793 .set_pcie_lanes
= &rv370_set_pcie_lanes
,
794 .set_clock_gating
= &radeon_atom_set_clock_gating
,
797 .page_flip
= &rs600_page_flip
,
798 .page_flip_pending
= &rs600_page_flip_pending
,
802 static struct radeon_asic r520_asic
= {
805 .suspend
= &rv515_suspend
,
806 .resume
= &r520_resume
,
807 .vga_set_state
= &r100_vga_set_state
,
808 .asic_reset
= &rs600_asic_reset
,
809 .ioctl_wait_idle
= NULL
,
810 .gui_idle
= &r100_gui_idle
,
811 .mc_wait_for_idle
= &r520_mc_wait_for_idle
,
813 .tlb_flush
= &rv370_pcie_gart_tlb_flush
,
814 .set_page
= &rv370_pcie_gart_set_page
,
817 [RADEON_RING_TYPE_GFX_INDEX
] = &r300_gfx_ring
820 .set
= &rs600_irq_set
,
821 .process
= &rs600_irq_process
,
824 .bandwidth_update
= &rv515_bandwidth_update
,
825 .get_vblank_counter
= &rs600_get_vblank_counter
,
826 .wait_for_vblank
= &avivo_wait_for_vblank
,
827 .set_backlight_level
= &atombios_set_backlight_level
,
828 .get_backlight_level
= &atombios_get_backlight_level
,
831 .blit
= &r100_copy_blit
,
832 .blit_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
833 .dma
= &r200_copy_dma
,
834 .dma_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
835 .copy
= &r100_copy_blit
,
836 .copy_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
839 .set_reg
= r100_set_surface_reg
,
840 .clear_reg
= r100_clear_surface_reg
,
843 .init
= &rs600_hpd_init
,
844 .fini
= &rs600_hpd_fini
,
845 .sense
= &rs600_hpd_sense
,
846 .set_polarity
= &rs600_hpd_set_polarity
,
849 .misc
= &rs600_pm_misc
,
850 .prepare
= &rs600_pm_prepare
,
851 .finish
= &rs600_pm_finish
,
852 .init_profile
= &r420_pm_init_profile
,
853 .get_dynpm_state
= &r100_pm_get_dynpm_state
,
854 .get_engine_clock
= &radeon_atom_get_engine_clock
,
855 .set_engine_clock
= &radeon_atom_set_engine_clock
,
856 .get_memory_clock
= &radeon_atom_get_memory_clock
,
857 .set_memory_clock
= &radeon_atom_set_memory_clock
,
858 .get_pcie_lanes
= &rv370_get_pcie_lanes
,
859 .set_pcie_lanes
= &rv370_set_pcie_lanes
,
860 .set_clock_gating
= &radeon_atom_set_clock_gating
,
863 .page_flip
= &rs600_page_flip
,
864 .page_flip_pending
= &rs600_page_flip_pending
,
868 static struct radeon_asic_ring r600_gfx_ring
= {
869 .ib_execute
= &r600_ring_ib_execute
,
870 .emit_fence
= &r600_fence_ring_emit
,
871 .emit_semaphore
= &r600_semaphore_ring_emit
,
872 .cs_parse
= &r600_cs_parse
,
873 .ring_test
= &r600_ring_test
,
874 .ib_test
= &r600_ib_test
,
875 .is_lockup
= &r600_gfx_is_lockup
,
876 .get_rptr
= &r600_gfx_get_rptr
,
877 .get_wptr
= &r600_gfx_get_wptr
,
878 .set_wptr
= &r600_gfx_set_wptr
,
881 static struct radeon_asic_ring r600_dma_ring
= {
882 .ib_execute
= &r600_dma_ring_ib_execute
,
883 .emit_fence
= &r600_dma_fence_ring_emit
,
884 .emit_semaphore
= &r600_dma_semaphore_ring_emit
,
885 .cs_parse
= &r600_dma_cs_parse
,
886 .ring_test
= &r600_dma_ring_test
,
887 .ib_test
= &r600_dma_ib_test
,
888 .is_lockup
= &r600_dma_is_lockup
,
889 .get_rptr
= &r600_dma_get_rptr
,
890 .get_wptr
= &r600_dma_get_wptr
,
891 .set_wptr
= &r600_dma_set_wptr
,
894 static struct radeon_asic r600_asic
= {
897 .suspend
= &r600_suspend
,
898 .resume
= &r600_resume
,
899 .vga_set_state
= &r600_vga_set_state
,
900 .asic_reset
= &r600_asic_reset
,
901 .ioctl_wait_idle
= r600_ioctl_wait_idle
,
902 .gui_idle
= &r600_gui_idle
,
903 .mc_wait_for_idle
= &r600_mc_wait_for_idle
,
904 .get_xclk
= &r600_get_xclk
,
905 .get_gpu_clock_counter
= &r600_get_gpu_clock_counter
,
907 .tlb_flush
= &r600_pcie_gart_tlb_flush
,
908 .set_page
= &rs600_gart_set_page
,
911 [RADEON_RING_TYPE_GFX_INDEX
] = &r600_gfx_ring
,
912 [R600_RING_TYPE_DMA_INDEX
] = &r600_dma_ring
,
915 .set
= &r600_irq_set
,
916 .process
= &r600_irq_process
,
919 .bandwidth_update
= &rv515_bandwidth_update
,
920 .get_vblank_counter
= &rs600_get_vblank_counter
,
921 .wait_for_vblank
= &avivo_wait_for_vblank
,
922 .set_backlight_level
= &atombios_set_backlight_level
,
923 .get_backlight_level
= &atombios_get_backlight_level
,
924 .hdmi_enable
= &r600_hdmi_enable
,
925 .hdmi_setmode
= &r600_hdmi_setmode
,
928 .blit
= &r600_copy_cpdma
,
929 .blit_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
930 .dma
= &r600_copy_dma
,
931 .dma_ring_index
= R600_RING_TYPE_DMA_INDEX
,
932 .copy
= &r600_copy_cpdma
,
933 .copy_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
936 .set_reg
= r600_set_surface_reg
,
937 .clear_reg
= r600_clear_surface_reg
,
940 .init
= &r600_hpd_init
,
941 .fini
= &r600_hpd_fini
,
942 .sense
= &r600_hpd_sense
,
943 .set_polarity
= &r600_hpd_set_polarity
,
946 .misc
= &r600_pm_misc
,
947 .prepare
= &rs600_pm_prepare
,
948 .finish
= &rs600_pm_finish
,
949 .init_profile
= &r600_pm_init_profile
,
950 .get_dynpm_state
= &r600_pm_get_dynpm_state
,
951 .get_engine_clock
= &radeon_atom_get_engine_clock
,
952 .set_engine_clock
= &radeon_atom_set_engine_clock
,
953 .get_memory_clock
= &radeon_atom_get_memory_clock
,
954 .set_memory_clock
= &radeon_atom_set_memory_clock
,
955 .get_pcie_lanes
= &r600_get_pcie_lanes
,
956 .set_pcie_lanes
= &r600_set_pcie_lanes
,
957 .set_clock_gating
= NULL
,
958 .get_temperature
= &rv6xx_get_temp
,
961 .page_flip
= &rs600_page_flip
,
962 .page_flip_pending
= &rs600_page_flip_pending
,
966 static struct radeon_asic rv6xx_asic
= {
969 .suspend
= &r600_suspend
,
970 .resume
= &r600_resume
,
971 .vga_set_state
= &r600_vga_set_state
,
972 .asic_reset
= &r600_asic_reset
,
973 .ioctl_wait_idle
= r600_ioctl_wait_idle
,
974 .gui_idle
= &r600_gui_idle
,
975 .mc_wait_for_idle
= &r600_mc_wait_for_idle
,
976 .get_xclk
= &r600_get_xclk
,
977 .get_gpu_clock_counter
= &r600_get_gpu_clock_counter
,
979 .tlb_flush
= &r600_pcie_gart_tlb_flush
,
980 .set_page
= &rs600_gart_set_page
,
983 [RADEON_RING_TYPE_GFX_INDEX
] = &r600_gfx_ring
,
984 [R600_RING_TYPE_DMA_INDEX
] = &r600_dma_ring
,
987 .set
= &r600_irq_set
,
988 .process
= &r600_irq_process
,
991 .bandwidth_update
= &rv515_bandwidth_update
,
992 .get_vblank_counter
= &rs600_get_vblank_counter
,
993 .wait_for_vblank
= &avivo_wait_for_vblank
,
994 .set_backlight_level
= &atombios_set_backlight_level
,
995 .get_backlight_level
= &atombios_get_backlight_level
,
996 .hdmi_enable
= &r600_hdmi_enable
,
997 .hdmi_setmode
= &r600_hdmi_setmode
,
1000 .blit
= &r600_copy_cpdma
,
1001 .blit_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
1002 .dma
= &r600_copy_dma
,
1003 .dma_ring_index
= R600_RING_TYPE_DMA_INDEX
,
1004 .copy
= &r600_copy_cpdma
,
1005 .copy_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
1008 .set_reg
= r600_set_surface_reg
,
1009 .clear_reg
= r600_clear_surface_reg
,
1012 .init
= &r600_hpd_init
,
1013 .fini
= &r600_hpd_fini
,
1014 .sense
= &r600_hpd_sense
,
1015 .set_polarity
= &r600_hpd_set_polarity
,
1018 .misc
= &r600_pm_misc
,
1019 .prepare
= &rs600_pm_prepare
,
1020 .finish
= &rs600_pm_finish
,
1021 .init_profile
= &r600_pm_init_profile
,
1022 .get_dynpm_state
= &r600_pm_get_dynpm_state
,
1023 .get_engine_clock
= &radeon_atom_get_engine_clock
,
1024 .set_engine_clock
= &radeon_atom_set_engine_clock
,
1025 .get_memory_clock
= &radeon_atom_get_memory_clock
,
1026 .set_memory_clock
= &radeon_atom_set_memory_clock
,
1027 .get_pcie_lanes
= &r600_get_pcie_lanes
,
1028 .set_pcie_lanes
= &r600_set_pcie_lanes
,
1029 .set_clock_gating
= NULL
,
1030 .get_temperature
= &rv6xx_get_temp
,
1031 .set_uvd_clocks
= &r600_set_uvd_clocks
,
1034 .init
= &rv6xx_dpm_init
,
1035 .setup_asic
= &rv6xx_setup_asic
,
1036 .enable
= &rv6xx_dpm_enable
,
1037 .late_enable
= &r600_dpm_late_enable
,
1038 .disable
= &rv6xx_dpm_disable
,
1039 .pre_set_power_state
= &r600_dpm_pre_set_power_state
,
1040 .set_power_state
= &rv6xx_dpm_set_power_state
,
1041 .post_set_power_state
= &r600_dpm_post_set_power_state
,
1042 .display_configuration_changed
= &rv6xx_dpm_display_configuration_changed
,
1043 .fini
= &rv6xx_dpm_fini
,
1044 .get_sclk
= &rv6xx_dpm_get_sclk
,
1045 .get_mclk
= &rv6xx_dpm_get_mclk
,
1046 .print_power_state
= &rv6xx_dpm_print_power_state
,
1047 .debugfs_print_current_performance_level
= &rv6xx_dpm_debugfs_print_current_performance_level
,
1048 .force_performance_level
= &rv6xx_dpm_force_performance_level
,
1051 .page_flip
= &rs600_page_flip
,
1052 .page_flip_pending
= &rs600_page_flip_pending
,
1056 static struct radeon_asic rs780_asic
= {
1059 .suspend
= &r600_suspend
,
1060 .resume
= &r600_resume
,
1061 .vga_set_state
= &r600_vga_set_state
,
1062 .asic_reset
= &r600_asic_reset
,
1063 .ioctl_wait_idle
= r600_ioctl_wait_idle
,
1064 .gui_idle
= &r600_gui_idle
,
1065 .mc_wait_for_idle
= &r600_mc_wait_for_idle
,
1066 .get_xclk
= &r600_get_xclk
,
1067 .get_gpu_clock_counter
= &r600_get_gpu_clock_counter
,
1069 .tlb_flush
= &r600_pcie_gart_tlb_flush
,
1070 .set_page
= &rs600_gart_set_page
,
1073 [RADEON_RING_TYPE_GFX_INDEX
] = &r600_gfx_ring
,
1074 [R600_RING_TYPE_DMA_INDEX
] = &r600_dma_ring
,
1077 .set
= &r600_irq_set
,
1078 .process
= &r600_irq_process
,
1081 .bandwidth_update
= &rs690_bandwidth_update
,
1082 .get_vblank_counter
= &rs600_get_vblank_counter
,
1083 .wait_for_vblank
= &avivo_wait_for_vblank
,
1084 .set_backlight_level
= &atombios_set_backlight_level
,
1085 .get_backlight_level
= &atombios_get_backlight_level
,
1086 .hdmi_enable
= &r600_hdmi_enable
,
1087 .hdmi_setmode
= &r600_hdmi_setmode
,
1090 .blit
= &r600_copy_cpdma
,
1091 .blit_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
1092 .dma
= &r600_copy_dma
,
1093 .dma_ring_index
= R600_RING_TYPE_DMA_INDEX
,
1094 .copy
= &r600_copy_cpdma
,
1095 .copy_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
1098 .set_reg
= r600_set_surface_reg
,
1099 .clear_reg
= r600_clear_surface_reg
,
1102 .init
= &r600_hpd_init
,
1103 .fini
= &r600_hpd_fini
,
1104 .sense
= &r600_hpd_sense
,
1105 .set_polarity
= &r600_hpd_set_polarity
,
1108 .misc
= &r600_pm_misc
,
1109 .prepare
= &rs600_pm_prepare
,
1110 .finish
= &rs600_pm_finish
,
1111 .init_profile
= &rs780_pm_init_profile
,
1112 .get_dynpm_state
= &r600_pm_get_dynpm_state
,
1113 .get_engine_clock
= &radeon_atom_get_engine_clock
,
1114 .set_engine_clock
= &radeon_atom_set_engine_clock
,
1115 .get_memory_clock
= NULL
,
1116 .set_memory_clock
= NULL
,
1117 .get_pcie_lanes
= NULL
,
1118 .set_pcie_lanes
= NULL
,
1119 .set_clock_gating
= NULL
,
1120 .get_temperature
= &rv6xx_get_temp
,
1121 .set_uvd_clocks
= &r600_set_uvd_clocks
,
1124 .init
= &rs780_dpm_init
,
1125 .setup_asic
= &rs780_dpm_setup_asic
,
1126 .enable
= &rs780_dpm_enable
,
1127 .late_enable
= &r600_dpm_late_enable
,
1128 .disable
= &rs780_dpm_disable
,
1129 .pre_set_power_state
= &r600_dpm_pre_set_power_state
,
1130 .set_power_state
= &rs780_dpm_set_power_state
,
1131 .post_set_power_state
= &r600_dpm_post_set_power_state
,
1132 .display_configuration_changed
= &rs780_dpm_display_configuration_changed
,
1133 .fini
= &rs780_dpm_fini
,
1134 .get_sclk
= &rs780_dpm_get_sclk
,
1135 .get_mclk
= &rs780_dpm_get_mclk
,
1136 .print_power_state
= &rs780_dpm_print_power_state
,
1137 .debugfs_print_current_performance_level
= &rs780_dpm_debugfs_print_current_performance_level
,
1138 .force_performance_level
= &rs780_dpm_force_performance_level
,
1141 .page_flip
= &rs600_page_flip
,
1142 .page_flip_pending
= &rs600_page_flip_pending
,
1146 static struct radeon_asic_ring rv770_uvd_ring
= {
1147 .ib_execute
= &uvd_v1_0_ib_execute
,
1148 .emit_fence
= &uvd_v2_2_fence_emit
,
1149 .emit_semaphore
= &uvd_v1_0_semaphore_emit
,
1150 .cs_parse
= &radeon_uvd_cs_parse
,
1151 .ring_test
= &uvd_v1_0_ring_test
,
1152 .ib_test
= &uvd_v1_0_ib_test
,
1153 .is_lockup
= &radeon_ring_test_lockup
,
1154 .get_rptr
= &uvd_v1_0_get_rptr
,
1155 .get_wptr
= &uvd_v1_0_get_wptr
,
1156 .set_wptr
= &uvd_v1_0_set_wptr
,
1159 static struct radeon_asic rv770_asic
= {
1160 .init
= &rv770_init
,
1161 .fini
= &rv770_fini
,
1162 .suspend
= &rv770_suspend
,
1163 .resume
= &rv770_resume
,
1164 .asic_reset
= &r600_asic_reset
,
1165 .vga_set_state
= &r600_vga_set_state
,
1166 .ioctl_wait_idle
= r600_ioctl_wait_idle
,
1167 .gui_idle
= &r600_gui_idle
,
1168 .mc_wait_for_idle
= &r600_mc_wait_for_idle
,
1169 .get_xclk
= &rv770_get_xclk
,
1170 .get_gpu_clock_counter
= &r600_get_gpu_clock_counter
,
1172 .tlb_flush
= &r600_pcie_gart_tlb_flush
,
1173 .set_page
= &rs600_gart_set_page
,
1176 [RADEON_RING_TYPE_GFX_INDEX
] = &r600_gfx_ring
,
1177 [R600_RING_TYPE_DMA_INDEX
] = &r600_dma_ring
,
1178 [R600_RING_TYPE_UVD_INDEX
] = &rv770_uvd_ring
,
1181 .set
= &r600_irq_set
,
1182 .process
= &r600_irq_process
,
1185 .bandwidth_update
= &rv515_bandwidth_update
,
1186 .get_vblank_counter
= &rs600_get_vblank_counter
,
1187 .wait_for_vblank
= &avivo_wait_for_vblank
,
1188 .set_backlight_level
= &atombios_set_backlight_level
,
1189 .get_backlight_level
= &atombios_get_backlight_level
,
1190 .hdmi_enable
= &r600_hdmi_enable
,
1191 .hdmi_setmode
= &dce3_1_hdmi_setmode
,
1194 .blit
= &r600_copy_cpdma
,
1195 .blit_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
1196 .dma
= &rv770_copy_dma
,
1197 .dma_ring_index
= R600_RING_TYPE_DMA_INDEX
,
1198 .copy
= &rv770_copy_dma
,
1199 .copy_ring_index
= R600_RING_TYPE_DMA_INDEX
,
1202 .set_reg
= r600_set_surface_reg
,
1203 .clear_reg
= r600_clear_surface_reg
,
1206 .init
= &r600_hpd_init
,
1207 .fini
= &r600_hpd_fini
,
1208 .sense
= &r600_hpd_sense
,
1209 .set_polarity
= &r600_hpd_set_polarity
,
1212 .misc
= &rv770_pm_misc
,
1213 .prepare
= &rs600_pm_prepare
,
1214 .finish
= &rs600_pm_finish
,
1215 .init_profile
= &r600_pm_init_profile
,
1216 .get_dynpm_state
= &r600_pm_get_dynpm_state
,
1217 .get_engine_clock
= &radeon_atom_get_engine_clock
,
1218 .set_engine_clock
= &radeon_atom_set_engine_clock
,
1219 .get_memory_clock
= &radeon_atom_get_memory_clock
,
1220 .set_memory_clock
= &radeon_atom_set_memory_clock
,
1221 .get_pcie_lanes
= &r600_get_pcie_lanes
,
1222 .set_pcie_lanes
= &r600_set_pcie_lanes
,
1223 .set_clock_gating
= &radeon_atom_set_clock_gating
,
1224 .set_uvd_clocks
= &rv770_set_uvd_clocks
,
1225 .get_temperature
= &rv770_get_temp
,
1228 .init
= &rv770_dpm_init
,
1229 .setup_asic
= &rv770_dpm_setup_asic
,
1230 .enable
= &rv770_dpm_enable
,
1231 .late_enable
= &rv770_dpm_late_enable
,
1232 .disable
= &rv770_dpm_disable
,
1233 .pre_set_power_state
= &r600_dpm_pre_set_power_state
,
1234 .set_power_state
= &rv770_dpm_set_power_state
,
1235 .post_set_power_state
= &r600_dpm_post_set_power_state
,
1236 .display_configuration_changed
= &rv770_dpm_display_configuration_changed
,
1237 .fini
= &rv770_dpm_fini
,
1238 .get_sclk
= &rv770_dpm_get_sclk
,
1239 .get_mclk
= &rv770_dpm_get_mclk
,
1240 .print_power_state
= &rv770_dpm_print_power_state
,
1241 .debugfs_print_current_performance_level
= &rv770_dpm_debugfs_print_current_performance_level
,
1242 .force_performance_level
= &rv770_dpm_force_performance_level
,
1243 .vblank_too_short
= &rv770_dpm_vblank_too_short
,
1246 .page_flip
= &rv770_page_flip
,
1247 .page_flip_pending
= &rv770_page_flip_pending
,
1251 static struct radeon_asic_ring evergreen_gfx_ring
= {
1252 .ib_execute
= &evergreen_ring_ib_execute
,
1253 .emit_fence
= &r600_fence_ring_emit
,
1254 .emit_semaphore
= &r600_semaphore_ring_emit
,
1255 .cs_parse
= &evergreen_cs_parse
,
1256 .ring_test
= &r600_ring_test
,
1257 .ib_test
= &r600_ib_test
,
1258 .is_lockup
= &evergreen_gfx_is_lockup
,
1259 .get_rptr
= &r600_gfx_get_rptr
,
1260 .get_wptr
= &r600_gfx_get_wptr
,
1261 .set_wptr
= &r600_gfx_set_wptr
,
1264 static struct radeon_asic_ring evergreen_dma_ring
= {
1265 .ib_execute
= &evergreen_dma_ring_ib_execute
,
1266 .emit_fence
= &evergreen_dma_fence_ring_emit
,
1267 .emit_semaphore
= &r600_dma_semaphore_ring_emit
,
1268 .cs_parse
= &evergreen_dma_cs_parse
,
1269 .ring_test
= &r600_dma_ring_test
,
1270 .ib_test
= &r600_dma_ib_test
,
1271 .is_lockup
= &evergreen_dma_is_lockup
,
1272 .get_rptr
= &r600_dma_get_rptr
,
1273 .get_wptr
= &r600_dma_get_wptr
,
1274 .set_wptr
= &r600_dma_set_wptr
,
1277 static struct radeon_asic evergreen_asic
= {
1278 .init
= &evergreen_init
,
1279 .fini
= &evergreen_fini
,
1280 .suspend
= &evergreen_suspend
,
1281 .resume
= &evergreen_resume
,
1282 .asic_reset
= &evergreen_asic_reset
,
1283 .vga_set_state
= &r600_vga_set_state
,
1284 .ioctl_wait_idle
= r600_ioctl_wait_idle
,
1285 .gui_idle
= &r600_gui_idle
,
1286 .mc_wait_for_idle
= &evergreen_mc_wait_for_idle
,
1287 .get_xclk
= &rv770_get_xclk
,
1288 .get_gpu_clock_counter
= &r600_get_gpu_clock_counter
,
1290 .tlb_flush
= &evergreen_pcie_gart_tlb_flush
,
1291 .set_page
= &rs600_gart_set_page
,
1294 [RADEON_RING_TYPE_GFX_INDEX
] = &evergreen_gfx_ring
,
1295 [R600_RING_TYPE_DMA_INDEX
] = &evergreen_dma_ring
,
1296 [R600_RING_TYPE_UVD_INDEX
] = &rv770_uvd_ring
,
1299 .set
= &evergreen_irq_set
,
1300 .process
= &evergreen_irq_process
,
1303 .bandwidth_update
= &evergreen_bandwidth_update
,
1304 .get_vblank_counter
= &evergreen_get_vblank_counter
,
1305 .wait_for_vblank
= &dce4_wait_for_vblank
,
1306 .set_backlight_level
= &atombios_set_backlight_level
,
1307 .get_backlight_level
= &atombios_get_backlight_level
,
1308 .hdmi_enable
= &evergreen_hdmi_enable
,
1309 .hdmi_setmode
= &evergreen_hdmi_setmode
,
1312 .blit
= &r600_copy_cpdma
,
1313 .blit_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
1314 .dma
= &evergreen_copy_dma
,
1315 .dma_ring_index
= R600_RING_TYPE_DMA_INDEX
,
1316 .copy
= &evergreen_copy_dma
,
1317 .copy_ring_index
= R600_RING_TYPE_DMA_INDEX
,
1320 .set_reg
= r600_set_surface_reg
,
1321 .clear_reg
= r600_clear_surface_reg
,
1324 .init
= &evergreen_hpd_init
,
1325 .fini
= &evergreen_hpd_fini
,
1326 .sense
= &evergreen_hpd_sense
,
1327 .set_polarity
= &evergreen_hpd_set_polarity
,
1330 .misc
= &evergreen_pm_misc
,
1331 .prepare
= &evergreen_pm_prepare
,
1332 .finish
= &evergreen_pm_finish
,
1333 .init_profile
= &r600_pm_init_profile
,
1334 .get_dynpm_state
= &r600_pm_get_dynpm_state
,
1335 .get_engine_clock
= &radeon_atom_get_engine_clock
,
1336 .set_engine_clock
= &radeon_atom_set_engine_clock
,
1337 .get_memory_clock
= &radeon_atom_get_memory_clock
,
1338 .set_memory_clock
= &radeon_atom_set_memory_clock
,
1339 .get_pcie_lanes
= &r600_get_pcie_lanes
,
1340 .set_pcie_lanes
= &r600_set_pcie_lanes
,
1341 .set_clock_gating
= NULL
,
1342 .set_uvd_clocks
= &evergreen_set_uvd_clocks
,
1343 .get_temperature
= &evergreen_get_temp
,
1346 .init
= &cypress_dpm_init
,
1347 .setup_asic
= &cypress_dpm_setup_asic
,
1348 .enable
= &cypress_dpm_enable
,
1349 .late_enable
= &rv770_dpm_late_enable
,
1350 .disable
= &cypress_dpm_disable
,
1351 .pre_set_power_state
= &r600_dpm_pre_set_power_state
,
1352 .set_power_state
= &cypress_dpm_set_power_state
,
1353 .post_set_power_state
= &r600_dpm_post_set_power_state
,
1354 .display_configuration_changed
= &cypress_dpm_display_configuration_changed
,
1355 .fini
= &cypress_dpm_fini
,
1356 .get_sclk
= &rv770_dpm_get_sclk
,
1357 .get_mclk
= &rv770_dpm_get_mclk
,
1358 .print_power_state
= &rv770_dpm_print_power_state
,
1359 .debugfs_print_current_performance_level
= &rv770_dpm_debugfs_print_current_performance_level
,
1360 .force_performance_level
= &rv770_dpm_force_performance_level
,
1361 .vblank_too_short
= &cypress_dpm_vblank_too_short
,
1364 .page_flip
= &evergreen_page_flip
,
1365 .page_flip_pending
= &evergreen_page_flip_pending
,
1369 static struct radeon_asic sumo_asic
= {
1370 .init
= &evergreen_init
,
1371 .fini
= &evergreen_fini
,
1372 .suspend
= &evergreen_suspend
,
1373 .resume
= &evergreen_resume
,
1374 .asic_reset
= &evergreen_asic_reset
,
1375 .vga_set_state
= &r600_vga_set_state
,
1376 .ioctl_wait_idle
= r600_ioctl_wait_idle
,
1377 .gui_idle
= &r600_gui_idle
,
1378 .mc_wait_for_idle
= &evergreen_mc_wait_for_idle
,
1379 .get_xclk
= &r600_get_xclk
,
1380 .get_gpu_clock_counter
= &r600_get_gpu_clock_counter
,
1382 .tlb_flush
= &evergreen_pcie_gart_tlb_flush
,
1383 .set_page
= &rs600_gart_set_page
,
1386 [RADEON_RING_TYPE_GFX_INDEX
] = &evergreen_gfx_ring
,
1387 [R600_RING_TYPE_DMA_INDEX
] = &evergreen_dma_ring
,
1388 [R600_RING_TYPE_UVD_INDEX
] = &rv770_uvd_ring
,
1391 .set
= &evergreen_irq_set
,
1392 .process
= &evergreen_irq_process
,
1395 .bandwidth_update
= &evergreen_bandwidth_update
,
1396 .get_vblank_counter
= &evergreen_get_vblank_counter
,
1397 .wait_for_vblank
= &dce4_wait_for_vblank
,
1398 .set_backlight_level
= &atombios_set_backlight_level
,
1399 .get_backlight_level
= &atombios_get_backlight_level
,
1400 .hdmi_enable
= &evergreen_hdmi_enable
,
1401 .hdmi_setmode
= &evergreen_hdmi_setmode
,
1404 .blit
= &r600_copy_cpdma
,
1405 .blit_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
1406 .dma
= &evergreen_copy_dma
,
1407 .dma_ring_index
= R600_RING_TYPE_DMA_INDEX
,
1408 .copy
= &evergreen_copy_dma
,
1409 .copy_ring_index
= R600_RING_TYPE_DMA_INDEX
,
1412 .set_reg
= r600_set_surface_reg
,
1413 .clear_reg
= r600_clear_surface_reg
,
1416 .init
= &evergreen_hpd_init
,
1417 .fini
= &evergreen_hpd_fini
,
1418 .sense
= &evergreen_hpd_sense
,
1419 .set_polarity
= &evergreen_hpd_set_polarity
,
1422 .misc
= &evergreen_pm_misc
,
1423 .prepare
= &evergreen_pm_prepare
,
1424 .finish
= &evergreen_pm_finish
,
1425 .init_profile
= &sumo_pm_init_profile
,
1426 .get_dynpm_state
= &r600_pm_get_dynpm_state
,
1427 .get_engine_clock
= &radeon_atom_get_engine_clock
,
1428 .set_engine_clock
= &radeon_atom_set_engine_clock
,
1429 .get_memory_clock
= NULL
,
1430 .set_memory_clock
= NULL
,
1431 .get_pcie_lanes
= NULL
,
1432 .set_pcie_lanes
= NULL
,
1433 .set_clock_gating
= NULL
,
1434 .set_uvd_clocks
= &sumo_set_uvd_clocks
,
1435 .get_temperature
= &sumo_get_temp
,
1438 .init
= &sumo_dpm_init
,
1439 .setup_asic
= &sumo_dpm_setup_asic
,
1440 .enable
= &sumo_dpm_enable
,
1441 .late_enable
= &sumo_dpm_late_enable
,
1442 .disable
= &sumo_dpm_disable
,
1443 .pre_set_power_state
= &sumo_dpm_pre_set_power_state
,
1444 .set_power_state
= &sumo_dpm_set_power_state
,
1445 .post_set_power_state
= &sumo_dpm_post_set_power_state
,
1446 .display_configuration_changed
= &sumo_dpm_display_configuration_changed
,
1447 .fini
= &sumo_dpm_fini
,
1448 .get_sclk
= &sumo_dpm_get_sclk
,
1449 .get_mclk
= &sumo_dpm_get_mclk
,
1450 .print_power_state
= &sumo_dpm_print_power_state
,
1451 .debugfs_print_current_performance_level
= &sumo_dpm_debugfs_print_current_performance_level
,
1452 .force_performance_level
= &sumo_dpm_force_performance_level
,
1455 .page_flip
= &evergreen_page_flip
,
1456 .page_flip_pending
= &evergreen_page_flip_pending
,
1460 static struct radeon_asic btc_asic
= {
1461 .init
= &evergreen_init
,
1462 .fini
= &evergreen_fini
,
1463 .suspend
= &evergreen_suspend
,
1464 .resume
= &evergreen_resume
,
1465 .asic_reset
= &evergreen_asic_reset
,
1466 .vga_set_state
= &r600_vga_set_state
,
1467 .ioctl_wait_idle
= r600_ioctl_wait_idle
,
1468 .gui_idle
= &r600_gui_idle
,
1469 .mc_wait_for_idle
= &evergreen_mc_wait_for_idle
,
1470 .get_xclk
= &rv770_get_xclk
,
1471 .get_gpu_clock_counter
= &r600_get_gpu_clock_counter
,
1473 .tlb_flush
= &evergreen_pcie_gart_tlb_flush
,
1474 .set_page
= &rs600_gart_set_page
,
1477 [RADEON_RING_TYPE_GFX_INDEX
] = &evergreen_gfx_ring
,
1478 [R600_RING_TYPE_DMA_INDEX
] = &evergreen_dma_ring
,
1479 [R600_RING_TYPE_UVD_INDEX
] = &rv770_uvd_ring
,
1482 .set
= &evergreen_irq_set
,
1483 .process
= &evergreen_irq_process
,
1486 .bandwidth_update
= &evergreen_bandwidth_update
,
1487 .get_vblank_counter
= &evergreen_get_vblank_counter
,
1488 .wait_for_vblank
= &dce4_wait_for_vblank
,
1489 .set_backlight_level
= &atombios_set_backlight_level
,
1490 .get_backlight_level
= &atombios_get_backlight_level
,
1491 .hdmi_enable
= &evergreen_hdmi_enable
,
1492 .hdmi_setmode
= &evergreen_hdmi_setmode
,
1495 .blit
= &r600_copy_cpdma
,
1496 .blit_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
1497 .dma
= &evergreen_copy_dma
,
1498 .dma_ring_index
= R600_RING_TYPE_DMA_INDEX
,
1499 .copy
= &evergreen_copy_dma
,
1500 .copy_ring_index
= R600_RING_TYPE_DMA_INDEX
,
1503 .set_reg
= r600_set_surface_reg
,
1504 .clear_reg
= r600_clear_surface_reg
,
1507 .init
= &evergreen_hpd_init
,
1508 .fini
= &evergreen_hpd_fini
,
1509 .sense
= &evergreen_hpd_sense
,
1510 .set_polarity
= &evergreen_hpd_set_polarity
,
1513 .misc
= &evergreen_pm_misc
,
1514 .prepare
= &evergreen_pm_prepare
,
1515 .finish
= &evergreen_pm_finish
,
1516 .init_profile
= &btc_pm_init_profile
,
1517 .get_dynpm_state
= &r600_pm_get_dynpm_state
,
1518 .get_engine_clock
= &radeon_atom_get_engine_clock
,
1519 .set_engine_clock
= &radeon_atom_set_engine_clock
,
1520 .get_memory_clock
= &radeon_atom_get_memory_clock
,
1521 .set_memory_clock
= &radeon_atom_set_memory_clock
,
1522 .get_pcie_lanes
= &r600_get_pcie_lanes
,
1523 .set_pcie_lanes
= &r600_set_pcie_lanes
,
1524 .set_clock_gating
= NULL
,
1525 .set_uvd_clocks
= &evergreen_set_uvd_clocks
,
1526 .get_temperature
= &evergreen_get_temp
,
1529 .init
= &btc_dpm_init
,
1530 .setup_asic
= &btc_dpm_setup_asic
,
1531 .enable
= &btc_dpm_enable
,
1532 .late_enable
= &rv770_dpm_late_enable
,
1533 .disable
= &btc_dpm_disable
,
1534 .pre_set_power_state
= &btc_dpm_pre_set_power_state
,
1535 .set_power_state
= &btc_dpm_set_power_state
,
1536 .post_set_power_state
= &btc_dpm_post_set_power_state
,
1537 .display_configuration_changed
= &cypress_dpm_display_configuration_changed
,
1538 .fini
= &btc_dpm_fini
,
1539 .get_sclk
= &btc_dpm_get_sclk
,
1540 .get_mclk
= &btc_dpm_get_mclk
,
1541 .print_power_state
= &rv770_dpm_print_power_state
,
1542 .debugfs_print_current_performance_level
= &btc_dpm_debugfs_print_current_performance_level
,
1543 .force_performance_level
= &rv770_dpm_force_performance_level
,
1544 .vblank_too_short
= &btc_dpm_vblank_too_short
,
1547 .page_flip
= &evergreen_page_flip
,
1548 .page_flip_pending
= &evergreen_page_flip_pending
,
1552 static struct radeon_asic_ring cayman_gfx_ring
= {
1553 .ib_execute
= &cayman_ring_ib_execute
,
1554 .ib_parse
= &evergreen_ib_parse
,
1555 .emit_fence
= &cayman_fence_ring_emit
,
1556 .emit_semaphore
= &r600_semaphore_ring_emit
,
1557 .cs_parse
= &evergreen_cs_parse
,
1558 .ring_test
= &r600_ring_test
,
1559 .ib_test
= &r600_ib_test
,
1560 .is_lockup
= &cayman_gfx_is_lockup
,
1561 .vm_flush
= &cayman_vm_flush
,
1562 .get_rptr
= &cayman_gfx_get_rptr
,
1563 .get_wptr
= &cayman_gfx_get_wptr
,
1564 .set_wptr
= &cayman_gfx_set_wptr
,
1567 static struct radeon_asic_ring cayman_dma_ring
= {
1568 .ib_execute
= &cayman_dma_ring_ib_execute
,
1569 .ib_parse
= &evergreen_dma_ib_parse
,
1570 .emit_fence
= &evergreen_dma_fence_ring_emit
,
1571 .emit_semaphore
= &r600_dma_semaphore_ring_emit
,
1572 .cs_parse
= &evergreen_dma_cs_parse
,
1573 .ring_test
= &r600_dma_ring_test
,
1574 .ib_test
= &r600_dma_ib_test
,
1575 .is_lockup
= &cayman_dma_is_lockup
,
1576 .vm_flush
= &cayman_dma_vm_flush
,
1577 .get_rptr
= &cayman_dma_get_rptr
,
1578 .get_wptr
= &cayman_dma_get_wptr
,
1579 .set_wptr
= &cayman_dma_set_wptr
1582 static struct radeon_asic_ring cayman_uvd_ring
= {
1583 .ib_execute
= &uvd_v1_0_ib_execute
,
1584 .emit_fence
= &uvd_v2_2_fence_emit
,
1585 .emit_semaphore
= &uvd_v3_1_semaphore_emit
,
1586 .cs_parse
= &radeon_uvd_cs_parse
,
1587 .ring_test
= &uvd_v1_0_ring_test
,
1588 .ib_test
= &uvd_v1_0_ib_test
,
1589 .is_lockup
= &radeon_ring_test_lockup
,
1590 .get_rptr
= &uvd_v1_0_get_rptr
,
1591 .get_wptr
= &uvd_v1_0_get_wptr
,
1592 .set_wptr
= &uvd_v1_0_set_wptr
,
1595 static struct radeon_asic cayman_asic
= {
1596 .init
= &cayman_init
,
1597 .fini
= &cayman_fini
,
1598 .suspend
= &cayman_suspend
,
1599 .resume
= &cayman_resume
,
1600 .asic_reset
= &cayman_asic_reset
,
1601 .vga_set_state
= &r600_vga_set_state
,
1602 .ioctl_wait_idle
= r600_ioctl_wait_idle
,
1603 .gui_idle
= &r600_gui_idle
,
1604 .mc_wait_for_idle
= &evergreen_mc_wait_for_idle
,
1605 .get_xclk
= &rv770_get_xclk
,
1606 .get_gpu_clock_counter
= &r600_get_gpu_clock_counter
,
1608 .tlb_flush
= &cayman_pcie_gart_tlb_flush
,
1609 .set_page
= &rs600_gart_set_page
,
1612 .init
= &cayman_vm_init
,
1613 .fini
= &cayman_vm_fini
,
1614 .set_page
= &cayman_dma_vm_set_page
,
1617 [RADEON_RING_TYPE_GFX_INDEX
] = &cayman_gfx_ring
,
1618 [CAYMAN_RING_TYPE_CP1_INDEX
] = &cayman_gfx_ring
,
1619 [CAYMAN_RING_TYPE_CP2_INDEX
] = &cayman_gfx_ring
,
1620 [R600_RING_TYPE_DMA_INDEX
] = &cayman_dma_ring
,
1621 [CAYMAN_RING_TYPE_DMA1_INDEX
] = &cayman_dma_ring
,
1622 [R600_RING_TYPE_UVD_INDEX
] = &cayman_uvd_ring
,
1625 .set
= &evergreen_irq_set
,
1626 .process
= &evergreen_irq_process
,
1629 .bandwidth_update
= &evergreen_bandwidth_update
,
1630 .get_vblank_counter
= &evergreen_get_vblank_counter
,
1631 .wait_for_vblank
= &dce4_wait_for_vblank
,
1632 .set_backlight_level
= &atombios_set_backlight_level
,
1633 .get_backlight_level
= &atombios_get_backlight_level
,
1634 .hdmi_enable
= &evergreen_hdmi_enable
,
1635 .hdmi_setmode
= &evergreen_hdmi_setmode
,
1638 .blit
= &r600_copy_cpdma
,
1639 .blit_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
1640 .dma
= &evergreen_copy_dma
,
1641 .dma_ring_index
= R600_RING_TYPE_DMA_INDEX
,
1642 .copy
= &evergreen_copy_dma
,
1643 .copy_ring_index
= R600_RING_TYPE_DMA_INDEX
,
1646 .set_reg
= r600_set_surface_reg
,
1647 .clear_reg
= r600_clear_surface_reg
,
1650 .init
= &evergreen_hpd_init
,
1651 .fini
= &evergreen_hpd_fini
,
1652 .sense
= &evergreen_hpd_sense
,
1653 .set_polarity
= &evergreen_hpd_set_polarity
,
1656 .misc
= &evergreen_pm_misc
,
1657 .prepare
= &evergreen_pm_prepare
,
1658 .finish
= &evergreen_pm_finish
,
1659 .init_profile
= &btc_pm_init_profile
,
1660 .get_dynpm_state
= &r600_pm_get_dynpm_state
,
1661 .get_engine_clock
= &radeon_atom_get_engine_clock
,
1662 .set_engine_clock
= &radeon_atom_set_engine_clock
,
1663 .get_memory_clock
= &radeon_atom_get_memory_clock
,
1664 .set_memory_clock
= &radeon_atom_set_memory_clock
,
1665 .get_pcie_lanes
= &r600_get_pcie_lanes
,
1666 .set_pcie_lanes
= &r600_set_pcie_lanes
,
1667 .set_clock_gating
= NULL
,
1668 .set_uvd_clocks
= &evergreen_set_uvd_clocks
,
1669 .get_temperature
= &evergreen_get_temp
,
1672 .init
= &ni_dpm_init
,
1673 .setup_asic
= &ni_dpm_setup_asic
,
1674 .enable
= &ni_dpm_enable
,
1675 .late_enable
= &rv770_dpm_late_enable
,
1676 .disable
= &ni_dpm_disable
,
1677 .pre_set_power_state
= &ni_dpm_pre_set_power_state
,
1678 .set_power_state
= &ni_dpm_set_power_state
,
1679 .post_set_power_state
= &ni_dpm_post_set_power_state
,
1680 .display_configuration_changed
= &cypress_dpm_display_configuration_changed
,
1681 .fini
= &ni_dpm_fini
,
1682 .get_sclk
= &ni_dpm_get_sclk
,
1683 .get_mclk
= &ni_dpm_get_mclk
,
1684 .print_power_state
= &ni_dpm_print_power_state
,
1685 .debugfs_print_current_performance_level
= &ni_dpm_debugfs_print_current_performance_level
,
1686 .force_performance_level
= &ni_dpm_force_performance_level
,
1687 .vblank_too_short
= &ni_dpm_vblank_too_short
,
1690 .page_flip
= &evergreen_page_flip
,
1691 .page_flip_pending
= &evergreen_page_flip_pending
,
1695 static struct radeon_asic trinity_asic
= {
1696 .init
= &cayman_init
,
1697 .fini
= &cayman_fini
,
1698 .suspend
= &cayman_suspend
,
1699 .resume
= &cayman_resume
,
1700 .asic_reset
= &cayman_asic_reset
,
1701 .vga_set_state
= &r600_vga_set_state
,
1702 .ioctl_wait_idle
= r600_ioctl_wait_idle
,
1703 .gui_idle
= &r600_gui_idle
,
1704 .mc_wait_for_idle
= &evergreen_mc_wait_for_idle
,
1705 .get_xclk
= &r600_get_xclk
,
1706 .get_gpu_clock_counter
= &r600_get_gpu_clock_counter
,
1708 .tlb_flush
= &cayman_pcie_gart_tlb_flush
,
1709 .set_page
= &rs600_gart_set_page
,
1712 .init
= &cayman_vm_init
,
1713 .fini
= &cayman_vm_fini
,
1714 .set_page
= &cayman_dma_vm_set_page
,
1717 [RADEON_RING_TYPE_GFX_INDEX
] = &cayman_gfx_ring
,
1718 [CAYMAN_RING_TYPE_CP1_INDEX
] = &cayman_gfx_ring
,
1719 [CAYMAN_RING_TYPE_CP2_INDEX
] = &cayman_gfx_ring
,
1720 [R600_RING_TYPE_DMA_INDEX
] = &cayman_dma_ring
,
1721 [CAYMAN_RING_TYPE_DMA1_INDEX
] = &cayman_dma_ring
,
1722 [R600_RING_TYPE_UVD_INDEX
] = &cayman_uvd_ring
,
1725 .set
= &evergreen_irq_set
,
1726 .process
= &evergreen_irq_process
,
1729 .bandwidth_update
= &dce6_bandwidth_update
,
1730 .get_vblank_counter
= &evergreen_get_vblank_counter
,
1731 .wait_for_vblank
= &dce4_wait_for_vblank
,
1732 .set_backlight_level
= &atombios_set_backlight_level
,
1733 .get_backlight_level
= &atombios_get_backlight_level
,
1734 .hdmi_enable
= &evergreen_hdmi_enable
,
1735 .hdmi_setmode
= &evergreen_hdmi_setmode
,
1738 .blit
= &r600_copy_cpdma
,
1739 .blit_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
1740 .dma
= &evergreen_copy_dma
,
1741 .dma_ring_index
= R600_RING_TYPE_DMA_INDEX
,
1742 .copy
= &evergreen_copy_dma
,
1743 .copy_ring_index
= R600_RING_TYPE_DMA_INDEX
,
1746 .set_reg
= r600_set_surface_reg
,
1747 .clear_reg
= r600_clear_surface_reg
,
1750 .init
= &evergreen_hpd_init
,
1751 .fini
= &evergreen_hpd_fini
,
1752 .sense
= &evergreen_hpd_sense
,
1753 .set_polarity
= &evergreen_hpd_set_polarity
,
1756 .misc
= &evergreen_pm_misc
,
1757 .prepare
= &evergreen_pm_prepare
,
1758 .finish
= &evergreen_pm_finish
,
1759 .init_profile
= &sumo_pm_init_profile
,
1760 .get_dynpm_state
= &r600_pm_get_dynpm_state
,
1761 .get_engine_clock
= &radeon_atom_get_engine_clock
,
1762 .set_engine_clock
= &radeon_atom_set_engine_clock
,
1763 .get_memory_clock
= NULL
,
1764 .set_memory_clock
= NULL
,
1765 .get_pcie_lanes
= NULL
,
1766 .set_pcie_lanes
= NULL
,
1767 .set_clock_gating
= NULL
,
1768 .set_uvd_clocks
= &sumo_set_uvd_clocks
,
1769 .get_temperature
= &tn_get_temp
,
1772 .init
= &trinity_dpm_init
,
1773 .setup_asic
= &trinity_dpm_setup_asic
,
1774 .enable
= &trinity_dpm_enable
,
1775 .late_enable
= &trinity_dpm_late_enable
,
1776 .disable
= &trinity_dpm_disable
,
1777 .pre_set_power_state
= &trinity_dpm_pre_set_power_state
,
1778 .set_power_state
= &trinity_dpm_set_power_state
,
1779 .post_set_power_state
= &trinity_dpm_post_set_power_state
,
1780 .display_configuration_changed
= &trinity_dpm_display_configuration_changed
,
1781 .fini
= &trinity_dpm_fini
,
1782 .get_sclk
= &trinity_dpm_get_sclk
,
1783 .get_mclk
= &trinity_dpm_get_mclk
,
1784 .print_power_state
= &trinity_dpm_print_power_state
,
1785 .debugfs_print_current_performance_level
= &trinity_dpm_debugfs_print_current_performance_level
,
1786 .force_performance_level
= &trinity_dpm_force_performance_level
,
1787 .enable_bapm
= &trinity_dpm_enable_bapm
,
1790 .page_flip
= &evergreen_page_flip
,
1791 .page_flip_pending
= &evergreen_page_flip_pending
,
1795 static struct radeon_asic_ring si_gfx_ring
= {
1796 .ib_execute
= &si_ring_ib_execute
,
1797 .ib_parse
= &si_ib_parse
,
1798 .emit_fence
= &si_fence_ring_emit
,
1799 .emit_semaphore
= &r600_semaphore_ring_emit
,
1801 .ring_test
= &r600_ring_test
,
1802 .ib_test
= &r600_ib_test
,
1803 .is_lockup
= &si_gfx_is_lockup
,
1804 .vm_flush
= &si_vm_flush
,
1805 .get_rptr
= &cayman_gfx_get_rptr
,
1806 .get_wptr
= &cayman_gfx_get_wptr
,
1807 .set_wptr
= &cayman_gfx_set_wptr
,
1810 static struct radeon_asic_ring si_dma_ring
= {
1811 .ib_execute
= &cayman_dma_ring_ib_execute
,
1812 .ib_parse
= &evergreen_dma_ib_parse
,
1813 .emit_fence
= &evergreen_dma_fence_ring_emit
,
1814 .emit_semaphore
= &r600_dma_semaphore_ring_emit
,
1816 .ring_test
= &r600_dma_ring_test
,
1817 .ib_test
= &r600_dma_ib_test
,
1818 .is_lockup
= &si_dma_is_lockup
,
1819 .vm_flush
= &si_dma_vm_flush
,
1820 .get_rptr
= &cayman_dma_get_rptr
,
1821 .get_wptr
= &cayman_dma_get_wptr
,
1822 .set_wptr
= &cayman_dma_set_wptr
,
1825 static struct radeon_asic si_asic
= {
1828 .suspend
= &si_suspend
,
1829 .resume
= &si_resume
,
1830 .asic_reset
= &si_asic_reset
,
1831 .vga_set_state
= &r600_vga_set_state
,
1832 .ioctl_wait_idle
= r600_ioctl_wait_idle
,
1833 .gui_idle
= &r600_gui_idle
,
1834 .mc_wait_for_idle
= &evergreen_mc_wait_for_idle
,
1835 .get_xclk
= &si_get_xclk
,
1836 .get_gpu_clock_counter
= &si_get_gpu_clock_counter
,
1838 .tlb_flush
= &si_pcie_gart_tlb_flush
,
1839 .set_page
= &rs600_gart_set_page
,
1842 .init
= &si_vm_init
,
1843 .fini
= &si_vm_fini
,
1844 .set_page
= &si_dma_vm_set_page
,
1847 [RADEON_RING_TYPE_GFX_INDEX
] = &si_gfx_ring
,
1848 [CAYMAN_RING_TYPE_CP1_INDEX
] = &si_gfx_ring
,
1849 [CAYMAN_RING_TYPE_CP2_INDEX
] = &si_gfx_ring
,
1850 [R600_RING_TYPE_DMA_INDEX
] = &si_dma_ring
,
1851 [CAYMAN_RING_TYPE_DMA1_INDEX
] = &si_dma_ring
,
1852 [R600_RING_TYPE_UVD_INDEX
] = &cayman_uvd_ring
,
1856 .process
= &si_irq_process
,
1859 .bandwidth_update
= &dce6_bandwidth_update
,
1860 .get_vblank_counter
= &evergreen_get_vblank_counter
,
1861 .wait_for_vblank
= &dce4_wait_for_vblank
,
1862 .set_backlight_level
= &atombios_set_backlight_level
,
1863 .get_backlight_level
= &atombios_get_backlight_level
,
1864 .hdmi_enable
= &evergreen_hdmi_enable
,
1865 .hdmi_setmode
= &evergreen_hdmi_setmode
,
1868 .blit
= &r600_copy_cpdma
,
1869 .blit_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
1870 .dma
= &si_copy_dma
,
1871 .dma_ring_index
= R600_RING_TYPE_DMA_INDEX
,
1872 .copy
= &si_copy_dma
,
1873 .copy_ring_index
= R600_RING_TYPE_DMA_INDEX
,
1876 .set_reg
= r600_set_surface_reg
,
1877 .clear_reg
= r600_clear_surface_reg
,
1880 .init
= &evergreen_hpd_init
,
1881 .fini
= &evergreen_hpd_fini
,
1882 .sense
= &evergreen_hpd_sense
,
1883 .set_polarity
= &evergreen_hpd_set_polarity
,
1886 .misc
= &evergreen_pm_misc
,
1887 .prepare
= &evergreen_pm_prepare
,
1888 .finish
= &evergreen_pm_finish
,
1889 .init_profile
= &sumo_pm_init_profile
,
1890 .get_dynpm_state
= &r600_pm_get_dynpm_state
,
1891 .get_engine_clock
= &radeon_atom_get_engine_clock
,
1892 .set_engine_clock
= &radeon_atom_set_engine_clock
,
1893 .get_memory_clock
= &radeon_atom_get_memory_clock
,
1894 .set_memory_clock
= &radeon_atom_set_memory_clock
,
1895 .get_pcie_lanes
= &r600_get_pcie_lanes
,
1896 .set_pcie_lanes
= &r600_set_pcie_lanes
,
1897 .set_clock_gating
= NULL
,
1898 .set_uvd_clocks
= &si_set_uvd_clocks
,
1899 .get_temperature
= &si_get_temp
,
1902 .init
= &si_dpm_init
,
1903 .setup_asic
= &si_dpm_setup_asic
,
1904 .enable
= &si_dpm_enable
,
1905 .late_enable
= &si_dpm_late_enable
,
1906 .disable
= &si_dpm_disable
,
1907 .pre_set_power_state
= &si_dpm_pre_set_power_state
,
1908 .set_power_state
= &si_dpm_set_power_state
,
1909 .post_set_power_state
= &si_dpm_post_set_power_state
,
1910 .display_configuration_changed
= &si_dpm_display_configuration_changed
,
1911 .fini
= &si_dpm_fini
,
1912 .get_sclk
= &ni_dpm_get_sclk
,
1913 .get_mclk
= &ni_dpm_get_mclk
,
1914 .print_power_state
= &ni_dpm_print_power_state
,
1915 .debugfs_print_current_performance_level
= &si_dpm_debugfs_print_current_performance_level
,
1916 .force_performance_level
= &si_dpm_force_performance_level
,
1917 .vblank_too_short
= &ni_dpm_vblank_too_short
,
1920 .page_flip
= &evergreen_page_flip
,
1921 .page_flip_pending
= &evergreen_page_flip_pending
,
1925 static struct radeon_asic_ring ci_gfx_ring
= {
1926 .ib_execute
= &cik_ring_ib_execute
,
1927 .ib_parse
= &cik_ib_parse
,
1928 .emit_fence
= &cik_fence_gfx_ring_emit
,
1929 .emit_semaphore
= &cik_semaphore_ring_emit
,
1931 .ring_test
= &cik_ring_test
,
1932 .ib_test
= &cik_ib_test
,
1933 .is_lockup
= &cik_gfx_is_lockup
,
1934 .vm_flush
= &cik_vm_flush
,
1935 .get_rptr
= &cik_gfx_get_rptr
,
1936 .get_wptr
= &cik_gfx_get_wptr
,
1937 .set_wptr
= &cik_gfx_set_wptr
,
1940 static struct radeon_asic_ring ci_cp_ring
= {
1941 .ib_execute
= &cik_ring_ib_execute
,
1942 .ib_parse
= &cik_ib_parse
,
1943 .emit_fence
= &cik_fence_compute_ring_emit
,
1944 .emit_semaphore
= &cik_semaphore_ring_emit
,
1946 .ring_test
= &cik_ring_test
,
1947 .ib_test
= &cik_ib_test
,
1948 .is_lockup
= &cik_gfx_is_lockup
,
1949 .vm_flush
= &cik_vm_flush
,
1950 .get_rptr
= &cik_compute_get_rptr
,
1951 .get_wptr
= &cik_compute_get_wptr
,
1952 .set_wptr
= &cik_compute_set_wptr
,
1955 static struct radeon_asic_ring ci_dma_ring
= {
1956 .ib_execute
= &cik_sdma_ring_ib_execute
,
1957 .ib_parse
= &cik_ib_parse
,
1958 .emit_fence
= &cik_sdma_fence_ring_emit
,
1959 .emit_semaphore
= &cik_sdma_semaphore_ring_emit
,
1961 .ring_test
= &cik_sdma_ring_test
,
1962 .ib_test
= &cik_sdma_ib_test
,
1963 .is_lockup
= &cik_sdma_is_lockup
,
1964 .vm_flush
= &cik_dma_vm_flush
,
1965 .get_rptr
= &cik_sdma_get_rptr
,
1966 .get_wptr
= &cik_sdma_get_wptr
,
1967 .set_wptr
= &cik_sdma_set_wptr
,
1970 static struct radeon_asic_ring ci_vce_ring
= {
1971 .ib_execute
= &radeon_vce_ib_execute
,
1972 .emit_fence
= &radeon_vce_fence_emit
,
1973 .emit_semaphore
= &radeon_vce_semaphore_emit
,
1974 .cs_parse
= &radeon_vce_cs_parse
,
1975 .ring_test
= &radeon_vce_ring_test
,
1976 .ib_test
= &radeon_vce_ib_test
,
1977 .is_lockup
= &radeon_ring_test_lockup
,
1978 .get_rptr
= &vce_v1_0_get_rptr
,
1979 .get_wptr
= &vce_v1_0_get_wptr
,
1980 .set_wptr
= &vce_v1_0_set_wptr
,
1983 static struct radeon_asic ci_asic
= {
1986 .suspend
= &cik_suspend
,
1987 .resume
= &cik_resume
,
1988 .asic_reset
= &cik_asic_reset
,
1989 .vga_set_state
= &r600_vga_set_state
,
1990 .ioctl_wait_idle
= NULL
,
1991 .gui_idle
= &r600_gui_idle
,
1992 .mc_wait_for_idle
= &evergreen_mc_wait_for_idle
,
1993 .get_xclk
= &cik_get_xclk
,
1994 .get_gpu_clock_counter
= &cik_get_gpu_clock_counter
,
1996 .tlb_flush
= &cik_pcie_gart_tlb_flush
,
1997 .set_page
= &rs600_gart_set_page
,
2000 .init
= &cik_vm_init
,
2001 .fini
= &cik_vm_fini
,
2002 .set_page
= &cik_sdma_vm_set_page
,
2005 [RADEON_RING_TYPE_GFX_INDEX
] = &ci_gfx_ring
,
2006 [CAYMAN_RING_TYPE_CP1_INDEX
] = &ci_cp_ring
,
2007 [CAYMAN_RING_TYPE_CP2_INDEX
] = &ci_cp_ring
,
2008 [R600_RING_TYPE_DMA_INDEX
] = &ci_dma_ring
,
2009 [CAYMAN_RING_TYPE_DMA1_INDEX
] = &ci_dma_ring
,
2010 [R600_RING_TYPE_UVD_INDEX
] = &cayman_uvd_ring
,
2011 [TN_RING_TYPE_VCE1_INDEX
] = &ci_vce_ring
,
2012 [TN_RING_TYPE_VCE2_INDEX
] = &ci_vce_ring
,
2015 .set
= &cik_irq_set
,
2016 .process
= &cik_irq_process
,
2019 .bandwidth_update
= &dce8_bandwidth_update
,
2020 .get_vblank_counter
= &evergreen_get_vblank_counter
,
2021 .wait_for_vblank
= &dce4_wait_for_vblank
,
2022 .set_backlight_level
= &atombios_set_backlight_level
,
2023 .get_backlight_level
= &atombios_get_backlight_level
,
2024 .hdmi_enable
= &evergreen_hdmi_enable
,
2025 .hdmi_setmode
= &evergreen_hdmi_setmode
,
2028 .blit
= &cik_copy_cpdma
,
2029 .blit_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
2030 .dma
= &cik_copy_dma
,
2031 .dma_ring_index
= R600_RING_TYPE_DMA_INDEX
,
2032 .copy
= &cik_copy_dma
,
2033 .copy_ring_index
= R600_RING_TYPE_DMA_INDEX
,
2036 .set_reg
= r600_set_surface_reg
,
2037 .clear_reg
= r600_clear_surface_reg
,
2040 .init
= &evergreen_hpd_init
,
2041 .fini
= &evergreen_hpd_fini
,
2042 .sense
= &evergreen_hpd_sense
,
2043 .set_polarity
= &evergreen_hpd_set_polarity
,
2046 .misc
= &evergreen_pm_misc
,
2047 .prepare
= &evergreen_pm_prepare
,
2048 .finish
= &evergreen_pm_finish
,
2049 .init_profile
= &sumo_pm_init_profile
,
2050 .get_dynpm_state
= &r600_pm_get_dynpm_state
,
2051 .get_engine_clock
= &radeon_atom_get_engine_clock
,
2052 .set_engine_clock
= &radeon_atom_set_engine_clock
,
2053 .get_memory_clock
= &radeon_atom_get_memory_clock
,
2054 .set_memory_clock
= &radeon_atom_set_memory_clock
,
2055 .get_pcie_lanes
= NULL
,
2056 .set_pcie_lanes
= NULL
,
2057 .set_clock_gating
= NULL
,
2058 .set_uvd_clocks
= &cik_set_uvd_clocks
,
2059 .set_vce_clocks
= &cik_set_vce_clocks
,
2060 .get_temperature
= &ci_get_temp
,
2063 .init
= &ci_dpm_init
,
2064 .setup_asic
= &ci_dpm_setup_asic
,
2065 .enable
= &ci_dpm_enable
,
2066 .late_enable
= &ci_dpm_late_enable
,
2067 .disable
= &ci_dpm_disable
,
2068 .pre_set_power_state
= &ci_dpm_pre_set_power_state
,
2069 .set_power_state
= &ci_dpm_set_power_state
,
2070 .post_set_power_state
= &ci_dpm_post_set_power_state
,
2071 .display_configuration_changed
= &ci_dpm_display_configuration_changed
,
2072 .fini
= &ci_dpm_fini
,
2073 .get_sclk
= &ci_dpm_get_sclk
,
2074 .get_mclk
= &ci_dpm_get_mclk
,
2075 .print_power_state
= &ci_dpm_print_power_state
,
2076 .debugfs_print_current_performance_level
= &ci_dpm_debugfs_print_current_performance_level
,
2077 .force_performance_level
= &ci_dpm_force_performance_level
,
2078 .vblank_too_short
= &ci_dpm_vblank_too_short
,
2079 .powergate_uvd
= &ci_dpm_powergate_uvd
,
2082 .page_flip
= &evergreen_page_flip
,
2083 .page_flip_pending
= &evergreen_page_flip_pending
,
2087 static struct radeon_asic kv_asic
= {
2090 .suspend
= &cik_suspend
,
2091 .resume
= &cik_resume
,
2092 .asic_reset
= &cik_asic_reset
,
2093 .vga_set_state
= &r600_vga_set_state
,
2094 .ioctl_wait_idle
= NULL
,
2095 .gui_idle
= &r600_gui_idle
,
2096 .mc_wait_for_idle
= &evergreen_mc_wait_for_idle
,
2097 .get_xclk
= &cik_get_xclk
,
2098 .get_gpu_clock_counter
= &cik_get_gpu_clock_counter
,
2100 .tlb_flush
= &cik_pcie_gart_tlb_flush
,
2101 .set_page
= &rs600_gart_set_page
,
2104 .init
= &cik_vm_init
,
2105 .fini
= &cik_vm_fini
,
2106 .set_page
= &cik_sdma_vm_set_page
,
2109 [RADEON_RING_TYPE_GFX_INDEX
] = &ci_gfx_ring
,
2110 [CAYMAN_RING_TYPE_CP1_INDEX
] = &ci_cp_ring
,
2111 [CAYMAN_RING_TYPE_CP2_INDEX
] = &ci_cp_ring
,
2112 [R600_RING_TYPE_DMA_INDEX
] = &ci_dma_ring
,
2113 [CAYMAN_RING_TYPE_DMA1_INDEX
] = &ci_dma_ring
,
2114 [R600_RING_TYPE_UVD_INDEX
] = &cayman_uvd_ring
,
2115 [TN_RING_TYPE_VCE1_INDEX
] = &ci_vce_ring
,
2116 [TN_RING_TYPE_VCE2_INDEX
] = &ci_vce_ring
,
2119 .set
= &cik_irq_set
,
2120 .process
= &cik_irq_process
,
2123 .bandwidth_update
= &dce8_bandwidth_update
,
2124 .get_vblank_counter
= &evergreen_get_vblank_counter
,
2125 .wait_for_vblank
= &dce4_wait_for_vblank
,
2126 .set_backlight_level
= &atombios_set_backlight_level
,
2127 .get_backlight_level
= &atombios_get_backlight_level
,
2128 .hdmi_enable
= &evergreen_hdmi_enable
,
2129 .hdmi_setmode
= &evergreen_hdmi_setmode
,
2132 .blit
= &cik_copy_cpdma
,
2133 .blit_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
2134 .dma
= &cik_copy_dma
,
2135 .dma_ring_index
= R600_RING_TYPE_DMA_INDEX
,
2136 .copy
= &cik_copy_dma
,
2137 .copy_ring_index
= R600_RING_TYPE_DMA_INDEX
,
2140 .set_reg
= r600_set_surface_reg
,
2141 .clear_reg
= r600_clear_surface_reg
,
2144 .init
= &evergreen_hpd_init
,
2145 .fini
= &evergreen_hpd_fini
,
2146 .sense
= &evergreen_hpd_sense
,
2147 .set_polarity
= &evergreen_hpd_set_polarity
,
2150 .misc
= &evergreen_pm_misc
,
2151 .prepare
= &evergreen_pm_prepare
,
2152 .finish
= &evergreen_pm_finish
,
2153 .init_profile
= &sumo_pm_init_profile
,
2154 .get_dynpm_state
= &r600_pm_get_dynpm_state
,
2155 .get_engine_clock
= &radeon_atom_get_engine_clock
,
2156 .set_engine_clock
= &radeon_atom_set_engine_clock
,
2157 .get_memory_clock
= &radeon_atom_get_memory_clock
,
2158 .set_memory_clock
= &radeon_atom_set_memory_clock
,
2159 .get_pcie_lanes
= NULL
,
2160 .set_pcie_lanes
= NULL
,
2161 .set_clock_gating
= NULL
,
2162 .set_uvd_clocks
= &cik_set_uvd_clocks
,
2163 .set_vce_clocks
= &cik_set_vce_clocks
,
2164 .get_temperature
= &kv_get_temp
,
2167 .init
= &kv_dpm_init
,
2168 .setup_asic
= &kv_dpm_setup_asic
,
2169 .enable
= &kv_dpm_enable
,
2170 .late_enable
= &kv_dpm_late_enable
,
2171 .disable
= &kv_dpm_disable
,
2172 .pre_set_power_state
= &kv_dpm_pre_set_power_state
,
2173 .set_power_state
= &kv_dpm_set_power_state
,
2174 .post_set_power_state
= &kv_dpm_post_set_power_state
,
2175 .display_configuration_changed
= &kv_dpm_display_configuration_changed
,
2176 .fini
= &kv_dpm_fini
,
2177 .get_sclk
= &kv_dpm_get_sclk
,
2178 .get_mclk
= &kv_dpm_get_mclk
,
2179 .print_power_state
= &kv_dpm_print_power_state
,
2180 .debugfs_print_current_performance_level
= &kv_dpm_debugfs_print_current_performance_level
,
2181 .force_performance_level
= &kv_dpm_force_performance_level
,
2182 .powergate_uvd
= &kv_dpm_powergate_uvd
,
2183 .enable_bapm
= &kv_dpm_enable_bapm
,
2186 .page_flip
= &evergreen_page_flip
,
2187 .page_flip_pending
= &evergreen_page_flip_pending
,
2192 * radeon_asic_init - register asic specific callbacks
2194 * @rdev: radeon device pointer
2196 * Registers the appropriate asic specific callbacks for each
2197 * chip family. Also sets other asics specific info like the number
2198 * of crtcs and the register aperture accessors (all asics).
2199 * Returns 0 for success.
2201 int radeon_asic_init(struct radeon_device
*rdev
)
2203 radeon_register_accessor_init(rdev
);
2205 /* set the number of crtcs */
2206 if (rdev
->flags
& RADEON_SINGLE_CRTC
)
2211 rdev
->has_uvd
= false;
2213 switch (rdev
->family
) {
2219 rdev
->asic
= &r100_asic
;
2225 rdev
->asic
= &r200_asic
;
2231 if (rdev
->flags
& RADEON_IS_PCIE
)
2232 rdev
->asic
= &r300_asic_pcie
;
2234 rdev
->asic
= &r300_asic
;
2239 rdev
->asic
= &r420_asic
;
2241 if (rdev
->bios
== NULL
) {
2242 rdev
->asic
->pm
.get_engine_clock
= &radeon_legacy_get_engine_clock
;
2243 rdev
->asic
->pm
.set_engine_clock
= &radeon_legacy_set_engine_clock
;
2244 rdev
->asic
->pm
.get_memory_clock
= &radeon_legacy_get_memory_clock
;
2245 rdev
->asic
->pm
.set_memory_clock
= NULL
;
2246 rdev
->asic
->display
.set_backlight_level
= &radeon_legacy_set_backlight_level
;
2251 rdev
->asic
= &rs400_asic
;
2254 rdev
->asic
= &rs600_asic
;
2258 rdev
->asic
= &rs690_asic
;
2261 rdev
->asic
= &rv515_asic
;
2268 rdev
->asic
= &r520_asic
;
2271 rdev
->asic
= &r600_asic
;
2278 rdev
->asic
= &rv6xx_asic
;
2279 rdev
->has_uvd
= true;
2283 rdev
->asic
= &rs780_asic
;
2284 rdev
->has_uvd
= true;
2290 rdev
->asic
= &rv770_asic
;
2291 rdev
->has_uvd
= true;
2299 if (rdev
->family
== CHIP_CEDAR
)
2303 rdev
->asic
= &evergreen_asic
;
2304 rdev
->has_uvd
= true;
2309 rdev
->asic
= &sumo_asic
;
2310 rdev
->has_uvd
= true;
2316 if (rdev
->family
== CHIP_CAICOS
)
2320 rdev
->asic
= &btc_asic
;
2321 rdev
->has_uvd
= true;
2324 rdev
->asic
= &cayman_asic
;
2327 rdev
->has_uvd
= true;
2330 rdev
->asic
= &trinity_asic
;
2333 rdev
->has_uvd
= true;
2340 rdev
->asic
= &si_asic
;
2342 if (rdev
->family
== CHIP_HAINAN
)
2344 else if (rdev
->family
== CHIP_OLAND
)
2348 if (rdev
->family
== CHIP_HAINAN
)
2349 rdev
->has_uvd
= false;
2351 rdev
->has_uvd
= true;
2352 switch (rdev
->family
) {
2355 RADEON_CG_SUPPORT_GFX_MGCG
|
2356 RADEON_CG_SUPPORT_GFX_MGLS
|
2357 /*RADEON_CG_SUPPORT_GFX_CGCG |*/
2358 RADEON_CG_SUPPORT_GFX_CGLS
|
2359 RADEON_CG_SUPPORT_GFX_CGTS
|
2360 RADEON_CG_SUPPORT_GFX_CP_LS
|
2361 RADEON_CG_SUPPORT_MC_MGCG
|
2362 RADEON_CG_SUPPORT_SDMA_MGCG
|
2363 RADEON_CG_SUPPORT_BIF_LS
|
2364 RADEON_CG_SUPPORT_VCE_MGCG
|
2365 RADEON_CG_SUPPORT_UVD_MGCG
|
2366 RADEON_CG_SUPPORT_HDP_LS
|
2367 RADEON_CG_SUPPORT_HDP_MGCG
;
2372 RADEON_CG_SUPPORT_GFX_MGCG
|
2373 RADEON_CG_SUPPORT_GFX_MGLS
|
2374 /*RADEON_CG_SUPPORT_GFX_CGCG |*/
2375 RADEON_CG_SUPPORT_GFX_CGLS
|
2376 RADEON_CG_SUPPORT_GFX_CGTS
|
2377 RADEON_CG_SUPPORT_GFX_CP_LS
|
2378 RADEON_CG_SUPPORT_GFX_RLC_LS
|
2379 RADEON_CG_SUPPORT_MC_LS
|
2380 RADEON_CG_SUPPORT_MC_MGCG
|
2381 RADEON_CG_SUPPORT_SDMA_MGCG
|
2382 RADEON_CG_SUPPORT_BIF_LS
|
2383 RADEON_CG_SUPPORT_VCE_MGCG
|
2384 RADEON_CG_SUPPORT_UVD_MGCG
|
2385 RADEON_CG_SUPPORT_HDP_LS
|
2386 RADEON_CG_SUPPORT_HDP_MGCG
;
2391 RADEON_CG_SUPPORT_GFX_MGCG
|
2392 RADEON_CG_SUPPORT_GFX_MGLS
|
2393 /*RADEON_CG_SUPPORT_GFX_CGCG |*/
2394 RADEON_CG_SUPPORT_GFX_CGLS
|
2395 RADEON_CG_SUPPORT_GFX_CGTS
|
2396 RADEON_CG_SUPPORT_GFX_CP_LS
|
2397 RADEON_CG_SUPPORT_GFX_RLC_LS
|
2398 RADEON_CG_SUPPORT_MC_LS
|
2399 RADEON_CG_SUPPORT_MC_MGCG
|
2400 RADEON_CG_SUPPORT_SDMA_MGCG
|
2401 RADEON_CG_SUPPORT_BIF_LS
|
2402 RADEON_CG_SUPPORT_VCE_MGCG
|
2403 RADEON_CG_SUPPORT_UVD_MGCG
|
2404 RADEON_CG_SUPPORT_HDP_LS
|
2405 RADEON_CG_SUPPORT_HDP_MGCG
;
2406 rdev
->pg_flags
= 0 |
2407 /*RADEON_PG_SUPPORT_GFX_PG | */
2408 RADEON_PG_SUPPORT_SDMA
;
2412 RADEON_CG_SUPPORT_GFX_MGCG
|
2413 RADEON_CG_SUPPORT_GFX_MGLS
|
2414 /*RADEON_CG_SUPPORT_GFX_CGCG |*/
2415 RADEON_CG_SUPPORT_GFX_CGLS
|
2416 RADEON_CG_SUPPORT_GFX_CGTS
|
2417 RADEON_CG_SUPPORT_GFX_CP_LS
|
2418 RADEON_CG_SUPPORT_GFX_RLC_LS
|
2419 RADEON_CG_SUPPORT_MC_LS
|
2420 RADEON_CG_SUPPORT_MC_MGCG
|
2421 RADEON_CG_SUPPORT_SDMA_MGCG
|
2422 RADEON_CG_SUPPORT_BIF_LS
|
2423 RADEON_CG_SUPPORT_UVD_MGCG
|
2424 RADEON_CG_SUPPORT_HDP_LS
|
2425 RADEON_CG_SUPPORT_HDP_MGCG
;
2430 RADEON_CG_SUPPORT_GFX_MGCG
|
2431 RADEON_CG_SUPPORT_GFX_MGLS
|
2432 /*RADEON_CG_SUPPORT_GFX_CGCG |*/
2433 RADEON_CG_SUPPORT_GFX_CGLS
|
2434 RADEON_CG_SUPPORT_GFX_CGTS
|
2435 RADEON_CG_SUPPORT_GFX_CP_LS
|
2436 RADEON_CG_SUPPORT_GFX_RLC_LS
|
2437 RADEON_CG_SUPPORT_MC_LS
|
2438 RADEON_CG_SUPPORT_MC_MGCG
|
2439 RADEON_CG_SUPPORT_SDMA_MGCG
|
2440 RADEON_CG_SUPPORT_BIF_LS
|
2441 RADEON_CG_SUPPORT_HDP_LS
|
2442 RADEON_CG_SUPPORT_HDP_MGCG
;
2453 rdev
->asic
= &ci_asic
;
2455 rdev
->has_uvd
= true;
2456 if (rdev
->family
== CHIP_BONAIRE
) {
2458 RADEON_CG_SUPPORT_GFX_MGCG
|
2459 RADEON_CG_SUPPORT_GFX_MGLS
|
2460 RADEON_CG_SUPPORT_GFX_CGCG
|
2461 RADEON_CG_SUPPORT_GFX_CGLS
|
2462 RADEON_CG_SUPPORT_GFX_CGTS
|
2463 RADEON_CG_SUPPORT_GFX_CGTS_LS
|
2464 RADEON_CG_SUPPORT_GFX_CP_LS
|
2465 RADEON_CG_SUPPORT_MC_LS
|
2466 RADEON_CG_SUPPORT_MC_MGCG
|
2467 RADEON_CG_SUPPORT_SDMA_MGCG
|
2468 RADEON_CG_SUPPORT_SDMA_LS
|
2469 RADEON_CG_SUPPORT_BIF_LS
|
2470 RADEON_CG_SUPPORT_VCE_MGCG
|
2471 RADEON_CG_SUPPORT_UVD_MGCG
|
2472 RADEON_CG_SUPPORT_HDP_LS
|
2473 RADEON_CG_SUPPORT_HDP_MGCG
;
2477 RADEON_CG_SUPPORT_GFX_MGCG
|
2478 RADEON_CG_SUPPORT_GFX_MGLS
|
2479 RADEON_CG_SUPPORT_GFX_CGCG
|
2480 RADEON_CG_SUPPORT_GFX_CGLS
|
2481 RADEON_CG_SUPPORT_GFX_CGTS
|
2482 RADEON_CG_SUPPORT_GFX_CP_LS
|
2483 RADEON_CG_SUPPORT_MC_LS
|
2484 RADEON_CG_SUPPORT_MC_MGCG
|
2485 RADEON_CG_SUPPORT_SDMA_MGCG
|
2486 RADEON_CG_SUPPORT_SDMA_LS
|
2487 RADEON_CG_SUPPORT_BIF_LS
|
2488 RADEON_CG_SUPPORT_VCE_MGCG
|
2489 RADEON_CG_SUPPORT_UVD_MGCG
|
2490 RADEON_CG_SUPPORT_HDP_LS
|
2491 RADEON_CG_SUPPORT_HDP_MGCG
;
2498 rdev
->asic
= &kv_asic
;
2500 if (rdev
->family
== CHIP_KAVERI
) {
2503 RADEON_CG_SUPPORT_GFX_MGCG
|
2504 RADEON_CG_SUPPORT_GFX_MGLS
|
2505 RADEON_CG_SUPPORT_GFX_CGCG
|
2506 RADEON_CG_SUPPORT_GFX_CGLS
|
2507 RADEON_CG_SUPPORT_GFX_CGTS
|
2508 RADEON_CG_SUPPORT_GFX_CGTS_LS
|
2509 RADEON_CG_SUPPORT_GFX_CP_LS
|
2510 RADEON_CG_SUPPORT_SDMA_MGCG
|
2511 RADEON_CG_SUPPORT_SDMA_LS
|
2512 RADEON_CG_SUPPORT_BIF_LS
|
2513 RADEON_CG_SUPPORT_VCE_MGCG
|
2514 RADEON_CG_SUPPORT_UVD_MGCG
|
2515 RADEON_CG_SUPPORT_HDP_LS
|
2516 RADEON_CG_SUPPORT_HDP_MGCG
;
2518 /*RADEON_PG_SUPPORT_GFX_PG |
2519 RADEON_PG_SUPPORT_GFX_SMG |
2520 RADEON_PG_SUPPORT_GFX_DMG |
2521 RADEON_PG_SUPPORT_UVD |
2522 RADEON_PG_SUPPORT_VCE |
2523 RADEON_PG_SUPPORT_CP |
2524 RADEON_PG_SUPPORT_GDS |
2525 RADEON_PG_SUPPORT_RLC_SMU_HS |
2526 RADEON_PG_SUPPORT_ACP |
2527 RADEON_PG_SUPPORT_SAMU;*/
2531 RADEON_CG_SUPPORT_GFX_MGCG
|
2532 RADEON_CG_SUPPORT_GFX_MGLS
|
2533 RADEON_CG_SUPPORT_GFX_CGCG
|
2534 RADEON_CG_SUPPORT_GFX_CGLS
|
2535 RADEON_CG_SUPPORT_GFX_CGTS
|
2536 RADEON_CG_SUPPORT_GFX_CGTS_LS
|
2537 RADEON_CG_SUPPORT_GFX_CP_LS
|
2538 RADEON_CG_SUPPORT_SDMA_MGCG
|
2539 RADEON_CG_SUPPORT_SDMA_LS
|
2540 RADEON_CG_SUPPORT_BIF_LS
|
2541 RADEON_CG_SUPPORT_VCE_MGCG
|
2542 RADEON_CG_SUPPORT_UVD_MGCG
|
2543 RADEON_CG_SUPPORT_HDP_LS
|
2544 RADEON_CG_SUPPORT_HDP_MGCG
;
2546 /*RADEON_PG_SUPPORT_GFX_PG |
2547 RADEON_PG_SUPPORT_GFX_SMG |
2548 RADEON_PG_SUPPORT_UVD |
2549 RADEON_PG_SUPPORT_VCE |
2550 RADEON_PG_SUPPORT_CP |
2551 RADEON_PG_SUPPORT_GDS |
2552 RADEON_PG_SUPPORT_RLC_SMU_HS |
2553 RADEON_PG_SUPPORT_SAMU;*/
2555 rdev
->has_uvd
= true;
2558 /* FIXME: not supported yet */
2562 if (rdev
->flags
& RADEON_IS_IGP
) {
2563 rdev
->asic
->pm
.get_memory_clock
= NULL
;
2564 rdev
->asic
->pm
.set_memory_clock
= NULL
;