drivers/gpu/drm/radeon/radeon_asic.h

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28 #ifndef __RADEON_ASIC_H__
  29 #define __RADEON_ASIC_H__
  30
  31 /*
  32  * common functions
  33  */
  34 uint32_t radeon_legacy_get_engine_clock(struct radeon_device *rdev);
  35 void radeon_legacy_set_engine_clock(struct radeon_device *rdev, uint32_t eng_clock);
  36 uint32_t radeon_legacy_get_memory_clock(struct radeon_device *rdev);
  37 void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);
  38
  39 uint32_t radeon_atom_get_engine_clock(struct radeon_device *rdev);
  40 void radeon_atom_set_engine_clock(struct radeon_device *rdev, uint32_t eng_clock);
  41 uint32_t radeon_atom_get_memory_clock(struct radeon_device *rdev);
  42 void radeon_atom_set_memory_clock(struct radeon_device *rdev, uint32_t mem_clock);
  43 void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
  44
  45 void atombios_set_backlight_level(struct radeon_encoder *radeon_encoder, u8 level);
  46 u8 atombios_get_backlight_level(struct radeon_encoder *radeon_encoder);
  47 void radeon_legacy_set_backlight_level(struct radeon_encoder *radeon_encoder, u8 level);
  48 u8 radeon_legacy_get_backlight_level(struct radeon_encoder *radeon_encoder);
  49
  50 /*
  51  * r100,rv100,rs100,rv200,rs200
  52  */
  53 struct r100_mc_save {
  54         u32     GENMO_WT;
  55         u32     CRTC_EXT_CNTL;
  56         u32     CRTC_GEN_CNTL;
  57         u32     CRTC2_GEN_CNTL;
  58         u32     CUR_OFFSET;
  59         u32     CUR2_OFFSET;
  60 };
  61 int r100_init(struct radeon_device *rdev);
  62 void r100_fini(struct radeon_device *rdev);
  63 int r100_suspend(struct radeon_device *rdev);
  64 int r100_resume(struct radeon_device *rdev);
  65 void r100_vga_set_state(struct radeon_device *rdev, bool state);
  66 bool r100_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp);
  67 int r100_asic_reset(struct radeon_device *rdev);
  68 u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc);
  69 void r100_pci_gart_tlb_flush(struct radeon_device *rdev);
  70 void r100_pci_gart_set_page(struct radeon_device *rdev, unsigned i,
  71                             uint64_t addr);
  72 void r100_ring_start(struct radeon_device *rdev, struct radeon_ring *ring);
  73 int r100_irq_set(struct radeon_device *rdev);
  74 int r100_irq_process(struct radeon_device *rdev);
  75 void r100_fence_ring_emit(struct radeon_device *rdev,
  76                           struct radeon_fence *fence);
  77 bool r100_semaphore_ring_emit(struct radeon_device *rdev,
  78                               struct radeon_ring *cp,
  79                               struct radeon_semaphore *semaphore,
  80                               bool emit_wait);
  81 int r100_cs_parse(struct radeon_cs_parser *p);
  82 void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
  83 uint32_t r100_pll_rreg(struct radeon_device *rdev, uint32_t reg);
  84 int r100_copy_blit(struct radeon_device *rdev,
  85                    uint64_t src_offset,
  86                    uint64_t dst_offset,
  87                    unsigned num_gpu_pages,
  88                    struct radeon_fence **fence);
  89 int r100_set_surface_reg(struct radeon_device *rdev, int reg,
  90                          uint32_t tiling_flags, uint32_t pitch,
  91                          uint32_t offset, uint32_t obj_size);
  92 void r100_clear_surface_reg(struct radeon_device *rdev, int reg);
  93 void r100_bandwidth_update(struct radeon_device *rdev);
  94 void r100_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
  95 int r100_ring_test(struct radeon_device *rdev, struct radeon_ring *cp);
  96 void r100_hpd_init(struct radeon_device *rdev);
  97 void r100_hpd_fini(struct radeon_device *rdev);
  98 bool r100_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd);
  99 void r100_hpd_set_polarity(struct radeon_device *rdev,
 100                            enum radeon_hpd_id hpd);
 101 int r100_debugfs_rbbm_init(struct radeon_device *rdev);
 102 int r100_debugfs_cp_init(struct radeon_device *rdev);
 103 void r100_cp_disable(struct radeon_device *rdev);
 104 int r100_cp_init(struct radeon_device *rdev, unsigned ring_size);
 105 void r100_cp_fini(struct radeon_device *rdev);
 106 int r100_pci_gart_init(struct radeon_device *rdev);
 107 void r100_pci_gart_fini(struct radeon_device *rdev);
 108 int r100_pci_gart_enable(struct radeon_device *rdev);
 109 void r100_pci_gart_disable(struct radeon_device *rdev);
 110 int r100_debugfs_mc_info_init(struct radeon_device *rdev);
 111 int r100_gui_wait_for_idle(struct radeon_device *rdev);
 112 int r100_ib_test(struct radeon_device *rdev, struct radeon_ring *ring);
 113 void r100_irq_disable(struct radeon_device *rdev);
 114 void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save);
 115 void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save);
 116 void r100_vram_init_sizes(struct radeon_device *rdev);
 117 int r100_cp_reset(struct radeon_device *rdev);
 118 void r100_vga_render_disable(struct radeon_device *rdev);
 119 void r100_restore_sanity(struct radeon_device *rdev);
 120 int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p,
 121                                          struct radeon_cs_packet *pkt,
 122                                          struct radeon_bo *robj);
 123 int r100_cs_parse_packet0(struct radeon_cs_parser *p,
 124                           struct radeon_cs_packet *pkt,
 125                           const unsigned *auth, unsigned n,
 126                           radeon_packet0_check_t check);
 127 int r100_cs_packet_parse(struct radeon_cs_parser *p,
 128                          struct radeon_cs_packet *pkt,
 129                          unsigned idx);
 130 void r100_enable_bm(struct radeon_device *rdev);
 131 void r100_set_common_regs(struct radeon_device *rdev);
 132 void r100_bm_disable(struct radeon_device *rdev);
 133 extern bool r100_gui_idle(struct radeon_device *rdev);
 134 extern void r100_pm_misc(struct radeon_device *rdev);
 135 extern void r100_pm_prepare(struct radeon_device *rdev);
 136 extern void r100_pm_finish(struct radeon_device *rdev);
 137 extern void r100_pm_init_profile(struct radeon_device *rdev);
 138 extern void r100_pm_get_dynpm_state(struct radeon_device *rdev);
 139 extern void r100_page_flip(struct radeon_device *rdev, int crtc,
 140                            u64 crtc_base);
 141 extern bool r100_page_flip_pending(struct radeon_device *rdev, int crtc);
 142 extern void r100_wait_for_vblank(struct radeon_device *rdev, int crtc);
 143 extern int r100_mc_wait_for_idle(struct radeon_device *rdev);
 144
 145 u32 r100_gfx_get_rptr(struct radeon_device *rdev,
 146                       struct radeon_ring *ring);
 147 u32 r100_gfx_get_wptr(struct radeon_device *rdev,
 148                       struct radeon_ring *ring);
 149 void r100_gfx_set_wptr(struct radeon_device *rdev,
 150                        struct radeon_ring *ring);
 151
 152 /*
 153  * r200,rv250,rs300,rv280
 154  */
 155 extern int r200_copy_dma(struct radeon_device *rdev,
 156                          uint64_t src_offset,
 157                          uint64_t dst_offset,
 158                          unsigned num_gpu_pages,
 159                          struct radeon_fence **fence);
 160 void r200_set_safe_registers(struct radeon_device *rdev);
 161
 162 /*
 163  * r300,r350,rv350,rv380
 164  */
 165 extern int r300_init(struct radeon_device *rdev);
 166 extern void r300_fini(struct radeon_device *rdev);
 167 extern int r300_suspend(struct radeon_device *rdev);
 168 extern int r300_resume(struct radeon_device *rdev);
 169 extern int r300_asic_reset(struct radeon_device *rdev);
 170 extern void r300_ring_start(struct radeon_device *rdev, struct radeon_ring *ring);
 171 extern void r300_fence_ring_emit(struct radeon_device *rdev,
 172                                 struct radeon_fence *fence);
 173 extern int r300_cs_parse(struct radeon_cs_parser *p);
 174 extern void rv370_pcie_gart_tlb_flush(struct radeon_device *rdev);
 175 extern void rv370_pcie_gart_set_page(struct radeon_device *rdev, unsigned i,
 176                                      uint64_t addr);
 177 extern void rv370_set_pcie_lanes(struct radeon_device *rdev, int lanes);
 178 extern int rv370_get_pcie_lanes(struct radeon_device *rdev);
 179 extern void r300_set_reg_safe(struct radeon_device *rdev);
 180 extern void r300_mc_program(struct radeon_device *rdev);
 181 extern void r300_mc_init(struct radeon_device *rdev);
 182 extern void r300_clock_startup(struct radeon_device *rdev);
 183 extern int r300_mc_wait_for_idle(struct radeon_device *rdev);
 184 extern int rv370_pcie_gart_init(struct radeon_device *rdev);
 185 extern void rv370_pcie_gart_fini(struct radeon_device *rdev);
 186 extern int rv370_pcie_gart_enable(struct radeon_device *rdev);
 187 extern void rv370_pcie_gart_disable(struct radeon_device *rdev);
 188 extern int r300_mc_wait_for_idle(struct radeon_device *rdev);
 189
 190 /*
 191  * r420,r423,rv410
 192  */
 193 extern int r420_init(struct radeon_device *rdev);
 194 extern void r420_fini(struct radeon_device *rdev);
 195 extern int r420_suspend(struct radeon_device *rdev);
 196 extern int r420_resume(struct radeon_device *rdev);
 197 extern void r420_pm_init_profile(struct radeon_device *rdev);
 198 extern u32 r420_mc_rreg(struct radeon_device *rdev, u32 reg);
 199 extern void r420_mc_wreg(struct radeon_device *rdev, u32 reg, u32 v);
 200 extern int r420_debugfs_pipes_info_init(struct radeon_device *rdev);
 201 extern void r420_pipes_init(struct radeon_device *rdev);
 202
 203 /*
 204  * rs400,rs480
 205  */
 206 extern int rs400_init(struct radeon_device *rdev);
 207 extern void rs400_fini(struct radeon_device *rdev);
 208 extern int rs400_suspend(struct radeon_device *rdev);
 209 extern int rs400_resume(struct radeon_device *rdev);
 210 void rs400_gart_tlb_flush(struct radeon_device *rdev);
 211 void rs400_gart_set_page(struct radeon_device *rdev, unsigned i,
 212                          uint64_t addr);
 213 uint32_t rs400_mc_rreg(struct radeon_device *rdev, uint32_t reg);
 214 void rs400_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
 215 int rs400_gart_init(struct radeon_device *rdev);
 216 int rs400_gart_enable(struct radeon_device *rdev);
 217 void rs400_gart_adjust_size(struct radeon_device *rdev);
 218 void rs400_gart_disable(struct radeon_device *rdev);
 219 void rs400_gart_fini(struct radeon_device *rdev);
 220 extern int rs400_mc_wait_for_idle(struct radeon_device *rdev);
 221
 222 /*
 223  * rs600.
 224  */
 225 extern int rs600_asic_reset(struct radeon_device *rdev);
 226 extern int rs600_init(struct radeon_device *rdev);
 227 extern void rs600_fini(struct radeon_device *rdev);
 228 extern int rs600_suspend(struct radeon_device *rdev);
 229 extern int rs600_resume(struct radeon_device *rdev);
 230 int rs600_irq_set(struct radeon_device *rdev);
 231 int rs600_irq_process(struct radeon_device *rdev);
 232 void rs600_irq_disable(struct radeon_device *rdev);
 233 u32 rs600_get_vblank_counter(struct radeon_device *rdev, int crtc);
 234 void rs600_gart_tlb_flush(struct radeon_device *rdev);
 235 void rs600_gart_set_page(struct radeon_device *rdev, unsigned i,
 236                          uint64_t addr);
 237 uint32_t rs600_mc_rreg(struct radeon_device *rdev, uint32_t reg);
 238 void rs600_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
 239 void rs600_bandwidth_update(struct radeon_device *rdev);
 240 void rs600_hpd_init(struct radeon_device *rdev);
 241 void rs600_hpd_fini(struct radeon_device *rdev);
 242 bool rs600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd);
 243 void rs600_hpd_set_polarity(struct radeon_device *rdev,
 244                             enum radeon_hpd_id hpd);
 245 extern void rs600_pm_misc(struct radeon_device *rdev);
 246 extern void rs600_pm_prepare(struct radeon_device *rdev);
 247 extern void rs600_pm_finish(struct radeon_device *rdev);
 248 extern void rs600_page_flip(struct radeon_device *rdev, int crtc,
 249                             u64 crtc_base);
 250 extern bool rs600_page_flip_pending(struct radeon_device *rdev, int crtc);
 251 void rs600_set_safe_registers(struct radeon_device *rdev);
 252 extern void avivo_wait_for_vblank(struct radeon_device *rdev, int crtc);
 253 extern int rs600_mc_wait_for_idle(struct radeon_device *rdev);
 254
 255 /*
 256  * rs690,rs740
 257  */
 258 int rs690_init(struct radeon_device *rdev);
 259 void rs690_fini(struct radeon_device *rdev);
 260 int rs690_resume(struct radeon_device *rdev);
 261 int rs690_suspend(struct radeon_device *rdev);
 262 uint32_t rs690_mc_rreg(struct radeon_device *rdev, uint32_t reg);
 263 void rs690_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
 264 void rs690_bandwidth_update(struct radeon_device *rdev);
 265 void rs690_line_buffer_adjust(struct radeon_device *rdev,
 266                                         struct drm_display_mode *mode1,
 267                                         struct drm_display_mode *mode2);
 268 extern int rs690_mc_wait_for_idle(struct radeon_device *rdev);
 269
 270 /*
 271  * rv515
 272  */
 273 struct rv515_mc_save {
 274         u32 vga_render_control;
 275         u32 vga_hdp_control;
 276         bool crtc_enabled[2];
 277 };
 278
 279 int rv515_init(struct radeon_device *rdev);
 280 void rv515_fini(struct radeon_device *rdev);
 281 uint32_t rv515_mc_rreg(struct radeon_device *rdev, uint32_t reg);
 282 void rv515_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
 283 void rv515_ring_start(struct radeon_device *rdev, struct radeon_ring *ring);
 284 void rv515_bandwidth_update(struct radeon_device *rdev);
 285 int rv515_resume(struct radeon_device *rdev);
 286 int rv515_suspend(struct radeon_device *rdev);
 287 void rv515_bandwidth_avivo_update(struct radeon_device *rdev);
 288 void rv515_vga_render_disable(struct radeon_device *rdev);
 289 void rv515_set_safe_registers(struct radeon_device *rdev);
 290 void rv515_mc_stop(struct radeon_device *rdev, struct rv515_mc_save *save);
 291 void rv515_mc_resume(struct radeon_device *rdev, struct rv515_mc_save *save);
 292 void rv515_clock_startup(struct radeon_device *rdev);
 293 void rv515_debugfs(struct radeon_device *rdev);
 294 int rv515_mc_wait_for_idle(struct radeon_device *rdev);
 295
 296 /*
 297  * r520,rv530,rv560,rv570,r580
 298  */
 299 int r520_init(struct radeon_device *rdev);
 300 int r520_resume(struct radeon_device *rdev);
 301 int r520_mc_wait_for_idle(struct radeon_device *rdev);
 302
 303 /*
 304  * r600,rv610,rv630,rv620,rv635,rv670,rs780,rs880
 305  */
 306 int r600_init(struct radeon_device *rdev);
 307 void r600_fini(struct radeon_device *rdev);
 308 int r600_suspend(struct radeon_device *rdev);
 309 int r600_resume(struct radeon_device *rdev);
 310 void r600_vga_set_state(struct radeon_device *rdev, bool state);
 311 int r600_wb_init(struct radeon_device *rdev);
 312 void r600_wb_fini(struct radeon_device *rdev);
 313 void r600_pcie_gart_tlb_flush(struct radeon_device *rdev);
 314 uint32_t r600_pciep_rreg(struct radeon_device *rdev, uint32_t reg);
 315 void r600_pciep_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
 316 int r600_cs_parse(struct radeon_cs_parser *p);
 317 int r600_dma_cs_parse(struct radeon_cs_parser *p);
 318 void r600_fence_ring_emit(struct radeon_device *rdev,
 319                           struct radeon_fence *fence);
 320 bool r600_semaphore_ring_emit(struct radeon_device *rdev,
 321                               struct radeon_ring *cp,
 322                               struct radeon_semaphore *semaphore,
 323                               bool emit_wait);
 324 void r600_dma_fence_ring_emit(struct radeon_device *rdev,
 325                               struct radeon_fence *fence);
 326 bool r600_dma_semaphore_ring_emit(struct radeon_device *rdev,
 327                                   struct radeon_ring *ring,
 328                                   struct radeon_semaphore *semaphore,
 329                                   bool emit_wait);
 330 void r600_dma_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
 331 bool r600_dma_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring);
 332 bool r600_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp);
 333 int r600_asic_reset(struct radeon_device *rdev);
 334 int r600_set_surface_reg(struct radeon_device *rdev, int reg,
 335                          uint32_t tiling_flags, uint32_t pitch,
 336                          uint32_t offset, uint32_t obj_size);
 337 void r600_clear_surface_reg(struct radeon_device *rdev, int reg);
 338 int r600_ib_test(struct radeon_device *rdev, struct radeon_ring *ring);
 339 int r600_dma_ib_test(struct radeon_device *rdev, struct radeon_ring *ring);
 340 void r600_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
 341 int r600_ring_test(struct radeon_device *rdev, struct radeon_ring *cp);
 342 int r600_dma_ring_test(struct radeon_device *rdev, struct radeon_ring *cp);
 343 int r600_copy_cpdma(struct radeon_device *rdev,
 344                     uint64_t src_offset, uint64_t dst_offset,
 345                     unsigned num_gpu_pages, struct radeon_fence **fence);
 346 int r600_copy_dma(struct radeon_device *rdev,
 347                   uint64_t src_offset, uint64_t dst_offset,
 348                   unsigned num_gpu_pages, struct radeon_fence **fence);
 349 void r600_hpd_init(struct radeon_device *rdev);
 350 void r600_hpd_fini(struct radeon_device *rdev);
 351 bool r600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd);
 352 void r600_hpd_set_polarity(struct radeon_device *rdev,
 353                            enum radeon_hpd_id hpd);
 354 extern void r600_ioctl_wait_idle(struct radeon_device *rdev, struct radeon_bo *bo);
 355 extern bool r600_gui_idle(struct radeon_device *rdev);
 356 extern void r600_pm_misc(struct radeon_device *rdev);
 357 extern void r600_pm_init_profile(struct radeon_device *rdev);
 358 extern void rs780_pm_init_profile(struct radeon_device *rdev);
 359 extern uint32_t rs780_mc_rreg(struct radeon_device *rdev, uint32_t reg);
 360 extern void rs780_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
 361 extern void r600_pm_get_dynpm_state(struct radeon_device *rdev);
 362 extern void r600_set_pcie_lanes(struct radeon_device *rdev, int lanes);
 363 extern int r600_get_pcie_lanes(struct radeon_device *rdev);
 364 bool r600_card_posted(struct radeon_device *rdev);
 365 void r600_cp_stop(struct radeon_device *rdev);
 366 int r600_cp_start(struct radeon_device *rdev);
 367 void r600_ring_init(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ring_size);
 368 int r600_cp_resume(struct radeon_device *rdev);
 369 void r600_cp_fini(struct radeon_device *rdev);
 370 int r600_count_pipe_bits(uint32_t val);
 371 int r600_mc_wait_for_idle(struct radeon_device *rdev);
 372 int r600_pcie_gart_init(struct radeon_device *rdev);
 373 void r600_scratch_init(struct radeon_device *rdev);
 374 int r600_init_microcode(struct radeon_device *rdev);
 375 u32 r600_gfx_get_rptr(struct radeon_device *rdev,
 376                       struct radeon_ring *ring);
 377 u32 r600_gfx_get_wptr(struct radeon_device *rdev,
 378                       struct radeon_ring *ring);
 379 void r600_gfx_set_wptr(struct radeon_device *rdev,
 380                        struct radeon_ring *ring);
 381 /* r600 irq */
 382 int r600_irq_process(struct radeon_device *rdev);
 383 int r600_irq_init(struct radeon_device *rdev);
 384 void r600_irq_fini(struct radeon_device *rdev);
 385 void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size);
 386 int r600_irq_set(struct radeon_device *rdev);
 387 void r600_irq_suspend(struct radeon_device *rdev);
 388 void r600_disable_interrupts(struct radeon_device *rdev);
 389 void r600_rlc_stop(struct radeon_device *rdev);
 390 /* r600 audio */
 391 int r600_audio_init(struct radeon_device *rdev);
 392 struct r600_audio_pin r600_audio_status(struct radeon_device *rdev);
 393 void r600_audio_fini(struct radeon_device *rdev);
 394 void r600_audio_set_dto(struct drm_encoder *encoder, u32 clock);
 395 void r600_hdmi_update_avi_infoframe(struct drm_encoder *encoder, void *buffer,
 396                                     size_t size);
 397 void r600_hdmi_update_ACR(struct drm_encoder *encoder, uint32_t clock);
 398 void r600_hdmi_audio_workaround(struct drm_encoder *encoder);
 399 int r600_hdmi_buffer_status_changed(struct drm_encoder *encoder);
 400 void r600_hdmi_update_audio_settings(struct drm_encoder *encoder);
 401 void r600_hdmi_enable(struct drm_encoder *encoder, bool enable);
 402 void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode);
 403 int r600_mc_wait_for_idle(struct radeon_device *rdev);
 404 u32 r600_get_xclk(struct radeon_device *rdev);
 405 uint64_t r600_get_gpu_clock_counter(struct radeon_device *rdev);
 406 int rv6xx_get_temp(struct radeon_device *rdev);
 407 int r600_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
 408 int r600_dpm_pre_set_power_state(struct radeon_device *rdev);
 409 void r600_dpm_post_set_power_state(struct radeon_device *rdev);
 410 int r600_dpm_late_enable(struct radeon_device *rdev);
 411 /* r600 dma */
 412 uint32_t r600_dma_get_rptr(struct radeon_device *rdev,
 413                            struct radeon_ring *ring);
 414 uint32_t r600_dma_get_wptr(struct radeon_device *rdev,
 415                            struct radeon_ring *ring);
 416 void r600_dma_set_wptr(struct radeon_device *rdev,
 417                        struct radeon_ring *ring);
 418 /* rv6xx dpm */
 419 int rv6xx_dpm_init(struct radeon_device *rdev);
 420 int rv6xx_dpm_enable(struct radeon_device *rdev);
 421 void rv6xx_dpm_disable(struct radeon_device *rdev);
 422 int rv6xx_dpm_set_power_state(struct radeon_device *rdev);
 423 void rv6xx_setup_asic(struct radeon_device *rdev);
 424 void rv6xx_dpm_display_configuration_changed(struct radeon_device *rdev);
 425 void rv6xx_dpm_fini(struct radeon_device *rdev);
 426 u32 rv6xx_dpm_get_sclk(struct radeon_device *rdev, bool low);
 427 u32 rv6xx_dpm_get_mclk(struct radeon_device *rdev, bool low);
 428 void rv6xx_dpm_print_power_state(struct radeon_device *rdev,
 429                                  struct radeon_ps *ps);
 430 void rv6xx_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
 431                                                        struct seq_file *m);
 432 int rv6xx_dpm_force_performance_level(struct radeon_device *rdev,
 433                                       enum radeon_dpm_forced_level level);
 434 /* rs780 dpm */
 435 int rs780_dpm_init(struct radeon_device *rdev);
 436 int rs780_dpm_enable(struct radeon_device *rdev);
 437 void rs780_dpm_disable(struct radeon_device *rdev);
 438 int rs780_dpm_set_power_state(struct radeon_device *rdev);
 439 void rs780_dpm_setup_asic(struct radeon_device *rdev);
 440 void rs780_dpm_display_configuration_changed(struct radeon_device *rdev);
 441 void rs780_dpm_fini(struct radeon_device *rdev);
 442 u32 rs780_dpm_get_sclk(struct radeon_device *rdev, bool low);
 443 u32 rs780_dpm_get_mclk(struct radeon_device *rdev, bool low);
 444 void rs780_dpm_print_power_state(struct radeon_device *rdev,
 445                                  struct radeon_ps *ps);
 446 void rs780_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
 447                                                        struct seq_file *m);
 448 int rs780_dpm_force_performance_level(struct radeon_device *rdev,
 449                                       enum radeon_dpm_forced_level level);
 450
 451 /*
 452  * rv770,rv730,rv710,rv740
 453  */
 454 int rv770_init(struct radeon_device *rdev);
 455 void rv770_fini(struct radeon_device *rdev);
 456 int rv770_suspend(struct radeon_device *rdev);
 457 int rv770_resume(struct radeon_device *rdev);
 458 void rv770_pm_misc(struct radeon_device *rdev);
 459 void rv770_page_flip(struct radeon_device *rdev, int crtc, u64 crtc_base);
 460 bool rv770_page_flip_pending(struct radeon_device *rdev, int crtc);
 461 void r700_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc);
 462 void r700_cp_stop(struct radeon_device *rdev);
 463 void r700_cp_fini(struct radeon_device *rdev);
 464 int rv770_copy_dma(struct radeon_device *rdev,
 465                   uint64_t src_offset, uint64_t dst_offset,
 466                   unsigned num_gpu_pages,
 467                    struct radeon_fence **fence);
 468 u32 rv770_get_xclk(struct radeon_device *rdev);
 469 int rv770_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
 470 int rv770_get_temp(struct radeon_device *rdev);
 471 /* hdmi */
 472 void dce3_1_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode);
 473 /* rv7xx pm */
 474 int rv770_dpm_init(struct radeon_device *rdev);
 475 int rv770_dpm_enable(struct radeon_device *rdev);
 476 int rv770_dpm_late_enable(struct radeon_device *rdev);
 477 void rv770_dpm_disable(struct radeon_device *rdev);
 478 int rv770_dpm_set_power_state(struct radeon_device *rdev);
 479 void rv770_dpm_setup_asic(struct radeon_device *rdev);
 480 void rv770_dpm_display_configuration_changed(struct radeon_device *rdev);
 481 void rv770_dpm_fini(struct radeon_device *rdev);
 482 u32 rv770_dpm_get_sclk(struct radeon_device *rdev, bool low);
 483 u32 rv770_dpm_get_mclk(struct radeon_device *rdev, bool low);
 484 void rv770_dpm_print_power_state(struct radeon_device *rdev,
 485                                  struct radeon_ps *ps);
 486 void rv770_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
 487                                                        struct seq_file *m);
 488 int rv770_dpm_force_performance_level(struct radeon_device *rdev,
 489                                       enum radeon_dpm_forced_level level);
 490 bool rv770_dpm_vblank_too_short(struct radeon_device *rdev);
 491
 492 /*
 493  * evergreen
 494  */
 495 struct evergreen_mc_save {
 496         u32 vga_render_control;
 497         u32 vga_hdp_control;
 498         bool crtc_enabled[RADEON_MAX_CRTCS];
 499 };
 500
 501 void evergreen_pcie_gart_tlb_flush(struct radeon_device *rdev);
 502 int evergreen_init(struct radeon_device *rdev);
 503 void evergreen_fini(struct radeon_device *rdev);
 504 int evergreen_suspend(struct radeon_device *rdev);
 505 int evergreen_resume(struct radeon_device *rdev);
 506 bool evergreen_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp);
 507 bool evergreen_dma_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp);
 508 int evergreen_asic_reset(struct radeon_device *rdev);
 509 void evergreen_bandwidth_update(struct radeon_device *rdev);
 510 void evergreen_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
 511 void evergreen_hpd_init(struct radeon_device *rdev);
 512 void evergreen_hpd_fini(struct radeon_device *rdev);
 513 bool evergreen_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd);
 514 void evergreen_hpd_set_polarity(struct radeon_device *rdev,
 515                                 enum radeon_hpd_id hpd);
 516 u32 evergreen_get_vblank_counter(struct radeon_device *rdev, int crtc);
 517 int evergreen_irq_set(struct radeon_device *rdev);
 518 int evergreen_irq_process(struct radeon_device *rdev);
 519 extern int evergreen_cs_parse(struct radeon_cs_parser *p);
 520 extern int evergreen_dma_cs_parse(struct radeon_cs_parser *p);
 521 extern void evergreen_pm_misc(struct radeon_device *rdev);
 522 extern void evergreen_pm_prepare(struct radeon_device *rdev);
 523 extern void evergreen_pm_finish(struct radeon_device *rdev);
 524 extern void sumo_pm_init_profile(struct radeon_device *rdev);
 525 extern void btc_pm_init_profile(struct radeon_device *rdev);
 526 int sumo_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
 527 int evergreen_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
 528 extern void evergreen_page_flip(struct radeon_device *rdev, int crtc,
 529                                 u64 crtc_base);
 530 extern bool evergreen_page_flip_pending(struct radeon_device *rdev, int crtc);
 531 extern void dce4_wait_for_vblank(struct radeon_device *rdev, int crtc);
 532 void evergreen_disable_interrupt_state(struct radeon_device *rdev);
 533 int evergreen_mc_wait_for_idle(struct radeon_device *rdev);
 534 void evergreen_dma_fence_ring_emit(struct radeon_device *rdev,
 535                                    struct radeon_fence *fence);
 536 void evergreen_dma_ring_ib_execute(struct radeon_device *rdev,
 537                                    struct radeon_ib *ib);
 538 int evergreen_copy_dma(struct radeon_device *rdev,
 539                        uint64_t src_offset, uint64_t dst_offset,
 540                        unsigned num_gpu_pages,
 541                        struct radeon_fence **fence);
 542 void evergreen_hdmi_enable(struct drm_encoder *encoder, bool enable);
 543 void evergreen_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode);
 544 int evergreen_get_temp(struct radeon_device *rdev);
 545 int sumo_get_temp(struct radeon_device *rdev);
 546 int tn_get_temp(struct radeon_device *rdev);
 547 int cypress_dpm_init(struct radeon_device *rdev);
 548 void cypress_dpm_setup_asic(struct radeon_device *rdev);
 549 int cypress_dpm_enable(struct radeon_device *rdev);
 550 void cypress_dpm_disable(struct radeon_device *rdev);
 551 int cypress_dpm_set_power_state(struct radeon_device *rdev);
 552 void cypress_dpm_display_configuration_changed(struct radeon_device *rdev);
 553 void cypress_dpm_fini(struct radeon_device *rdev);
 554 bool cypress_dpm_vblank_too_short(struct radeon_device *rdev);
 555 int btc_dpm_init(struct radeon_device *rdev);
 556 void btc_dpm_setup_asic(struct radeon_device *rdev);
 557 int btc_dpm_enable(struct radeon_device *rdev);
 558 void btc_dpm_disable(struct radeon_device *rdev);
 559 int btc_dpm_pre_set_power_state(struct radeon_device *rdev);
 560 int btc_dpm_set_power_state(struct radeon_device *rdev);
 561 void btc_dpm_post_set_power_state(struct radeon_device *rdev);
 562 void btc_dpm_fini(struct radeon_device *rdev);
 563 u32 btc_dpm_get_sclk(struct radeon_device *rdev, bool low);
 564 u32 btc_dpm_get_mclk(struct radeon_device *rdev, bool low);
 565 bool btc_dpm_vblank_too_short(struct radeon_device *rdev);
 566 void btc_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
 567                                                      struct seq_file *m);
 568 int sumo_dpm_init(struct radeon_device *rdev);
 569 int sumo_dpm_enable(struct radeon_device *rdev);
 570 int sumo_dpm_late_enable(struct radeon_device *rdev);
 571 void sumo_dpm_disable(struct radeon_device *rdev);
 572 int sumo_dpm_pre_set_power_state(struct radeon_device *rdev);
 573 int sumo_dpm_set_power_state(struct radeon_device *rdev);
 574 void sumo_dpm_post_set_power_state(struct radeon_device *rdev);
 575 void sumo_dpm_setup_asic(struct radeon_device *rdev);
 576 void sumo_dpm_display_configuration_changed(struct radeon_device *rdev);
 577 void sumo_dpm_fini(struct radeon_device *rdev);
 578 u32 sumo_dpm_get_sclk(struct radeon_device *rdev, bool low);
 579 u32 sumo_dpm_get_mclk(struct radeon_device *rdev, bool low);
 580 void sumo_dpm_print_power_state(struct radeon_device *rdev,
 581                                 struct radeon_ps *ps);
 582 void sumo_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
 583                                                       struct seq_file *m);
 584 int sumo_dpm_force_performance_level(struct radeon_device *rdev,
 585                                      enum radeon_dpm_forced_level level);
 586
 587 /*
 588  * cayman
 589  */
 590 void cayman_fence_ring_emit(struct radeon_device *rdev,
 591                             struct radeon_fence *fence);
 592 void cayman_pcie_gart_tlb_flush(struct radeon_device *rdev);
 593 int cayman_init(struct radeon_device *rdev);
 594 void cayman_fini(struct radeon_device *rdev);
 595 int cayman_suspend(struct radeon_device *rdev);
 596 int cayman_resume(struct radeon_device *rdev);
 597 int cayman_asic_reset(struct radeon_device *rdev);
 598 void cayman_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
 599 int cayman_vm_init(struct radeon_device *rdev);
 600 void cayman_vm_fini(struct radeon_device *rdev);
 601 void cayman_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm);
 602 uint32_t cayman_vm_page_flags(struct radeon_device *rdev, uint32_t flags);
 603 int evergreen_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib);
 604 int evergreen_dma_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib);
 605 void cayman_dma_ring_ib_execute(struct radeon_device *rdev,
 606                                 struct radeon_ib *ib);
 607 bool cayman_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring);
 608 bool cayman_dma_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring);
 609 void cayman_dma_vm_set_page(struct radeon_device *rdev,
 610                             struct radeon_ib *ib,
 611                             uint64_t pe,
 612                             uint64_t addr, unsigned count,
 613                             uint32_t incr, uint32_t flags);
 614
 615 void cayman_dma_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm);
 616
 617 u32 cayman_gfx_get_rptr(struct radeon_device *rdev,
 618                         struct radeon_ring *ring);
 619 u32 cayman_gfx_get_wptr(struct radeon_device *rdev,
 620                         struct radeon_ring *ring);
 621 void cayman_gfx_set_wptr(struct radeon_device *rdev,
 622                          struct radeon_ring *ring);
 623 uint32_t cayman_dma_get_rptr(struct radeon_device *rdev,
 624                              struct radeon_ring *ring);
 625 uint32_t cayman_dma_get_wptr(struct radeon_device *rdev,
 626                              struct radeon_ring *ring);
 627 void cayman_dma_set_wptr(struct radeon_device *rdev,
 628                          struct radeon_ring *ring);
 629
 630 int ni_dpm_init(struct radeon_device *rdev);
 631 void ni_dpm_setup_asic(struct radeon_device *rdev);
 632 int ni_dpm_enable(struct radeon_device *rdev);
 633 void ni_dpm_disable(struct radeon_device *rdev);
 634 int ni_dpm_pre_set_power_state(struct radeon_device *rdev);
 635 int ni_dpm_set_power_state(struct radeon_device *rdev);
 636 void ni_dpm_post_set_power_state(struct radeon_device *rdev);
 637 void ni_dpm_fini(struct radeon_device *rdev);
 638 u32 ni_dpm_get_sclk(struct radeon_device *rdev, bool low);
 639 u32 ni_dpm_get_mclk(struct radeon_device *rdev, bool low);
 640 void ni_dpm_print_power_state(struct radeon_device *rdev,
 641                               struct radeon_ps *ps);
 642 void ni_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
 643                                                     struct seq_file *m);
 644 int ni_dpm_force_performance_level(struct radeon_device *rdev,
 645                                    enum radeon_dpm_forced_level level);
 646 bool ni_dpm_vblank_too_short(struct radeon_device *rdev);
 647 int trinity_dpm_init(struct radeon_device *rdev);
 648 int trinity_dpm_enable(struct radeon_device *rdev);
 649 int trinity_dpm_late_enable(struct radeon_device *rdev);
 650 void trinity_dpm_disable(struct radeon_device *rdev);
 651 int trinity_dpm_pre_set_power_state(struct radeon_device *rdev);
 652 int trinity_dpm_set_power_state(struct radeon_device *rdev);
 653 void trinity_dpm_post_set_power_state(struct radeon_device *rdev);
 654 void trinity_dpm_setup_asic(struct radeon_device *rdev);
 655 void trinity_dpm_display_configuration_changed(struct radeon_device *rdev);
 656 void trinity_dpm_fini(struct radeon_device *rdev);
 657 u32 trinity_dpm_get_sclk(struct radeon_device *rdev, bool low);
 658 u32 trinity_dpm_get_mclk(struct radeon_device *rdev, bool low);
 659 void trinity_dpm_print_power_state(struct radeon_device *rdev,
 660                                    struct radeon_ps *ps);
 661 void trinity_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
 662                                                          struct seq_file *m);
 663 int trinity_dpm_force_performance_level(struct radeon_device *rdev,
 664                                         enum radeon_dpm_forced_level level);
 665 void trinity_dpm_enable_bapm(struct radeon_device *rdev, bool enable);
 666
 667 /* DCE6 - SI */
 668 void dce6_bandwidth_update(struct radeon_device *rdev);
 669 int dce6_audio_init(struct radeon_device *rdev);
 670 void dce6_audio_fini(struct radeon_device *rdev);
 671
 672 /*
 673  * si
 674  */
 675 void si_fence_ring_emit(struct radeon_device *rdev,
 676                         struct radeon_fence *fence);
 677 void si_pcie_gart_tlb_flush(struct radeon_device *rdev);
 678 int si_init(struct radeon_device *rdev);
 679 void si_fini(struct radeon_device *rdev);
 680 int si_suspend(struct radeon_device *rdev);
 681 int si_resume(struct radeon_device *rdev);
 682 bool si_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp);
 683 bool si_dma_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp);
 684 int si_asic_reset(struct radeon_device *rdev);
 685 void si_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
 686 int si_irq_set(struct radeon_device *rdev);
 687 int si_irq_process(struct radeon_device *rdev);
 688 int si_vm_init(struct radeon_device *rdev);
 689 void si_vm_fini(struct radeon_device *rdev);
 690 void si_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm);
 691 int si_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib);
 692 int si_copy_dma(struct radeon_device *rdev,
 693                 uint64_t src_offset, uint64_t dst_offset,
 694                 unsigned num_gpu_pages,
 695                 struct radeon_fence **fence);
 696 void si_dma_vm_set_page(struct radeon_device *rdev,
 697                         struct radeon_ib *ib,
 698                         uint64_t pe,
 699                         uint64_t addr, unsigned count,
 700                         uint32_t incr, uint32_t flags);
 701 void si_dma_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm);
 702 u32 si_get_xclk(struct radeon_device *rdev);
 703 uint64_t si_get_gpu_clock_counter(struct radeon_device *rdev);
 704 int si_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
 705 int si_get_temp(struct radeon_device *rdev);
 706 int si_dpm_init(struct radeon_device *rdev);
 707 void si_dpm_setup_asic(struct radeon_device *rdev);
 708 int si_dpm_enable(struct radeon_device *rdev);
 709 int si_dpm_late_enable(struct radeon_device *rdev);
 710 void si_dpm_disable(struct radeon_device *rdev);
 711 int si_dpm_pre_set_power_state(struct radeon_device *rdev);
 712 int si_dpm_set_power_state(struct radeon_device *rdev);
 713 void si_dpm_post_set_power_state(struct radeon_device *rdev);
 714 void si_dpm_fini(struct radeon_device *rdev);
 715 void si_dpm_display_configuration_changed(struct radeon_device *rdev);
 716 void si_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
 717                                                     struct seq_file *m);
 718 int si_dpm_force_performance_level(struct radeon_device *rdev,
 719                                    enum radeon_dpm_forced_level level);
 720
 721 /* DCE8 - CIK */
 722 void dce8_bandwidth_update(struct radeon_device *rdev);
 723
 724 /*
 725  * cik
 726  */
 727 uint64_t cik_get_gpu_clock_counter(struct radeon_device *rdev);
 728 u32 cik_get_xclk(struct radeon_device *rdev);
 729 uint32_t cik_pciep_rreg(struct radeon_device *rdev, uint32_t reg);
 730 void cik_pciep_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
 731 int cik_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
 732 int cik_set_vce_clocks(struct radeon_device *rdev, u32 evclk, u32 ecclk);
 733 void cik_sdma_fence_ring_emit(struct radeon_device *rdev,
 734                               struct radeon_fence *fence);
 735 bool cik_sdma_semaphore_ring_emit(struct radeon_device *rdev,
 736                                   struct radeon_ring *ring,
 737                                   struct radeon_semaphore *semaphore,
 738                                   bool emit_wait);
 739 void cik_sdma_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
 740 int cik_copy_dma(struct radeon_device *rdev,
 741                  uint64_t src_offset, uint64_t dst_offset,
 742                  unsigned num_gpu_pages,
 743                  struct radeon_fence **fence);
 744 int cik_copy_cpdma(struct radeon_device *rdev,
 745                    uint64_t src_offset, uint64_t dst_offset,
 746                    unsigned num_gpu_pages,
 747                    struct radeon_fence **fence);
 748 int cik_sdma_ring_test(struct radeon_device *rdev, struct radeon_ring *ring);
 749 int cik_sdma_ib_test(struct radeon_device *rdev, struct radeon_ring *ring);
 750 bool cik_sdma_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring);
 751 void cik_fence_gfx_ring_emit(struct radeon_device *rdev,
 752                              struct radeon_fence *fence);
 753 void cik_fence_compute_ring_emit(struct radeon_device *rdev,
 754                                  struct radeon_fence *fence);
 755 bool cik_semaphore_ring_emit(struct radeon_device *rdev,
 756                              struct radeon_ring *cp,
 757                              struct radeon_semaphore *semaphore,
 758                              bool emit_wait);
 759 void cik_pcie_gart_tlb_flush(struct radeon_device *rdev);
 760 int cik_init(struct radeon_device *rdev);
 761 void cik_fini(struct radeon_device *rdev);
 762 int cik_suspend(struct radeon_device *rdev);
 763 int cik_resume(struct radeon_device *rdev);
 764 bool cik_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp);
 765 int cik_asic_reset(struct radeon_device *rdev);
 766 void cik_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
 767 int cik_ring_test(struct radeon_device *rdev, struct radeon_ring *ring);
 768 int cik_ib_test(struct radeon_device *rdev, struct radeon_ring *ring);
 769 int cik_irq_set(struct radeon_device *rdev);
 770 int cik_irq_process(struct radeon_device *rdev);
 771 int cik_vm_init(struct radeon_device *rdev);
 772 void cik_vm_fini(struct radeon_device *rdev);
 773 void cik_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm);
 774 void cik_sdma_vm_set_page(struct radeon_device *rdev,
 775                           struct radeon_ib *ib,
 776                           uint64_t pe,
 777                           uint64_t addr, unsigned count,
 778                           uint32_t incr, uint32_t flags);
 779 void cik_dma_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm);
 780 int cik_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib);
 781 u32 cik_gfx_get_rptr(struct radeon_device *rdev,
 782                      struct radeon_ring *ring);
 783 u32 cik_gfx_get_wptr(struct radeon_device *rdev,
 784                      struct radeon_ring *ring);
 785 void cik_gfx_set_wptr(struct radeon_device *rdev,
 786                       struct radeon_ring *ring);
 787 u32 cik_compute_get_rptr(struct radeon_device *rdev,
 788                          struct radeon_ring *ring);
 789 u32 cik_compute_get_wptr(struct radeon_device *rdev,
 790                          struct radeon_ring *ring);
 791 void cik_compute_set_wptr(struct radeon_device *rdev,
 792                           struct radeon_ring *ring);
 793 u32 cik_sdma_get_rptr(struct radeon_device *rdev,
 794                       struct radeon_ring *ring);
 795 u32 cik_sdma_get_wptr(struct radeon_device *rdev,
 796                       struct radeon_ring *ring);
 797 void cik_sdma_set_wptr(struct radeon_device *rdev,
 798                        struct radeon_ring *ring);
 799 int ci_get_temp(struct radeon_device *rdev);
 800 int kv_get_temp(struct radeon_device *rdev);
 801
 802 int ci_dpm_init(struct radeon_device *rdev);
 803 int ci_dpm_enable(struct radeon_device *rdev);
 804 int ci_dpm_late_enable(struct radeon_device *rdev);
 805 void ci_dpm_disable(struct radeon_device *rdev);
 806 int ci_dpm_pre_set_power_state(struct radeon_device *rdev);
 807 int ci_dpm_set_power_state(struct radeon_device *rdev);
 808 void ci_dpm_post_set_power_state(struct radeon_device *rdev);
 809 void ci_dpm_setup_asic(struct radeon_device *rdev);
 810 void ci_dpm_display_configuration_changed(struct radeon_device *rdev);
 811 void ci_dpm_fini(struct radeon_device *rdev);
 812 u32 ci_dpm_get_sclk(struct radeon_device *rdev, bool low);
 813 u32 ci_dpm_get_mclk(struct radeon_device *rdev, bool low);
 814 void ci_dpm_print_power_state(struct radeon_device *rdev,
 815                               struct radeon_ps *ps);
 816 void ci_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
 817                                                     struct seq_file *m);
 818 int ci_dpm_force_performance_level(struct radeon_device *rdev,
 819                                    enum radeon_dpm_forced_level level);
 820 bool ci_dpm_vblank_too_short(struct radeon_device *rdev);
 821 void ci_dpm_powergate_uvd(struct radeon_device *rdev, bool gate);
 822
 823 int kv_dpm_init(struct radeon_device *rdev);
 824 int kv_dpm_enable(struct radeon_device *rdev);
 825 int kv_dpm_late_enable(struct radeon_device *rdev);
 826 void kv_dpm_disable(struct radeon_device *rdev);
 827 int kv_dpm_pre_set_power_state(struct radeon_device *rdev);
 828 int kv_dpm_set_power_state(struct radeon_device *rdev);
 829 void kv_dpm_post_set_power_state(struct radeon_device *rdev);
 830 void kv_dpm_setup_asic(struct radeon_device *rdev);
 831 void kv_dpm_display_configuration_changed(struct radeon_device *rdev);
 832 void kv_dpm_fini(struct radeon_device *rdev);
 833 u32 kv_dpm_get_sclk(struct radeon_device *rdev, bool low);
 834 u32 kv_dpm_get_mclk(struct radeon_device *rdev, bool low);
 835 void kv_dpm_print_power_state(struct radeon_device *rdev,
 836                               struct radeon_ps *ps);
 837 void kv_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
 838                                                     struct seq_file *m);
 839 int kv_dpm_force_performance_level(struct radeon_device *rdev,
 840                                    enum radeon_dpm_forced_level level);
 841 void kv_dpm_powergate_uvd(struct radeon_device *rdev, bool gate);
 842 void kv_dpm_enable_bapm(struct radeon_device *rdev, bool enable);
 843
 844 /* uvd v1.0 */
 845 uint32_t uvd_v1_0_get_rptr(struct radeon_device *rdev,
 846                            struct radeon_ring *ring);
 847 uint32_t uvd_v1_0_get_wptr(struct radeon_device *rdev,
 848                            struct radeon_ring *ring);
 849 void uvd_v1_0_set_wptr(struct radeon_device *rdev,
 850                        struct radeon_ring *ring);
 851
 852 int uvd_v1_0_init(struct radeon_device *rdev);
 853 void uvd_v1_0_fini(struct radeon_device *rdev);
 854 int uvd_v1_0_start(struct radeon_device *rdev);
 855 void uvd_v1_0_stop(struct radeon_device *rdev);
 856
 857 int uvd_v1_0_ring_test(struct radeon_device *rdev, struct radeon_ring *ring);
 858 int uvd_v1_0_ib_test(struct radeon_device *rdev, struct radeon_ring *ring);
 859 bool uvd_v1_0_semaphore_emit(struct radeon_device *rdev,
 860                              struct radeon_ring *ring,
 861                              struct radeon_semaphore *semaphore,
 862                              bool emit_wait);
 863 void uvd_v1_0_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
 864
 865 /* uvd v2.2 */
 866 int uvd_v2_2_resume(struct radeon_device *rdev);
 867 void uvd_v2_2_fence_emit(struct radeon_device *rdev,
 868                          struct radeon_fence *fence);
 869
 870 /* uvd v3.1 */
 871 bool uvd_v3_1_semaphore_emit(struct radeon_device *rdev,
 872                              struct radeon_ring *ring,
 873                              struct radeon_semaphore *semaphore,
 874                              bool emit_wait);
 875
 876 /* uvd v4.2 */
 877 int uvd_v4_2_resume(struct radeon_device *rdev);
 878
 879 /* vce v1.0 */
 880 uint32_t vce_v1_0_get_rptr(struct radeon_device *rdev,
 881                            struct radeon_ring *ring);
 882 uint32_t vce_v1_0_get_wptr(struct radeon_device *rdev,
 883                            struct radeon_ring *ring);
 884 void vce_v1_0_set_wptr(struct radeon_device *rdev,
 885                        struct radeon_ring *ring);
 886 int vce_v1_0_init(struct radeon_device *rdev);
 887 int vce_v1_0_start(struct radeon_device *rdev);
 888
 889 /* vce v2.0 */
 890 int vce_v2_0_resume(struct radeon_device *rdev);
 891
 892 #endif