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sched: Remove double_rq_lock() from __migrate_task()
[linux/fpc-iii.git] / drivers / gpu / drm / radeon / radeon_display.c
blobbf25061c8ac4ee37b0f1c72b003427eb551dca22
1 /*
2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: Dave Airlie
24 * Alex Deucher
25 */
26 #include <drm/drmP.h>
27 #include <drm/radeon_drm.h>
28 #include "radeon.h"
29
30 #include "atom.h"
31 #include <asm/div64.h>
32
33 #include <linux/pm_runtime.h>
34 #include <drm/drm_crtc_helper.h>
35 #include <drm/drm_edid.h>
36
37 #include <linux/gcd.h>
38
39 static void avivo_crtc_load_lut(struct drm_crtc *crtc)
40 {
41 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
42 struct drm_device *dev = crtc->dev;
43 struct radeon_device *rdev = dev->dev_private;
44 int i;
45
46 DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id);
47 WREG32(AVIVO_DC_LUTA_CONTROL + radeon_crtc->crtc_offset, 0);
48
49 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
50 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
51 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
52
53 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);
54 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);
55 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);
56
57 WREG32(AVIVO_DC_LUT_RW_SELECT, radeon_crtc->crtc_id);
58 WREG32(AVIVO_DC_LUT_RW_MODE, 0);
59 WREG32(AVIVO_DC_LUT_WRITE_EN_MASK, 0x0000003f);
60
61 WREG8(AVIVO_DC_LUT_RW_INDEX, 0);
62 for (i = 0; i < 256; i++) {
63 WREG32(AVIVO_DC_LUT_30_COLOR,
64 (radeon_crtc->lut_r[i] << 20) |
65 (radeon_crtc->lut_g[i] << 10) |
66 (radeon_crtc->lut_b[i] << 0));
67 }
68
69 /* Only change bit 0 of LUT_SEL, other bits are set elsewhere */
70 WREG32_P(AVIVO_D1GRPH_LUT_SEL + radeon_crtc->crtc_offset, radeon_crtc->crtc_id, ~1);
71 }
72
73 static void dce4_crtc_load_lut(struct drm_crtc *crtc)
74 {
75 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
76 struct drm_device *dev = crtc->dev;
77 struct radeon_device *rdev = dev->dev_private;
78 int i;
79
80 DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id);
81 WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0);
82
83 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
84 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
85 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
86
87 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);
88 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);
89 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);
90
91 WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0);
92 WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007);
93
94 WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0);
95 for (i = 0; i < 256; i++) {
96 WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset,
97 (radeon_crtc->lut_r[i] << 20) |
98 (radeon_crtc->lut_g[i] << 10) |
99 (radeon_crtc->lut_b[i] << 0));
100 }
101 }
102
103 static void dce5_crtc_load_lut(struct drm_crtc *crtc)
104 {
105 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
106 struct drm_device *dev = crtc->dev;
107 struct radeon_device *rdev = dev->dev_private;
108 int i;
109
110 DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id);
111
112 WREG32(NI_INPUT_CSC_CONTROL + radeon_crtc->crtc_offset,
113 (NI_INPUT_CSC_GRPH_MODE(NI_INPUT_CSC_BYPASS) |
114 NI_INPUT_CSC_OVL_MODE(NI_INPUT_CSC_BYPASS)));
115 WREG32(NI_PRESCALE_GRPH_CONTROL + radeon_crtc->crtc_offset,
116 NI_GRPH_PRESCALE_BYPASS);
117 WREG32(NI_PRESCALE_OVL_CONTROL + radeon_crtc->crtc_offset,
118 NI_OVL_PRESCALE_BYPASS);
119 WREG32(NI_INPUT_GAMMA_CONTROL + radeon_crtc->crtc_offset,
120 (NI_GRPH_INPUT_GAMMA_MODE(NI_INPUT_GAMMA_USE_LUT) |
121 NI_OVL_INPUT_GAMMA_MODE(NI_INPUT_GAMMA_USE_LUT)));
122
123 WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0);
124
125 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
126 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
127 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
128
129 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);
130 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);
131 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);
132
133 WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0);
134 WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007);
135
136 WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0);
137 for (i = 0; i < 256; i++) {
138 WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset,
139 (radeon_crtc->lut_r[i] << 20) |
140 (radeon_crtc->lut_g[i] << 10) |
141 (radeon_crtc->lut_b[i] << 0));
142 }
143
144 WREG32(NI_DEGAMMA_CONTROL + radeon_crtc->crtc_offset,
145 (NI_GRPH_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) |
146 NI_OVL_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) |
147 NI_ICON_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) |
148 NI_CURSOR_DEGAMMA_MODE(NI_DEGAMMA_BYPASS)));
149 WREG32(NI_GAMUT_REMAP_CONTROL + radeon_crtc->crtc_offset,
150 (NI_GRPH_GAMUT_REMAP_MODE(NI_GAMUT_REMAP_BYPASS) |
151 NI_OVL_GAMUT_REMAP_MODE(NI_GAMUT_REMAP_BYPASS)));
152 WREG32(NI_REGAMMA_CONTROL + radeon_crtc->crtc_offset,
153 (NI_GRPH_REGAMMA_MODE(NI_REGAMMA_BYPASS) |
154 NI_OVL_REGAMMA_MODE(NI_REGAMMA_BYPASS)));
155 WREG32(NI_OUTPUT_CSC_CONTROL + radeon_crtc->crtc_offset,
156 (NI_OUTPUT_CSC_GRPH_MODE(NI_OUTPUT_CSC_BYPASS) |
157 NI_OUTPUT_CSC_OVL_MODE(NI_OUTPUT_CSC_BYPASS)));
158 /* XXX match this to the depth of the crtc fmt block, move to modeset? */
159 WREG32(0x6940 + radeon_crtc->crtc_offset, 0);
160 if (ASIC_IS_DCE8(rdev)) {
161 /* XXX this only needs to be programmed once per crtc at startup,
162 * not sure where the best place for it is
163 */
164 WREG32(CIK_ALPHA_CONTROL + radeon_crtc->crtc_offset,
165 CIK_CURSOR_ALPHA_BLND_ENA);
166 }
167 }
168
169 static void legacy_crtc_load_lut(struct drm_crtc *crtc)
170 {
171 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
172 struct drm_device *dev = crtc->dev;
173 struct radeon_device *rdev = dev->dev_private;
174 int i;
175 uint32_t dac2_cntl;
176
177 dac2_cntl = RREG32(RADEON_DAC_CNTL2);
178 if (radeon_crtc->crtc_id == 0)
179 dac2_cntl &= (uint32_t)~RADEON_DAC2_PALETTE_ACC_CTL;
180 else
181 dac2_cntl |= RADEON_DAC2_PALETTE_ACC_CTL;
182 WREG32(RADEON_DAC_CNTL2, dac2_cntl);
183
184 WREG8(RADEON_PALETTE_INDEX, 0);
185 for (i = 0; i < 256; i++) {
186 WREG32(RADEON_PALETTE_30_DATA,
187 (radeon_crtc->lut_r[i] << 20) |
188 (radeon_crtc->lut_g[i] << 10) |
189 (radeon_crtc->lut_b[i] << 0));
190 }
191 }
192
193 void radeon_crtc_load_lut(struct drm_crtc *crtc)
194 {
195 struct drm_device *dev = crtc->dev;
196 struct radeon_device *rdev = dev->dev_private;
197
198 if (!crtc->enabled)
199 return;
200
201 if (ASIC_IS_DCE5(rdev))
202 dce5_crtc_load_lut(crtc);
203 else if (ASIC_IS_DCE4(rdev))
204 dce4_crtc_load_lut(crtc);
205 else if (ASIC_IS_AVIVO(rdev))
206 avivo_crtc_load_lut(crtc);
207 else
208 legacy_crtc_load_lut(crtc);
209 }
210
211 /** Sets the color ramps on behalf of fbcon */
212 void radeon_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
213 u16 blue, int regno)
214 {
215 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
216
217 radeon_crtc->lut_r[regno] = red >> 6;
218 radeon_crtc->lut_g[regno] = green >> 6;
219 radeon_crtc->lut_b[regno] = blue >> 6;
220 }
221
222 /** Gets the color ramps on behalf of fbcon */
223 void radeon_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
224 u16 *blue, int regno)
225 {
226 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
227
228 *red = radeon_crtc->lut_r[regno] << 6;
229 *green = radeon_crtc->lut_g[regno] << 6;
230 *blue = radeon_crtc->lut_b[regno] << 6;
231 }
232
233 static void radeon_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
234 u16 *blue, uint32_t start, uint32_t size)
235 {
236 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
237 int end = (start + size > 256) ? 256 : start + size, i;
238
239 /* userspace palettes are always correct as is */
240 for (i = start; i < end; i++) {
241 radeon_crtc->lut_r[i] = red[i] >> 6;
242 radeon_crtc->lut_g[i] = green[i] >> 6;
243 radeon_crtc->lut_b[i] = blue[i] >> 6;
244 }
245 radeon_crtc_load_lut(crtc);
246 }
247
248 static void radeon_crtc_destroy(struct drm_crtc *crtc)
249 {
250 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
251
252 drm_crtc_cleanup(crtc);
253 destroy_workqueue(radeon_crtc->flip_queue);
254 kfree(radeon_crtc);
255 }
256
257 /**
258 * radeon_unpin_work_func - unpin old buffer object
259 *
260 * @__work - kernel work item
261 *
262 * Unpin the old frame buffer object outside of the interrupt handler
263 */
264 static void radeon_unpin_work_func(struct work_struct *__work)
265 {
266 struct radeon_flip_work *work =
267 container_of(__work, struct radeon_flip_work, unpin_work);
268 int r;
269
270 /* unpin of the old buffer */
271 r = radeon_bo_reserve(work->old_rbo, false);
272 if (likely(r == 0)) {
273 r = radeon_bo_unpin(work->old_rbo);
274 if (unlikely(r != 0)) {
275 DRM_ERROR("failed to unpin buffer after flip\n");
276 }
277 radeon_bo_unreserve(work->old_rbo);
278 } else
279 DRM_ERROR("failed to reserve buffer after flip\n");
280
281 drm_gem_object_unreference_unlocked(&work->old_rbo->gem_base);
282 kfree(work);
283 }
284
285 void radeon_crtc_handle_vblank(struct radeon_device *rdev, int crtc_id)
286 {
287 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
288 unsigned long flags;
289 u32 update_pending;
290 int vpos, hpos;
291
292 /* can happen during initialization */
293 if (radeon_crtc == NULL)
294 return;
295
296 spin_lock_irqsave(&rdev->ddev->event_lock, flags);
297 if (radeon_crtc->flip_status != RADEON_FLIP_SUBMITTED) {
298 DRM_DEBUG_DRIVER("radeon_crtc->flip_status = %d != "
299 "RADEON_FLIP_SUBMITTED(%d)\n",
300 radeon_crtc->flip_status,
301 RADEON_FLIP_SUBMITTED);
302 spin_unlock_irqrestore(&rdev->ddev->event_lock, flags);
303 return;
304 }
305
306 update_pending = radeon_page_flip_pending(rdev, crtc_id);
307
308 /* Has the pageflip already completed in crtc, or is it certain
309 * to complete in this vblank?
310 */
311 if (update_pending &&
312 (DRM_SCANOUTPOS_VALID & radeon_get_crtc_scanoutpos(rdev->ddev, crtc_id, 0,
313 &vpos, &hpos, NULL, NULL)) &&
314 ((vpos >= (99 * rdev->mode_info.crtcs[crtc_id]->base.hwmode.crtc_vdisplay)/100) ||
315 (vpos < 0 && !ASIC_IS_AVIVO(rdev)))) {
316 /* crtc didn't flip in this target vblank interval,
317 * but flip is pending in crtc. Based on the current
318 * scanout position we know that the current frame is
319 * (nearly) complete and the flip will (likely)
320 * complete before the start of the next frame.
321 */
322 update_pending = 0;
323 }
324 spin_unlock_irqrestore(&rdev->ddev->event_lock, flags);
325 if (!update_pending)
326 radeon_crtc_handle_flip(rdev, crtc_id);
327 }
328
329 /**
330 * radeon_crtc_handle_flip - page flip completed
331 *
332 * @rdev: radeon device pointer
333 * @crtc_id: crtc number this event is for
334 *
335 * Called when we are sure that a page flip for this crtc is completed.
336 */
337 void radeon_crtc_handle_flip(struct radeon_device *rdev, int crtc_id)
338 {
339 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
340 struct radeon_flip_work *work;
341 unsigned long flags;
342
343 /* this can happen at init */
344 if (radeon_crtc == NULL)
345 return;
346
347 spin_lock_irqsave(&rdev->ddev->event_lock, flags);
348 work = radeon_crtc->flip_work;
349 if (radeon_crtc->flip_status != RADEON_FLIP_SUBMITTED) {
350 DRM_DEBUG_DRIVER("radeon_crtc->flip_status = %d != "
351 "RADEON_FLIP_SUBMITTED(%d)\n",
352 radeon_crtc->flip_status,
353 RADEON_FLIP_SUBMITTED);
354 spin_unlock_irqrestore(&rdev->ddev->event_lock, flags);
355 return;
356 }
357
358 /* Pageflip completed. Clean up. */
359 radeon_crtc->flip_status = RADEON_FLIP_NONE;
360 radeon_crtc->flip_work = NULL;
361
362 /* wakeup userspace */
363 if (work->event)
364 drm_send_vblank_event(rdev->ddev, crtc_id, work->event);
365
366 spin_unlock_irqrestore(&rdev->ddev->event_lock, flags);
367
368 drm_vblank_put(rdev->ddev, radeon_crtc->crtc_id);
369 radeon_irq_kms_pflip_irq_put(rdev, work->crtc_id);
370 queue_work(radeon_crtc->flip_queue, &work->unpin_work);
371 }
372
373 /**
374 * radeon_flip_work_func - page flip framebuffer
375 *
376 * @work - kernel work item
377 *
378 * Wait for the buffer object to become idle and do the actual page flip
379 */
380 static void radeon_flip_work_func(struct work_struct *__work)
381 {
382 struct radeon_flip_work *work =
383 container_of(__work, struct radeon_flip_work, flip_work);
384 struct radeon_device *rdev = work->rdev;
385 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[work->crtc_id];
386
387 struct drm_crtc *crtc = &radeon_crtc->base;
388 unsigned long flags;
389 int r;
390
391 down_read(&rdev->exclusive_lock);
392 if (work->fence) {
393 r = radeon_fence_wait(work->fence, false);
394 if (r == -EDEADLK) {
395 up_read(&rdev->exclusive_lock);
396 r = radeon_gpu_reset(rdev);
397 down_read(&rdev->exclusive_lock);
398 }
399 if (r)
400 DRM_ERROR("failed to wait on page flip fence (%d)!\n", r);
401
402 /* We continue with the page flip even if we failed to wait on
403 * the fence, otherwise the DRM core and userspace will be
404 * confused about which BO the CRTC is scanning out
405 */
406
407 radeon_fence_unref(&work->fence);
408 }
409
410 /* We borrow the event spin lock for protecting flip_status */
411 spin_lock_irqsave(&crtc->dev->event_lock, flags);
412
413 /* set the proper interrupt */
414 radeon_irq_kms_pflip_irq_get(rdev, radeon_crtc->crtc_id);
415
416 /* do the flip (mmio) */
417 radeon_page_flip(rdev, radeon_crtc->crtc_id, work->base);
418
419 radeon_crtc->flip_status = RADEON_FLIP_SUBMITTED;
420 spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
421 up_read(&rdev->exclusive_lock);
422 }
423
424 static int radeon_crtc_page_flip(struct drm_crtc *crtc,
425 struct drm_framebuffer *fb,
426 struct drm_pending_vblank_event *event,
427 uint32_t page_flip_flags)
428 {
429 struct drm_device *dev = crtc->dev;
430 struct radeon_device *rdev = dev->dev_private;
431 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
432 struct radeon_framebuffer *old_radeon_fb;
433 struct radeon_framebuffer *new_radeon_fb;
434 struct drm_gem_object *obj;
435 struct radeon_flip_work *work;
436 struct radeon_bo *new_rbo;
437 uint32_t tiling_flags, pitch_pixels;
438 uint64_t base;
439 unsigned long flags;
440 int r;
441
442 work = kzalloc(sizeof *work, GFP_KERNEL);
443 if (work == NULL)
444 return -ENOMEM;
445
446 INIT_WORK(&work->flip_work, radeon_flip_work_func);
447 INIT_WORK(&work->unpin_work, radeon_unpin_work_func);
448
449 work->rdev = rdev;
450 work->crtc_id = radeon_crtc->crtc_id;
451 work->event = event;
452
453 /* schedule unpin of the old buffer */
454 old_radeon_fb = to_radeon_framebuffer(crtc->primary->fb);
455 obj = old_radeon_fb->obj;
456
457 /* take a reference to the old object */
458 drm_gem_object_reference(obj);
459 work->old_rbo = gem_to_radeon_bo(obj);
460
461 new_radeon_fb = to_radeon_framebuffer(fb);
462 obj = new_radeon_fb->obj;
463 new_rbo = gem_to_radeon_bo(obj);
464
465 spin_lock(&new_rbo->tbo.bdev->fence_lock);
466 if (new_rbo->tbo.sync_obj)
467 work->fence = radeon_fence_ref(new_rbo->tbo.sync_obj);
468 spin_unlock(&new_rbo->tbo.bdev->fence_lock);
469
470 /* pin the new buffer */
471 DRM_DEBUG_DRIVER("flip-ioctl() cur_rbo = %p, new_rbo = %p\n",
472 work->old_rbo, new_rbo);
473
474 r = radeon_bo_reserve(new_rbo, false);
475 if (unlikely(r != 0)) {
476 DRM_ERROR("failed to reserve new rbo buffer before flip\n");
477 goto cleanup;
478 }
479 /* Only 27 bit offset for legacy CRTC */
480 r = radeon_bo_pin_restricted(new_rbo, RADEON_GEM_DOMAIN_VRAM,
481 ASIC_IS_AVIVO(rdev) ? 0 : 1 << 27, &base);
482 if (unlikely(r != 0)) {
483 radeon_bo_unreserve(new_rbo);
484 r = -EINVAL;
485 DRM_ERROR("failed to pin new rbo buffer before flip\n");
486 goto cleanup;
487 }
488 radeon_bo_get_tiling_flags(new_rbo, &tiling_flags, NULL);
489 radeon_bo_unreserve(new_rbo);
490
491 if (!ASIC_IS_AVIVO(rdev)) {
492 /* crtc offset is from display base addr not FB location */
493 base -= radeon_crtc->legacy_display_base_addr;
494 pitch_pixels = fb->pitches[0] / (fb->bits_per_pixel / 8);
495
496 if (tiling_flags & RADEON_TILING_MACRO) {
497 if (ASIC_IS_R300(rdev)) {
498 base &= ~0x7ff;
499 } else {
500 int byteshift = fb->bits_per_pixel >> 4;
501 int tile_addr = (((crtc->y >> 3) * pitch_pixels + crtc->x) >> (8 - byteshift)) << 11;
502 base += tile_addr + ((crtc->x << byteshift) % 256) + ((crtc->y % 8) << 8);
503 }
504 } else {
505 int offset = crtc->y * pitch_pixels + crtc->x;
506 switch (fb->bits_per_pixel) {
507 case 8:
508 default:
509 offset *= 1;
510 break;
511 case 15:
512 case 16:
513 offset *= 2;
514 break;
515 case 24:
516 offset *= 3;
517 break;
518 case 32:
519 offset *= 4;
520 break;
521 }
522 base += offset;
523 }
524 base &= ~7;
525 }
526 work->base = base;
527
528 r = drm_vblank_get(crtc->dev, radeon_crtc->crtc_id);
529 if (r) {
530 DRM_ERROR("failed to get vblank before flip\n");
531 goto pflip_cleanup;
532 }
533
534 /* We borrow the event spin lock for protecting flip_work */
535 spin_lock_irqsave(&crtc->dev->event_lock, flags);
536
537 if (radeon_crtc->flip_status != RADEON_FLIP_NONE) {
538 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
539 spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
540 r = -EBUSY;
541 goto vblank_cleanup;
542 }
543 radeon_crtc->flip_status = RADEON_FLIP_PENDING;
544 radeon_crtc->flip_work = work;
545
546 /* update crtc fb */
547 crtc->primary->fb = fb;
548
549 spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
550
551 queue_work(radeon_crtc->flip_queue, &work->flip_work);
552 return 0;
553
554 vblank_cleanup:
555 drm_vblank_put(crtc->dev, radeon_crtc->crtc_id);
556
557 pflip_cleanup:
558 if (unlikely(radeon_bo_reserve(new_rbo, false) != 0)) {
559 DRM_ERROR("failed to reserve new rbo in error path\n");
560 goto cleanup;
561 }
562 if (unlikely(radeon_bo_unpin(new_rbo) != 0)) {
563 DRM_ERROR("failed to unpin new rbo in error path\n");
564 }
565 radeon_bo_unreserve(new_rbo);
566
567 cleanup:
568 drm_gem_object_unreference_unlocked(&work->old_rbo->gem_base);
569 radeon_fence_unref(&work->fence);
570 kfree(work);
571
572 return r;
573 }
574
575 static int
576 radeon_crtc_set_config(struct drm_mode_set *set)
577 {
578 struct drm_device *dev;
579 struct radeon_device *rdev;
580 struct drm_crtc *crtc;
581 bool active = false;
582 int ret;
583
584 if (!set || !set->crtc)
585 return -EINVAL;
586
587 dev = set->crtc->dev;
588
589 ret = pm_runtime_get_sync(dev->dev);
590 if (ret < 0)
591 return ret;
592
593 ret = drm_crtc_helper_set_config(set);
594
595 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
596 if (crtc->enabled)
597 active = true;
598
599 pm_runtime_mark_last_busy(dev->dev);
600
601 rdev = dev->dev_private;
602 /* if we have active crtcs and we don't have a power ref,
603 take the current one */
604 if (active && !rdev->have_disp_power_ref) {
605 rdev->have_disp_power_ref = true;
606 return ret;
607 }
608 /* if we have no active crtcs, then drop the power ref
609 we got before */
610 if (!active && rdev->have_disp_power_ref) {
611 pm_runtime_put_autosuspend(dev->dev);
612 rdev->have_disp_power_ref = false;
613 }
614
615 /* drop the power reference we got coming in here */
616 pm_runtime_put_autosuspend(dev->dev);
617 return ret;
618 }
619 static const struct drm_crtc_funcs radeon_crtc_funcs = {
620 .cursor_set = radeon_crtc_cursor_set,
621 .cursor_move = radeon_crtc_cursor_move,
622 .gamma_set = radeon_crtc_gamma_set,
623 .set_config = radeon_crtc_set_config,
624 .destroy = radeon_crtc_destroy,
625 .page_flip = radeon_crtc_page_flip,
626 };
627
628 static void radeon_crtc_init(struct drm_device *dev, int index)
629 {
630 struct radeon_device *rdev = dev->dev_private;
631 struct radeon_crtc *radeon_crtc;
632 int i;
633
634 radeon_crtc = kzalloc(sizeof(struct radeon_crtc) + (RADEONFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
635 if (radeon_crtc == NULL)
636 return;
637
638 drm_crtc_init(dev, &radeon_crtc->base, &radeon_crtc_funcs);
639
640 drm_mode_crtc_set_gamma_size(&radeon_crtc->base, 256);
641 radeon_crtc->crtc_id = index;
642 radeon_crtc->flip_queue = create_singlethread_workqueue("radeon-crtc");
643 rdev->mode_info.crtcs[index] = radeon_crtc;
644
645 if (rdev->family >= CHIP_BONAIRE) {
646 radeon_crtc->max_cursor_width = CIK_CURSOR_WIDTH;
647 radeon_crtc->max_cursor_height = CIK_CURSOR_HEIGHT;
648 } else {
649 radeon_crtc->max_cursor_width = CURSOR_WIDTH;
650 radeon_crtc->max_cursor_height = CURSOR_HEIGHT;
651 }
652 dev->mode_config.cursor_width = radeon_crtc->max_cursor_width;
653 dev->mode_config.cursor_height = radeon_crtc->max_cursor_height;
654
655 #if 0
656 radeon_crtc->mode_set.crtc = &radeon_crtc->base;
657 radeon_crtc->mode_set.connectors = (struct drm_connector **)(radeon_crtc + 1);
658 radeon_crtc->mode_set.num_connectors = 0;
659 #endif
660
661 for (i = 0; i < 256; i++) {
662 radeon_crtc->lut_r[i] = i << 2;
663 radeon_crtc->lut_g[i] = i << 2;
664 radeon_crtc->lut_b[i] = i << 2;
665 }
666
667 if (rdev->is_atom_bios && (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom))
668 radeon_atombios_init_crtc(dev, radeon_crtc);
669 else
670 radeon_legacy_init_crtc(dev, radeon_crtc);
671 }
672
673 static const char *encoder_names[38] = {
674 "NONE",
675 "INTERNAL_LVDS",
676 "INTERNAL_TMDS1",
677 "INTERNAL_TMDS2",
678 "INTERNAL_DAC1",
679 "INTERNAL_DAC2",
680 "INTERNAL_SDVOA",
681 "INTERNAL_SDVOB",
682 "SI170B",
683 "CH7303",
684 "CH7301",
685 "INTERNAL_DVO1",
686 "EXTERNAL_SDVOA",
687 "EXTERNAL_SDVOB",
688 "TITFP513",
689 "INTERNAL_LVTM1",
690 "VT1623",
691 "HDMI_SI1930",
692 "HDMI_INTERNAL",
693 "INTERNAL_KLDSCP_TMDS1",
694 "INTERNAL_KLDSCP_DVO1",
695 "INTERNAL_KLDSCP_DAC1",
696 "INTERNAL_KLDSCP_DAC2",
697 "SI178",
698 "MVPU_FPGA",
699 "INTERNAL_DDI",
700 "VT1625",
701 "HDMI_SI1932",
702 "DP_AN9801",
703 "DP_DP501",
704 "INTERNAL_UNIPHY",
705 "INTERNAL_KLDSCP_LVTMA",
706 "INTERNAL_UNIPHY1",
707 "INTERNAL_UNIPHY2",
708 "NUTMEG",
709 "TRAVIS",
710 "INTERNAL_VCE",
711 "INTERNAL_UNIPHY3",
712 };
713
714 static const char *hpd_names[6] = {
715 "HPD1",
716 "HPD2",
717 "HPD3",
718 "HPD4",
719 "HPD5",
720 "HPD6",
721 };
722
723 static void radeon_print_display_setup(struct drm_device *dev)
724 {
725 struct drm_connector *connector;
726 struct radeon_connector *radeon_connector;
727 struct drm_encoder *encoder;
728 struct radeon_encoder *radeon_encoder;
729 uint32_t devices;
730 int i = 0;
731
732 DRM_INFO("Radeon Display Connectors\n");
733 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
734 radeon_connector = to_radeon_connector(connector);
735 DRM_INFO("Connector %d:\n", i);
736 DRM_INFO(" %s\n", connector->name);
737 if (radeon_connector->hpd.hpd != RADEON_HPD_NONE)
738 DRM_INFO(" %s\n", hpd_names[radeon_connector->hpd.hpd]);
739 if (radeon_connector->ddc_bus) {
740 DRM_INFO(" DDC: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n",
741 radeon_connector->ddc_bus->rec.mask_clk_reg,
742 radeon_connector->ddc_bus->rec.mask_data_reg,
743 radeon_connector->ddc_bus->rec.a_clk_reg,
744 radeon_connector->ddc_bus->rec.a_data_reg,
745 radeon_connector->ddc_bus->rec.en_clk_reg,
746 radeon_connector->ddc_bus->rec.en_data_reg,
747 radeon_connector->ddc_bus->rec.y_clk_reg,
748 radeon_connector->ddc_bus->rec.y_data_reg);
749 if (radeon_connector->router.ddc_valid)
750 DRM_INFO(" DDC Router 0x%x/0x%x\n",
751 radeon_connector->router.ddc_mux_control_pin,
752 radeon_connector->router.ddc_mux_state);
753 if (radeon_connector->router.cd_valid)
754 DRM_INFO(" Clock/Data Router 0x%x/0x%x\n",
755 radeon_connector->router.cd_mux_control_pin,
756 radeon_connector->router.cd_mux_state);
757 } else {
758 if (connector->connector_type == DRM_MODE_CONNECTOR_VGA ||
759 connector->connector_type == DRM_MODE_CONNECTOR_DVII ||
760 connector->connector_type == DRM_MODE_CONNECTOR_DVID ||
761 connector->connector_type == DRM_MODE_CONNECTOR_DVIA ||
762 connector->connector_type == DRM_MODE_CONNECTOR_HDMIA ||
763 connector->connector_type == DRM_MODE_CONNECTOR_HDMIB)
764 DRM_INFO(" DDC: no ddc bus - possible BIOS bug - please report to xorg-driver-ati@lists.x.org\n");
765 }
766 DRM_INFO(" Encoders:\n");
767 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
768 radeon_encoder = to_radeon_encoder(encoder);
769 devices = radeon_encoder->devices & radeon_connector->devices;
770 if (devices) {
771 if (devices & ATOM_DEVICE_CRT1_SUPPORT)
772 DRM_INFO(" CRT1: %s\n", encoder_names[radeon_encoder->encoder_id]);
773 if (devices & ATOM_DEVICE_CRT2_SUPPORT)
774 DRM_INFO(" CRT2: %s\n", encoder_names[radeon_encoder->encoder_id]);
775 if (devices & ATOM_DEVICE_LCD1_SUPPORT)
776 DRM_INFO(" LCD1: %s\n", encoder_names[radeon_encoder->encoder_id]);
777 if (devices & ATOM_DEVICE_DFP1_SUPPORT)
778 DRM_INFO(" DFP1: %s\n", encoder_names[radeon_encoder->encoder_id]);
779 if (devices & ATOM_DEVICE_DFP2_SUPPORT)
780 DRM_INFO(" DFP2: %s\n", encoder_names[radeon_encoder->encoder_id]);
781 if (devices & ATOM_DEVICE_DFP3_SUPPORT)
782 DRM_INFO(" DFP3: %s\n", encoder_names[radeon_encoder->encoder_id]);
783 if (devices & ATOM_DEVICE_DFP4_SUPPORT)
784 DRM_INFO(" DFP4: %s\n", encoder_names[radeon_encoder->encoder_id]);
785 if (devices & ATOM_DEVICE_DFP5_SUPPORT)
786 DRM_INFO(" DFP5: %s\n", encoder_names[radeon_encoder->encoder_id]);
787 if (devices & ATOM_DEVICE_DFP6_SUPPORT)
788 DRM_INFO(" DFP6: %s\n", encoder_names[radeon_encoder->encoder_id]);
789 if (devices & ATOM_DEVICE_TV1_SUPPORT)
790 DRM_INFO(" TV1: %s\n", encoder_names[radeon_encoder->encoder_id]);
791 if (devices & ATOM_DEVICE_CV_SUPPORT)
792 DRM_INFO(" CV: %s\n", encoder_names[radeon_encoder->encoder_id]);
793 }
794 }
795 i++;
796 }
797 }
798
799 static bool radeon_setup_enc_conn(struct drm_device *dev)
800 {
801 struct radeon_device *rdev = dev->dev_private;
802 bool ret = false;
803
804 if (rdev->bios) {
805 if (rdev->is_atom_bios) {
806 ret = radeon_get_atom_connector_info_from_supported_devices_table(dev);
807 if (ret == false)
808 ret = radeon_get_atom_connector_info_from_object_table(dev);
809 } else {
810 ret = radeon_get_legacy_connector_info_from_bios(dev);
811 if (ret == false)
812 ret = radeon_get_legacy_connector_info_from_table(dev);
813 }
814 } else {
815 if (!ASIC_IS_AVIVO(rdev))
816 ret = radeon_get_legacy_connector_info_from_table(dev);
817 }
818 if (ret) {
819 radeon_setup_encoder_clones(dev);
820 radeon_print_display_setup(dev);
821 }
822
823 return ret;
824 }
825
826 int radeon_ddc_get_modes(struct radeon_connector *radeon_connector)
827 {
828 struct drm_device *dev = radeon_connector->base.dev;
829 struct radeon_device *rdev = dev->dev_private;
830 int ret = 0;
831
832 /* don't leak the edid if we already fetched it in detect() */
833 if (radeon_connector->edid)
834 goto got_edid;
835
836 /* on hw with routers, select right port */
837 if (radeon_connector->router.ddc_valid)
838 radeon_router_select_ddc_port(radeon_connector);
839
840 if (radeon_connector_encoder_get_dp_bridge_encoder_id(&radeon_connector->base) !=
841 ENCODER_OBJECT_ID_NONE) {
842 if (radeon_connector->ddc_bus->has_aux)
843 radeon_connector->edid = drm_get_edid(&radeon_connector->base,
844 &radeon_connector->ddc_bus->aux.ddc);
845 } else if ((radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_DisplayPort) ||
846 (radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_eDP)) {
847 struct radeon_connector_atom_dig *dig = radeon_connector->con_priv;
848
849 if ((dig->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT ||
850 dig->dp_sink_type == CONNECTOR_OBJECT_ID_eDP) &&
851 radeon_connector->ddc_bus->has_aux)
852 radeon_connector->edid = drm_get_edid(&radeon_connector->base,
853 &radeon_connector->ddc_bus->aux.ddc);
854 else if (radeon_connector->ddc_bus && !radeon_connector->edid)
855 radeon_connector->edid = drm_get_edid(&radeon_connector->base,
856 &radeon_connector->ddc_bus->adapter);
857 } else {
858 if (radeon_connector->ddc_bus && !radeon_connector->edid)
859 radeon_connector->edid = drm_get_edid(&radeon_connector->base,
860 &radeon_connector->ddc_bus->adapter);
861 }
862
863 if (!radeon_connector->edid) {
864 if (rdev->is_atom_bios) {
865 /* some laptops provide a hardcoded edid in rom for LCDs */
866 if (((radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_LVDS) ||
867 (radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_eDP)))
868 radeon_connector->edid = radeon_bios_get_hardcoded_edid(rdev);
869 } else
870 /* some servers provide a hardcoded edid in rom for KVMs */
871 radeon_connector->edid = radeon_bios_get_hardcoded_edid(rdev);
872 }
873 if (radeon_connector->edid) {
874 got_edid:
875 drm_mode_connector_update_edid_property(&radeon_connector->base, radeon_connector->edid);
876 ret = drm_add_edid_modes(&radeon_connector->base, radeon_connector->edid);
877 drm_edid_to_eld(&radeon_connector->base, radeon_connector->edid);
878 return ret;
879 }
880 drm_mode_connector_update_edid_property(&radeon_connector->base, NULL);
881 return 0;
882 }
883
884 /* avivo */
885
886 /**
887 * avivo_reduce_ratio - fractional number reduction
888 *
889 * @nom: nominator
890 * @den: denominator
891 * @nom_min: minimum value for nominator
892 * @den_min: minimum value for denominator
893 *
894 * Find the greatest common divisor and apply it on both nominator and
895 * denominator, but make nominator and denominator are at least as large
896 * as their minimum values.
897 */
898 static void avivo_reduce_ratio(unsigned *nom, unsigned *den,
899 unsigned nom_min, unsigned den_min)
900 {
901 unsigned tmp;
902
903 /* reduce the numbers to a simpler ratio */
904 tmp = gcd(*nom, *den);
905 *nom /= tmp;
906 *den /= tmp;
907
908 /* make sure nominator is large enough */
909 if (*nom < nom_min) {
910 tmp = DIV_ROUND_UP(nom_min, *nom);
911 *nom *= tmp;
912 *den *= tmp;
913 }
914
915 /* make sure the denominator is large enough */
916 if (*den < den_min) {
917 tmp = DIV_ROUND_UP(den_min, *den);
918 *nom *= tmp;
919 *den *= tmp;
920 }
921 }
922
923 /**
924 * avivo_get_fb_ref_div - feedback and ref divider calculation
925 *
926 * @nom: nominator
927 * @den: denominator
928 * @post_div: post divider
929 * @fb_div_max: feedback divider maximum
930 * @ref_div_max: reference divider maximum
931 * @fb_div: resulting feedback divider
932 * @ref_div: resulting reference divider
933 *
934 * Calculate feedback and reference divider for a given post divider. Makes
935 * sure we stay within the limits.
936 */
937 static void avivo_get_fb_ref_div(unsigned nom, unsigned den, unsigned post_div,
938 unsigned fb_div_max, unsigned ref_div_max,
939 unsigned *fb_div, unsigned *ref_div)
940 {
941 /* limit reference * post divider to a maximum */
942 ref_div_max = max(min(100 / post_div, ref_div_max), 1u);
943
944 /* get matching reference and feedback divider */
945 *ref_div = min(max(DIV_ROUND_CLOSEST(den, post_div), 1u), ref_div_max);
946 *fb_div = DIV_ROUND_CLOSEST(nom * *ref_div * post_div, den);
947
948 /* limit fb divider to its maximum */
949 if (*fb_div > fb_div_max) {
950 *ref_div = DIV_ROUND_CLOSEST(*ref_div * fb_div_max, *fb_div);
951 *fb_div = fb_div_max;
952 }
953 }
954
955 /**
956 * radeon_compute_pll_avivo - compute PLL paramaters
957 *
958 * @pll: information about the PLL
959 * @dot_clock_p: resulting pixel clock
960 * fb_div_p: resulting feedback divider
961 * frac_fb_div_p: fractional part of the feedback divider
962 * ref_div_p: resulting reference divider
963 * post_div_p: resulting reference divider
964 *
965 * Try to calculate the PLL parameters to generate the given frequency:
966 * dot_clock = (ref_freq * feedback_div) / (ref_div * post_div)
967 */
968 void radeon_compute_pll_avivo(struct radeon_pll *pll,
969 u32 freq,
970 u32 *dot_clock_p,
971 u32 *fb_div_p,
972 u32 *frac_fb_div_p,
973 u32 *ref_div_p,
974 u32 *post_div_p)
975 {
976 unsigned target_clock = pll->flags & RADEON_PLL_USE_FRAC_FB_DIV ?
977 freq : freq / 10;
978
979 unsigned fb_div_min, fb_div_max, fb_div;
980 unsigned post_div_min, post_div_max, post_div;
981 unsigned ref_div_min, ref_div_max, ref_div;
982 unsigned post_div_best, diff_best;
983 unsigned nom, den;
984
985 /* determine allowed feedback divider range */
986 fb_div_min = pll->min_feedback_div;
987 fb_div_max = pll->max_feedback_div;
988
989 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
990 fb_div_min *= 10;
991 fb_div_max *= 10;
992 }
993
994 /* determine allowed ref divider range */
995 if (pll->flags & RADEON_PLL_USE_REF_DIV)
996 ref_div_min = pll->reference_div;
997 else
998 ref_div_min = pll->min_ref_div;
999
1000 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV &&
1001 pll->flags & RADEON_PLL_USE_REF_DIV)
1002 ref_div_max = pll->reference_div;
1003 else
1004 ref_div_max = pll->max_ref_div;
1005
1006 /* determine allowed post divider range */
1007 if (pll->flags & RADEON_PLL_USE_POST_DIV) {
1008 post_div_min = pll->post_div;
1009 post_div_max = pll->post_div;
1010 } else {
1011 unsigned vco_min, vco_max;
1012
1013 if (pll->flags & RADEON_PLL_IS_LCD) {
1014 vco_min = pll->lcd_pll_out_min;
1015 vco_max = pll->lcd_pll_out_max;
1016 } else {
1017 vco_min = pll->pll_out_min;
1018 vco_max = pll->pll_out_max;
1019 }
1020
1021 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
1022 vco_min *= 10;
1023 vco_max *= 10;
1024 }
1025
1026 post_div_min = vco_min / target_clock;
1027 if ((target_clock * post_div_min) < vco_min)
1028 ++post_div_min;
1029 if (post_div_min < pll->min_post_div)
1030 post_div_min = pll->min_post_div;
1031
1032 post_div_max = vco_max / target_clock;
1033 if ((target_clock * post_div_max) > vco_max)
1034 --post_div_max;
1035 if (post_div_max > pll->max_post_div)
1036 post_div_max = pll->max_post_div;
1037 }
1038
1039 /* represent the searched ratio as fractional number */
1040 nom = target_clock;
1041 den = pll->reference_freq;
1042
1043 /* reduce the numbers to a simpler ratio */
1044 avivo_reduce_ratio(&nom, &den, fb_div_min, post_div_min);
1045
1046 /* now search for a post divider */
1047 if (pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP)
1048 post_div_best = post_div_min;
1049 else
1050 post_div_best = post_div_max;
1051 diff_best = ~0;
1052
1053 for (post_div = post_div_min; post_div <= post_div_max; ++post_div) {
1054 unsigned diff;
1055 avivo_get_fb_ref_div(nom, den, post_div, fb_div_max,
1056 ref_div_max, &fb_div, &ref_div);
1057 diff = abs(target_clock - (pll->reference_freq * fb_div) /
1058 (ref_div * post_div));
1059
1060 if (diff < diff_best || (diff == diff_best &&
1061 !(pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP))) {
1062
1063 post_div_best = post_div;
1064 diff_best = diff;
1065 }
1066 }
1067 post_div = post_div_best;
1068
1069 /* get the feedback and reference divider for the optimal value */
1070 avivo_get_fb_ref_div(nom, den, post_div, fb_div_max, ref_div_max,
1071 &fb_div, &ref_div);
1072
1073 /* reduce the numbers to a simpler ratio once more */
1074 /* this also makes sure that the reference divider is large enough */
1075 avivo_reduce_ratio(&fb_div, &ref_div, fb_div_min, ref_div_min);
1076
1077 /* avoid high jitter with small fractional dividers */
1078 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV && (fb_div % 10)) {
1079 fb_div_min = max(fb_div_min, (9 - (fb_div % 10)) * 20 + 50);
1080 if (fb_div < fb_div_min) {
1081 unsigned tmp = DIV_ROUND_UP(fb_div_min, fb_div);
1082 fb_div *= tmp;
1083 ref_div *= tmp;
1084 }
1085 }
1086
1087 /* and finally save the result */
1088 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
1089 *fb_div_p = fb_div / 10;
1090 *frac_fb_div_p = fb_div % 10;
1091 } else {
1092 *fb_div_p = fb_div;
1093 *frac_fb_div_p = 0;
1094 }
1095
1096 *dot_clock_p = ((pll->reference_freq * *fb_div_p * 10) +
1097 (pll->reference_freq * *frac_fb_div_p)) /
1098 (ref_div * post_div * 10);
1099 *ref_div_p = ref_div;
1100 *post_div_p = post_div;
1101
1102 DRM_DEBUG_KMS("%d - %d, pll dividers - fb: %d.%d ref: %d, post %d\n",
1103 freq, *dot_clock_p * 10, *fb_div_p, *frac_fb_div_p,
1104 ref_div, post_div);
1105 }
1106
1107 /* pre-avivo */
1108 static inline uint32_t radeon_div(uint64_t n, uint32_t d)
1109 {
1110 uint64_t mod;
1111
1112 n += d / 2;
1113
1114 mod = do_div(n, d);
1115 return n;
1116 }
1117
1118 void radeon_compute_pll_legacy(struct radeon_pll *pll,
1119 uint64_t freq,
1120 uint32_t *dot_clock_p,
1121 uint32_t *fb_div_p,
1122 uint32_t *frac_fb_div_p,
1123 uint32_t *ref_div_p,
1124 uint32_t *post_div_p)
1125 {
1126 uint32_t min_ref_div = pll->min_ref_div;
1127 uint32_t max_ref_div = pll->max_ref_div;
1128 uint32_t min_post_div = pll->min_post_div;
1129 uint32_t max_post_div = pll->max_post_div;
1130 uint32_t min_fractional_feed_div = 0;
1131 uint32_t max_fractional_feed_div = 0;
1132 uint32_t best_vco = pll->best_vco;
1133 uint32_t best_post_div = 1;
1134 uint32_t best_ref_div = 1;
1135 uint32_t best_feedback_div = 1;
1136 uint32_t best_frac_feedback_div = 0;
1137 uint32_t best_freq = -1;
1138 uint32_t best_error = 0xffffffff;
1139 uint32_t best_vco_diff = 1;
1140 uint32_t post_div;
1141 u32 pll_out_min, pll_out_max;
1142
1143 DRM_DEBUG_KMS("PLL freq %llu %u %u\n", freq, pll->min_ref_div, pll->max_ref_div);
1144 freq = freq * 1000;
1145
1146 if (pll->flags & RADEON_PLL_IS_LCD) {
1147 pll_out_min = pll->lcd_pll_out_min;
1148 pll_out_max = pll->lcd_pll_out_max;
1149 } else {
1150 pll_out_min = pll->pll_out_min;
1151 pll_out_max = pll->pll_out_max;
1152 }
1153
1154 if (pll_out_min > 64800)
1155 pll_out_min = 64800;
1156
1157 if (pll->flags & RADEON_PLL_USE_REF_DIV)
1158 min_ref_div = max_ref_div = pll->reference_div;
1159 else {
1160 while (min_ref_div < max_ref_div-1) {
1161 uint32_t mid = (min_ref_div + max_ref_div) / 2;
1162 uint32_t pll_in = pll->reference_freq / mid;
1163 if (pll_in < pll->pll_in_min)
1164 max_ref_div = mid;
1165 else if (pll_in > pll->pll_in_max)
1166 min_ref_div = mid;
1167 else
1168 break;
1169 }
1170 }
1171
1172 if (pll->flags & RADEON_PLL_USE_POST_DIV)
1173 min_post_div = max_post_div = pll->post_div;
1174
1175 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
1176 min_fractional_feed_div = pll->min_frac_feedback_div;
1177 max_fractional_feed_div = pll->max_frac_feedback_div;
1178 }
1179
1180 for (post_div = max_post_div; post_div >= min_post_div; --post_div) {
1181 uint32_t ref_div;
1182
1183 if ((pll->flags & RADEON_PLL_NO_ODD_POST_DIV) && (post_div & 1))
1184 continue;
1185
1186 /* legacy radeons only have a few post_divs */
1187 if (pll->flags & RADEON_PLL_LEGACY) {
1188 if ((post_div == 5) ||
1189 (post_div == 7) ||
1190 (post_div == 9) ||
1191 (post_div == 10) ||
1192 (post_div == 11) ||
1193 (post_div == 13) ||
1194 (post_div == 14) ||
1195 (post_div == 15))
1196 continue;
1197 }
1198
1199 for (ref_div = min_ref_div; ref_div <= max_ref_div; ++ref_div) {
1200 uint32_t feedback_div, current_freq = 0, error, vco_diff;
1201 uint32_t pll_in = pll->reference_freq / ref_div;
1202 uint32_t min_feed_div = pll->min_feedback_div;
1203 uint32_t max_feed_div = pll->max_feedback_div + 1;
1204
1205 if (pll_in < pll->pll_in_min || pll_in > pll->pll_in_max)
1206 continue;
1207
1208 while (min_feed_div < max_feed_div) {
1209 uint32_t vco;
1210 uint32_t min_frac_feed_div = min_fractional_feed_div;
1211 uint32_t max_frac_feed_div = max_fractional_feed_div + 1;
1212 uint32_t frac_feedback_div;
1213 uint64_t tmp;
1214
1215 feedback_div = (min_feed_div + max_feed_div) / 2;
1216
1217 tmp = (uint64_t)pll->reference_freq * feedback_div;
1218 vco = radeon_div(tmp, ref_div);
1219
1220 if (vco < pll_out_min) {
1221 min_feed_div = feedback_div + 1;
1222 continue;
1223 } else if (vco > pll_out_max) {
1224 max_feed_div = feedback_div;
1225 continue;
1226 }
1227
1228 while (min_frac_feed_div < max_frac_feed_div) {
1229 frac_feedback_div = (min_frac_feed_div + max_frac_feed_div) / 2;
1230 tmp = (uint64_t)pll->reference_freq * 10000 * feedback_div;
1231 tmp += (uint64_t)pll->reference_freq * 1000 * frac_feedback_div;
1232 current_freq = radeon_div(tmp, ref_div * post_div);
1233
1234 if (pll->flags & RADEON_PLL_PREFER_CLOSEST_LOWER) {
1235 if (freq < current_freq)
1236 error = 0xffffffff;
1237 else
1238 error = freq - current_freq;
1239 } else
1240 error = abs(current_freq - freq);
1241 vco_diff = abs(vco - best_vco);
1242
1243 if ((best_vco == 0 && error < best_error) ||
1244 (best_vco != 0 &&
1245 ((best_error > 100 && error < best_error - 100) ||
1246 (abs(error - best_error) < 100 && vco_diff < best_vco_diff)))) {
1247 best_post_div = post_div;
1248 best_ref_div = ref_div;
1249 best_feedback_div = feedback_div;
1250 best_frac_feedback_div = frac_feedback_div;
1251 best_freq = current_freq;
1252 best_error = error;
1253 best_vco_diff = vco_diff;
1254 } else if (current_freq == freq) {
1255 if (best_freq == -1) {
1256 best_post_div = post_div;
1257 best_ref_div = ref_div;
1258 best_feedback_div = feedback_div;
1259 best_frac_feedback_div = frac_feedback_div;
1260 best_freq = current_freq;
1261 best_error = error;
1262 best_vco_diff = vco_diff;
1263 } else if (((pll->flags & RADEON_PLL_PREFER_LOW_REF_DIV) && (ref_div < best_ref_div)) ||
1264 ((pll->flags & RADEON_PLL_PREFER_HIGH_REF_DIV) && (ref_div > best_ref_div)) ||
1265 ((pll->flags & RADEON_PLL_PREFER_LOW_FB_DIV) && (feedback_div < best_feedback_div)) ||
1266 ((pll->flags & RADEON_PLL_PREFER_HIGH_FB_DIV) && (feedback_div > best_feedback_div)) ||
1267 ((pll->flags & RADEON_PLL_PREFER_LOW_POST_DIV) && (post_div < best_post_div)) ||
1268 ((pll->flags & RADEON_PLL_PREFER_HIGH_POST_DIV) && (post_div > best_post_div))) {
1269 best_post_div = post_div;
1270 best_ref_div = ref_div;
1271 best_feedback_div = feedback_div;
1272 best_frac_feedback_div = frac_feedback_div;
1273 best_freq = current_freq;
1274 best_error = error;
1275 best_vco_diff = vco_diff;
1276 }
1277 }
1278 if (current_freq < freq)
1279 min_frac_feed_div = frac_feedback_div + 1;
1280 else
1281 max_frac_feed_div = frac_feedback_div;
1282 }
1283 if (current_freq < freq)
1284 min_feed_div = feedback_div + 1;
1285 else
1286 max_feed_div = feedback_div;
1287 }
1288 }
1289 }
1290
1291 *dot_clock_p = best_freq / 10000;
1292 *fb_div_p = best_feedback_div;
1293 *frac_fb_div_p = best_frac_feedback_div;
1294 *ref_div_p = best_ref_div;
1295 *post_div_p = best_post_div;
1296 DRM_DEBUG_KMS("%lld %d, pll dividers - fb: %d.%d ref: %d, post %d\n",
1297 (long long)freq,
1298 best_freq / 1000, best_feedback_div, best_frac_feedback_div,
1299 best_ref_div, best_post_div);
1300
1301 }
1302
1303 static void radeon_user_framebuffer_destroy(struct drm_framebuffer *fb)
1304 {
1305 struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb);
1306
1307 if (radeon_fb->obj) {
1308 drm_gem_object_unreference_unlocked(radeon_fb->obj);
1309 }
1310 drm_framebuffer_cleanup(fb);
1311 kfree(radeon_fb);
1312 }
1313
1314 static int radeon_user_framebuffer_create_handle(struct drm_framebuffer *fb,
1315 struct drm_file *file_priv,
1316 unsigned int *handle)
1317 {
1318 struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb);
1319
1320 return drm_gem_handle_create(file_priv, radeon_fb->obj, handle);
1321 }
1322
1323 static const struct drm_framebuffer_funcs radeon_fb_funcs = {
1324 .destroy = radeon_user_framebuffer_destroy,
1325 .create_handle = radeon_user_framebuffer_create_handle,
1326 };
1327
1328 int
1329 radeon_framebuffer_init(struct drm_device *dev,
1330 struct radeon_framebuffer *rfb,
1331 struct drm_mode_fb_cmd2 *mode_cmd,
1332 struct drm_gem_object *obj)
1333 {
1334 int ret;
1335 rfb->obj = obj;
1336 drm_helper_mode_fill_fb_struct(&rfb->base, mode_cmd);
1337 ret = drm_framebuffer_init(dev, &rfb->base, &radeon_fb_funcs);
1338 if (ret) {
1339 rfb->obj = NULL;
1340 return ret;
1341 }
1342 return 0;
1343 }
1344
1345 static struct drm_framebuffer *
1346 radeon_user_framebuffer_create(struct drm_device *dev,
1347 struct drm_file *file_priv,
1348 struct drm_mode_fb_cmd2 *mode_cmd)
1349 {
1350 struct drm_gem_object *obj;
1351 struct radeon_framebuffer *radeon_fb;
1352 int ret;
1353
1354 obj = drm_gem_object_lookup(dev, file_priv, mode_cmd->handles[0]);
1355 if (obj == NULL) {
1356 dev_err(&dev->pdev->dev, "No GEM object associated to handle 0x%08X, "
1357 "can't create framebuffer\n", mode_cmd->handles[0]);
1358 return ERR_PTR(-ENOENT);
1359 }
1360
1361 radeon_fb = kzalloc(sizeof(*radeon_fb), GFP_KERNEL);
1362 if (radeon_fb == NULL) {
1363 drm_gem_object_unreference_unlocked(obj);
1364 return ERR_PTR(-ENOMEM);
1365 }
1366
1367 ret = radeon_framebuffer_init(dev, radeon_fb, mode_cmd, obj);
1368 if (ret) {
1369 kfree(radeon_fb);
1370 drm_gem_object_unreference_unlocked(obj);
1371 return ERR_PTR(ret);
1372 }
1373
1374 return &radeon_fb->base;
1375 }
1376
1377 static void radeon_output_poll_changed(struct drm_device *dev)
1378 {
1379 struct radeon_device *rdev = dev->dev_private;
1380 radeon_fb_output_poll_changed(rdev);
1381 }
1382
1383 static const struct drm_mode_config_funcs radeon_mode_funcs = {
1384 .fb_create = radeon_user_framebuffer_create,
1385 .output_poll_changed = radeon_output_poll_changed
1386 };
1387
1388 static struct drm_prop_enum_list radeon_tmds_pll_enum_list[] =
1389 { { 0, "driver" },
1390 { 1, "bios" },
1391 };
1392
1393 static struct drm_prop_enum_list radeon_tv_std_enum_list[] =
1394 { { TV_STD_NTSC, "ntsc" },
1395 { TV_STD_PAL, "pal" },
1396 { TV_STD_PAL_M, "pal-m" },
1397 { TV_STD_PAL_60, "pal-60" },
1398 { TV_STD_NTSC_J, "ntsc-j" },
1399 { TV_STD_SCART_PAL, "scart-pal" },
1400 { TV_STD_PAL_CN, "pal-cn" },
1401 { TV_STD_SECAM, "secam" },
1402 };
1403
1404 static struct drm_prop_enum_list radeon_underscan_enum_list[] =
1405 { { UNDERSCAN_OFF, "off" },
1406 { UNDERSCAN_ON, "on" },
1407 { UNDERSCAN_AUTO, "auto" },
1408 };
1409
1410 static struct drm_prop_enum_list radeon_audio_enum_list[] =
1411 { { RADEON_AUDIO_DISABLE, "off" },
1412 { RADEON_AUDIO_ENABLE, "on" },
1413 { RADEON_AUDIO_AUTO, "auto" },
1414 };
1415
1416 /* XXX support different dither options? spatial, temporal, both, etc. */
1417 static struct drm_prop_enum_list radeon_dither_enum_list[] =
1418 { { RADEON_FMT_DITHER_DISABLE, "off" },
1419 { RADEON_FMT_DITHER_ENABLE, "on" },
1420 };
1421
1422 static int radeon_modeset_create_props(struct radeon_device *rdev)
1423 {
1424 int sz;
1425
1426 if (rdev->is_atom_bios) {
1427 rdev->mode_info.coherent_mode_property =
1428 drm_property_create_range(rdev->ddev, 0 , "coherent", 0, 1);
1429 if (!rdev->mode_info.coherent_mode_property)
1430 return -ENOMEM;
1431 }
1432
1433 if (!ASIC_IS_AVIVO(rdev)) {
1434 sz = ARRAY_SIZE(radeon_tmds_pll_enum_list);
1435 rdev->mode_info.tmds_pll_property =
1436 drm_property_create_enum(rdev->ddev, 0,
1437 "tmds_pll",
1438 radeon_tmds_pll_enum_list, sz);
1439 }
1440
1441 rdev->mode_info.load_detect_property =
1442 drm_property_create_range(rdev->ddev, 0, "load detection", 0, 1);
1443 if (!rdev->mode_info.load_detect_property)
1444 return -ENOMEM;
1445
1446 drm_mode_create_scaling_mode_property(rdev->ddev);
1447
1448 sz = ARRAY_SIZE(radeon_tv_std_enum_list);
1449 rdev->mode_info.tv_std_property =
1450 drm_property_create_enum(rdev->ddev, 0,
1451 "tv standard",
1452 radeon_tv_std_enum_list, sz);
1453
1454 sz = ARRAY_SIZE(radeon_underscan_enum_list);
1455 rdev->mode_info.underscan_property =
1456 drm_property_create_enum(rdev->ddev, 0,
1457 "underscan",
1458 radeon_underscan_enum_list, sz);
1459
1460 rdev->mode_info.underscan_hborder_property =
1461 drm_property_create_range(rdev->ddev, 0,
1462 "underscan hborder", 0, 128);
1463 if (!rdev->mode_info.underscan_hborder_property)
1464 return -ENOMEM;
1465
1466 rdev->mode_info.underscan_vborder_property =
1467 drm_property_create_range(rdev->ddev, 0,
1468 "underscan vborder", 0, 128);
1469 if (!rdev->mode_info.underscan_vborder_property)
1470 return -ENOMEM;
1471
1472 sz = ARRAY_SIZE(radeon_audio_enum_list);
1473 rdev->mode_info.audio_property =
1474 drm_property_create_enum(rdev->ddev, 0,
1475 "audio",
1476 radeon_audio_enum_list, sz);
1477
1478 sz = ARRAY_SIZE(radeon_dither_enum_list);
1479 rdev->mode_info.dither_property =
1480 drm_property_create_enum(rdev->ddev, 0,
1481 "dither",
1482 radeon_dither_enum_list, sz);
1483
1484 return 0;
1485 }
1486
1487 void radeon_update_display_priority(struct radeon_device *rdev)
1488 {
1489 /* adjustment options for the display watermarks */
1490 if ((radeon_disp_priority == 0) || (radeon_disp_priority > 2)) {
1491 /* set display priority to high for r3xx, rv515 chips
1492 * this avoids flickering due to underflow to the
1493 * display controllers during heavy acceleration.
1494 * Don't force high on rs4xx igp chips as it seems to
1495 * affect the sound card. See kernel bug 15982.
1496 */
1497 if ((ASIC_IS_R300(rdev) || (rdev->family == CHIP_RV515)) &&
1498 !(rdev->flags & RADEON_IS_IGP))
1499 rdev->disp_priority = 2;
1500 else
1501 rdev->disp_priority = 0;
1502 } else
1503 rdev->disp_priority = radeon_disp_priority;
1504
1505 }
1506
1507 /*
1508 * Allocate hdmi structs and determine register offsets
1509 */
1510 static void radeon_afmt_init(struct radeon_device *rdev)
1511 {
1512 int i;
1513
1514 for (i = 0; i < RADEON_MAX_AFMT_BLOCKS; i++)
1515 rdev->mode_info.afmt[i] = NULL;
1516
1517 if (ASIC_IS_NODCE(rdev)) {
1518 /* nothing to do */
1519 } else if (ASIC_IS_DCE4(rdev)) {
1520 static uint32_t eg_offsets[] = {
1521 EVERGREEN_CRTC0_REGISTER_OFFSET,
1522 EVERGREEN_CRTC1_REGISTER_OFFSET,
1523 EVERGREEN_CRTC2_REGISTER_OFFSET,
1524 EVERGREEN_CRTC3_REGISTER_OFFSET,
1525 EVERGREEN_CRTC4_REGISTER_OFFSET,
1526 EVERGREEN_CRTC5_REGISTER_OFFSET,
1527 0x13830 - 0x7030,
1528 };
1529 int num_afmt;
1530
1531 /* DCE8 has 7 audio blocks tied to DIG encoders */
1532 /* DCE6 has 6 audio blocks tied to DIG encoders */
1533 /* DCE4/5 has 6 audio blocks tied to DIG encoders */
1534 /* DCE4.1 has 2 audio blocks tied to DIG encoders */
1535 if (ASIC_IS_DCE8(rdev))
1536 num_afmt = 7;
1537 else if (ASIC_IS_DCE6(rdev))
1538 num_afmt = 6;
1539 else if (ASIC_IS_DCE5(rdev))
1540 num_afmt = 6;
1541 else if (ASIC_IS_DCE41(rdev))
1542 num_afmt = 2;
1543 else /* DCE4 */
1544 num_afmt = 6;
1545
1546 BUG_ON(num_afmt > ARRAY_SIZE(eg_offsets));
1547 for (i = 0; i < num_afmt; i++) {
1548 rdev->mode_info.afmt[i] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1549 if (rdev->mode_info.afmt[i]) {
1550 rdev->mode_info.afmt[i]->offset = eg_offsets[i];
1551 rdev->mode_info.afmt[i]->id = i;
1552 }
1553 }
1554 } else if (ASIC_IS_DCE3(rdev)) {
1555 /* DCE3.x has 2 audio blocks tied to DIG encoders */
1556 rdev->mode_info.afmt[0] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1557 if (rdev->mode_info.afmt[0]) {
1558 rdev->mode_info.afmt[0]->offset = DCE3_HDMI_OFFSET0;
1559 rdev->mode_info.afmt[0]->id = 0;
1560 }
1561 rdev->mode_info.afmt[1] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1562 if (rdev->mode_info.afmt[1]) {
1563 rdev->mode_info.afmt[1]->offset = DCE3_HDMI_OFFSET1;
1564 rdev->mode_info.afmt[1]->id = 1;
1565 }
1566 } else if (ASIC_IS_DCE2(rdev)) {
1567 /* DCE2 has at least 1 routable audio block */
1568 rdev->mode_info.afmt[0] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1569 if (rdev->mode_info.afmt[0]) {
1570 rdev->mode_info.afmt[0]->offset = DCE2_HDMI_OFFSET0;
1571 rdev->mode_info.afmt[0]->id = 0;
1572 }
1573 /* r6xx has 2 routable audio blocks */
1574 if (rdev->family >= CHIP_R600) {
1575 rdev->mode_info.afmt[1] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1576 if (rdev->mode_info.afmt[1]) {
1577 rdev->mode_info.afmt[1]->offset = DCE2_HDMI_OFFSET1;
1578 rdev->mode_info.afmt[1]->id = 1;
1579 }
1580 }
1581 }
1582 }
1583
1584 static void radeon_afmt_fini(struct radeon_device *rdev)
1585 {
1586 int i;
1587
1588 for (i = 0; i < RADEON_MAX_AFMT_BLOCKS; i++) {
1589 kfree(rdev->mode_info.afmt[i]);
1590 rdev->mode_info.afmt[i] = NULL;
1591 }
1592 }
1593
1594 int radeon_modeset_init(struct radeon_device *rdev)
1595 {
1596 int i;
1597 int ret;
1598
1599 drm_mode_config_init(rdev->ddev);
1600 rdev->mode_info.mode_config_initialized = true;
1601
1602 rdev->ddev->mode_config.funcs = &radeon_mode_funcs;
1603
1604 if (ASIC_IS_DCE5(rdev)) {
1605 rdev->ddev->mode_config.max_width = 16384;
1606 rdev->ddev->mode_config.max_height = 16384;
1607 } else if (ASIC_IS_AVIVO(rdev)) {
1608 rdev->ddev->mode_config.max_width = 8192;
1609 rdev->ddev->mode_config.max_height = 8192;
1610 } else {
1611 rdev->ddev->mode_config.max_width = 4096;
1612 rdev->ddev->mode_config.max_height = 4096;
1613 }
1614
1615 rdev->ddev->mode_config.preferred_depth = 24;
1616 rdev->ddev->mode_config.prefer_shadow = 1;
1617
1618 rdev->ddev->mode_config.fb_base = rdev->mc.aper_base;
1619
1620 ret = radeon_modeset_create_props(rdev);
1621 if (ret) {
1622 return ret;
1623 }
1624
1625 /* init i2c buses */
1626 radeon_i2c_init(rdev);
1627
1628 /* check combios for a valid hardcoded EDID - Sun servers */
1629 if (!rdev->is_atom_bios) {
1630 /* check for hardcoded EDID in BIOS */
1631 radeon_combios_check_hardcoded_edid(rdev);
1632 }
1633
1634 /* allocate crtcs */
1635 for (i = 0; i < rdev->num_crtc; i++) {
1636 radeon_crtc_init(rdev->ddev, i);
1637 }
1638
1639 /* okay we should have all the bios connectors */
1640 ret = radeon_setup_enc_conn(rdev->ddev);
1641 if (!ret) {
1642 return ret;
1643 }
1644
1645 /* init dig PHYs, disp eng pll */
1646 if (rdev->is_atom_bios) {
1647 radeon_atom_encoder_init(rdev);
1648 radeon_atom_disp_eng_pll_init(rdev);
1649 }
1650
1651 /* initialize hpd */
1652 radeon_hpd_init(rdev);
1653
1654 /* setup afmt */
1655 radeon_afmt_init(rdev);
1656
1657 radeon_fbdev_init(rdev);
1658 drm_kms_helper_poll_init(rdev->ddev);
1659
1660 if (rdev->pm.dpm_enabled) {
1661 /* do dpm late init */
1662 ret = radeon_pm_late_init(rdev);
1663 if (ret) {
1664 rdev->pm.dpm_enabled = false;
1665 DRM_ERROR("radeon_pm_late_init failed, disabling dpm\n");
1666 }
1667 /* set the dpm state for PX since there won't be
1668 * a modeset to call this.
1669 */
1670 radeon_pm_compute_clocks(rdev);
1671 }
1672
1673 return 0;
1674 }
1675
1676 void radeon_modeset_fini(struct radeon_device *rdev)
1677 {
1678 radeon_fbdev_fini(rdev);
1679 kfree(rdev->mode_info.bios_hardcoded_edid);
1680
1681 if (rdev->mode_info.mode_config_initialized) {
1682 radeon_afmt_fini(rdev);
1683 drm_kms_helper_poll_fini(rdev->ddev);
1684 radeon_hpd_fini(rdev);
1685 drm_mode_config_cleanup(rdev->ddev);
1686 rdev->mode_info.mode_config_initialized = false;
1687 }
1688 /* free i2c buses */
1689 radeon_i2c_fini(rdev);
1690 }
1691
1692 static bool is_hdtv_mode(const struct drm_display_mode *mode)
1693 {
1694 /* try and guess if this is a tv or a monitor */
1695 if ((mode->vdisplay == 480 && mode->hdisplay == 720) || /* 480p */
1696 (mode->vdisplay == 576) || /* 576p */
1697 (mode->vdisplay == 720) || /* 720p */
1698 (mode->vdisplay == 1080)) /* 1080p */
1699 return true;
1700 else
1701 return false;
1702 }
1703
1704 bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc,
1705 const struct drm_display_mode *mode,
1706 struct drm_display_mode *adjusted_mode)
1707 {
1708 struct drm_device *dev = crtc->dev;
1709 struct radeon_device *rdev = dev->dev_private;
1710 struct drm_encoder *encoder;
1711 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1712 struct radeon_encoder *radeon_encoder;
1713 struct drm_connector *connector;
1714 struct radeon_connector *radeon_connector;
1715 bool first = true;
1716 u32 src_v = 1, dst_v = 1;
1717 u32 src_h = 1, dst_h = 1;
1718
1719 radeon_crtc->h_border = 0;
1720 radeon_crtc->v_border = 0;
1721
1722 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1723 if (encoder->crtc != crtc)
1724 continue;
1725 radeon_encoder = to_radeon_encoder(encoder);
1726 connector = radeon_get_connector_for_encoder(encoder);
1727 radeon_connector = to_radeon_connector(connector);
1728
1729 if (first) {
1730 /* set scaling */
1731 if (radeon_encoder->rmx_type == RMX_OFF)
1732 radeon_crtc->rmx_type = RMX_OFF;
1733 else if (mode->hdisplay < radeon_encoder->native_mode.hdisplay ||
1734 mode->vdisplay < radeon_encoder->native_mode.vdisplay)
1735 radeon_crtc->rmx_type = radeon_encoder->rmx_type;
1736 else
1737 radeon_crtc->rmx_type = RMX_OFF;
1738 /* copy native mode */
1739 memcpy(&radeon_crtc->native_mode,
1740 &radeon_encoder->native_mode,
1741 sizeof(struct drm_display_mode));
1742 src_v = crtc->mode.vdisplay;
1743 dst_v = radeon_crtc->native_mode.vdisplay;
1744 src_h = crtc->mode.hdisplay;
1745 dst_h = radeon_crtc->native_mode.hdisplay;
1746
1747 /* fix up for overscan on hdmi */
1748 if (ASIC_IS_AVIVO(rdev) &&
1749 (!(mode->flags & DRM_MODE_FLAG_INTERLACE)) &&
1750 ((radeon_encoder->underscan_type == UNDERSCAN_ON) ||
1751 ((radeon_encoder->underscan_type == UNDERSCAN_AUTO) &&
1752 drm_detect_hdmi_monitor(radeon_connector->edid) &&
1753 is_hdtv_mode(mode)))) {
1754 if (radeon_encoder->underscan_hborder != 0)
1755 radeon_crtc->h_border = radeon_encoder->underscan_hborder;
1756 else
1757 radeon_crtc->h_border = (mode->hdisplay >> 5) + 16;
1758 if (radeon_encoder->underscan_vborder != 0)
1759 radeon_crtc->v_border = radeon_encoder->underscan_vborder;
1760 else
1761 radeon_crtc->v_border = (mode->vdisplay >> 5) + 16;
1762 radeon_crtc->rmx_type = RMX_FULL;
1763 src_v = crtc->mode.vdisplay;
1764 dst_v = crtc->mode.vdisplay - (radeon_crtc->v_border * 2);
1765 src_h = crtc->mode.hdisplay;
1766 dst_h = crtc->mode.hdisplay - (radeon_crtc->h_border * 2);
1767 }
1768 first = false;
1769 } else {
1770 if (radeon_crtc->rmx_type != radeon_encoder->rmx_type) {
1771 /* WARNING: Right now this can't happen but
1772 * in the future we need to check that scaling
1773 * are consistent across different encoder
1774 * (ie all encoder can work with the same
1775 * scaling).
1776 */
1777 DRM_ERROR("Scaling not consistent across encoder.\n");
1778 return false;
1779 }
1780 }
1781 }
1782 if (radeon_crtc->rmx_type != RMX_OFF) {
1783 fixed20_12 a, b;
1784 a.full = dfixed_const(src_v);
1785 b.full = dfixed_const(dst_v);
1786 radeon_crtc->vsc.full = dfixed_div(a, b);
1787 a.full = dfixed_const(src_h);
1788 b.full = dfixed_const(dst_h);
1789 radeon_crtc->hsc.full = dfixed_div(a, b);
1790 } else {
1791 radeon_crtc->vsc.full = dfixed_const(1);
1792 radeon_crtc->hsc.full = dfixed_const(1);
1793 }
1794 return true;
1795 }
1796
1797 /*
1798 * Retrieve current video scanout position of crtc on a given gpu, and
1799 * an optional accurate timestamp of when query happened.
1800 *
1801 * \param dev Device to query.
1802 * \param crtc Crtc to query.
1803 * \param flags Flags from caller (DRM_CALLED_FROM_VBLIRQ or 0).
1804 * \param *vpos Location where vertical scanout position should be stored.
1805 * \param *hpos Location where horizontal scanout position should go.
1806 * \param *stime Target location for timestamp taken immediately before
1807 * scanout position query. Can be NULL to skip timestamp.
1808 * \param *etime Target location for timestamp taken immediately after
1809 * scanout position query. Can be NULL to skip timestamp.
1810 *
1811 * Returns vpos as a positive number while in active scanout area.
1812 * Returns vpos as a negative number inside vblank, counting the number
1813 * of scanlines to go until end of vblank, e.g., -1 means "one scanline
1814 * until start of active scanout / end of vblank."
1815 *
1816 * \return Flags, or'ed together as follows:
1817 *
1818 * DRM_SCANOUTPOS_VALID = Query successful.
1819 * DRM_SCANOUTPOS_INVBL = Inside vblank.
1820 * DRM_SCANOUTPOS_ACCURATE = Returned position is accurate. A lack of
1821 * this flag means that returned position may be offset by a constant but
1822 * unknown small number of scanlines wrt. real scanout position.
1823 *
1824 */
1825 int radeon_get_crtc_scanoutpos(struct drm_device *dev, int crtc, unsigned int flags,
1826 int *vpos, int *hpos, ktime_t *stime, ktime_t *etime)
1827 {
1828 u32 stat_crtc = 0, vbl = 0, position = 0;
1829 int vbl_start, vbl_end, vtotal, ret = 0;
1830 bool in_vbl = true;
1831
1832 struct radeon_device *rdev = dev->dev_private;
1833
1834 /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */
1835
1836 /* Get optional system timestamp before query. */
1837 if (stime)
1838 *stime = ktime_get();
1839
1840 if (ASIC_IS_DCE4(rdev)) {
1841 if (crtc == 0) {
1842 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1843 EVERGREEN_CRTC0_REGISTER_OFFSET);
1844 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1845 EVERGREEN_CRTC0_REGISTER_OFFSET);
1846 ret |= DRM_SCANOUTPOS_VALID;
1847 }
1848 if (crtc == 1) {
1849 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1850 EVERGREEN_CRTC1_REGISTER_OFFSET);
1851 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1852 EVERGREEN_CRTC1_REGISTER_OFFSET);
1853 ret |= DRM_SCANOUTPOS_VALID;
1854 }
1855 if (crtc == 2) {
1856 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1857 EVERGREEN_CRTC2_REGISTER_OFFSET);
1858 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1859 EVERGREEN_CRTC2_REGISTER_OFFSET);
1860 ret |= DRM_SCANOUTPOS_VALID;
1861 }
1862 if (crtc == 3) {
1863 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1864 EVERGREEN_CRTC3_REGISTER_OFFSET);
1865 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1866 EVERGREEN_CRTC3_REGISTER_OFFSET);
1867 ret |= DRM_SCANOUTPOS_VALID;
1868 }
1869 if (crtc == 4) {
1870 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1871 EVERGREEN_CRTC4_REGISTER_OFFSET);
1872 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1873 EVERGREEN_CRTC4_REGISTER_OFFSET);
1874 ret |= DRM_SCANOUTPOS_VALID;
1875 }
1876 if (crtc == 5) {
1877 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1878 EVERGREEN_CRTC5_REGISTER_OFFSET);
1879 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1880 EVERGREEN_CRTC5_REGISTER_OFFSET);
1881 ret |= DRM_SCANOUTPOS_VALID;
1882 }
1883 } else if (ASIC_IS_AVIVO(rdev)) {
1884 if (crtc == 0) {
1885 vbl = RREG32(AVIVO_D1CRTC_V_BLANK_START_END);
1886 position = RREG32(AVIVO_D1CRTC_STATUS_POSITION);
1887 ret |= DRM_SCANOUTPOS_VALID;
1888 }
1889 if (crtc == 1) {
1890 vbl = RREG32(AVIVO_D2CRTC_V_BLANK_START_END);
1891 position = RREG32(AVIVO_D2CRTC_STATUS_POSITION);
1892 ret |= DRM_SCANOUTPOS_VALID;
1893 }
1894 } else {
1895 /* Pre-AVIVO: Different encoding of scanout pos and vblank interval. */
1896 if (crtc == 0) {
1897 /* Assume vbl_end == 0, get vbl_start from
1898 * upper 16 bits.
1899 */
1900 vbl = (RREG32(RADEON_CRTC_V_TOTAL_DISP) &
1901 RADEON_CRTC_V_DISP) >> RADEON_CRTC_V_DISP_SHIFT;
1902 /* Only retrieve vpos from upper 16 bits, set hpos == 0. */
1903 position = (RREG32(RADEON_CRTC_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
1904 stat_crtc = RREG32(RADEON_CRTC_STATUS);
1905 if (!(stat_crtc & 1))
1906 in_vbl = false;
1907
1908 ret |= DRM_SCANOUTPOS_VALID;
1909 }
1910 if (crtc == 1) {
1911 vbl = (RREG32(RADEON_CRTC2_V_TOTAL_DISP) &
1912 RADEON_CRTC_V_DISP) >> RADEON_CRTC_V_DISP_SHIFT;
1913 position = (RREG32(RADEON_CRTC2_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
1914 stat_crtc = RREG32(RADEON_CRTC2_STATUS);
1915 if (!(stat_crtc & 1))
1916 in_vbl = false;
1917
1918 ret |= DRM_SCANOUTPOS_VALID;
1919 }
1920 }
1921
1922 /* Get optional system timestamp after query. */
1923 if (etime)
1924 *etime = ktime_get();
1925
1926 /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */
1927
1928 /* Decode into vertical and horizontal scanout position. */
1929 *vpos = position & 0x1fff;
1930 *hpos = (position >> 16) & 0x1fff;
1931
1932 /* Valid vblank area boundaries from gpu retrieved? */
1933 if (vbl > 0) {
1934 /* Yes: Decode. */
1935 ret |= DRM_SCANOUTPOS_ACCURATE;
1936 vbl_start = vbl & 0x1fff;
1937 vbl_end = (vbl >> 16) & 0x1fff;
1938 }
1939 else {
1940 /* No: Fake something reasonable which gives at least ok results. */
1941 vbl_start = rdev->mode_info.crtcs[crtc]->base.hwmode.crtc_vdisplay;
1942 vbl_end = 0;
1943 }
1944
1945 /* Test scanout position against vblank region. */
1946 if ((*vpos < vbl_start) && (*vpos >= vbl_end))
1947 in_vbl = false;
1948
1949 /* Check if inside vblank area and apply corrective offsets:
1950 * vpos will then be >=0 in video scanout area, but negative
1951 * within vblank area, counting down the number of lines until
1952 * start of scanout.
1953 */
1954
1955 /* Inside "upper part" of vblank area? Apply corrective offset if so: */
1956 if (in_vbl && (*vpos >= vbl_start)) {
1957 vtotal = rdev->mode_info.crtcs[crtc]->base.hwmode.crtc_vtotal;
1958 *vpos = *vpos - vtotal;
1959 }
1960
1961 /* Correct for shifted end of vbl at vbl_end. */
1962 *vpos = *vpos - vbl_end;
1963
1964 /* In vblank? */
1965 if (in_vbl)
1966 ret |= DRM_SCANOUTPOS_INVBL;
1967
1968 /* Is vpos outside nominal vblank area, but less than
1969 * 1/100 of a frame height away from start of vblank?
1970 * If so, assume this isn't a massively delayed vblank
1971 * interrupt, but a vblank interrupt that fired a few
1972 * microseconds before true start of vblank. Compensate
1973 * by adding a full frame duration to the final timestamp.
1974 * Happens, e.g., on ATI R500, R600.
1975 *
1976 * We only do this if DRM_CALLED_FROM_VBLIRQ.
1977 */
1978 if ((flags & DRM_CALLED_FROM_VBLIRQ) && !in_vbl) {
1979 vbl_start = rdev->mode_info.crtcs[crtc]->base.hwmode.crtc_vdisplay;
1980 vtotal = rdev->mode_info.crtcs[crtc]->base.hwmode.crtc_vtotal;
1981
1982 if (vbl_start - *vpos < vtotal / 100) {
1983 *vpos -= vtotal;
1984
1985 /* Signal this correction as "applied". */
1986 ret |= 0x8;
1987 }
1988 }
1989
1990 return ret;
1991 }
Linux with added FPC-III support