drivers/gpu/drm/tilcdc/tilcdc_crtc.c

   1 /*
   2  * Copyright (C) 2012 Texas Instruments
   3  * Author: Rob Clark <robdclark@gmail.com>
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License version 2 as published by
   7  * the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program.  If not, see <http://www.gnu.org/licenses/>.
  16  */
  17
  18 #include "drm_flip_work.h"
  19
  20 #include "tilcdc_drv.h"
  21 #include "tilcdc_regs.h"
  22
  23 struct tilcdc_crtc {
  24         struct drm_crtc base;
  25
  26         const struct tilcdc_panel_info *info;
  27         uint32_t dirty;
  28         dma_addr_t start, end;
  29         struct drm_pending_vblank_event *event;
  30         int dpms;
  31         wait_queue_head_t frame_done_wq;
  32         bool frame_done;
  33
  34         /* fb currently set to scanout 0/1: */
  35         struct drm_framebuffer *scanout[2];
  36
  37         /* for deferred fb unref's: */
  38         struct drm_flip_work unref_work;
  39 };
  40 #define to_tilcdc_crtc(x) container_of(x, struct tilcdc_crtc, base)
  41
  42 static void unref_worker(struct drm_flip_work *work, void *val)
  43 {
  44         struct tilcdc_crtc *tilcdc_crtc =
  45                 container_of(work, struct tilcdc_crtc, unref_work);
  46         struct drm_device *dev = tilcdc_crtc->base.dev;
  47
  48         mutex_lock(&dev->mode_config.mutex);
  49         drm_framebuffer_unreference(val);
  50         mutex_unlock(&dev->mode_config.mutex);
  51 }
  52
  53 static void set_scanout(struct drm_crtc *crtc, int n)
  54 {
  55         static const uint32_t base_reg[] = {
  56                         LCDC_DMA_FB_BASE_ADDR_0_REG,
  57                         LCDC_DMA_FB_BASE_ADDR_1_REG,
  58         };
  59         static const uint32_t ceil_reg[] = {
  60                         LCDC_DMA_FB_CEILING_ADDR_0_REG,
  61                         LCDC_DMA_FB_CEILING_ADDR_1_REG,
  62         };
  63         static const uint32_t stat[] = {
  64                         LCDC_END_OF_FRAME0, LCDC_END_OF_FRAME1,
  65         };
  66         struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
  67         struct drm_device *dev = crtc->dev;
  68         struct tilcdc_drm_private *priv = dev->dev_private;
  69
  70         pm_runtime_get_sync(dev->dev);
  71         tilcdc_write(dev, base_reg[n], tilcdc_crtc->start);
  72         tilcdc_write(dev, ceil_reg[n], tilcdc_crtc->end);
  73         if (tilcdc_crtc->scanout[n]) {
  74                 drm_flip_work_queue(&tilcdc_crtc->unref_work, tilcdc_crtc->scanout[n]);
  75                 drm_flip_work_commit(&tilcdc_crtc->unref_work, priv->wq);
  76         }
  77         tilcdc_crtc->scanout[n] = crtc->primary->fb;
  78         drm_framebuffer_reference(tilcdc_crtc->scanout[n]);
  79         tilcdc_crtc->dirty &= ~stat[n];
  80         pm_runtime_put_sync(dev->dev);
  81 }
  82
  83 static void update_scanout(struct drm_crtc *crtc)
  84 {
  85         struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
  86         struct drm_device *dev = crtc->dev;
  87         struct drm_framebuffer *fb = crtc->primary->fb;
  88         struct drm_gem_cma_object *gem;
  89         unsigned int depth, bpp;
  90
  91         drm_fb_get_bpp_depth(fb->pixel_format, &depth, &bpp);
  92         gem = drm_fb_cma_get_gem_obj(fb, 0);
  93
  94         tilcdc_crtc->start = gem->paddr + fb->offsets[0] +
  95                         (crtc->y * fb->pitches[0]) + (crtc->x * bpp/8);
  96
  97         tilcdc_crtc->end = tilcdc_crtc->start +
  98                         (crtc->mode.vdisplay * fb->pitches[0]);
  99
 100         if (tilcdc_crtc->dpms == DRM_MODE_DPMS_ON) {
 101                 /* already enabled, so just mark the frames that need
 102                  * updating and they will be updated on vblank:
 103                  */
 104                 tilcdc_crtc->dirty |= LCDC_END_OF_FRAME0 | LCDC_END_OF_FRAME1;
 105                 drm_vblank_get(dev, 0);
 106         } else {
 107                 /* not enabled yet, so update registers immediately: */
 108                 set_scanout(crtc, 0);
 109                 set_scanout(crtc, 1);
 110         }
 111 }
 112
 113 static void start(struct drm_crtc *crtc)
 114 {
 115         struct drm_device *dev = crtc->dev;
 116         struct tilcdc_drm_private *priv = dev->dev_private;
 117
 118         if (priv->rev == 2) {
 119                 tilcdc_set(dev, LCDC_CLK_RESET_REG, LCDC_CLK_MAIN_RESET);
 120                 msleep(1);
 121                 tilcdc_clear(dev, LCDC_CLK_RESET_REG, LCDC_CLK_MAIN_RESET);
 122                 msleep(1);
 123         }
 124
 125         tilcdc_set(dev, LCDC_DMA_CTRL_REG, LCDC_DUAL_FRAME_BUFFER_ENABLE);
 126         tilcdc_set(dev, LCDC_RASTER_CTRL_REG, LCDC_PALETTE_LOAD_MODE(DATA_ONLY));
 127         tilcdc_set(dev, LCDC_RASTER_CTRL_REG, LCDC_RASTER_ENABLE);
 128 }
 129
 130 static void stop(struct drm_crtc *crtc)
 131 {
 132         struct drm_device *dev = crtc->dev;
 133
 134         tilcdc_clear(dev, LCDC_RASTER_CTRL_REG, LCDC_RASTER_ENABLE);
 135 }
 136
 137 static void tilcdc_crtc_destroy(struct drm_crtc *crtc)
 138 {
 139         struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
 140
 141         WARN_ON(tilcdc_crtc->dpms == DRM_MODE_DPMS_ON);
 142
 143         drm_crtc_cleanup(crtc);
 144         drm_flip_work_cleanup(&tilcdc_crtc->unref_work);
 145
 146         kfree(tilcdc_crtc);
 147 }
 148
 149 static int tilcdc_crtc_page_flip(struct drm_crtc *crtc,
 150                 struct drm_framebuffer *fb,
 151                 struct drm_pending_vblank_event *event,
 152                 uint32_t page_flip_flags)
 153 {
 154         struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
 155         struct drm_device *dev = crtc->dev;
 156
 157         if (tilcdc_crtc->event) {
 158                 dev_err(dev->dev, "already pending page flip!\n");
 159                 return -EBUSY;
 160         }
 161
 162         crtc->primary->fb = fb;
 163         tilcdc_crtc->event = event;
 164         update_scanout(crtc);
 165
 166         return 0;
 167 }
 168
 169 static void tilcdc_crtc_dpms(struct drm_crtc *crtc, int mode)
 170 {
 171         struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
 172         struct drm_device *dev = crtc->dev;
 173         struct tilcdc_drm_private *priv = dev->dev_private;
 174
 175         /* we really only care about on or off: */
 176         if (mode != DRM_MODE_DPMS_ON)
 177                 mode = DRM_MODE_DPMS_OFF;
 178
 179         if (tilcdc_crtc->dpms == mode)
 180                 return;
 181
 182         tilcdc_crtc->dpms = mode;
 183
 184         pm_runtime_get_sync(dev->dev);
 185
 186         if (mode == DRM_MODE_DPMS_ON) {
 187                 pm_runtime_forbid(dev->dev);
 188                 start(crtc);
 189         } else {
 190                 tilcdc_crtc->frame_done = false;
 191                 stop(crtc);
 192
 193                 /*
 194                  * if necessary wait for framedone irq which will still come
 195                  * before putting things to sleep..
 196                  */
 197                 if (priv->rev == 2) {
 198                         int ret = wait_event_timeout(
 199                                         tilcdc_crtc->frame_done_wq,
 200                                         tilcdc_crtc->frame_done,
 201                                         msecs_to_jiffies(50));
 202                         if (ret == 0)
 203                                 dev_err(dev->dev, "timeout waiting for framedone\n");
 204                 }
 205                 pm_runtime_allow(dev->dev);
 206         }
 207
 208         pm_runtime_put_sync(dev->dev);
 209 }
 210
 211 static bool tilcdc_crtc_mode_fixup(struct drm_crtc *crtc,
 212                 const struct drm_display_mode *mode,
 213                 struct drm_display_mode *adjusted_mode)
 214 {
 215         return true;
 216 }
 217
 218 static void tilcdc_crtc_prepare(struct drm_crtc *crtc)
 219 {
 220         tilcdc_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
 221 }
 222
 223 static void tilcdc_crtc_commit(struct drm_crtc *crtc)
 224 {
 225         tilcdc_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
 226 }
 227
 228 static int tilcdc_crtc_mode_set(struct drm_crtc *crtc,
 229                 struct drm_display_mode *mode,
 230                 struct drm_display_mode *adjusted_mode,
 231                 int x, int y,
 232                 struct drm_framebuffer *old_fb)
 233 {
 234         struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
 235         struct drm_device *dev = crtc->dev;
 236         struct tilcdc_drm_private *priv = dev->dev_private;
 237         const struct tilcdc_panel_info *info = tilcdc_crtc->info;
 238         uint32_t reg, hbp, hfp, hsw, vbp, vfp, vsw;
 239         int ret;
 240
 241         ret = tilcdc_crtc_mode_valid(crtc, mode);
 242         if (WARN_ON(ret))
 243                 return ret;
 244
 245         if (WARN_ON(!info))
 246                 return -EINVAL;
 247
 248         pm_runtime_get_sync(dev->dev);
 249
 250         /* Configure the Burst Size and fifo threshold of DMA: */
 251         reg = tilcdc_read(dev, LCDC_DMA_CTRL_REG) & ~0x00000770;
 252         switch (info->dma_burst_sz) {
 253         case 1:
 254                 reg |= LCDC_DMA_BURST_SIZE(LCDC_DMA_BURST_1);
 255                 break;
 256         case 2:
 257                 reg |= LCDC_DMA_BURST_SIZE(LCDC_DMA_BURST_2);
 258                 break;
 259         case 4:
 260                 reg |= LCDC_DMA_BURST_SIZE(LCDC_DMA_BURST_4);
 261                 break;
 262         case 8:
 263                 reg |= LCDC_DMA_BURST_SIZE(LCDC_DMA_BURST_8);
 264                 break;
 265         case 16:
 266                 reg |= LCDC_DMA_BURST_SIZE(LCDC_DMA_BURST_16);
 267                 break;
 268         default:
 269                 return -EINVAL;
 270         }
 271         reg |= (info->fifo_th << 8);
 272         tilcdc_write(dev, LCDC_DMA_CTRL_REG, reg);
 273
 274         /* Configure timings: */
 275         hbp = mode->htotal - mode->hsync_end;
 276         hfp = mode->hsync_start - mode->hdisplay;
 277         hsw = mode->hsync_end - mode->hsync_start;
 278         vbp = mode->vtotal - mode->vsync_end;
 279         vfp = mode->vsync_start - mode->vdisplay;
 280         vsw = mode->vsync_end - mode->vsync_start;
 281
 282         DBG("%dx%d, hbp=%u, hfp=%u, hsw=%u, vbp=%u, vfp=%u, vsw=%u",
 283                         mode->hdisplay, mode->vdisplay, hbp, hfp, hsw, vbp, vfp, vsw);
 284
 285         /* Configure the AC Bias Period and Number of Transitions per Interrupt: */
 286         reg = tilcdc_read(dev, LCDC_RASTER_TIMING_2_REG) & ~0x000fff00;
 287         reg |= LCDC_AC_BIAS_FREQUENCY(info->ac_bias) |
 288                 LCDC_AC_BIAS_TRANSITIONS_PER_INT(info->ac_bias_intrpt);
 289
 290         /*
 291          * subtract one from hfp, hbp, hsw because the hardware uses
 292          * a value of 0 as 1
 293          */
 294         if (priv->rev == 2) {
 295                 /* clear bits we're going to set */
 296                 reg &= ~0x78000033;
 297                 reg |= ((hfp-1) & 0x300) >> 8;
 298                 reg |= ((hbp-1) & 0x300) >> 4;
 299                 reg |= ((hsw-1) & 0x3c0) << 21;
 300         }
 301         tilcdc_write(dev, LCDC_RASTER_TIMING_2_REG, reg);
 302
 303         reg = (((mode->hdisplay >> 4) - 1) << 4) |
 304                 (((hbp-1) & 0xff) << 24) |
 305                 (((hfp-1) & 0xff) << 16) |
 306                 (((hsw-1) & 0x3f) << 10);
 307         if (priv->rev == 2)
 308                 reg |= (((mode->hdisplay >> 4) - 1) & 0x40) >> 3;
 309         tilcdc_write(dev, LCDC_RASTER_TIMING_0_REG, reg);
 310
 311         reg = ((mode->vdisplay - 1) & 0x3ff) |
 312                 ((vbp & 0xff) << 24) |
 313                 ((vfp & 0xff) << 16) |
 314                 (((vsw-1) & 0x3f) << 10);
 315         tilcdc_write(dev, LCDC_RASTER_TIMING_1_REG, reg);
 316
 317         /*
 318          * be sure to set Bit 10 for the V2 LCDC controller,
 319          * otherwise limited to 1024 pixels width, stopping
 320          * 1920x1080 being suppoted.
 321          */
 322         if (priv->rev == 2) {
 323                 if ((mode->vdisplay - 1) & 0x400) {
 324                         tilcdc_set(dev, LCDC_RASTER_TIMING_2_REG,
 325                                 LCDC_LPP_B10);
 326                 } else {
 327                         tilcdc_clear(dev, LCDC_RASTER_TIMING_2_REG,
 328                                 LCDC_LPP_B10);
 329                 }
 330         }
 331
 332         /* Configure display type: */
 333         reg = tilcdc_read(dev, LCDC_RASTER_CTRL_REG) &
 334                 ~(LCDC_TFT_MODE | LCDC_MONO_8BIT_MODE | LCDC_MONOCHROME_MODE |
 335                         LCDC_V2_TFT_24BPP_MODE | LCDC_V2_TFT_24BPP_UNPACK | 0x000ff000);
 336         reg |= LCDC_TFT_MODE; /* no monochrome/passive support */
 337         if (info->tft_alt_mode)
 338                 reg |= LCDC_TFT_ALT_ENABLE;
 339         if (priv->rev == 2) {
 340                 unsigned int depth, bpp;
 341
 342                 drm_fb_get_bpp_depth(crtc->primary->fb->pixel_format, &depth, &bpp);
 343                 switch (bpp) {
 344                 case 16:
 345                         break;
 346                 case 32:
 347                         reg |= LCDC_V2_TFT_24BPP_UNPACK;
 348                         /* fallthrough */
 349                 case 24:
 350                         reg |= LCDC_V2_TFT_24BPP_MODE;
 351                         break;
 352                 default:
 353                         dev_err(dev->dev, "invalid pixel format\n");
 354                         return -EINVAL;
 355                 }
 356         }
 357         reg |= info->fdd < 12;
 358         tilcdc_write(dev, LCDC_RASTER_CTRL_REG, reg);
 359
 360         if (info->invert_pxl_clk)
 361                 tilcdc_set(dev, LCDC_RASTER_TIMING_2_REG, LCDC_INVERT_PIXEL_CLOCK);
 362         else
 363                 tilcdc_clear(dev, LCDC_RASTER_TIMING_2_REG, LCDC_INVERT_PIXEL_CLOCK);
 364
 365         if (info->sync_ctrl)
 366                 tilcdc_set(dev, LCDC_RASTER_TIMING_2_REG, LCDC_SYNC_CTRL);
 367         else
 368                 tilcdc_clear(dev, LCDC_RASTER_TIMING_2_REG, LCDC_SYNC_CTRL);
 369
 370         if (info->sync_edge)
 371                 tilcdc_set(dev, LCDC_RASTER_TIMING_2_REG, LCDC_SYNC_EDGE);
 372         else
 373                 tilcdc_clear(dev, LCDC_RASTER_TIMING_2_REG, LCDC_SYNC_EDGE);
 374
 375         /*
 376          * use value from adjusted_mode here as this might have been
 377          * changed as part of the fixup for slave encoders to solve the
 378          * issue where tilcdc timings are not VESA compliant
 379          */
 380         if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
 381                 tilcdc_set(dev, LCDC_RASTER_TIMING_2_REG, LCDC_INVERT_HSYNC);
 382         else
 383                 tilcdc_clear(dev, LCDC_RASTER_TIMING_2_REG, LCDC_INVERT_HSYNC);
 384
 385         if (mode->flags & DRM_MODE_FLAG_NVSYNC)
 386                 tilcdc_set(dev, LCDC_RASTER_TIMING_2_REG, LCDC_INVERT_VSYNC);
 387         else
 388                 tilcdc_clear(dev, LCDC_RASTER_TIMING_2_REG, LCDC_INVERT_VSYNC);
 389
 390         if (info->raster_order)
 391                 tilcdc_set(dev, LCDC_RASTER_CTRL_REG, LCDC_RASTER_ORDER);
 392         else
 393                 tilcdc_clear(dev, LCDC_RASTER_CTRL_REG, LCDC_RASTER_ORDER);
 394
 395
 396         update_scanout(crtc);
 397         tilcdc_crtc_update_clk(crtc);
 398
 399         pm_runtime_put_sync(dev->dev);
 400
 401         return 0;
 402 }
 403
 404 static int tilcdc_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y,
 405                 struct drm_framebuffer *old_fb)
 406 {
 407         update_scanout(crtc);
 408         return 0;
 409 }
 410
 411 static const struct drm_crtc_funcs tilcdc_crtc_funcs = {
 412                 .destroy        = tilcdc_crtc_destroy,
 413                 .set_config     = drm_crtc_helper_set_config,
 414                 .page_flip      = tilcdc_crtc_page_flip,
 415 };
 416
 417 static const struct drm_crtc_helper_funcs tilcdc_crtc_helper_funcs = {
 418                 .dpms           = tilcdc_crtc_dpms,
 419                 .mode_fixup     = tilcdc_crtc_mode_fixup,
 420                 .prepare        = tilcdc_crtc_prepare,
 421                 .commit         = tilcdc_crtc_commit,
 422                 .mode_set       = tilcdc_crtc_mode_set,
 423                 .mode_set_base  = tilcdc_crtc_mode_set_base,
 424 };
 425
 426 int tilcdc_crtc_max_width(struct drm_crtc *crtc)
 427 {
 428         struct drm_device *dev = crtc->dev;
 429         struct tilcdc_drm_private *priv = dev->dev_private;
 430         int max_width = 0;
 431
 432         if (priv->rev == 1)
 433                 max_width = 1024;
 434         else if (priv->rev == 2)
 435                 max_width = 2048;
 436
 437         return max_width;
 438 }
 439
 440 int tilcdc_crtc_mode_valid(struct drm_crtc *crtc, struct drm_display_mode *mode)
 441 {
 442         struct tilcdc_drm_private *priv = crtc->dev->dev_private;
 443         unsigned int bandwidth;
 444         uint32_t hbp, hfp, hsw, vbp, vfp, vsw;
 445
 446         /*
 447          * check to see if the width is within the range that
 448          * the LCD Controller physically supports
 449          */
 450         if (mode->hdisplay > tilcdc_crtc_max_width(crtc))
 451                 return MODE_VIRTUAL_X;
 452
 453         /* width must be multiple of 16 */
 454         if (mode->hdisplay & 0xf)
 455                 return MODE_VIRTUAL_X;
 456
 457         if (mode->vdisplay > 2048)
 458                 return MODE_VIRTUAL_Y;
 459
 460         DBG("Processing mode %dx%d@%d with pixel clock %d",
 461                 mode->hdisplay, mode->vdisplay,
 462                 drm_mode_vrefresh(mode), mode->clock);
 463
 464         hbp = mode->htotal - mode->hsync_end;
 465         hfp = mode->hsync_start - mode->hdisplay;
 466         hsw = mode->hsync_end - mode->hsync_start;
 467         vbp = mode->vtotal - mode->vsync_end;
 468         vfp = mode->vsync_start - mode->vdisplay;
 469         vsw = mode->vsync_end - mode->vsync_start;
 470
 471         if ((hbp-1) & ~0x3ff) {
 472                 DBG("Pruning mode: Horizontal Back Porch out of range");
 473                 return MODE_HBLANK_WIDE;
 474         }
 475
 476         if ((hfp-1) & ~0x3ff) {
 477                 DBG("Pruning mode: Horizontal Front Porch out of range");
 478                 return MODE_HBLANK_WIDE;
 479         }
 480
 481         if ((hsw-1) & ~0x3ff) {
 482                 DBG("Pruning mode: Horizontal Sync Width out of range");
 483                 return MODE_HSYNC_WIDE;
 484         }
 485
 486         if (vbp & ~0xff) {
 487                 DBG("Pruning mode: Vertical Back Porch out of range");
 488                 return MODE_VBLANK_WIDE;
 489         }
 490
 491         if (vfp & ~0xff) {
 492                 DBG("Pruning mode: Vertical Front Porch out of range");
 493                 return MODE_VBLANK_WIDE;
 494         }
 495
 496         if ((vsw-1) & ~0x3f) {
 497                 DBG("Pruning mode: Vertical Sync Width out of range");
 498                 return MODE_VSYNC_WIDE;
 499         }
 500
 501         /*
 502          * some devices have a maximum allowed pixel clock
 503          * configured from the DT
 504          */
 505         if (mode->clock > priv->max_pixelclock) {
 506                 DBG("Pruning mode: pixel clock too high");
 507                 return MODE_CLOCK_HIGH;
 508         }
 509
 510         /*
 511          * some devices further limit the max horizontal resolution
 512          * configured from the DT
 513          */
 514         if (mode->hdisplay > priv->max_width)
 515                 return MODE_BAD_WIDTH;
 516
 517         /* filter out modes that would require too much memory bandwidth: */
 518         bandwidth = mode->hdisplay * mode->vdisplay *
 519                 drm_mode_vrefresh(mode);
 520         if (bandwidth > priv->max_bandwidth) {
 521                 DBG("Pruning mode: exceeds defined bandwidth limit");
 522                 return MODE_BAD;
 523         }
 524
 525         return MODE_OK;
 526 }
 527
 528 void tilcdc_crtc_set_panel_info(struct drm_crtc *crtc,
 529                 const struct tilcdc_panel_info *info)
 530 {
 531         struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
 532         tilcdc_crtc->info = info;
 533 }
 534
 535 void tilcdc_crtc_update_clk(struct drm_crtc *crtc)
 536 {
 537         struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
 538         struct drm_device *dev = crtc->dev;
 539         struct tilcdc_drm_private *priv = dev->dev_private;
 540         int dpms = tilcdc_crtc->dpms;
 541         unsigned int lcd_clk, div;
 542         int ret;
 543
 544         pm_runtime_get_sync(dev->dev);
 545
 546         if (dpms == DRM_MODE_DPMS_ON)
 547                 tilcdc_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
 548
 549         /* in raster mode, minimum divisor is 2: */
 550         ret = clk_set_rate(priv->disp_clk, crtc->mode.clock * 1000 * 2);
 551         if (ret) {
 552                 dev_err(dev->dev, "failed to set display clock rate to: %d\n",
 553                                 crtc->mode.clock);
 554                 goto out;
 555         }
 556
 557         lcd_clk = clk_get_rate(priv->clk);
 558         div = lcd_clk / (crtc->mode.clock * 1000);
 559
 560         DBG("lcd_clk=%u, mode clock=%d, div=%u", lcd_clk, crtc->mode.clock, div);
 561         DBG("fck=%lu, dpll_disp_ck=%lu", clk_get_rate(priv->clk), clk_get_rate(priv->disp_clk));
 562
 563         /* Configure the LCD clock divisor. */
 564         tilcdc_write(dev, LCDC_CTRL_REG, LCDC_CLK_DIVISOR(div) |
 565                         LCDC_RASTER_MODE);
 566
 567         if (priv->rev == 2)
 568                 tilcdc_set(dev, LCDC_CLK_ENABLE_REG,
 569                                 LCDC_V2_DMA_CLK_EN | LCDC_V2_LIDD_CLK_EN |
 570                                 LCDC_V2_CORE_CLK_EN);
 571
 572         if (dpms == DRM_MODE_DPMS_ON)
 573                 tilcdc_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
 574
 575 out:
 576         pm_runtime_put_sync(dev->dev);
 577 }
 578
 579 irqreturn_t tilcdc_crtc_irq(struct drm_crtc *crtc)
 580 {
 581         struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
 582         struct drm_device *dev = crtc->dev;
 583         struct tilcdc_drm_private *priv = dev->dev_private;
 584         uint32_t stat = tilcdc_read_irqstatus(dev);
 585
 586         if ((stat & LCDC_SYNC_LOST) && (stat & LCDC_FIFO_UNDERFLOW)) {
 587                 stop(crtc);
 588                 dev_err(dev->dev, "error: %08x\n", stat);
 589                 tilcdc_clear_irqstatus(dev, stat);
 590                 start(crtc);
 591         } else if (stat & LCDC_PL_LOAD_DONE) {
 592                 tilcdc_clear_irqstatus(dev, stat);
 593         } else {
 594                 struct drm_pending_vblank_event *event;
 595                 unsigned long flags;
 596                 uint32_t dirty = tilcdc_crtc->dirty & stat;
 597
 598                 tilcdc_clear_irqstatus(dev, stat);
 599
 600                 if (dirty & LCDC_END_OF_FRAME0)
 601                         set_scanout(crtc, 0);
 602
 603                 if (dirty & LCDC_END_OF_FRAME1)
 604                         set_scanout(crtc, 1);
 605
 606                 drm_handle_vblank(dev, 0);
 607
 608                 spin_lock_irqsave(&dev->event_lock, flags);
 609                 event = tilcdc_crtc->event;
 610                 tilcdc_crtc->event = NULL;
 611                 if (event)
 612                         drm_send_vblank_event(dev, 0, event);
 613                 spin_unlock_irqrestore(&dev->event_lock, flags);
 614
 615                 if (dirty && !tilcdc_crtc->dirty)
 616                         drm_vblank_put(dev, 0);
 617         }
 618
 619         if (priv->rev == 2) {
 620                 if (stat & LCDC_FRAME_DONE) {
 621                         tilcdc_crtc->frame_done = true;
 622                         wake_up(&tilcdc_crtc->frame_done_wq);
 623                 }
 624                 tilcdc_write(dev, LCDC_END_OF_INT_IND_REG, 0);
 625         }
 626
 627         return IRQ_HANDLED;
 628 }
 629
 630 void tilcdc_crtc_cancel_page_flip(struct drm_crtc *crtc, struct drm_file *file)
 631 {
 632         struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
 633         struct drm_pending_vblank_event *event;
 634         struct drm_device *dev = crtc->dev;
 635         unsigned long flags;
 636
 637         /* Destroy the pending vertical blanking event associated with the
 638          * pending page flip, if any, and disable vertical blanking interrupts.
 639          */
 640         spin_lock_irqsave(&dev->event_lock, flags);
 641         event = tilcdc_crtc->event;
 642         if (event && event->base.file_priv == file) {
 643                 tilcdc_crtc->event = NULL;
 644                 event->base.destroy(&event->base);
 645                 drm_vblank_put(dev, 0);
 646         }
 647         spin_unlock_irqrestore(&dev->event_lock, flags);
 648 }
 649
 650 struct drm_crtc *tilcdc_crtc_create(struct drm_device *dev)
 651 {
 652         struct tilcdc_crtc *tilcdc_crtc;
 653         struct drm_crtc *crtc;
 654         int ret;
 655
 656         tilcdc_crtc = kzalloc(sizeof(*tilcdc_crtc), GFP_KERNEL);
 657         if (!tilcdc_crtc) {
 658                 dev_err(dev->dev, "allocation failed\n");
 659                 return NULL;
 660         }
 661
 662         crtc = &tilcdc_crtc->base;
 663
 664         tilcdc_crtc->dpms = DRM_MODE_DPMS_OFF;
 665         init_waitqueue_head(&tilcdc_crtc->frame_done_wq);
 666
 667         ret = drm_flip_work_init(&tilcdc_crtc->unref_work, 16,
 668                         "unref", unref_worker);
 669         if (ret) {
 670                 dev_err(dev->dev, "could not allocate unref FIFO\n");
 671                 goto fail;
 672         }
 673
 674         ret = drm_crtc_init(dev, crtc, &tilcdc_crtc_funcs);
 675         if (ret < 0)
 676                 goto fail;
 677
 678         drm_crtc_helper_add(crtc, &tilcdc_crtc_helper_funcs);
 679
 680         return crtc;
 681
 682 fail:
 683         tilcdc_crtc_destroy(crtc);
 684         return NULL;
 685 }