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sched: Remove double_rq_lock() from __migrate_task()
[linux/fpc-iii.git] / drivers / media / dvb-frontends / drxd_firm.c
blob5418b0b1dadc6acc7502bc5e70357aba93f3d0a8
1 /*
2 * drxd_firm.c : DRXD firmware tables
3 *
4 * Copyright (C) 2006-2007 Micronas
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * version 2 only, as published by the Free Software Foundation.
9 *
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
20 * 02110-1301, USA
21 * Or, point your browser to http://www.gnu.org/copyleft/gpl.html
22 */
23
24 /* TODO: generate this file with a script from a settings file */
25
26 /* Contains A2 firmware version: 1.4.2
27 * Contains B1 firmware version: 3.3.33
28 * Contains settings from driver 1.4.23
29 */
30
31 #include "drxd_firm.h"
32
33 #define ADDRESS(x) ((x) & 0xFF), (((x)>>8) & 0xFF), (((x)>>16) & 0xFF), (((x)>>24) & 0xFF)
34 #define LENGTH(x) ((x) & 0xFF), (((x)>>8) & 0xFF)
35
36 /* Is written via block write, must be little endian */
37 #define DATA16(x) ((x) & 0xFF), (((x)>>8) & 0xFF)
38
39 #define WRBLOCK(a, l) ADDRESS(a), LENGTH(l)
40 #define WR16(a, d) ADDRESS(a), LENGTH(1), DATA16(d)
41
42 #define END_OF_TABLE 0xFF, 0xFF, 0xFF, 0xFF
43
44 /* HI firmware patches */
45
46 #define HI_TR_FUNC_ADDR HI_IF_RAM_USR_BEGIN__A
47 #define HI_TR_FUNC_SIZE 9 /* size of this function in instruction words */
48
49 u8 DRXD_InitAtomicRead[] = {
50 WRBLOCK(HI_TR_FUNC_ADDR, HI_TR_FUNC_SIZE),
51 0x26, 0x00, /* 0 -> ring.rdy; */
52 0x60, 0x04, /* r0rami.dt -> ring.xba; */
53 0x61, 0x04, /* r0rami.dt -> ring.xad; */
54 0xE3, 0x07, /* HI_RA_RAM_USR_BEGIN -> ring.iad; */
55 0x40, 0x00, /* (long immediate) */
56 0x64, 0x04, /* r0rami.dt -> ring.len; */
57 0x65, 0x04, /* r0rami.dt -> ring.ctl; */
58 0x26, 0x00, /* 0 -> ring.rdy; */
59 0x38, 0x00, /* 0 -> jumps.ad; */
60 END_OF_TABLE
61 };
62
63 /* Pins D0 and D1 of the parallel MPEG output can be used
64 to set the I2C address of a device. */
65
66 #define HI_RST_FUNC_ADDR (HI_IF_RAM_USR_BEGIN__A + HI_TR_FUNC_SIZE)
67 #define HI_RST_FUNC_SIZE 54 /* size of this function in instruction words */
68
69 /* D0 Version */
70 u8 DRXD_HiI2cPatch_1[] = {
71 WRBLOCK(HI_RST_FUNC_ADDR, HI_RST_FUNC_SIZE),
72 0xC8, 0x07, 0x01, 0x00, /* MASK -> reg0.dt; */
73 0xE0, 0x07, 0x15, 0x02, /* (EC__BLK << 6) + EC_OC_REG__BNK -> ring.xba; */
74 0xE1, 0x07, 0x12, 0x00, /* EC_OC_REG_OC_MPG_SIO__A -> ring.xad; */
75 0xA2, 0x00, /* M_BNK_ID_DAT -> ring.iba; */
76 0x23, 0x00, /* &data -> ring.iad; */
77 0x24, 0x00, /* 0 -> ring.len; */
78 0xA5, 0x02, /* M_RC_CTR_SWAP | M_RC_CTR_READ -> ring.ctl; */
79 0x26, 0x00, /* 0 -> ring.rdy; */
80 0x42, 0x00, /* &data+1 -> w0ram.ad; */
81 0xC0, 0x07, 0xFF, 0x0F, /* -1 -> w0ram.dt; */
82 0x63, 0x00, /* &data+1 -> ring.iad; */
83 0x65, 0x02, /* M_RC_CTR_SWAP | M_RC_CTR_WRITE -> ring.ctl; */
84 0x26, 0x00, /* 0 -> ring.rdy; */
85 0xE1, 0x07, 0x38, 0x00, /* EC_OC_REG_OCR_MPG_USR_DAT__A -> ring.xad; */
86 0xA5, 0x02, /* M_RC_CTR_SWAP | M_RC_CTR_READ -> ring.ctl; */
87 0x26, 0x00, /* 0 -> ring.rdy; */
88 0xE1, 0x07, 0x12, 0x00, /* EC_OC_REG_OC_MPG_SIO__A -> ring.xad; */
89 0x23, 0x00, /* &data -> ring.iad; */
90 0x65, 0x02, /* M_RC_CTR_SWAP | M_RC_CTR_WRITE -> ring.ctl; */
91 0x26, 0x00, /* 0 -> ring.rdy; */
92 0x42, 0x00, /* &data+1 -> w0ram.ad; */
93 0x0F, 0x04, /* r0ram.dt -> and.op; */
94 0x1C, 0x06, /* reg0.dt -> and.tr; */
95 0xCF, 0x04, /* and.rs -> add.op; */
96 0xD0, 0x07, 0x70, 0x00, /* DEF_DEV_ID -> add.tr; */
97 0xD0, 0x04, /* add.rs -> add.tr; */
98 0xC8, 0x04, /* add.rs -> reg0.dt; */
99 0x60, 0x00, /* reg0.dt -> w0ram.dt; */
100 0xC2, 0x07, 0x10, 0x00, /* SLV0_BASE -> w0rami.ad; */
101 0x01, 0x00, /* 0 -> w0rami.dt; */
102 0x01, 0x06, /* reg0.dt -> w0rami.dt; */
103 0xC2, 0x07, 0x20, 0x00, /* SLV1_BASE -> w0rami.ad; */
104 0x01, 0x00, /* 0 -> w0rami.dt; */
105 0x01, 0x06, /* reg0.dt -> w0rami.dt; */
106 0xC2, 0x07, 0x30, 0x00, /* CMD_BASE -> w0rami.ad; */
107 0x01, 0x00, /* 0 -> w0rami.dt; */
108 0x01, 0x00, /* 0 -> w0rami.dt; */
109 0x01, 0x00, /* 0 -> w0rami.dt; */
110 0x68, 0x00, /* M_IC_SEL_PT1 -> i2c.sel; */
111 0x29, 0x00, /* M_IC_CMD_RESET -> i2c.cmd; */
112 0x28, 0x00, /* M_IC_SEL_PT0 -> i2c.sel; */
113 0x29, 0x00, /* M_IC_CMD_RESET -> i2c.cmd; */
114 0xF8, 0x07, 0x2F, 0x00, /* 0x2F -> jumps.ad; */
115
116 WR16((B_HI_IF_RAM_TRP_BPT0__AX + ((2 * 0) + 1)),
117 (u16) (HI_RST_FUNC_ADDR & 0x3FF)),
118 WR16((B_HI_IF_RAM_TRP_BPT0__AX + ((2 * 1) + 1)),
119 (u16) (HI_RST_FUNC_ADDR & 0x3FF)),
120 WR16((B_HI_IF_RAM_TRP_BPT0__AX + ((2 * 2) + 1)),
121 (u16) (HI_RST_FUNC_ADDR & 0x3FF)),
122 WR16((B_HI_IF_RAM_TRP_BPT0__AX + ((2 * 3) + 1)),
123 (u16) (HI_RST_FUNC_ADDR & 0x3FF)),
124
125 /* Force quick and dirty reset */
126 WR16(B_HI_CT_REG_COMM_STATE__A, 0),
127 END_OF_TABLE
128 };
129
130 /* D0,D1 Version */
131 u8 DRXD_HiI2cPatch_3[] = {
132 WRBLOCK(HI_RST_FUNC_ADDR, HI_RST_FUNC_SIZE),
133 0xC8, 0x07, 0x03, 0x00, /* MASK -> reg0.dt; */
134 0xE0, 0x07, 0x15, 0x02, /* (EC__BLK << 6) + EC_OC_REG__BNK -> ring.xba; */
135 0xE1, 0x07, 0x12, 0x00, /* EC_OC_REG_OC_MPG_SIO__A -> ring.xad; */
136 0xA2, 0x00, /* M_BNK_ID_DAT -> ring.iba; */
137 0x23, 0x00, /* &data -> ring.iad; */
138 0x24, 0x00, /* 0 -> ring.len; */
139 0xA5, 0x02, /* M_RC_CTR_SWAP | M_RC_CTR_READ -> ring.ctl; */
140 0x26, 0x00, /* 0 -> ring.rdy; */
141 0x42, 0x00, /* &data+1 -> w0ram.ad; */
142 0xC0, 0x07, 0xFF, 0x0F, /* -1 -> w0ram.dt; */
143 0x63, 0x00, /* &data+1 -> ring.iad; */
144 0x65, 0x02, /* M_RC_CTR_SWAP | M_RC_CTR_WRITE -> ring.ctl; */
145 0x26, 0x00, /* 0 -> ring.rdy; */
146 0xE1, 0x07, 0x38, 0x00, /* EC_OC_REG_OCR_MPG_USR_DAT__A -> ring.xad; */
147 0xA5, 0x02, /* M_RC_CTR_SWAP | M_RC_CTR_READ -> ring.ctl; */
148 0x26, 0x00, /* 0 -> ring.rdy; */
149 0xE1, 0x07, 0x12, 0x00, /* EC_OC_REG_OC_MPG_SIO__A -> ring.xad; */
150 0x23, 0x00, /* &data -> ring.iad; */
151 0x65, 0x02, /* M_RC_CTR_SWAP | M_RC_CTR_WRITE -> ring.ctl; */
152 0x26, 0x00, /* 0 -> ring.rdy; */
153 0x42, 0x00, /* &data+1 -> w0ram.ad; */
154 0x0F, 0x04, /* r0ram.dt -> and.op; */
155 0x1C, 0x06, /* reg0.dt -> and.tr; */
156 0xCF, 0x04, /* and.rs -> add.op; */
157 0xD0, 0x07, 0x70, 0x00, /* DEF_DEV_ID -> add.tr; */
158 0xD0, 0x04, /* add.rs -> add.tr; */
159 0xC8, 0x04, /* add.rs -> reg0.dt; */
160 0x60, 0x00, /* reg0.dt -> w0ram.dt; */
161 0xC2, 0x07, 0x10, 0x00, /* SLV0_BASE -> w0rami.ad; */
162 0x01, 0x00, /* 0 -> w0rami.dt; */
163 0x01, 0x06, /* reg0.dt -> w0rami.dt; */
164 0xC2, 0x07, 0x20, 0x00, /* SLV1_BASE -> w0rami.ad; */
165 0x01, 0x00, /* 0 -> w0rami.dt; */
166 0x01, 0x06, /* reg0.dt -> w0rami.dt; */
167 0xC2, 0x07, 0x30, 0x00, /* CMD_BASE -> w0rami.ad; */
168 0x01, 0x00, /* 0 -> w0rami.dt; */
169 0x01, 0x00, /* 0 -> w0rami.dt; */
170 0x01, 0x00, /* 0 -> w0rami.dt; */
171 0x68, 0x00, /* M_IC_SEL_PT1 -> i2c.sel; */
172 0x29, 0x00, /* M_IC_CMD_RESET -> i2c.cmd; */
173 0x28, 0x00, /* M_IC_SEL_PT0 -> i2c.sel; */
174 0x29, 0x00, /* M_IC_CMD_RESET -> i2c.cmd; */
175 0xF8, 0x07, 0x2F, 0x00, /* 0x2F -> jumps.ad; */
176
177 WR16((B_HI_IF_RAM_TRP_BPT0__AX + ((2 * 0) + 1)),
178 (u16) (HI_RST_FUNC_ADDR & 0x3FF)),
179 WR16((B_HI_IF_RAM_TRP_BPT0__AX + ((2 * 1) + 1)),
180 (u16) (HI_RST_FUNC_ADDR & 0x3FF)),
181 WR16((B_HI_IF_RAM_TRP_BPT0__AX + ((2 * 2) + 1)),
182 (u16) (HI_RST_FUNC_ADDR & 0x3FF)),
183 WR16((B_HI_IF_RAM_TRP_BPT0__AX + ((2 * 3) + 1)),
184 (u16) (HI_RST_FUNC_ADDR & 0x3FF)),
185
186 /* Force quick and dirty reset */
187 WR16(B_HI_CT_REG_COMM_STATE__A, 0),
188 END_OF_TABLE
189 };
190
191 u8 DRXD_ResetCEFR[] = {
192 WRBLOCK(CE_REG_FR_TREAL00__A, 57),
193 0x52, 0x00, /* CE_REG_FR_TREAL00__A */
194 0x00, 0x00, /* CE_REG_FR_TIMAG00__A */
195 0x52, 0x00, /* CE_REG_FR_TREAL01__A */
196 0x00, 0x00, /* CE_REG_FR_TIMAG01__A */
197 0x52, 0x00, /* CE_REG_FR_TREAL02__A */
198 0x00, 0x00, /* CE_REG_FR_TIMAG02__A */
199 0x52, 0x00, /* CE_REG_FR_TREAL03__A */
200 0x00, 0x00, /* CE_REG_FR_TIMAG03__A */
201 0x52, 0x00, /* CE_REG_FR_TREAL04__A */
202 0x00, 0x00, /* CE_REG_FR_TIMAG04__A */
203 0x52, 0x00, /* CE_REG_FR_TREAL05__A */
204 0x00, 0x00, /* CE_REG_FR_TIMAG05__A */
205 0x52, 0x00, /* CE_REG_FR_TREAL06__A */
206 0x00, 0x00, /* CE_REG_FR_TIMAG06__A */
207 0x52, 0x00, /* CE_REG_FR_TREAL07__A */
208 0x00, 0x00, /* CE_REG_FR_TIMAG07__A */
209 0x52, 0x00, /* CE_REG_FR_TREAL08__A */
210 0x00, 0x00, /* CE_REG_FR_TIMAG08__A */
211 0x52, 0x00, /* CE_REG_FR_TREAL09__A */
212 0x00, 0x00, /* CE_REG_FR_TIMAG09__A */
213 0x52, 0x00, /* CE_REG_FR_TREAL10__A */
214 0x00, 0x00, /* CE_REG_FR_TIMAG10__A */
215 0x52, 0x00, /* CE_REG_FR_TREAL11__A */
216 0x00, 0x00, /* CE_REG_FR_TIMAG11__A */
217
218 0x52, 0x00, /* CE_REG_FR_MID_TAP__A */
219
220 0x0B, 0x00, /* CE_REG_FR_SQS_G00__A */
221 0x0B, 0x00, /* CE_REG_FR_SQS_G01__A */
222 0x0B, 0x00, /* CE_REG_FR_SQS_G02__A */
223 0x0B, 0x00, /* CE_REG_FR_SQS_G03__A */
224 0x0B, 0x00, /* CE_REG_FR_SQS_G04__A */
225 0x0B, 0x00, /* CE_REG_FR_SQS_G05__A */
226 0x0B, 0x00, /* CE_REG_FR_SQS_G06__A */
227 0x0B, 0x00, /* CE_REG_FR_SQS_G07__A */
228 0x0B, 0x00, /* CE_REG_FR_SQS_G08__A */
229 0x0B, 0x00, /* CE_REG_FR_SQS_G09__A */
230 0x0B, 0x00, /* CE_REG_FR_SQS_G10__A */
231 0x0B, 0x00, /* CE_REG_FR_SQS_G11__A */
232 0x0B, 0x00, /* CE_REG_FR_SQS_G12__A */
233
234 0xFF, 0x01, /* CE_REG_FR_RIO_G00__A */
235 0x90, 0x01, /* CE_REG_FR_RIO_G01__A */
236 0x0B, 0x01, /* CE_REG_FR_RIO_G02__A */
237 0xC8, 0x00, /* CE_REG_FR_RIO_G03__A */
238 0xA0, 0x00, /* CE_REG_FR_RIO_G04__A */
239 0x85, 0x00, /* CE_REG_FR_RIO_G05__A */
240 0x72, 0x00, /* CE_REG_FR_RIO_G06__A */
241 0x64, 0x00, /* CE_REG_FR_RIO_G07__A */
242 0x59, 0x00, /* CE_REG_FR_RIO_G08__A */
243 0x50, 0x00, /* CE_REG_FR_RIO_G09__A */
244 0x49, 0x00, /* CE_REG_FR_RIO_G10__A */
245
246 0x10, 0x00, /* CE_REG_FR_MODE__A */
247 0x78, 0x00, /* CE_REG_FR_SQS_TRH__A */
248 0x00, 0x00, /* CE_REG_FR_RIO_GAIN__A */
249 0x00, 0x02, /* CE_REG_FR_BYPASS__A */
250 0x0D, 0x00, /* CE_REG_FR_PM_SET__A */
251 0x07, 0x00, /* CE_REG_FR_ERR_SH__A */
252 0x04, 0x00, /* CE_REG_FR_MAN_SH__A */
253 0x06, 0x00, /* CE_REG_FR_TAP_SH__A */
254
255 END_OF_TABLE
256 };
257
258 u8 DRXD_InitFEA2_1[] = {
259 WRBLOCK(FE_AD_REG_PD__A, 3),
260 0x00, 0x00, /* FE_AD_REG_PD__A */
261 0x01, 0x00, /* FE_AD_REG_INVEXT__A */
262 0x00, 0x00, /* FE_AD_REG_CLKNEG__A */
263
264 WRBLOCK(FE_AG_REG_DCE_AUR_CNT__A, 2),
265 0x10, 0x00, /* FE_AG_REG_DCE_AUR_CNT__A */
266 0x10, 0x00, /* FE_AG_REG_DCE_RUR_CNT__A */
267
268 WRBLOCK(FE_AG_REG_ACE_AUR_CNT__A, 2),
269 0x0E, 0x00, /* FE_AG_REG_ACE_AUR_CNT__A */
270 0x00, 0x00, /* FE_AG_REG_ACE_RUR_CNT__A */
271
272 WRBLOCK(FE_AG_REG_EGC_FLA_RGN__A, 5),
273 0x04, 0x00, /* FE_AG_REG_EGC_FLA_RGN__A */
274 0x1F, 0x00, /* FE_AG_REG_EGC_SLO_RGN__A */
275 0x00, 0x00, /* FE_AG_REG_EGC_JMP_PSN__A */
276 0x00, 0x00, /* FE_AG_REG_EGC_FLA_INC__A */
277 0x00, 0x00, /* FE_AG_REG_EGC_FLA_DEC__A */
278
279 WRBLOCK(FE_AG_REG_GC1_AGC_MAX__A, 2),
280 0xFF, 0x01, /* FE_AG_REG_GC1_AGC_MAX__A */
281 0x00, 0xFE, /* FE_AG_REG_GC1_AGC_MIN__A */
282
283 WRBLOCK(FE_AG_REG_IND_WIN__A, 29),
284 0x00, 0x00, /* FE_AG_REG_IND_WIN__A */
285 0x05, 0x00, /* FE_AG_REG_IND_THD_LOL__A */
286 0x0F, 0x00, /* FE_AG_REG_IND_THD_HIL__A */
287 0x00, 0x00, /* FE_AG_REG_IND_DEL__A don't care */
288 0x1E, 0x00, /* FE_AG_REG_IND_PD1_WRI__A */
289 0x0C, 0x00, /* FE_AG_REG_PDA_AUR_CNT__A */
290 0x00, 0x00, /* FE_AG_REG_PDA_RUR_CNT__A */
291 0x00, 0x00, /* FE_AG_REG_PDA_AVE_DAT__A don't care */
292 0x00, 0x00, /* FE_AG_REG_PDC_RUR_CNT__A */
293 0x01, 0x00, /* FE_AG_REG_PDC_SET_LVL__A */
294 0x02, 0x00, /* FE_AG_REG_PDC_FLA_RGN__A */
295 0x00, 0x00, /* FE_AG_REG_PDC_JMP_PSN__A don't care */
296 0xFF, 0xFF, /* FE_AG_REG_PDC_FLA_STP__A */
297 0xFF, 0xFF, /* FE_AG_REG_PDC_SLO_STP__A */
298 0x00, 0x1F, /* FE_AG_REG_PDC_PD2_WRI__A don't care */
299 0x00, 0x00, /* FE_AG_REG_PDC_MAP_DAT__A don't care */
300 0x02, 0x00, /* FE_AG_REG_PDC_MAX__A */
301 0x0C, 0x00, /* FE_AG_REG_TGA_AUR_CNT__A */
302 0x00, 0x00, /* FE_AG_REG_TGA_RUR_CNT__A */
303 0x00, 0x00, /* FE_AG_REG_TGA_AVE_DAT__A don't care */
304 0x00, 0x00, /* FE_AG_REG_TGC_RUR_CNT__A */
305 0x22, 0x00, /* FE_AG_REG_TGC_SET_LVL__A */
306 0x15, 0x00, /* FE_AG_REG_TGC_FLA_RGN__A */
307 0x00, 0x00, /* FE_AG_REG_TGC_JMP_PSN__A don't care */
308 0x01, 0x00, /* FE_AG_REG_TGC_FLA_STP__A */
309 0x0A, 0x00, /* FE_AG_REG_TGC_SLO_STP__A */
310 0x00, 0x00, /* FE_AG_REG_TGC_MAP_DAT__A don't care */
311 0x10, 0x00, /* FE_AG_REG_FGA_AUR_CNT__A */
312 0x10, 0x00, /* FE_AG_REG_FGA_RUR_CNT__A */
313
314 WRBLOCK(FE_AG_REG_BGC_FGC_WRI__A, 2),
315 0x00, 0x00, /* FE_AG_REG_BGC_FGC_WRI__A */
316 0x00, 0x00, /* FE_AG_REG_BGC_CGC_WRI__A */
317
318 WRBLOCK(FE_FD_REG_SCL__A, 3),
319 0x05, 0x00, /* FE_FD_REG_SCL__A */
320 0x03, 0x00, /* FE_FD_REG_MAX_LEV__A */
321 0x05, 0x00, /* FE_FD_REG_NR__A */
322
323 WRBLOCK(FE_CF_REG_SCL__A, 5),
324 0x16, 0x00, /* FE_CF_REG_SCL__A */
325 0x04, 0x00, /* FE_CF_REG_MAX_LEV__A */
326 0x06, 0x00, /* FE_CF_REG_NR__A */
327 0x00, 0x00, /* FE_CF_REG_IMP_VAL__A */
328 0x01, 0x00, /* FE_CF_REG_MEAS_VAL__A */
329
330 WRBLOCK(FE_CU_REG_FRM_CNT_RST__A, 2),
331 0x00, 0x08, /* FE_CU_REG_FRM_CNT_RST__A */
332 0x00, 0x00, /* FE_CU_REG_FRM_CNT_STR__A */
333
334 END_OF_TABLE
335 };
336
337 /* with PGA */
338 /* WR16COND( DRXD_WITH_PGA, FE_AG_REG_AG_PGA_MODE__A , 0x0004), */
339 /* without PGA */
340 /* WR16COND( DRXD_WITHOUT_PGA, FE_AG_REG_AG_PGA_MODE__A , 0x0001), */
341 /* WR16(FE_AG_REG_AG_AGC_SIO__A, (extAttr -> FeAgRegAgAgcSio), 0x0000 );*/
342 /* WR16(FE_AG_REG_AG_PWD__A ,(extAttr -> FeAgRegAgPwd), 0x0000 );*/
343
344 u8 DRXD_InitFEA2_2[] = {
345 WR16(FE_AG_REG_CDR_RUR_CNT__A, 0x0010),
346 WR16(FE_AG_REG_FGM_WRI__A, 48),
347 /* Activate measurement, activate scale */
348 WR16(FE_FD_REG_MEAS_VAL__A, 0x0001),
349
350 WR16(FE_CU_REG_COMM_EXEC__A, 0x0001),
351 WR16(FE_CF_REG_COMM_EXEC__A, 0x0001),
352 WR16(FE_IF_REG_COMM_EXEC__A, 0x0001),
353 WR16(FE_FD_REG_COMM_EXEC__A, 0x0001),
354 WR16(FE_FS_REG_COMM_EXEC__A, 0x0001),
355 WR16(FE_AD_REG_COMM_EXEC__A, 0x0001),
356 WR16(FE_AG_REG_COMM_EXEC__A, 0x0001),
357 WR16(FE_AG_REG_AG_MODE_LOP__A, 0x895E),
358
359 END_OF_TABLE
360 };
361
362 u8 DRXD_InitFEB1_1[] = {
363 WR16(B_FE_AD_REG_PD__A, 0x0000),
364 WR16(B_FE_AD_REG_CLKNEG__A, 0x0000),
365 WR16(B_FE_AG_REG_BGC_FGC_WRI__A, 0x0000),
366 WR16(B_FE_AG_REG_BGC_CGC_WRI__A, 0x0000),
367 WR16(B_FE_AG_REG_AG_MODE_LOP__A, 0x000a),
368 WR16(B_FE_AG_REG_IND_PD1_WRI__A, 35),
369 WR16(B_FE_AG_REG_IND_WIN__A, 0),
370 WR16(B_FE_AG_REG_IND_THD_LOL__A, 8),
371 WR16(B_FE_AG_REG_IND_THD_HIL__A, 8),
372 WR16(B_FE_CF_REG_IMP_VAL__A, 1),
373 WR16(B_FE_AG_REG_EGC_FLA_RGN__A, 7),
374 END_OF_TABLE
375 };
376
377 /* with PGA */
378 /* WR16(B_FE_AG_REG_AG_PGA_MODE__A , 0x0000, 0x0000); */
379 /* without PGA */
380 /* WR16(B_FE_AG_REG_AG_PGA_MODE__A ,
381 B_FE_AG_REG_AG_PGA_MODE_PFN_PCN_AFY_REN, 0x0000);*/
382 /* WR16(B_FE_AG_REG_AG_AGC_SIO__A,(extAttr -> FeAgRegAgAgcSio), 0x0000 );*//*added HS 23-05-2005 */
383 /* WR16(B_FE_AG_REG_AG_PWD__A ,(extAttr -> FeAgRegAgPwd), 0x0000 );*/
384
385 u8 DRXD_InitFEB1_2[] = {
386 WR16(B_FE_COMM_EXEC__A, 0x0001),
387
388 /* RF-AGC setup */
389 WR16(B_FE_AG_REG_PDA_AUR_CNT__A, 0x0C),
390 WR16(B_FE_AG_REG_PDC_SET_LVL__A, 0x01),
391 WR16(B_FE_AG_REG_PDC_FLA_RGN__A, 0x02),
392 WR16(B_FE_AG_REG_PDC_FLA_STP__A, 0xFFFF),
393 WR16(B_FE_AG_REG_PDC_SLO_STP__A, 0xFFFF),
394 WR16(B_FE_AG_REG_PDC_MAX__A, 0x02),
395 WR16(B_FE_AG_REG_TGA_AUR_CNT__A, 0x0C),
396 WR16(B_FE_AG_REG_TGC_SET_LVL__A, 0x22),
397 WR16(B_FE_AG_REG_TGC_FLA_RGN__A, 0x15),
398 WR16(B_FE_AG_REG_TGC_FLA_STP__A, 0x01),
399 WR16(B_FE_AG_REG_TGC_SLO_STP__A, 0x0A),
400
401 WR16(B_FE_CU_REG_DIV_NFC_CLP__A, 0),
402 WR16(B_FE_CU_REG_CTR_NFC_OCR__A, 25000),
403 WR16(B_FE_CU_REG_CTR_NFC_ICR__A, 1),
404 END_OF_TABLE
405 };
406
407 u8 DRXD_InitCPA2[] = {
408 WRBLOCK(CP_REG_BR_SPL_OFFSET__A, 2),
409 0x07, 0x00, /* CP_REG_BR_SPL_OFFSET__A */
410 0x0A, 0x00, /* CP_REG_BR_STR_DEL__A */
411
412 WRBLOCK(CP_REG_RT_ANG_INC0__A, 4),
413 0x00, 0x00, /* CP_REG_RT_ANG_INC0__A */
414 0x00, 0x00, /* CP_REG_RT_ANG_INC1__A */
415 0x03, 0x00, /* CP_REG_RT_DETECT_ENA__A */
416 0x03, 0x00, /* CP_REG_RT_DETECT_TRH__A */
417
418 WRBLOCK(CP_REG_AC_NEXP_OFFS__A, 5),
419 0x32, 0x00, /* CP_REG_AC_NEXP_OFFS__A */
420 0x62, 0x00, /* CP_REG_AC_AVER_POW__A */
421 0x82, 0x00, /* CP_REG_AC_MAX_POW__A */
422 0x26, 0x00, /* CP_REG_AC_WEIGHT_MAN__A */
423 0x0F, 0x00, /* CP_REG_AC_WEIGHT_EXP__A */
424
425 WRBLOCK(CP_REG_AC_AMP_MODE__A, 2),
426 0x02, 0x00, /* CP_REG_AC_AMP_MODE__A */
427 0x01, 0x00, /* CP_REG_AC_AMP_FIX__A */
428
429 WR16(CP_REG_INTERVAL__A, 0x0005),
430 WR16(CP_REG_RT_EXP_MARG__A, 0x0004),
431 WR16(CP_REG_AC_ANG_MODE__A, 0x0003),
432
433 WR16(CP_REG_COMM_EXEC__A, 0x0001),
434 END_OF_TABLE
435 };
436
437 u8 DRXD_InitCPB1[] = {
438 WR16(B_CP_REG_BR_SPL_OFFSET__A, 0x0008),
439 WR16(B_CP_COMM_EXEC__A, 0x0001),
440 END_OF_TABLE
441 };
442
443 u8 DRXD_InitCEA2[] = {
444 WRBLOCK(CE_REG_AVG_POW__A, 4),
445 0x62, 0x00, /* CE_REG_AVG_POW__A */
446 0x78, 0x00, /* CE_REG_MAX_POW__A */
447 0x62, 0x00, /* CE_REG_ATT__A */
448 0x17, 0x00, /* CE_REG_NRED__A */
449
450 WRBLOCK(CE_REG_NE_ERR_SELECT__A, 2),
451 0x07, 0x00, /* CE_REG_NE_ERR_SELECT__A */
452 0xEB, 0xFF, /* CE_REG_NE_TD_CAL__A */
453
454 WRBLOCK(CE_REG_NE_MIXAVG__A, 2),
455 0x06, 0x00, /* CE_REG_NE_MIXAVG__A */
456 0x00, 0x00, /* CE_REG_NE_NUPD_OFS__A */
457
458 WRBLOCK(CE_REG_PE_NEXP_OFFS__A, 2),
459 0x00, 0x00, /* CE_REG_PE_NEXP_OFFS__A */
460 0x00, 0x00, /* CE_REG_PE_TIMESHIFT__A */
461
462 WRBLOCK(CE_REG_TP_A0_TAP_NEW__A, 3),
463 0x00, 0x01, /* CE_REG_TP_A0_TAP_NEW__A */
464 0x01, 0x00, /* CE_REG_TP_A0_TAP_NEW_VALID__A */
465 0x0E, 0x00, /* CE_REG_TP_A0_MU_LMS_STEP__A */
466
467 WRBLOCK(CE_REG_TP_A1_TAP_NEW__A, 3),
468 0x00, 0x00, /* CE_REG_TP_A1_TAP_NEW__A */
469 0x01, 0x00, /* CE_REG_TP_A1_TAP_NEW_VALID__A */
470 0x0A, 0x00, /* CE_REG_TP_A1_MU_LMS_STEP__A */
471
472 WRBLOCK(CE_REG_FI_SHT_INCR__A, 2),
473 0x12, 0x00, /* CE_REG_FI_SHT_INCR__A */
474 0x0C, 0x00, /* CE_REG_FI_EXP_NORM__A */
475
476 WRBLOCK(CE_REG_IR_INPUTSEL__A, 3),
477 0x00, 0x00, /* CE_REG_IR_INPUTSEL__A */
478 0x00, 0x00, /* CE_REG_IR_STARTPOS__A */
479 0xFF, 0x00, /* CE_REG_IR_NEXP_THRES__A */
480
481 WR16(CE_REG_TI_NEXP_OFFS__A, 0x0000),
482
483 END_OF_TABLE
484 };
485
486 u8 DRXD_InitCEB1[] = {
487 WR16(B_CE_REG_TI_PHN_ENABLE__A, 0x0001),
488 WR16(B_CE_REG_FR_PM_SET__A, 0x000D),
489
490 END_OF_TABLE
491 };
492
493 u8 DRXD_InitEQA2[] = {
494 WRBLOCK(EQ_REG_OT_QNT_THRES0__A, 4),
495 0x1E, 0x00, /* EQ_REG_OT_QNT_THRES0__A */
496 0x1F, 0x00, /* EQ_REG_OT_QNT_THRES1__A */
497 0x06, 0x00, /* EQ_REG_OT_CSI_STEP__A */
498 0x02, 0x00, /* EQ_REG_OT_CSI_OFFSET__A */
499
500 WR16(EQ_REG_TD_REQ_SMB_CNT__A, 0x0200),
501 WR16(EQ_REG_IS_CLIP_EXP__A, 0x001F),
502 WR16(EQ_REG_SN_OFFSET__A, (u16) (-7)),
503 WR16(EQ_REG_RC_SEL_CAR__A, 0x0002),
504 WR16(EQ_REG_COMM_EXEC__A, 0x0001),
505 END_OF_TABLE
506 };
507
508 u8 DRXD_InitEQB1[] = {
509 WR16(B_EQ_REG_COMM_EXEC__A, 0x0001),
510 END_OF_TABLE
511 };
512
513 u8 DRXD_ResetECRAM[] = {
514 /* Reset packet sync bytes in EC_VD ram */
515 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (0 * 17), 0x0000),
516 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (1 * 17), 0x0000),
517 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (2 * 17), 0x0000),
518 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (3 * 17), 0x0000),
519 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (4 * 17), 0x0000),
520 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (5 * 17), 0x0000),
521 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (6 * 17), 0x0000),
522 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (7 * 17), 0x0000),
523 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (8 * 17), 0x0000),
524 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (9 * 17), 0x0000),
525 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (10 * 17), 0x0000),
526
527 /* Reset packet sync bytes in EC_RS ram */
528 WR16(EC_RS_EC_RAM__A, 0x0000),
529 WR16(EC_RS_EC_RAM__A + 204, 0x0000),
530 END_OF_TABLE
531 };
532
533 u8 DRXD_InitECA2[] = {
534 WRBLOCK(EC_SB_REG_CSI_HI__A, 6),
535 0x1F, 0x00, /* EC_SB_REG_CSI_HI__A */
536 0x1E, 0x00, /* EC_SB_REG_CSI_LO__A */
537 0x01, 0x00, /* EC_SB_REG_SMB_TGL__A */
538 0x7F, 0x00, /* EC_SB_REG_SNR_HI__A */
539 0x7F, 0x00, /* EC_SB_REG_SNR_MID__A */
540 0x7F, 0x00, /* EC_SB_REG_SNR_LO__A */
541
542 WRBLOCK(EC_RS_REG_REQ_PCK_CNT__A, 2),
543 0x00, 0x10, /* EC_RS_REG_REQ_PCK_CNT__A */
544 DATA16(EC_RS_REG_VAL_PCK), /* EC_RS_REG_VAL__A */
545
546 WRBLOCK(EC_OC_REG_TMD_TOP_MODE__A, 5),
547 0x03, 0x00, /* EC_OC_REG_TMD_TOP_MODE__A */
548 0xF4, 0x01, /* EC_OC_REG_TMD_TOP_CNT__A */
549 0xC0, 0x03, /* EC_OC_REG_TMD_HIL_MAR__A */
550 0x40, 0x00, /* EC_OC_REG_TMD_LOL_MAR__A */
551 0x03, 0x00, /* EC_OC_REG_TMD_CUR_CNT__A */
552
553 WRBLOCK(EC_OC_REG_AVR_ASH_CNT__A, 2),
554 0x06, 0x00, /* EC_OC_REG_AVR_ASH_CNT__A */
555 0x02, 0x00, /* EC_OC_REG_AVR_BSH_CNT__A */
556
557 WRBLOCK(EC_OC_REG_RCN_MODE__A, 7),
558 0x07, 0x00, /* EC_OC_REG_RCN_MODE__A */
559 0x00, 0x00, /* EC_OC_REG_RCN_CRA_LOP__A */
560 0xc0, 0x00, /* EC_OC_REG_RCN_CRA_HIP__A */
561 0x00, 0x10, /* EC_OC_REG_RCN_CST_LOP__A */
562 0x00, 0x00, /* EC_OC_REG_RCN_CST_HIP__A */
563 0xFF, 0x01, /* EC_OC_REG_RCN_SET_LVL__A */
564 0x0D, 0x00, /* EC_OC_REG_RCN_GAI_LVL__A */
565
566 WRBLOCK(EC_OC_REG_RCN_CLP_LOP__A, 2),
567 0x00, 0x00, /* EC_OC_REG_RCN_CLP_LOP__A */
568 0xC0, 0x00, /* EC_OC_REG_RCN_CLP_HIP__A */
569
570 WR16(EC_SB_REG_CSI_OFS__A, 0x0001),
571 WR16(EC_VD_REG_FORCE__A, 0x0002),
572 WR16(EC_VD_REG_REQ_SMB_CNT__A, 0x0001),
573 WR16(EC_VD_REG_RLK_ENA__A, 0x0001),
574 WR16(EC_OD_REG_SYNC__A, 0x0664),
575 WR16(EC_OC_REG_OC_MON_SIO__A, 0x0000),
576 WR16(EC_OC_REG_SNC_ISC_LVL__A, 0x0D0C),
577 /* Output zero on monitorbus pads, power saving */
578 WR16(EC_OC_REG_OCR_MON_UOS__A,
579 (EC_OC_REG_OCR_MON_UOS_DAT_0_ENABLE |
580 EC_OC_REG_OCR_MON_UOS_DAT_1_ENABLE |
581 EC_OC_REG_OCR_MON_UOS_DAT_2_ENABLE |
582 EC_OC_REG_OCR_MON_UOS_DAT_3_ENABLE |
583 EC_OC_REG_OCR_MON_UOS_DAT_4_ENABLE |
584 EC_OC_REG_OCR_MON_UOS_DAT_5_ENABLE |
585 EC_OC_REG_OCR_MON_UOS_DAT_6_ENABLE |
586 EC_OC_REG_OCR_MON_UOS_DAT_7_ENABLE |
587 EC_OC_REG_OCR_MON_UOS_DAT_8_ENABLE |
588 EC_OC_REG_OCR_MON_UOS_DAT_9_ENABLE |
589 EC_OC_REG_OCR_MON_UOS_VAL_ENABLE |
590 EC_OC_REG_OCR_MON_UOS_CLK_ENABLE)),
591 WR16(EC_OC_REG_OCR_MON_WRI__A,
592 EC_OC_REG_OCR_MON_WRI_INIT),
593
594 /* CHK_ERROR(ResetECRAM(demod)); */
595 /* Reset packet sync bytes in EC_VD ram */
596 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (0 * 17), 0x0000),
597 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (1 * 17), 0x0000),
598 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (2 * 17), 0x0000),
599 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (3 * 17), 0x0000),
600 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (4 * 17), 0x0000),
601 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (5 * 17), 0x0000),
602 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (6 * 17), 0x0000),
603 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (7 * 17), 0x0000),
604 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (8 * 17), 0x0000),
605 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (9 * 17), 0x0000),
606 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (10 * 17), 0x0000),
607
608 /* Reset packet sync bytes in EC_RS ram */
609 WR16(EC_RS_EC_RAM__A, 0x0000),
610 WR16(EC_RS_EC_RAM__A + 204, 0x0000),
611
612 WR16(EC_SB_REG_COMM_EXEC__A, 0x0001),
613 WR16(EC_VD_REG_COMM_EXEC__A, 0x0001),
614 WR16(EC_OD_REG_COMM_EXEC__A, 0x0001),
615 WR16(EC_RS_REG_COMM_EXEC__A, 0x0001),
616 END_OF_TABLE
617 };
618
619 u8 DRXD_InitECB1[] = {
620 WR16(B_EC_SB_REG_CSI_OFS0__A, 0x0001),
621 WR16(B_EC_SB_REG_CSI_OFS1__A, 0x0001),
622 WR16(B_EC_SB_REG_CSI_OFS2__A, 0x0001),
623 WR16(B_EC_SB_REG_CSI_LO__A, 0x000c),
624 WR16(B_EC_SB_REG_CSI_HI__A, 0x0018),
625 WR16(B_EC_SB_REG_SNR_HI__A, 0x007f),
626 WR16(B_EC_SB_REG_SNR_MID__A, 0x007f),
627 WR16(B_EC_SB_REG_SNR_LO__A, 0x007f),
628
629 WR16(B_EC_OC_REG_DTO_CLKMODE__A, 0x0002),
630 WR16(B_EC_OC_REG_DTO_PER__A, 0x0006),
631 WR16(B_EC_OC_REG_DTO_BUR__A, 0x0001),
632 WR16(B_EC_OC_REG_RCR_CLKMODE__A, 0x0000),
633 WR16(B_EC_OC_REG_RCN_GAI_LVL__A, 0x000D),
634 WR16(B_EC_OC_REG_OC_MPG_SIO__A, 0x0000),
635
636 /* Needed because shadow registers do not have correct default value */
637 WR16(B_EC_OC_REG_RCN_CST_LOP__A, 0x1000),
638 WR16(B_EC_OC_REG_RCN_CST_HIP__A, 0x0000),
639 WR16(B_EC_OC_REG_RCN_CRA_LOP__A, 0x0000),
640 WR16(B_EC_OC_REG_RCN_CRA_HIP__A, 0x00C0),
641 WR16(B_EC_OC_REG_RCN_CLP_LOP__A, 0x0000),
642 WR16(B_EC_OC_REG_RCN_CLP_HIP__A, 0x00C0),
643 WR16(B_EC_OC_REG_DTO_INC_LOP__A, 0x0000),
644 WR16(B_EC_OC_REG_DTO_INC_HIP__A, 0x00C0),
645
646 WR16(B_EC_OD_REG_SYNC__A, 0x0664),
647 WR16(B_EC_RS_REG_REQ_PCK_CNT__A, 0x1000),
648
649 /* CHK_ERROR(ResetECRAM(demod)); */
650 /* Reset packet sync bytes in EC_VD ram */
651 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (0 * 17), 0x0000),
652 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (1 * 17), 0x0000),
653 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (2 * 17), 0x0000),
654 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (3 * 17), 0x0000),
655 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (4 * 17), 0x0000),
656 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (5 * 17), 0x0000),
657 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (6 * 17), 0x0000),
658 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (7 * 17), 0x0000),
659 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (8 * 17), 0x0000),
660 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (9 * 17), 0x0000),
661 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (10 * 17), 0x0000),
662
663 /* Reset packet sync bytes in EC_RS ram */
664 WR16(EC_RS_EC_RAM__A, 0x0000),
665 WR16(EC_RS_EC_RAM__A + 204, 0x0000),
666
667 WR16(B_EC_SB_REG_COMM_EXEC__A, 0x0001),
668 WR16(B_EC_VD_REG_COMM_EXEC__A, 0x0001),
669 WR16(B_EC_OD_REG_COMM_EXEC__A, 0x0001),
670 WR16(B_EC_RS_REG_COMM_EXEC__A, 0x0001),
671 END_OF_TABLE
672 };
673
674 u8 DRXD_ResetECA2[] = {
675
676 WR16(EC_OC_REG_COMM_EXEC__A, 0x0000),
677 WR16(EC_OD_REG_COMM_EXEC__A, 0x0000),
678
679 WRBLOCK(EC_OC_REG_TMD_TOP_MODE__A, 5),
680 0x03, 0x00, /* EC_OC_REG_TMD_TOP_MODE__A */
681 0xF4, 0x01, /* EC_OC_REG_TMD_TOP_CNT__A */
682 0xC0, 0x03, /* EC_OC_REG_TMD_HIL_MAR__A */
683 0x40, 0x00, /* EC_OC_REG_TMD_LOL_MAR__A */
684 0x03, 0x00, /* EC_OC_REG_TMD_CUR_CNT__A */
685
686 WRBLOCK(EC_OC_REG_AVR_ASH_CNT__A, 2),
687 0x06, 0x00, /* EC_OC_REG_AVR_ASH_CNT__A */
688 0x02, 0x00, /* EC_OC_REG_AVR_BSH_CNT__A */
689
690 WRBLOCK(EC_OC_REG_RCN_MODE__A, 7),
691 0x07, 0x00, /* EC_OC_REG_RCN_MODE__A */
692 0x00, 0x00, /* EC_OC_REG_RCN_CRA_LOP__A */
693 0xc0, 0x00, /* EC_OC_REG_RCN_CRA_HIP__A */
694 0x00, 0x10, /* EC_OC_REG_RCN_CST_LOP__A */
695 0x00, 0x00, /* EC_OC_REG_RCN_CST_HIP__A */
696 0xFF, 0x01, /* EC_OC_REG_RCN_SET_LVL__A */
697 0x0D, 0x00, /* EC_OC_REG_RCN_GAI_LVL__A */
698
699 WRBLOCK(EC_OC_REG_RCN_CLP_LOP__A, 2),
700 0x00, 0x00, /* EC_OC_REG_RCN_CLP_LOP__A */
701 0xC0, 0x00, /* EC_OC_REG_RCN_CLP_HIP__A */
702
703 WR16(EC_OD_REG_SYNC__A, 0x0664),
704 WR16(EC_OC_REG_OC_MON_SIO__A, 0x0000),
705 WR16(EC_OC_REG_SNC_ISC_LVL__A, 0x0D0C),
706 /* Output zero on monitorbus pads, power saving */
707 WR16(EC_OC_REG_OCR_MON_UOS__A,
708 (EC_OC_REG_OCR_MON_UOS_DAT_0_ENABLE |
709 EC_OC_REG_OCR_MON_UOS_DAT_1_ENABLE |
710 EC_OC_REG_OCR_MON_UOS_DAT_2_ENABLE |
711 EC_OC_REG_OCR_MON_UOS_DAT_3_ENABLE |
712 EC_OC_REG_OCR_MON_UOS_DAT_4_ENABLE |
713 EC_OC_REG_OCR_MON_UOS_DAT_5_ENABLE |
714 EC_OC_REG_OCR_MON_UOS_DAT_6_ENABLE |
715 EC_OC_REG_OCR_MON_UOS_DAT_7_ENABLE |
716 EC_OC_REG_OCR_MON_UOS_DAT_8_ENABLE |
717 EC_OC_REG_OCR_MON_UOS_DAT_9_ENABLE |
718 EC_OC_REG_OCR_MON_UOS_VAL_ENABLE |
719 EC_OC_REG_OCR_MON_UOS_CLK_ENABLE)),
720 WR16(EC_OC_REG_OCR_MON_WRI__A,
721 EC_OC_REG_OCR_MON_WRI_INIT),
722
723 /* CHK_ERROR(ResetECRAM(demod)); */
724 /* Reset packet sync bytes in EC_VD ram */
725 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (0 * 17), 0x0000),
726 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (1 * 17), 0x0000),
727 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (2 * 17), 0x0000),
728 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (3 * 17), 0x0000),
729 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (4 * 17), 0x0000),
730 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (5 * 17), 0x0000),
731 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (6 * 17), 0x0000),
732 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (7 * 17), 0x0000),
733 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (8 * 17), 0x0000),
734 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (9 * 17), 0x0000),
735 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (10 * 17), 0x0000),
736
737 /* Reset packet sync bytes in EC_RS ram */
738 WR16(EC_RS_EC_RAM__A, 0x0000),
739 WR16(EC_RS_EC_RAM__A + 204, 0x0000),
740
741 WR16(EC_OD_REG_COMM_EXEC__A, 0x0001),
742 END_OF_TABLE
743 };
744
745 u8 DRXD_InitSC[] = {
746 WR16(SC_COMM_EXEC__A, 0),
747 WR16(SC_COMM_STATE__A, 0),
748
749 #ifdef COMPILE_FOR_QT
750 WR16(SC_RA_RAM_BE_OPT_DELAY__A, 0x100),
751 #endif
752
753 /* SC is not started, this is done in SetChannels() */
754 END_OF_TABLE
755 };
756
757 /* Diversity settings */
758
759 u8 DRXD_InitDiversityFront[] = {
760 /* Start demod ********* RF in , diversity out **************************** */
761 WR16(B_SC_RA_RAM_CONFIG__A, B_SC_RA_RAM_CONFIG_FR_ENABLE__M |
762 B_SC_RA_RAM_CONFIG_FREQSCAN__M),
763
764 WR16(B_SC_RA_RAM_LC_ABS_2K__A, 0x7),
765 WR16(B_SC_RA_RAM_LC_ABS_8K__A, 0x7),
766 WR16(B_SC_RA_RAM_IR_COARSE_8K_LENGTH__A, IRLEN_COARSE_8K),
767 WR16(B_SC_RA_RAM_IR_COARSE_8K_FREQINC__A, 1 << (11 - IRLEN_COARSE_8K)),
768 WR16(B_SC_RA_RAM_IR_COARSE_8K_KAISINC__A, 1 << (17 - IRLEN_COARSE_8K)),
769 WR16(B_SC_RA_RAM_IR_FINE_8K_LENGTH__A, IRLEN_FINE_8K),
770 WR16(B_SC_RA_RAM_IR_FINE_8K_FREQINC__A, 1 << (11 - IRLEN_FINE_8K)),
771 WR16(B_SC_RA_RAM_IR_FINE_8K_KAISINC__A, 1 << (17 - IRLEN_FINE_8K)),
772
773 WR16(B_SC_RA_RAM_IR_COARSE_2K_LENGTH__A, IRLEN_COARSE_2K),
774 WR16(B_SC_RA_RAM_IR_COARSE_2K_FREQINC__A, 1 << (11 - IRLEN_COARSE_2K)),
775 WR16(B_SC_RA_RAM_IR_COARSE_2K_KAISINC__A, 1 << (17 - IRLEN_COARSE_2K)),
776 WR16(B_SC_RA_RAM_IR_FINE_2K_LENGTH__A, IRLEN_FINE_2K),
777 WR16(B_SC_RA_RAM_IR_FINE_2K_FREQINC__A, 1 << (11 - IRLEN_FINE_2K)),
778 WR16(B_SC_RA_RAM_IR_FINE_2K_KAISINC__A, 1 << (17 - IRLEN_FINE_2K)),
779
780 WR16(B_LC_RA_RAM_FILTER_CRMM_A__A, 7),
781 WR16(B_LC_RA_RAM_FILTER_CRMM_B__A, 4),
782 WR16(B_LC_RA_RAM_FILTER_SRMM_A__A, 7),
783 WR16(B_LC_RA_RAM_FILTER_SRMM_B__A, 4),
784 WR16(B_LC_RA_RAM_FILTER_SYM_SET__A, 500),
785
786 WR16(B_CC_REG_DIVERSITY__A, 0x0001),
787 WR16(B_EC_OC_REG_OC_MODE_HIP__A, 0x0010),
788 WR16(B_EQ_REG_RC_SEL_CAR__A, B_EQ_REG_RC_SEL_CAR_PASS_B_CE |
789 B_EQ_REG_RC_SEL_CAR_LOCAL_B_CE | B_EQ_REG_RC_SEL_CAR_MEAS_B_CE),
790
791 /* 0x2a ), *//* CE to PASS mux */
792
793 END_OF_TABLE
794 };
795
796 u8 DRXD_InitDiversityEnd[] = {
797 /* End demod *********** combining RF in and diversity in, MPEG TS out **** */
798 /* disable near/far; switch on timing slave mode */
799 WR16(B_SC_RA_RAM_CONFIG__A, B_SC_RA_RAM_CONFIG_FR_ENABLE__M |
800 B_SC_RA_RAM_CONFIG_FREQSCAN__M |
801 B_SC_RA_RAM_CONFIG_DIV_ECHO_ENABLE__M |
802 B_SC_RA_RAM_CONFIG_SLAVE__M |
803 B_SC_RA_RAM_CONFIG_DIV_BLANK_ENABLE__M
804 /* MV from CtrlDiversity */
805 ),
806 #ifdef DRXDDIV_SRMM_SLAVING
807 WR16(SC_RA_RAM_LC_ABS_2K__A, 0x3c7),
808 WR16(SC_RA_RAM_LC_ABS_8K__A, 0x3c7),
809 #else
810 WR16(SC_RA_RAM_LC_ABS_2K__A, 0x7),
811 WR16(SC_RA_RAM_LC_ABS_8K__A, 0x7),
812 #endif
813
814 WR16(B_SC_RA_RAM_IR_COARSE_8K_LENGTH__A, IRLEN_COARSE_8K),
815 WR16(B_SC_RA_RAM_IR_COARSE_8K_FREQINC__A, 1 << (11 - IRLEN_COARSE_8K)),
816 WR16(B_SC_RA_RAM_IR_COARSE_8K_KAISINC__A, 1 << (17 - IRLEN_COARSE_8K)),
817 WR16(B_SC_RA_RAM_IR_FINE_8K_LENGTH__A, IRLEN_FINE_8K),
818 WR16(B_SC_RA_RAM_IR_FINE_8K_FREQINC__A, 1 << (11 - IRLEN_FINE_8K)),
819 WR16(B_SC_RA_RAM_IR_FINE_8K_KAISINC__A, 1 << (17 - IRLEN_FINE_8K)),
820
821 WR16(B_SC_RA_RAM_IR_COARSE_2K_LENGTH__A, IRLEN_COARSE_2K),
822 WR16(B_SC_RA_RAM_IR_COARSE_2K_FREQINC__A, 1 << (11 - IRLEN_COARSE_2K)),
823 WR16(B_SC_RA_RAM_IR_COARSE_2K_KAISINC__A, 1 << (17 - IRLEN_COARSE_2K)),
824 WR16(B_SC_RA_RAM_IR_FINE_2K_LENGTH__A, IRLEN_FINE_2K),
825 WR16(B_SC_RA_RAM_IR_FINE_2K_FREQINC__A, 1 << (11 - IRLEN_FINE_2K)),
826 WR16(B_SC_RA_RAM_IR_FINE_2K_KAISINC__A, 1 << (17 - IRLEN_FINE_2K)),
827
828 WR16(B_LC_RA_RAM_FILTER_CRMM_A__A, 7),
829 WR16(B_LC_RA_RAM_FILTER_CRMM_B__A, 4),
830 WR16(B_LC_RA_RAM_FILTER_SRMM_A__A, 7),
831 WR16(B_LC_RA_RAM_FILTER_SRMM_B__A, 4),
832 WR16(B_LC_RA_RAM_FILTER_SYM_SET__A, 500),
833
834 WR16(B_CC_REG_DIVERSITY__A, 0x0001),
835 END_OF_TABLE
836 };
837
838 u8 DRXD_DisableDiversity[] = {
839 WR16(B_SC_RA_RAM_LC_ABS_2K__A, B_SC_RA_RAM_LC_ABS_2K__PRE),
840 WR16(B_SC_RA_RAM_LC_ABS_8K__A, B_SC_RA_RAM_LC_ABS_8K__PRE),
841 WR16(B_SC_RA_RAM_IR_COARSE_8K_LENGTH__A,
842 B_SC_RA_RAM_IR_COARSE_8K_LENGTH__PRE),
843 WR16(B_SC_RA_RAM_IR_COARSE_8K_FREQINC__A,
844 B_SC_RA_RAM_IR_COARSE_8K_FREQINC__PRE),
845 WR16(B_SC_RA_RAM_IR_COARSE_8K_KAISINC__A,
846 B_SC_RA_RAM_IR_COARSE_8K_KAISINC__PRE),
847 WR16(B_SC_RA_RAM_IR_FINE_8K_LENGTH__A,
848 B_SC_RA_RAM_IR_FINE_8K_LENGTH__PRE),
849 WR16(B_SC_RA_RAM_IR_FINE_8K_FREQINC__A,
850 B_SC_RA_RAM_IR_FINE_8K_FREQINC__PRE),
851 WR16(B_SC_RA_RAM_IR_FINE_8K_KAISINC__A,
852 B_SC_RA_RAM_IR_FINE_8K_KAISINC__PRE),
853
854 WR16(B_SC_RA_RAM_IR_COARSE_2K_LENGTH__A,
855 B_SC_RA_RAM_IR_COARSE_2K_LENGTH__PRE),
856 WR16(B_SC_RA_RAM_IR_COARSE_2K_FREQINC__A,
857 B_SC_RA_RAM_IR_COARSE_2K_FREQINC__PRE),
858 WR16(B_SC_RA_RAM_IR_COARSE_2K_KAISINC__A,
859 B_SC_RA_RAM_IR_COARSE_2K_KAISINC__PRE),
860 WR16(B_SC_RA_RAM_IR_FINE_2K_LENGTH__A,
861 B_SC_RA_RAM_IR_FINE_2K_LENGTH__PRE),
862 WR16(B_SC_RA_RAM_IR_FINE_2K_FREQINC__A,
863 B_SC_RA_RAM_IR_FINE_2K_FREQINC__PRE),
864 WR16(B_SC_RA_RAM_IR_FINE_2K_KAISINC__A,
865 B_SC_RA_RAM_IR_FINE_2K_KAISINC__PRE),
866
867 WR16(B_LC_RA_RAM_FILTER_CRMM_A__A, B_LC_RA_RAM_FILTER_CRMM_A__PRE),
868 WR16(B_LC_RA_RAM_FILTER_CRMM_B__A, B_LC_RA_RAM_FILTER_CRMM_B__PRE),
869 WR16(B_LC_RA_RAM_FILTER_SRMM_A__A, B_LC_RA_RAM_FILTER_SRMM_A__PRE),
870 WR16(B_LC_RA_RAM_FILTER_SRMM_B__A, B_LC_RA_RAM_FILTER_SRMM_B__PRE),
871 WR16(B_LC_RA_RAM_FILTER_SYM_SET__A, B_LC_RA_RAM_FILTER_SYM_SET__PRE),
872
873 WR16(B_CC_REG_DIVERSITY__A, 0x0000),
874 WR16(B_EQ_REG_RC_SEL_CAR__A, B_EQ_REG_RC_SEL_CAR_INIT), /* combining disabled */
875
876 END_OF_TABLE
877 };
878
879 u8 DRXD_StartDiversityFront[] = {
880 /* Start demod, RF in and diversity out, no combining */
881 WR16(B_FE_CF_REG_IMP_VAL__A, 0x0),
882 WR16(B_FE_AD_REG_FDB_IN__A, 0x0),
883 WR16(B_FE_AD_REG_INVEXT__A, 0x0),
884 WR16(B_EQ_REG_COMM_MB__A, 0x12), /* EQ to MB out */
885 WR16(B_EQ_REG_RC_SEL_CAR__A, B_EQ_REG_RC_SEL_CAR_PASS_B_CE | /* CE to PASS mux */
886 B_EQ_REG_RC_SEL_CAR_LOCAL_B_CE | B_EQ_REG_RC_SEL_CAR_MEAS_B_CE),
887
888 WR16(SC_RA_RAM_ECHO_SHIFT_LIM__A, 2),
889
890 END_OF_TABLE
891 };
892
893 u8 DRXD_StartDiversityEnd[] = {
894 /* End demod, combining RF in and diversity in, MPEG TS out */
895 WR16(B_FE_CF_REG_IMP_VAL__A, 0x0), /* disable impulse noise cruncher */
896 WR16(B_FE_AD_REG_INVEXT__A, 0x0), /* clock inversion (for sohard board) */
897 WR16(B_CP_REG_BR_STR_DEL__A, 10), /* apperently no mb delay matching is best */
898
899 WR16(B_EQ_REG_RC_SEL_CAR__A, B_EQ_REG_RC_SEL_CAR_DIV_ON | /* org = 0x81 combining enabled */
900 B_EQ_REG_RC_SEL_CAR_MEAS_A_CC |
901 B_EQ_REG_RC_SEL_CAR_PASS_A_CC | B_EQ_REG_RC_SEL_CAR_LOCAL_A_CC),
902
903 END_OF_TABLE
904 };
905
906 u8 DRXD_DiversityDelay8MHZ[] = {
907 WR16(B_SC_RA_RAM_DIVERSITY_DELAY_2K_32__A, 1150 - 50),
908 WR16(B_SC_RA_RAM_DIVERSITY_DELAY_2K_16__A, 1100 - 50),
909 WR16(B_SC_RA_RAM_DIVERSITY_DELAY_2K_8__A, 1000 - 50),
910 WR16(B_SC_RA_RAM_DIVERSITY_DELAY_2K_4__A, 800 - 50),
911 WR16(B_SC_RA_RAM_DIVERSITY_DELAY_8K_32__A, 5420 - 50),
912 WR16(B_SC_RA_RAM_DIVERSITY_DELAY_8K_16__A, 5200 - 50),
913 WR16(B_SC_RA_RAM_DIVERSITY_DELAY_8K_8__A, 4800 - 50),
914 WR16(B_SC_RA_RAM_DIVERSITY_DELAY_8K_4__A, 4000 - 50),
915 END_OF_TABLE
916 };
917
918 u8 DRXD_DiversityDelay6MHZ[] = /* also used ok for 7 MHz */
919 {
920 WR16(B_SC_RA_RAM_DIVERSITY_DELAY_2K_32__A, 1100 - 50),
921 WR16(B_SC_RA_RAM_DIVERSITY_DELAY_2K_16__A, 1000 - 50),
922 WR16(B_SC_RA_RAM_DIVERSITY_DELAY_2K_8__A, 900 - 50),
923 WR16(B_SC_RA_RAM_DIVERSITY_DELAY_2K_4__A, 600 - 50),
924 WR16(B_SC_RA_RAM_DIVERSITY_DELAY_8K_32__A, 5300 - 50),
925 WR16(B_SC_RA_RAM_DIVERSITY_DELAY_8K_16__A, 5000 - 50),
926 WR16(B_SC_RA_RAM_DIVERSITY_DELAY_8K_8__A, 4500 - 50),
927 WR16(B_SC_RA_RAM_DIVERSITY_DELAY_8K_4__A, 3500 - 50),
928 END_OF_TABLE
929 };
Linux with added FPC-III support