2 * adv7604 - Analog Devices ADV7604 video decoder driver
4 * Copyright 2012 Cisco Systems, Inc. and/or its affiliates. All rights reserved.
6 * This program is free software; you may redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
10 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
11 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
12 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
13 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
14 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
15 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
16 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
22 * References (c = chapter, p = page):
23 * REF_01 - Analog devices, ADV7604, Register Settings Recommendations,
24 * Revision 2.5, June 2010
25 * REF_02 - Analog devices, Register map documentation, Documentation of
26 * the register maps, Software manual, Rev. F, June 2010
27 * REF_03 - Analog devices, ADV7604, Hardware Manual, Rev. F, August 2010
30 #include <linux/delay.h>
31 #include <linux/gpio/consumer.h>
32 #include <linux/i2c.h>
33 #include <linux/kernel.h>
34 #include <linux/module.h>
35 #include <linux/slab.h>
36 #include <linux/v4l2-dv-timings.h>
37 #include <linux/videodev2.h>
38 #include <linux/workqueue.h>
40 #include <media/adv7604.h>
41 #include <media/v4l2-ctrls.h>
42 #include <media/v4l2-device.h>
43 #include <media/v4l2-dv-timings.h>
44 #include <media/v4l2-of.h>
47 module_param(debug
, int, 0644);
48 MODULE_PARM_DESC(debug
, "debug level (0-2)");
50 MODULE_DESCRIPTION("Analog Devices ADV7604 video decoder driver");
51 MODULE_AUTHOR("Hans Verkuil <hans.verkuil@cisco.com>");
52 MODULE_AUTHOR("Mats Randgaard <mats.randgaard@cisco.com>");
53 MODULE_LICENSE("GPL");
55 /* ADV7604 system clock frequency */
56 #define ADV7604_fsc (28636360)
58 #define ADV7604_RGB_OUT (1 << 1)
60 #define ADV7604_OP_FORMAT_SEL_8BIT (0 << 0)
61 #define ADV7604_OP_FORMAT_SEL_10BIT (1 << 0)
62 #define ADV7604_OP_FORMAT_SEL_12BIT (2 << 0)
64 #define ADV7604_OP_MODE_SEL_SDR_422 (0 << 5)
65 #define ADV7604_OP_MODE_SEL_DDR_422 (1 << 5)
66 #define ADV7604_OP_MODE_SEL_SDR_444 (2 << 5)
67 #define ADV7604_OP_MODE_SEL_DDR_444 (3 << 5)
68 #define ADV7604_OP_MODE_SEL_SDR_422_2X (4 << 5)
69 #define ADV7604_OP_MODE_SEL_ADI_CM (5 << 5)
71 #define ADV7604_OP_CH_SEL_GBR (0 << 5)
72 #define ADV7604_OP_CH_SEL_GRB (1 << 5)
73 #define ADV7604_OP_CH_SEL_BGR (2 << 5)
74 #define ADV7604_OP_CH_SEL_RGB (3 << 5)
75 #define ADV7604_OP_CH_SEL_BRG (4 << 5)
76 #define ADV7604_OP_CH_SEL_RBG (5 << 5)
78 #define ADV7604_OP_SWAP_CB_CR (1 << 0)
85 struct adv7604_reg_seq
{
90 struct adv7604_format_info
{
91 enum v4l2_mbus_pixelcode code
;
98 struct adv7604_chip_info
{
99 enum adv7604_type type
;
102 unsigned int max_port
;
103 unsigned int num_dv_ports
;
105 unsigned int edid_enable_reg
;
106 unsigned int edid_status_reg
;
107 unsigned int lcf_reg
;
109 unsigned int cable_det_mask
;
110 unsigned int tdms_lock_mask
;
111 unsigned int fmt_change_digital_mask
;
113 const struct adv7604_format_info
*formats
;
114 unsigned int nformats
;
116 void (*set_termination
)(struct v4l2_subdev
*sd
, bool enable
);
117 void (*setup_irqs
)(struct v4l2_subdev
*sd
);
118 unsigned int (*read_hdmi_pixelclock
)(struct v4l2_subdev
*sd
);
119 unsigned int (*read_cable_det
)(struct v4l2_subdev
*sd
);
121 /* 0 = AFE, 1 = HDMI */
122 const struct adv7604_reg_seq
*recommended_settings
[2];
123 unsigned int num_recommended_settings
[2];
125 unsigned long page_mask
;
129 **********************************************************************
131 * Arrays with configuration parameters for the ADV7604
133 **********************************************************************
136 struct adv7604_state
{
137 const struct adv7604_chip_info
*info
;
138 struct adv7604_platform_data pdata
;
140 struct gpio_desc
*hpd_gpio
[4];
142 struct v4l2_subdev sd
;
143 struct media_pad pads
[ADV7604_PAD_MAX
];
144 unsigned int source_pad
;
146 struct v4l2_ctrl_handler hdl
;
148 enum adv7604_pad selected_input
;
150 struct v4l2_dv_timings timings
;
151 const struct adv7604_format_info
*format
;
159 struct v4l2_fract aspect_ratio
;
160 u32 rgb_quantization_range
;
161 struct workqueue_struct
*work_queues
;
162 struct delayed_work delayed_work_enable_hotplug
;
163 bool restart_stdi_once
;
166 struct i2c_client
*i2c_clients
[ADV7604_PAGE_MAX
];
169 struct v4l2_ctrl
*detect_tx_5v_ctrl
;
170 struct v4l2_ctrl
*analog_sampling_phase_ctrl
;
171 struct v4l2_ctrl
*free_run_color_manual_ctrl
;
172 struct v4l2_ctrl
*free_run_color_ctrl
;
173 struct v4l2_ctrl
*rgb_quantization_range_ctrl
;
176 static bool adv7604_has_afe(struct adv7604_state
*state
)
178 return state
->info
->has_afe
;
181 /* Supported CEA and DMT timings */
182 static const struct v4l2_dv_timings adv7604_timings
[] = {
183 V4L2_DV_BT_CEA_720X480P59_94
,
184 V4L2_DV_BT_CEA_720X576P50
,
185 V4L2_DV_BT_CEA_1280X720P24
,
186 V4L2_DV_BT_CEA_1280X720P25
,
187 V4L2_DV_BT_CEA_1280X720P50
,
188 V4L2_DV_BT_CEA_1280X720P60
,
189 V4L2_DV_BT_CEA_1920X1080P24
,
190 V4L2_DV_BT_CEA_1920X1080P25
,
191 V4L2_DV_BT_CEA_1920X1080P30
,
192 V4L2_DV_BT_CEA_1920X1080P50
,
193 V4L2_DV_BT_CEA_1920X1080P60
,
195 /* sorted by DMT ID */
196 V4L2_DV_BT_DMT_640X350P85
,
197 V4L2_DV_BT_DMT_640X400P85
,
198 V4L2_DV_BT_DMT_720X400P85
,
199 V4L2_DV_BT_DMT_640X480P60
,
200 V4L2_DV_BT_DMT_640X480P72
,
201 V4L2_DV_BT_DMT_640X480P75
,
202 V4L2_DV_BT_DMT_640X480P85
,
203 V4L2_DV_BT_DMT_800X600P56
,
204 V4L2_DV_BT_DMT_800X600P60
,
205 V4L2_DV_BT_DMT_800X600P72
,
206 V4L2_DV_BT_DMT_800X600P75
,
207 V4L2_DV_BT_DMT_800X600P85
,
208 V4L2_DV_BT_DMT_848X480P60
,
209 V4L2_DV_BT_DMT_1024X768P60
,
210 V4L2_DV_BT_DMT_1024X768P70
,
211 V4L2_DV_BT_DMT_1024X768P75
,
212 V4L2_DV_BT_DMT_1024X768P85
,
213 V4L2_DV_BT_DMT_1152X864P75
,
214 V4L2_DV_BT_DMT_1280X768P60_RB
,
215 V4L2_DV_BT_DMT_1280X768P60
,
216 V4L2_DV_BT_DMT_1280X768P75
,
217 V4L2_DV_BT_DMT_1280X768P85
,
218 V4L2_DV_BT_DMT_1280X800P60_RB
,
219 V4L2_DV_BT_DMT_1280X800P60
,
220 V4L2_DV_BT_DMT_1280X800P75
,
221 V4L2_DV_BT_DMT_1280X800P85
,
222 V4L2_DV_BT_DMT_1280X960P60
,
223 V4L2_DV_BT_DMT_1280X960P85
,
224 V4L2_DV_BT_DMT_1280X1024P60
,
225 V4L2_DV_BT_DMT_1280X1024P75
,
226 V4L2_DV_BT_DMT_1280X1024P85
,
227 V4L2_DV_BT_DMT_1360X768P60
,
228 V4L2_DV_BT_DMT_1400X1050P60_RB
,
229 V4L2_DV_BT_DMT_1400X1050P60
,
230 V4L2_DV_BT_DMT_1400X1050P75
,
231 V4L2_DV_BT_DMT_1400X1050P85
,
232 V4L2_DV_BT_DMT_1440X900P60_RB
,
233 V4L2_DV_BT_DMT_1440X900P60
,
234 V4L2_DV_BT_DMT_1600X1200P60
,
235 V4L2_DV_BT_DMT_1680X1050P60_RB
,
236 V4L2_DV_BT_DMT_1680X1050P60
,
237 V4L2_DV_BT_DMT_1792X1344P60
,
238 V4L2_DV_BT_DMT_1856X1392P60
,
239 V4L2_DV_BT_DMT_1920X1200P60_RB
,
240 V4L2_DV_BT_DMT_1366X768P60_RB
,
241 V4L2_DV_BT_DMT_1366X768P60
,
242 V4L2_DV_BT_DMT_1920X1080P60
,
246 struct adv7604_video_standards
{
247 struct v4l2_dv_timings timings
;
252 /* sorted by number of lines */
253 static const struct adv7604_video_standards adv7604_prim_mode_comp
[] = {
254 /* { V4L2_DV_BT_CEA_720X480P59_94, 0x0a, 0x00 }, TODO flickering */
255 { V4L2_DV_BT_CEA_720X576P50
, 0x0b, 0x00 },
256 { V4L2_DV_BT_CEA_1280X720P50
, 0x19, 0x01 },
257 { V4L2_DV_BT_CEA_1280X720P60
, 0x19, 0x00 },
258 { V4L2_DV_BT_CEA_1920X1080P24
, 0x1e, 0x04 },
259 { V4L2_DV_BT_CEA_1920X1080P25
, 0x1e, 0x03 },
260 { V4L2_DV_BT_CEA_1920X1080P30
, 0x1e, 0x02 },
261 { V4L2_DV_BT_CEA_1920X1080P50
, 0x1e, 0x01 },
262 { V4L2_DV_BT_CEA_1920X1080P60
, 0x1e, 0x00 },
263 /* TODO add 1920x1080P60_RB (CVT timing) */
267 /* sorted by number of lines */
268 static const struct adv7604_video_standards adv7604_prim_mode_gr
[] = {
269 { V4L2_DV_BT_DMT_640X480P60
, 0x08, 0x00 },
270 { V4L2_DV_BT_DMT_640X480P72
, 0x09, 0x00 },
271 { V4L2_DV_BT_DMT_640X480P75
, 0x0a, 0x00 },
272 { V4L2_DV_BT_DMT_640X480P85
, 0x0b, 0x00 },
273 { V4L2_DV_BT_DMT_800X600P56
, 0x00, 0x00 },
274 { V4L2_DV_BT_DMT_800X600P60
, 0x01, 0x00 },
275 { V4L2_DV_BT_DMT_800X600P72
, 0x02, 0x00 },
276 { V4L2_DV_BT_DMT_800X600P75
, 0x03, 0x00 },
277 { V4L2_DV_BT_DMT_800X600P85
, 0x04, 0x00 },
278 { V4L2_DV_BT_DMT_1024X768P60
, 0x0c, 0x00 },
279 { V4L2_DV_BT_DMT_1024X768P70
, 0x0d, 0x00 },
280 { V4L2_DV_BT_DMT_1024X768P75
, 0x0e, 0x00 },
281 { V4L2_DV_BT_DMT_1024X768P85
, 0x0f, 0x00 },
282 { V4L2_DV_BT_DMT_1280X1024P60
, 0x05, 0x00 },
283 { V4L2_DV_BT_DMT_1280X1024P75
, 0x06, 0x00 },
284 { V4L2_DV_BT_DMT_1360X768P60
, 0x12, 0x00 },
285 { V4L2_DV_BT_DMT_1366X768P60
, 0x13, 0x00 },
286 { V4L2_DV_BT_DMT_1400X1050P60
, 0x14, 0x00 },
287 { V4L2_DV_BT_DMT_1400X1050P75
, 0x15, 0x00 },
288 { V4L2_DV_BT_DMT_1600X1200P60
, 0x16, 0x00 }, /* TODO not tested */
289 /* TODO add 1600X1200P60_RB (not a DMT timing) */
290 { V4L2_DV_BT_DMT_1680X1050P60
, 0x18, 0x00 },
291 { V4L2_DV_BT_DMT_1920X1200P60_RB
, 0x19, 0x00 }, /* TODO not tested */
295 /* sorted by number of lines */
296 static const struct adv7604_video_standards adv7604_prim_mode_hdmi_comp
[] = {
297 { V4L2_DV_BT_CEA_720X480P59_94
, 0x0a, 0x00 },
298 { V4L2_DV_BT_CEA_720X576P50
, 0x0b, 0x00 },
299 { V4L2_DV_BT_CEA_1280X720P50
, 0x13, 0x01 },
300 { V4L2_DV_BT_CEA_1280X720P60
, 0x13, 0x00 },
301 { V4L2_DV_BT_CEA_1920X1080P24
, 0x1e, 0x04 },
302 { V4L2_DV_BT_CEA_1920X1080P25
, 0x1e, 0x03 },
303 { V4L2_DV_BT_CEA_1920X1080P30
, 0x1e, 0x02 },
304 { V4L2_DV_BT_CEA_1920X1080P50
, 0x1e, 0x01 },
305 { V4L2_DV_BT_CEA_1920X1080P60
, 0x1e, 0x00 },
309 /* sorted by number of lines */
310 static const struct adv7604_video_standards adv7604_prim_mode_hdmi_gr
[] = {
311 { V4L2_DV_BT_DMT_640X480P60
, 0x08, 0x00 },
312 { V4L2_DV_BT_DMT_640X480P72
, 0x09, 0x00 },
313 { V4L2_DV_BT_DMT_640X480P75
, 0x0a, 0x00 },
314 { V4L2_DV_BT_DMT_640X480P85
, 0x0b, 0x00 },
315 { V4L2_DV_BT_DMT_800X600P56
, 0x00, 0x00 },
316 { V4L2_DV_BT_DMT_800X600P60
, 0x01, 0x00 },
317 { V4L2_DV_BT_DMT_800X600P72
, 0x02, 0x00 },
318 { V4L2_DV_BT_DMT_800X600P75
, 0x03, 0x00 },
319 { V4L2_DV_BT_DMT_800X600P85
, 0x04, 0x00 },
320 { V4L2_DV_BT_DMT_1024X768P60
, 0x0c, 0x00 },
321 { V4L2_DV_BT_DMT_1024X768P70
, 0x0d, 0x00 },
322 { V4L2_DV_BT_DMT_1024X768P75
, 0x0e, 0x00 },
323 { V4L2_DV_BT_DMT_1024X768P85
, 0x0f, 0x00 },
324 { V4L2_DV_BT_DMT_1280X1024P60
, 0x05, 0x00 },
325 { V4L2_DV_BT_DMT_1280X1024P75
, 0x06, 0x00 },
329 /* ----------------------------------------------------------------------- */
331 static inline struct adv7604_state
*to_state(struct v4l2_subdev
*sd
)
333 return container_of(sd
, struct adv7604_state
, sd
);
336 static inline unsigned hblanking(const struct v4l2_bt_timings
*t
)
338 return V4L2_DV_BT_BLANKING_WIDTH(t
);
341 static inline unsigned htotal(const struct v4l2_bt_timings
*t
)
343 return V4L2_DV_BT_FRAME_WIDTH(t
);
346 static inline unsigned vblanking(const struct v4l2_bt_timings
*t
)
348 return V4L2_DV_BT_BLANKING_HEIGHT(t
);
351 static inline unsigned vtotal(const struct v4l2_bt_timings
*t
)
353 return V4L2_DV_BT_FRAME_HEIGHT(t
);
356 /* ----------------------------------------------------------------------- */
358 static s32
adv_smbus_read_byte_data_check(struct i2c_client
*client
,
359 u8 command
, bool check
)
361 union i2c_smbus_data data
;
363 if (!i2c_smbus_xfer(client
->adapter
, client
->addr
, client
->flags
,
364 I2C_SMBUS_READ
, command
,
365 I2C_SMBUS_BYTE_DATA
, &data
))
368 v4l_err(client
, "error reading %02x, %02x\n",
369 client
->addr
, command
);
373 static s32
adv_smbus_read_byte_data(struct adv7604_state
*state
,
374 enum adv7604_page page
, u8 command
)
376 return adv_smbus_read_byte_data_check(state
->i2c_clients
[page
],
380 static s32
adv_smbus_write_byte_data(struct adv7604_state
*state
,
381 enum adv7604_page page
, u8 command
,
384 struct i2c_client
*client
= state
->i2c_clients
[page
];
385 union i2c_smbus_data data
;
390 for (i
= 0; i
< 3; i
++) {
391 err
= i2c_smbus_xfer(client
->adapter
, client
->addr
,
393 I2C_SMBUS_WRITE
, command
,
394 I2C_SMBUS_BYTE_DATA
, &data
);
399 v4l_err(client
, "error writing %02x, %02x, %02x\n",
400 client
->addr
, command
, value
);
404 static s32
adv_smbus_write_i2c_block_data(struct adv7604_state
*state
,
405 enum adv7604_page page
, u8 command
,
406 unsigned length
, const u8
*values
)
408 struct i2c_client
*client
= state
->i2c_clients
[page
];
409 union i2c_smbus_data data
;
411 if (length
> I2C_SMBUS_BLOCK_MAX
)
412 length
= I2C_SMBUS_BLOCK_MAX
;
413 data
.block
[0] = length
;
414 memcpy(data
.block
+ 1, values
, length
);
415 return i2c_smbus_xfer(client
->adapter
, client
->addr
, client
->flags
,
416 I2C_SMBUS_WRITE
, command
,
417 I2C_SMBUS_I2C_BLOCK_DATA
, &data
);
420 /* ----------------------------------------------------------------------- */
422 static inline int io_read(struct v4l2_subdev
*sd
, u8 reg
)
424 struct adv7604_state
*state
= to_state(sd
);
426 return adv_smbus_read_byte_data(state
, ADV7604_PAGE_IO
, reg
);
429 static inline int io_write(struct v4l2_subdev
*sd
, u8 reg
, u8 val
)
431 struct adv7604_state
*state
= to_state(sd
);
433 return adv_smbus_write_byte_data(state
, ADV7604_PAGE_IO
, reg
, val
);
436 static inline int io_write_clr_set(struct v4l2_subdev
*sd
, u8 reg
, u8 mask
, u8 val
)
438 return io_write(sd
, reg
, (io_read(sd
, reg
) & ~mask
) | val
);
441 static inline int avlink_read(struct v4l2_subdev
*sd
, u8 reg
)
443 struct adv7604_state
*state
= to_state(sd
);
445 return adv_smbus_read_byte_data(state
, ADV7604_PAGE_AVLINK
, reg
);
448 static inline int avlink_write(struct v4l2_subdev
*sd
, u8 reg
, u8 val
)
450 struct adv7604_state
*state
= to_state(sd
);
452 return adv_smbus_write_byte_data(state
, ADV7604_PAGE_AVLINK
, reg
, val
);
455 static inline int cec_read(struct v4l2_subdev
*sd
, u8 reg
)
457 struct adv7604_state
*state
= to_state(sd
);
459 return adv_smbus_read_byte_data(state
, ADV7604_PAGE_CEC
, reg
);
462 static inline int cec_write(struct v4l2_subdev
*sd
, u8 reg
, u8 val
)
464 struct adv7604_state
*state
= to_state(sd
);
466 return adv_smbus_write_byte_data(state
, ADV7604_PAGE_CEC
, reg
, val
);
469 static inline int cec_write_clr_set(struct v4l2_subdev
*sd
, u8 reg
, u8 mask
, u8 val
)
471 return cec_write(sd
, reg
, (cec_read(sd
, reg
) & ~mask
) | val
);
474 static inline int infoframe_read(struct v4l2_subdev
*sd
, u8 reg
)
476 struct adv7604_state
*state
= to_state(sd
);
478 return adv_smbus_read_byte_data(state
, ADV7604_PAGE_INFOFRAME
, reg
);
481 static inline int infoframe_write(struct v4l2_subdev
*sd
, u8 reg
, u8 val
)
483 struct adv7604_state
*state
= to_state(sd
);
485 return adv_smbus_write_byte_data(state
, ADV7604_PAGE_INFOFRAME
,
489 static inline int esdp_read(struct v4l2_subdev
*sd
, u8 reg
)
491 struct adv7604_state
*state
= to_state(sd
);
493 return adv_smbus_read_byte_data(state
, ADV7604_PAGE_ESDP
, reg
);
496 static inline int esdp_write(struct v4l2_subdev
*sd
, u8 reg
, u8 val
)
498 struct adv7604_state
*state
= to_state(sd
);
500 return adv_smbus_write_byte_data(state
, ADV7604_PAGE_ESDP
, reg
, val
);
503 static inline int dpp_read(struct v4l2_subdev
*sd
, u8 reg
)
505 struct adv7604_state
*state
= to_state(sd
);
507 return adv_smbus_read_byte_data(state
, ADV7604_PAGE_DPP
, reg
);
510 static inline int dpp_write(struct v4l2_subdev
*sd
, u8 reg
, u8 val
)
512 struct adv7604_state
*state
= to_state(sd
);
514 return adv_smbus_write_byte_data(state
, ADV7604_PAGE_DPP
, reg
, val
);
517 static inline int afe_read(struct v4l2_subdev
*sd
, u8 reg
)
519 struct adv7604_state
*state
= to_state(sd
);
521 return adv_smbus_read_byte_data(state
, ADV7604_PAGE_AFE
, reg
);
524 static inline int afe_write(struct v4l2_subdev
*sd
, u8 reg
, u8 val
)
526 struct adv7604_state
*state
= to_state(sd
);
528 return adv_smbus_write_byte_data(state
, ADV7604_PAGE_AFE
, reg
, val
);
531 static inline int rep_read(struct v4l2_subdev
*sd
, u8 reg
)
533 struct adv7604_state
*state
= to_state(sd
);
535 return adv_smbus_read_byte_data(state
, ADV7604_PAGE_REP
, reg
);
538 static inline int rep_write(struct v4l2_subdev
*sd
, u8 reg
, u8 val
)
540 struct adv7604_state
*state
= to_state(sd
);
542 return adv_smbus_write_byte_data(state
, ADV7604_PAGE_REP
, reg
, val
);
545 static inline int rep_write_clr_set(struct v4l2_subdev
*sd
, u8 reg
, u8 mask
, u8 val
)
547 return rep_write(sd
, reg
, (rep_read(sd
, reg
) & ~mask
) | val
);
550 static inline int edid_read(struct v4l2_subdev
*sd
, u8 reg
)
552 struct adv7604_state
*state
= to_state(sd
);
554 return adv_smbus_read_byte_data(state
, ADV7604_PAGE_EDID
, reg
);
557 static inline int edid_write(struct v4l2_subdev
*sd
, u8 reg
, u8 val
)
559 struct adv7604_state
*state
= to_state(sd
);
561 return adv_smbus_write_byte_data(state
, ADV7604_PAGE_EDID
, reg
, val
);
564 static inline int edid_read_block(struct v4l2_subdev
*sd
, unsigned len
, u8
*val
)
566 struct adv7604_state
*state
= to_state(sd
);
567 struct i2c_client
*client
= state
->i2c_clients
[ADV7604_PAGE_EDID
];
568 u8 msgbuf0
[1] = { 0 };
570 struct i2c_msg msg
[2] = {
572 .addr
= client
->addr
,
577 .addr
= client
->addr
,
584 if (i2c_transfer(client
->adapter
, msg
, 2) < 0)
586 memcpy(val
, msgbuf1
, len
);
590 static inline int edid_write_block(struct v4l2_subdev
*sd
,
591 unsigned len
, const u8
*val
)
593 struct adv7604_state
*state
= to_state(sd
);
597 v4l2_dbg(2, debug
, sd
, "%s: write EDID block (%d byte)\n", __func__
, len
);
599 for (i
= 0; !err
&& i
< len
; i
+= I2C_SMBUS_BLOCK_MAX
)
600 err
= adv_smbus_write_i2c_block_data(state
, ADV7604_PAGE_EDID
,
601 i
, I2C_SMBUS_BLOCK_MAX
, val
+ i
);
605 static void adv7604_set_hpd(struct adv7604_state
*state
, unsigned int hpd
)
609 for (i
= 0; i
< state
->info
->num_dv_ports
; ++i
) {
610 if (IS_ERR(state
->hpd_gpio
[i
]))
613 gpiod_set_value_cansleep(state
->hpd_gpio
[i
], hpd
& BIT(i
));
616 v4l2_subdev_notify(&state
->sd
, ADV7604_HOTPLUG
, &hpd
);
619 static void adv7604_delayed_work_enable_hotplug(struct work_struct
*work
)
621 struct delayed_work
*dwork
= to_delayed_work(work
);
622 struct adv7604_state
*state
= container_of(dwork
, struct adv7604_state
,
623 delayed_work_enable_hotplug
);
624 struct v4l2_subdev
*sd
= &state
->sd
;
626 v4l2_dbg(2, debug
, sd
, "%s: enable hotplug\n", __func__
);
628 adv7604_set_hpd(state
, state
->edid
.present
);
631 static inline int hdmi_read(struct v4l2_subdev
*sd
, u8 reg
)
633 struct adv7604_state
*state
= to_state(sd
);
635 return adv_smbus_read_byte_data(state
, ADV7604_PAGE_HDMI
, reg
);
638 static u16
hdmi_read16(struct v4l2_subdev
*sd
, u8 reg
, u16 mask
)
640 return ((hdmi_read(sd
, reg
) << 8) | hdmi_read(sd
, reg
+ 1)) & mask
;
643 static inline int hdmi_write(struct v4l2_subdev
*sd
, u8 reg
, u8 val
)
645 struct adv7604_state
*state
= to_state(sd
);
647 return adv_smbus_write_byte_data(state
, ADV7604_PAGE_HDMI
, reg
, val
);
650 static inline int hdmi_write_clr_set(struct v4l2_subdev
*sd
, u8 reg
, u8 mask
, u8 val
)
652 return hdmi_write(sd
, reg
, (hdmi_read(sd
, reg
) & ~mask
) | val
);
655 static inline int test_read(struct v4l2_subdev
*sd
, u8 reg
)
657 struct adv7604_state
*state
= to_state(sd
);
659 return adv_smbus_read_byte_data(state
, ADV7604_PAGE_TEST
, reg
);
662 static inline int test_write(struct v4l2_subdev
*sd
, u8 reg
, u8 val
)
664 struct adv7604_state
*state
= to_state(sd
);
666 return adv_smbus_write_byte_data(state
, ADV7604_PAGE_TEST
, reg
, val
);
669 static inline int cp_read(struct v4l2_subdev
*sd
, u8 reg
)
671 struct adv7604_state
*state
= to_state(sd
);
673 return adv_smbus_read_byte_data(state
, ADV7604_PAGE_CP
, reg
);
676 static u16
cp_read16(struct v4l2_subdev
*sd
, u8 reg
, u16 mask
)
678 return ((cp_read(sd
, reg
) << 8) | cp_read(sd
, reg
+ 1)) & mask
;
681 static inline int cp_write(struct v4l2_subdev
*sd
, u8 reg
, u8 val
)
683 struct adv7604_state
*state
= to_state(sd
);
685 return adv_smbus_write_byte_data(state
, ADV7604_PAGE_CP
, reg
, val
);
688 static inline int cp_write_clr_set(struct v4l2_subdev
*sd
, u8 reg
, u8 mask
, u8 val
)
690 return cp_write(sd
, reg
, (cp_read(sd
, reg
) & ~mask
) | val
);
693 static inline int vdp_read(struct v4l2_subdev
*sd
, u8 reg
)
695 struct adv7604_state
*state
= to_state(sd
);
697 return adv_smbus_read_byte_data(state
, ADV7604_PAGE_VDP
, reg
);
700 static inline int vdp_write(struct v4l2_subdev
*sd
, u8 reg
, u8 val
)
702 struct adv7604_state
*state
= to_state(sd
);
704 return adv_smbus_write_byte_data(state
, ADV7604_PAGE_VDP
, reg
, val
);
707 #define ADV7604_REG(page, offset) (((page) << 8) | (offset))
708 #define ADV7604_REG_SEQ_TERM 0xffff
710 #ifdef CONFIG_VIDEO_ADV_DEBUG
711 static int adv7604_read_reg(struct v4l2_subdev
*sd
, unsigned int reg
)
713 struct adv7604_state
*state
= to_state(sd
);
714 unsigned int page
= reg
>> 8;
716 if (!(BIT(page
) & state
->info
->page_mask
))
721 return adv_smbus_read_byte_data(state
, page
, reg
);
725 static int adv7604_write_reg(struct v4l2_subdev
*sd
, unsigned int reg
, u8 val
)
727 struct adv7604_state
*state
= to_state(sd
);
728 unsigned int page
= reg
>> 8;
730 if (!(BIT(page
) & state
->info
->page_mask
))
735 return adv_smbus_write_byte_data(state
, page
, reg
, val
);
738 static void adv7604_write_reg_seq(struct v4l2_subdev
*sd
,
739 const struct adv7604_reg_seq
*reg_seq
)
743 for (i
= 0; reg_seq
[i
].reg
!= ADV7604_REG_SEQ_TERM
; i
++)
744 adv7604_write_reg(sd
, reg_seq
[i
].reg
, reg_seq
[i
].val
);
747 /* -----------------------------------------------------------------------------
751 static const struct adv7604_format_info adv7604_formats
[] = {
752 { V4L2_MBUS_FMT_RGB888_1X24
, ADV7604_OP_CH_SEL_RGB
, true, false,
753 ADV7604_OP_MODE_SEL_SDR_444
| ADV7604_OP_FORMAT_SEL_8BIT
},
754 { V4L2_MBUS_FMT_YUYV8_2X8
, ADV7604_OP_CH_SEL_RGB
, false, false,
755 ADV7604_OP_MODE_SEL_SDR_422
| ADV7604_OP_FORMAT_SEL_8BIT
},
756 { V4L2_MBUS_FMT_YVYU8_2X8
, ADV7604_OP_CH_SEL_RGB
, false, true,
757 ADV7604_OP_MODE_SEL_SDR_422
| ADV7604_OP_FORMAT_SEL_8BIT
},
758 { V4L2_MBUS_FMT_YUYV10_2X10
, ADV7604_OP_CH_SEL_RGB
, false, false,
759 ADV7604_OP_MODE_SEL_SDR_422
| ADV7604_OP_FORMAT_SEL_10BIT
},
760 { V4L2_MBUS_FMT_YVYU10_2X10
, ADV7604_OP_CH_SEL_RGB
, false, true,
761 ADV7604_OP_MODE_SEL_SDR_422
| ADV7604_OP_FORMAT_SEL_10BIT
},
762 { V4L2_MBUS_FMT_YUYV12_2X12
, ADV7604_OP_CH_SEL_RGB
, false, false,
763 ADV7604_OP_MODE_SEL_SDR_422
| ADV7604_OP_FORMAT_SEL_12BIT
},
764 { V4L2_MBUS_FMT_YVYU12_2X12
, ADV7604_OP_CH_SEL_RGB
, false, true,
765 ADV7604_OP_MODE_SEL_SDR_422
| ADV7604_OP_FORMAT_SEL_12BIT
},
766 { V4L2_MBUS_FMT_UYVY8_1X16
, ADV7604_OP_CH_SEL_RBG
, false, false,
767 ADV7604_OP_MODE_SEL_SDR_422_2X
| ADV7604_OP_FORMAT_SEL_8BIT
},
768 { V4L2_MBUS_FMT_VYUY8_1X16
, ADV7604_OP_CH_SEL_RBG
, false, true,
769 ADV7604_OP_MODE_SEL_SDR_422_2X
| ADV7604_OP_FORMAT_SEL_8BIT
},
770 { V4L2_MBUS_FMT_YUYV8_1X16
, ADV7604_OP_CH_SEL_RGB
, false, false,
771 ADV7604_OP_MODE_SEL_SDR_422_2X
| ADV7604_OP_FORMAT_SEL_8BIT
},
772 { V4L2_MBUS_FMT_YVYU8_1X16
, ADV7604_OP_CH_SEL_RGB
, false, true,
773 ADV7604_OP_MODE_SEL_SDR_422_2X
| ADV7604_OP_FORMAT_SEL_8BIT
},
774 { V4L2_MBUS_FMT_UYVY10_1X20
, ADV7604_OP_CH_SEL_RBG
, false, false,
775 ADV7604_OP_MODE_SEL_SDR_422_2X
| ADV7604_OP_FORMAT_SEL_10BIT
},
776 { V4L2_MBUS_FMT_VYUY10_1X20
, ADV7604_OP_CH_SEL_RBG
, false, true,
777 ADV7604_OP_MODE_SEL_SDR_422_2X
| ADV7604_OP_FORMAT_SEL_10BIT
},
778 { V4L2_MBUS_FMT_YUYV10_1X20
, ADV7604_OP_CH_SEL_RGB
, false, false,
779 ADV7604_OP_MODE_SEL_SDR_422_2X
| ADV7604_OP_FORMAT_SEL_10BIT
},
780 { V4L2_MBUS_FMT_YVYU10_1X20
, ADV7604_OP_CH_SEL_RGB
, false, true,
781 ADV7604_OP_MODE_SEL_SDR_422_2X
| ADV7604_OP_FORMAT_SEL_10BIT
},
782 { V4L2_MBUS_FMT_UYVY12_1X24
, ADV7604_OP_CH_SEL_RBG
, false, false,
783 ADV7604_OP_MODE_SEL_SDR_422_2X
| ADV7604_OP_FORMAT_SEL_12BIT
},
784 { V4L2_MBUS_FMT_VYUY12_1X24
, ADV7604_OP_CH_SEL_RBG
, false, true,
785 ADV7604_OP_MODE_SEL_SDR_422_2X
| ADV7604_OP_FORMAT_SEL_12BIT
},
786 { V4L2_MBUS_FMT_YUYV12_1X24
, ADV7604_OP_CH_SEL_RGB
, false, false,
787 ADV7604_OP_MODE_SEL_SDR_422_2X
| ADV7604_OP_FORMAT_SEL_12BIT
},
788 { V4L2_MBUS_FMT_YVYU12_1X24
, ADV7604_OP_CH_SEL_RGB
, false, true,
789 ADV7604_OP_MODE_SEL_SDR_422_2X
| ADV7604_OP_FORMAT_SEL_12BIT
},
792 static const struct adv7604_format_info adv7611_formats
[] = {
793 { V4L2_MBUS_FMT_RGB888_1X24
, ADV7604_OP_CH_SEL_RGB
, true, false,
794 ADV7604_OP_MODE_SEL_SDR_444
| ADV7604_OP_FORMAT_SEL_8BIT
},
795 { V4L2_MBUS_FMT_YUYV8_2X8
, ADV7604_OP_CH_SEL_RGB
, false, false,
796 ADV7604_OP_MODE_SEL_SDR_422
| ADV7604_OP_FORMAT_SEL_8BIT
},
797 { V4L2_MBUS_FMT_YVYU8_2X8
, ADV7604_OP_CH_SEL_RGB
, false, true,
798 ADV7604_OP_MODE_SEL_SDR_422
| ADV7604_OP_FORMAT_SEL_8BIT
},
799 { V4L2_MBUS_FMT_YUYV12_2X12
, ADV7604_OP_CH_SEL_RGB
, false, false,
800 ADV7604_OP_MODE_SEL_SDR_422
| ADV7604_OP_FORMAT_SEL_12BIT
},
801 { V4L2_MBUS_FMT_YVYU12_2X12
, ADV7604_OP_CH_SEL_RGB
, false, true,
802 ADV7604_OP_MODE_SEL_SDR_422
| ADV7604_OP_FORMAT_SEL_12BIT
},
803 { V4L2_MBUS_FMT_UYVY8_1X16
, ADV7604_OP_CH_SEL_RBG
, false, false,
804 ADV7604_OP_MODE_SEL_SDR_422_2X
| ADV7604_OP_FORMAT_SEL_8BIT
},
805 { V4L2_MBUS_FMT_VYUY8_1X16
, ADV7604_OP_CH_SEL_RBG
, false, true,
806 ADV7604_OP_MODE_SEL_SDR_422_2X
| ADV7604_OP_FORMAT_SEL_8BIT
},
807 { V4L2_MBUS_FMT_YUYV8_1X16
, ADV7604_OP_CH_SEL_RGB
, false, false,
808 ADV7604_OP_MODE_SEL_SDR_422_2X
| ADV7604_OP_FORMAT_SEL_8BIT
},
809 { V4L2_MBUS_FMT_YVYU8_1X16
, ADV7604_OP_CH_SEL_RGB
, false, true,
810 ADV7604_OP_MODE_SEL_SDR_422_2X
| ADV7604_OP_FORMAT_SEL_8BIT
},
811 { V4L2_MBUS_FMT_UYVY12_1X24
, ADV7604_OP_CH_SEL_RBG
, false, false,
812 ADV7604_OP_MODE_SEL_SDR_422_2X
| ADV7604_OP_FORMAT_SEL_12BIT
},
813 { V4L2_MBUS_FMT_VYUY12_1X24
, ADV7604_OP_CH_SEL_RBG
, false, true,
814 ADV7604_OP_MODE_SEL_SDR_422_2X
| ADV7604_OP_FORMAT_SEL_12BIT
},
815 { V4L2_MBUS_FMT_YUYV12_1X24
, ADV7604_OP_CH_SEL_RGB
, false, false,
816 ADV7604_OP_MODE_SEL_SDR_422_2X
| ADV7604_OP_FORMAT_SEL_12BIT
},
817 { V4L2_MBUS_FMT_YVYU12_1X24
, ADV7604_OP_CH_SEL_RGB
, false, true,
818 ADV7604_OP_MODE_SEL_SDR_422_2X
| ADV7604_OP_FORMAT_SEL_12BIT
},
821 static const struct adv7604_format_info
*
822 adv7604_format_info(struct adv7604_state
*state
, enum v4l2_mbus_pixelcode code
)
826 for (i
= 0; i
< state
->info
->nformats
; ++i
) {
827 if (state
->info
->formats
[i
].code
== code
)
828 return &state
->info
->formats
[i
];
834 /* ----------------------------------------------------------------------- */
836 static inline bool is_analog_input(struct v4l2_subdev
*sd
)
838 struct adv7604_state
*state
= to_state(sd
);
840 return state
->selected_input
== ADV7604_PAD_VGA_RGB
||
841 state
->selected_input
== ADV7604_PAD_VGA_COMP
;
844 static inline bool is_digital_input(struct v4l2_subdev
*sd
)
846 struct adv7604_state
*state
= to_state(sd
);
848 return state
->selected_input
== ADV7604_PAD_HDMI_PORT_A
||
849 state
->selected_input
== ADV7604_PAD_HDMI_PORT_B
||
850 state
->selected_input
== ADV7604_PAD_HDMI_PORT_C
||
851 state
->selected_input
== ADV7604_PAD_HDMI_PORT_D
;
854 /* ----------------------------------------------------------------------- */
856 #ifdef CONFIG_VIDEO_ADV_DEBUG
857 static void adv7604_inv_register(struct v4l2_subdev
*sd
)
859 v4l2_info(sd
, "0x000-0x0ff: IO Map\n");
860 v4l2_info(sd
, "0x100-0x1ff: AVLink Map\n");
861 v4l2_info(sd
, "0x200-0x2ff: CEC Map\n");
862 v4l2_info(sd
, "0x300-0x3ff: InfoFrame Map\n");
863 v4l2_info(sd
, "0x400-0x4ff: ESDP Map\n");
864 v4l2_info(sd
, "0x500-0x5ff: DPP Map\n");
865 v4l2_info(sd
, "0x600-0x6ff: AFE Map\n");
866 v4l2_info(sd
, "0x700-0x7ff: Repeater Map\n");
867 v4l2_info(sd
, "0x800-0x8ff: EDID Map\n");
868 v4l2_info(sd
, "0x900-0x9ff: HDMI Map\n");
869 v4l2_info(sd
, "0xa00-0xaff: Test Map\n");
870 v4l2_info(sd
, "0xb00-0xbff: CP Map\n");
871 v4l2_info(sd
, "0xc00-0xcff: VDP Map\n");
874 static int adv7604_g_register(struct v4l2_subdev
*sd
,
875 struct v4l2_dbg_register
*reg
)
879 ret
= adv7604_read_reg(sd
, reg
->reg
);
881 v4l2_info(sd
, "Register %03llx not supported\n", reg
->reg
);
882 adv7604_inv_register(sd
);
892 static int adv7604_s_register(struct v4l2_subdev
*sd
,
893 const struct v4l2_dbg_register
*reg
)
897 ret
= adv7604_write_reg(sd
, reg
->reg
, reg
->val
);
899 v4l2_info(sd
, "Register %03llx not supported\n", reg
->reg
);
900 adv7604_inv_register(sd
);
908 static unsigned int adv7604_read_cable_det(struct v4l2_subdev
*sd
)
910 u8 value
= io_read(sd
, 0x6f);
912 return ((value
& 0x10) >> 4)
913 | ((value
& 0x08) >> 2)
914 | ((value
& 0x04) << 0)
915 | ((value
& 0x02) << 2);
918 static unsigned int adv7611_read_cable_det(struct v4l2_subdev
*sd
)
920 u8 value
= io_read(sd
, 0x6f);
925 static int adv7604_s_detect_tx_5v_ctrl(struct v4l2_subdev
*sd
)
927 struct adv7604_state
*state
= to_state(sd
);
928 const struct adv7604_chip_info
*info
= state
->info
;
930 return v4l2_ctrl_s_ctrl(state
->detect_tx_5v_ctrl
,
931 info
->read_cable_det(sd
));
934 static int find_and_set_predefined_video_timings(struct v4l2_subdev
*sd
,
936 const struct adv7604_video_standards
*predef_vid_timings
,
937 const struct v4l2_dv_timings
*timings
)
941 for (i
= 0; predef_vid_timings
[i
].timings
.bt
.width
; i
++) {
942 if (!v4l2_match_dv_timings(timings
, &predef_vid_timings
[i
].timings
,
943 is_digital_input(sd
) ? 250000 : 1000000))
945 io_write(sd
, 0x00, predef_vid_timings
[i
].vid_std
); /* video std */
946 io_write(sd
, 0x01, (predef_vid_timings
[i
].v_freq
<< 4) +
947 prim_mode
); /* v_freq and prim mode */
954 static int configure_predefined_video_timings(struct v4l2_subdev
*sd
,
955 struct v4l2_dv_timings
*timings
)
957 struct adv7604_state
*state
= to_state(sd
);
960 v4l2_dbg(1, debug
, sd
, "%s", __func__
);
962 if (adv7604_has_afe(state
)) {
963 /* reset to default values */
964 io_write(sd
, 0x16, 0x43);
965 io_write(sd
, 0x17, 0x5a);
967 /* disable embedded syncs for auto graphics mode */
968 cp_write_clr_set(sd
, 0x81, 0x10, 0x00);
969 cp_write(sd
, 0x8f, 0x00);
970 cp_write(sd
, 0x90, 0x00);
971 cp_write(sd
, 0xa2, 0x00);
972 cp_write(sd
, 0xa3, 0x00);
973 cp_write(sd
, 0xa4, 0x00);
974 cp_write(sd
, 0xa5, 0x00);
975 cp_write(sd
, 0xa6, 0x00);
976 cp_write(sd
, 0xa7, 0x00);
977 cp_write(sd
, 0xab, 0x00);
978 cp_write(sd
, 0xac, 0x00);
980 if (is_analog_input(sd
)) {
981 err
= find_and_set_predefined_video_timings(sd
,
982 0x01, adv7604_prim_mode_comp
, timings
);
984 err
= find_and_set_predefined_video_timings(sd
,
985 0x02, adv7604_prim_mode_gr
, timings
);
986 } else if (is_digital_input(sd
)) {
987 err
= find_and_set_predefined_video_timings(sd
,
988 0x05, adv7604_prim_mode_hdmi_comp
, timings
);
990 err
= find_and_set_predefined_video_timings(sd
,
991 0x06, adv7604_prim_mode_hdmi_gr
, timings
);
993 v4l2_dbg(2, debug
, sd
, "%s: Unknown port %d selected\n",
994 __func__
, state
->selected_input
);
1002 static void configure_custom_video_timings(struct v4l2_subdev
*sd
,
1003 const struct v4l2_bt_timings
*bt
)
1005 struct adv7604_state
*state
= to_state(sd
);
1006 u32 width
= htotal(bt
);
1007 u32 height
= vtotal(bt
);
1008 u16 cp_start_sav
= bt
->hsync
+ bt
->hbackporch
- 4;
1009 u16 cp_start_eav
= width
- bt
->hfrontporch
;
1010 u16 cp_start_vbi
= height
- bt
->vfrontporch
;
1011 u16 cp_end_vbi
= bt
->vsync
+ bt
->vbackporch
;
1012 u16 ch1_fr_ll
= (((u32
)bt
->pixelclock
/ 100) > 0) ?
1013 ((width
* (ADV7604_fsc
/ 100)) / ((u32
)bt
->pixelclock
/ 100)) : 0;
1015 0xc0 | ((width
>> 8) & 0x1f),
1019 v4l2_dbg(2, debug
, sd
, "%s\n", __func__
);
1021 if (is_analog_input(sd
)) {
1023 io_write(sd
, 0x00, 0x07); /* video std */
1024 io_write(sd
, 0x01, 0x02); /* prim mode */
1025 /* enable embedded syncs for auto graphics mode */
1026 cp_write_clr_set(sd
, 0x81, 0x10, 0x10);
1028 /* Should only be set in auto-graphics mode [REF_02, p. 91-92] */
1029 /* setup PLL_DIV_MAN_EN and PLL_DIV_RATIO */
1030 /* IO-map reg. 0x16 and 0x17 should be written in sequence */
1031 if (adv_smbus_write_i2c_block_data(state
, ADV7604_PAGE_IO
,
1033 v4l2_err(sd
, "writing to reg 0x16 and 0x17 failed\n");
1035 /* active video - horizontal timing */
1036 cp_write(sd
, 0xa2, (cp_start_sav
>> 4) & 0xff);
1037 cp_write(sd
, 0xa3, ((cp_start_sav
& 0x0f) << 4) |
1038 ((cp_start_eav
>> 8) & 0x0f));
1039 cp_write(sd
, 0xa4, cp_start_eav
& 0xff);
1041 /* active video - vertical timing */
1042 cp_write(sd
, 0xa5, (cp_start_vbi
>> 4) & 0xff);
1043 cp_write(sd
, 0xa6, ((cp_start_vbi
& 0xf) << 4) |
1044 ((cp_end_vbi
>> 8) & 0xf));
1045 cp_write(sd
, 0xa7, cp_end_vbi
& 0xff);
1046 } else if (is_digital_input(sd
)) {
1047 /* set default prim_mode/vid_std for HDMI
1048 according to [REF_03, c. 4.2] */
1049 io_write(sd
, 0x00, 0x02); /* video std */
1050 io_write(sd
, 0x01, 0x06); /* prim mode */
1052 v4l2_dbg(2, debug
, sd
, "%s: Unknown port %d selected\n",
1053 __func__
, state
->selected_input
);
1056 cp_write(sd
, 0x8f, (ch1_fr_ll
>> 8) & 0x7);
1057 cp_write(sd
, 0x90, ch1_fr_ll
& 0xff);
1058 cp_write(sd
, 0xab, (height
>> 4) & 0xff);
1059 cp_write(sd
, 0xac, (height
& 0x0f) << 4);
1062 static void adv7604_set_offset(struct v4l2_subdev
*sd
, bool auto_offset
, u16 offset_a
, u16 offset_b
, u16 offset_c
)
1064 struct adv7604_state
*state
= to_state(sd
);
1073 v4l2_dbg(2, debug
, sd
, "%s: %s offset: a = 0x%x, b = 0x%x, c = 0x%x\n",
1074 __func__
, auto_offset
? "Auto" : "Manual",
1075 offset_a
, offset_b
, offset_c
);
1077 offset_buf
[0] = (cp_read(sd
, 0x77) & 0xc0) | ((offset_a
& 0x3f0) >> 4);
1078 offset_buf
[1] = ((offset_a
& 0x00f) << 4) | ((offset_b
& 0x3c0) >> 6);
1079 offset_buf
[2] = ((offset_b
& 0x03f) << 2) | ((offset_c
& 0x300) >> 8);
1080 offset_buf
[3] = offset_c
& 0x0ff;
1082 /* Registers must be written in this order with no i2c access in between */
1083 if (adv_smbus_write_i2c_block_data(state
, ADV7604_PAGE_CP
,
1084 0x77, 4, offset_buf
))
1085 v4l2_err(sd
, "%s: i2c error writing to CP reg 0x77, 0x78, 0x79, 0x7a\n", __func__
);
1088 static void adv7604_set_gain(struct v4l2_subdev
*sd
, bool auto_gain
, u16 gain_a
, u16 gain_b
, u16 gain_c
)
1090 struct adv7604_state
*state
= to_state(sd
);
1093 u8 agc_mode_man
= 1;
1103 v4l2_dbg(2, debug
, sd
, "%s: %s gain: a = 0x%x, b = 0x%x, c = 0x%x\n",
1104 __func__
, auto_gain
? "Auto" : "Manual",
1105 gain_a
, gain_b
, gain_c
);
1107 gain_buf
[0] = ((gain_man
<< 7) | (agc_mode_man
<< 6) | ((gain_a
& 0x3f0) >> 4));
1108 gain_buf
[1] = (((gain_a
& 0x00f) << 4) | ((gain_b
& 0x3c0) >> 6));
1109 gain_buf
[2] = (((gain_b
& 0x03f) << 2) | ((gain_c
& 0x300) >> 8));
1110 gain_buf
[3] = ((gain_c
& 0x0ff));
1112 /* Registers must be written in this order with no i2c access in between */
1113 if (adv_smbus_write_i2c_block_data(state
, ADV7604_PAGE_CP
,
1115 v4l2_err(sd
, "%s: i2c error writing to CP reg 0x73, 0x74, 0x75, 0x76\n", __func__
);
1118 static void set_rgb_quantization_range(struct v4l2_subdev
*sd
)
1120 struct adv7604_state
*state
= to_state(sd
);
1121 bool rgb_output
= io_read(sd
, 0x02) & 0x02;
1122 bool hdmi_signal
= hdmi_read(sd
, 0x05) & 0x80;
1124 v4l2_dbg(2, debug
, sd
, "%s: RGB quantization range: %d, RGB out: %d, HDMI: %d\n",
1125 __func__
, state
->rgb_quantization_range
,
1126 rgb_output
, hdmi_signal
);
1128 adv7604_set_gain(sd
, true, 0x0, 0x0, 0x0);
1129 adv7604_set_offset(sd
, true, 0x0, 0x0, 0x0);
1131 switch (state
->rgb_quantization_range
) {
1132 case V4L2_DV_RGB_RANGE_AUTO
:
1133 if (state
->selected_input
== ADV7604_PAD_VGA_RGB
) {
1134 /* Receiving analog RGB signal
1135 * Set RGB full range (0-255) */
1136 io_write_clr_set(sd
, 0x02, 0xf0, 0x10);
1140 if (state
->selected_input
== ADV7604_PAD_VGA_COMP
) {
1141 /* Receiving analog YPbPr signal
1143 io_write_clr_set(sd
, 0x02, 0xf0, 0xf0);
1148 /* Receiving HDMI signal
1150 io_write_clr_set(sd
, 0x02, 0xf0, 0xf0);
1154 /* Receiving DVI-D signal
1155 * ADV7604 selects RGB limited range regardless of
1156 * input format (CE/IT) in automatic mode */
1157 if (state
->timings
.bt
.standards
& V4L2_DV_BT_STD_CEA861
) {
1158 /* RGB limited range (16-235) */
1159 io_write_clr_set(sd
, 0x02, 0xf0, 0x00);
1161 /* RGB full range (0-255) */
1162 io_write_clr_set(sd
, 0x02, 0xf0, 0x10);
1164 if (is_digital_input(sd
) && rgb_output
) {
1165 adv7604_set_offset(sd
, false, 0x40, 0x40, 0x40);
1167 adv7604_set_gain(sd
, false, 0xe0, 0xe0, 0xe0);
1168 adv7604_set_offset(sd
, false, 0x70, 0x70, 0x70);
1172 case V4L2_DV_RGB_RANGE_LIMITED
:
1173 if (state
->selected_input
== ADV7604_PAD_VGA_COMP
) {
1174 /* YCrCb limited range (16-235) */
1175 io_write_clr_set(sd
, 0x02, 0xf0, 0x20);
1179 /* RGB limited range (16-235) */
1180 io_write_clr_set(sd
, 0x02, 0xf0, 0x00);
1183 case V4L2_DV_RGB_RANGE_FULL
:
1184 if (state
->selected_input
== ADV7604_PAD_VGA_COMP
) {
1185 /* YCrCb full range (0-255) */
1186 io_write_clr_set(sd
, 0x02, 0xf0, 0x60);
1190 /* RGB full range (0-255) */
1191 io_write_clr_set(sd
, 0x02, 0xf0, 0x10);
1193 if (is_analog_input(sd
) || hdmi_signal
)
1196 /* Adjust gain/offset for DVI-D signals only */
1198 adv7604_set_offset(sd
, false, 0x40, 0x40, 0x40);
1200 adv7604_set_gain(sd
, false, 0xe0, 0xe0, 0xe0);
1201 adv7604_set_offset(sd
, false, 0x70, 0x70, 0x70);
1207 static int adv7604_s_ctrl(struct v4l2_ctrl
*ctrl
)
1209 struct v4l2_subdev
*sd
=
1210 &container_of(ctrl
->handler
, struct adv7604_state
, hdl
)->sd
;
1212 struct adv7604_state
*state
= to_state(sd
);
1215 case V4L2_CID_BRIGHTNESS
:
1216 cp_write(sd
, 0x3c, ctrl
->val
);
1218 case V4L2_CID_CONTRAST
:
1219 cp_write(sd
, 0x3a, ctrl
->val
);
1221 case V4L2_CID_SATURATION
:
1222 cp_write(sd
, 0x3b, ctrl
->val
);
1225 cp_write(sd
, 0x3d, ctrl
->val
);
1227 case V4L2_CID_DV_RX_RGB_RANGE
:
1228 state
->rgb_quantization_range
= ctrl
->val
;
1229 set_rgb_quantization_range(sd
);
1231 case V4L2_CID_ADV_RX_ANALOG_SAMPLING_PHASE
:
1232 if (!adv7604_has_afe(state
))
1234 /* Set the analog sampling phase. This is needed to find the
1235 best sampling phase for analog video: an application or
1236 driver has to try a number of phases and analyze the picture
1237 quality before settling on the best performing phase. */
1238 afe_write(sd
, 0xc8, ctrl
->val
);
1240 case V4L2_CID_ADV_RX_FREE_RUN_COLOR_MANUAL
:
1241 /* Use the default blue color for free running mode,
1242 or supply your own. */
1243 cp_write_clr_set(sd
, 0xbf, 0x04, ctrl
->val
<< 2);
1245 case V4L2_CID_ADV_RX_FREE_RUN_COLOR
:
1246 cp_write(sd
, 0xc0, (ctrl
->val
& 0xff0000) >> 16);
1247 cp_write(sd
, 0xc1, (ctrl
->val
& 0x00ff00) >> 8);
1248 cp_write(sd
, 0xc2, (u8
)(ctrl
->val
& 0x0000ff));
1254 /* ----------------------------------------------------------------------- */
1256 static inline bool no_power(struct v4l2_subdev
*sd
)
1258 /* Entire chip or CP powered off */
1259 return io_read(sd
, 0x0c) & 0x24;
1262 static inline bool no_signal_tmds(struct v4l2_subdev
*sd
)
1264 struct adv7604_state
*state
= to_state(sd
);
1266 return !(io_read(sd
, 0x6a) & (0x10 >> state
->selected_input
));
1269 static inline bool no_lock_tmds(struct v4l2_subdev
*sd
)
1271 struct adv7604_state
*state
= to_state(sd
);
1272 const struct adv7604_chip_info
*info
= state
->info
;
1274 return (io_read(sd
, 0x6a) & info
->tdms_lock_mask
) != info
->tdms_lock_mask
;
1277 static inline bool is_hdmi(struct v4l2_subdev
*sd
)
1279 return hdmi_read(sd
, 0x05) & 0x80;
1282 static inline bool no_lock_sspd(struct v4l2_subdev
*sd
)
1284 struct adv7604_state
*state
= to_state(sd
);
1287 * Chips without a AFE don't expose registers for the SSPD, so just assume
1288 * that we have a lock.
1290 if (adv7604_has_afe(state
))
1293 /* TODO channel 2 */
1294 return ((cp_read(sd
, 0xb5) & 0xd0) != 0xd0);
1297 static inline bool no_lock_stdi(struct v4l2_subdev
*sd
)
1299 /* TODO channel 2 */
1300 return !(cp_read(sd
, 0xb1) & 0x80);
1303 static inline bool no_signal(struct v4l2_subdev
*sd
)
1309 ret
|= no_lock_stdi(sd
);
1310 ret
|= no_lock_sspd(sd
);
1312 if (is_digital_input(sd
)) {
1313 ret
|= no_lock_tmds(sd
);
1314 ret
|= no_signal_tmds(sd
);
1320 static inline bool no_lock_cp(struct v4l2_subdev
*sd
)
1322 struct adv7604_state
*state
= to_state(sd
);
1324 if (!adv7604_has_afe(state
))
1327 /* CP has detected a non standard number of lines on the incoming
1328 video compared to what it is configured to receive by s_dv_timings */
1329 return io_read(sd
, 0x12) & 0x01;
1332 static int adv7604_g_input_status(struct v4l2_subdev
*sd
, u32
*status
)
1335 *status
|= no_power(sd
) ? V4L2_IN_ST_NO_POWER
: 0;
1336 *status
|= no_signal(sd
) ? V4L2_IN_ST_NO_SIGNAL
: 0;
1338 *status
|= is_digital_input(sd
) ? V4L2_IN_ST_NO_SYNC
: V4L2_IN_ST_NO_H_LOCK
;
1340 v4l2_dbg(1, debug
, sd
, "%s: status = 0x%x\n", __func__
, *status
);
1345 /* ----------------------------------------------------------------------- */
1347 struct stdi_readback
{
1353 static int stdi2dv_timings(struct v4l2_subdev
*sd
,
1354 struct stdi_readback
*stdi
,
1355 struct v4l2_dv_timings
*timings
)
1357 struct adv7604_state
*state
= to_state(sd
);
1358 u32 hfreq
= (ADV7604_fsc
* 8) / stdi
->bl
;
1362 for (i
= 0; adv7604_timings
[i
].bt
.height
; i
++) {
1363 if (vtotal(&adv7604_timings
[i
].bt
) != stdi
->lcf
+ 1)
1365 if (adv7604_timings
[i
].bt
.vsync
!= stdi
->lcvs
)
1368 pix_clk
= hfreq
* htotal(&adv7604_timings
[i
].bt
);
1370 if ((pix_clk
< adv7604_timings
[i
].bt
.pixelclock
+ 1000000) &&
1371 (pix_clk
> adv7604_timings
[i
].bt
.pixelclock
- 1000000)) {
1372 *timings
= adv7604_timings
[i
];
1377 if (v4l2_detect_cvt(stdi
->lcf
+ 1, hfreq
, stdi
->lcvs
,
1378 (stdi
->hs_pol
== '+' ? V4L2_DV_HSYNC_POS_POL
: 0) |
1379 (stdi
->vs_pol
== '+' ? V4L2_DV_VSYNC_POS_POL
: 0),
1382 if (v4l2_detect_gtf(stdi
->lcf
+ 1, hfreq
, stdi
->lcvs
,
1383 (stdi
->hs_pol
== '+' ? V4L2_DV_HSYNC_POS_POL
: 0) |
1384 (stdi
->vs_pol
== '+' ? V4L2_DV_VSYNC_POS_POL
: 0),
1385 state
->aspect_ratio
, timings
))
1388 v4l2_dbg(2, debug
, sd
,
1389 "%s: No format candidate found for lcvs = %d, lcf=%d, bl = %d, %chsync, %cvsync\n",
1390 __func__
, stdi
->lcvs
, stdi
->lcf
, stdi
->bl
,
1391 stdi
->hs_pol
, stdi
->vs_pol
);
1396 static int read_stdi(struct v4l2_subdev
*sd
, struct stdi_readback
*stdi
)
1398 struct adv7604_state
*state
= to_state(sd
);
1399 const struct adv7604_chip_info
*info
= state
->info
;
1402 if (no_lock_stdi(sd
) || no_lock_sspd(sd
)) {
1403 v4l2_dbg(2, debug
, sd
, "%s: STDI and/or SSPD not locked\n", __func__
);
1408 stdi
->bl
= cp_read16(sd
, 0xb1, 0x3fff);
1409 stdi
->lcf
= cp_read16(sd
, info
->lcf_reg
, 0x7ff);
1410 stdi
->lcvs
= cp_read(sd
, 0xb3) >> 3;
1411 stdi
->interlaced
= io_read(sd
, 0x12) & 0x10;
1413 if (adv7604_has_afe(state
)) {
1415 polarity
= cp_read(sd
, 0xb5);
1416 if ((polarity
& 0x03) == 0x01) {
1417 stdi
->hs_pol
= polarity
& 0x10
1418 ? (polarity
& 0x08 ? '+' : '-') : 'x';
1419 stdi
->vs_pol
= polarity
& 0x40
1420 ? (polarity
& 0x20 ? '+' : '-') : 'x';
1426 polarity
= hdmi_read(sd
, 0x05);
1427 stdi
->hs_pol
= polarity
& 0x20 ? '+' : '-';
1428 stdi
->vs_pol
= polarity
& 0x10 ? '+' : '-';
1431 if (no_lock_stdi(sd
) || no_lock_sspd(sd
)) {
1432 v4l2_dbg(2, debug
, sd
,
1433 "%s: signal lost during readout of STDI/SSPD\n", __func__
);
1437 if (stdi
->lcf
< 239 || stdi
->bl
< 8 || stdi
->bl
== 0x3fff) {
1438 v4l2_dbg(2, debug
, sd
, "%s: invalid signal\n", __func__
);
1439 memset(stdi
, 0, sizeof(struct stdi_readback
));
1443 v4l2_dbg(2, debug
, sd
,
1444 "%s: lcf (frame height - 1) = %d, bl = %d, lcvs (vsync) = %d, %chsync, %cvsync, %s\n",
1445 __func__
, stdi
->lcf
, stdi
->bl
, stdi
->lcvs
,
1446 stdi
->hs_pol
, stdi
->vs_pol
,
1447 stdi
->interlaced
? "interlaced" : "progressive");
1452 static int adv7604_enum_dv_timings(struct v4l2_subdev
*sd
,
1453 struct v4l2_enum_dv_timings
*timings
)
1455 struct adv7604_state
*state
= to_state(sd
);
1457 if (timings
->index
>= ARRAY_SIZE(adv7604_timings
) - 1)
1460 if (timings
->pad
>= state
->source_pad
)
1463 memset(timings
->reserved
, 0, sizeof(timings
->reserved
));
1464 timings
->timings
= adv7604_timings
[timings
->index
];
1468 static int adv7604_dv_timings_cap(struct v4l2_subdev
*sd
,
1469 struct v4l2_dv_timings_cap
*cap
)
1471 struct adv7604_state
*state
= to_state(sd
);
1473 if (cap
->pad
>= state
->source_pad
)
1476 cap
->type
= V4L2_DV_BT_656_1120
;
1477 cap
->bt
.max_width
= 1920;
1478 cap
->bt
.max_height
= 1200;
1479 cap
->bt
.min_pixelclock
= 25000000;
1482 case ADV7604_PAD_HDMI_PORT_A
:
1483 case ADV7604_PAD_HDMI_PORT_B
:
1484 case ADV7604_PAD_HDMI_PORT_C
:
1485 case ADV7604_PAD_HDMI_PORT_D
:
1486 cap
->bt
.max_pixelclock
= 225000000;
1488 case ADV7604_PAD_VGA_RGB
:
1489 case ADV7604_PAD_VGA_COMP
:
1491 cap
->bt
.max_pixelclock
= 170000000;
1495 cap
->bt
.standards
= V4L2_DV_BT_STD_CEA861
| V4L2_DV_BT_STD_DMT
|
1496 V4L2_DV_BT_STD_GTF
| V4L2_DV_BT_STD_CVT
;
1497 cap
->bt
.capabilities
= V4L2_DV_BT_CAP_PROGRESSIVE
|
1498 V4L2_DV_BT_CAP_REDUCED_BLANKING
| V4L2_DV_BT_CAP_CUSTOM
;
1502 /* Fill the optional fields .standards and .flags in struct v4l2_dv_timings
1503 if the format is listed in adv7604_timings[] */
1504 static void adv7604_fill_optional_dv_timings_fields(struct v4l2_subdev
*sd
,
1505 struct v4l2_dv_timings
*timings
)
1509 for (i
= 0; adv7604_timings
[i
].bt
.width
; i
++) {
1510 if (v4l2_match_dv_timings(timings
, &adv7604_timings
[i
],
1511 is_digital_input(sd
) ? 250000 : 1000000)) {
1512 *timings
= adv7604_timings
[i
];
1518 static unsigned int adv7604_read_hdmi_pixelclock(struct v4l2_subdev
*sd
)
1523 a
= hdmi_read(sd
, 0x06);
1524 b
= hdmi_read(sd
, 0x3b);
1527 freq
= a
* 1000000 + ((b
& 0x30) >> 4) * 250000;
1530 /* adjust for deep color mode */
1531 unsigned bits_per_channel
= ((hdmi_read(sd
, 0x0b) & 0x60) >> 4) + 8;
1533 freq
= freq
* 8 / bits_per_channel
;
1539 static unsigned int adv7611_read_hdmi_pixelclock(struct v4l2_subdev
*sd
)
1543 a
= hdmi_read(sd
, 0x51);
1544 b
= hdmi_read(sd
, 0x52);
1547 return ((a
<< 1) | (b
>> 7)) * 1000000 + (b
& 0x7f) * 1000000 / 128;
1550 static int adv7604_query_dv_timings(struct v4l2_subdev
*sd
,
1551 struct v4l2_dv_timings
*timings
)
1553 struct adv7604_state
*state
= to_state(sd
);
1554 const struct adv7604_chip_info
*info
= state
->info
;
1555 struct v4l2_bt_timings
*bt
= &timings
->bt
;
1556 struct stdi_readback stdi
;
1561 memset(timings
, 0, sizeof(struct v4l2_dv_timings
));
1563 if (no_signal(sd
)) {
1564 state
->restart_stdi_once
= true;
1565 v4l2_dbg(1, debug
, sd
, "%s: no valid signal\n", __func__
);
1570 if (read_stdi(sd
, &stdi
)) {
1571 v4l2_dbg(1, debug
, sd
, "%s: STDI/SSPD not locked\n", __func__
);
1574 bt
->interlaced
= stdi
.interlaced
?
1575 V4L2_DV_INTERLACED
: V4L2_DV_PROGRESSIVE
;
1577 if (is_digital_input(sd
)) {
1578 timings
->type
= V4L2_DV_BT_656_1120
;
1580 /* FIXME: All masks are incorrect for ADV7611 */
1581 bt
->width
= hdmi_read16(sd
, 0x07, 0xfff);
1582 bt
->height
= hdmi_read16(sd
, 0x09, 0xfff);
1583 bt
->pixelclock
= info
->read_hdmi_pixelclock(sd
);
1584 bt
->hfrontporch
= hdmi_read16(sd
, 0x20, 0x3ff);
1585 bt
->hsync
= hdmi_read16(sd
, 0x22, 0x3ff);
1586 bt
->hbackporch
= hdmi_read16(sd
, 0x24, 0x3ff);
1587 bt
->vfrontporch
= hdmi_read16(sd
, 0x2a, 0x1fff) / 2;
1588 bt
->vsync
= hdmi_read16(sd
, 0x2e, 0x1fff) / 2;
1589 bt
->vbackporch
= hdmi_read16(sd
, 0x32, 0x1fff) / 2;
1590 bt
->polarities
= ((hdmi_read(sd
, 0x05) & 0x10) ? V4L2_DV_VSYNC_POS_POL
: 0) |
1591 ((hdmi_read(sd
, 0x05) & 0x20) ? V4L2_DV_HSYNC_POS_POL
: 0);
1592 if (bt
->interlaced
== V4L2_DV_INTERLACED
) {
1593 bt
->height
+= hdmi_read16(sd
, 0x0b, 0xfff);
1594 bt
->il_vfrontporch
= hdmi_read16(sd
, 0x2c, 0x1fff) / 2;
1595 bt
->il_vsync
= hdmi_read16(sd
, 0x30, 0x1fff) / 2;
1596 bt
->vbackporch
= hdmi_read16(sd
, 0x34, 0x1fff) / 2;
1598 adv7604_fill_optional_dv_timings_fields(sd
, timings
);
1601 * Since LCVS values are inaccurate [REF_03, p. 275-276],
1602 * stdi2dv_timings() is called with lcvs +-1 if the first attempt fails.
1604 if (!stdi2dv_timings(sd
, &stdi
, timings
))
1607 v4l2_dbg(1, debug
, sd
, "%s: lcvs + 1 = %d\n", __func__
, stdi
.lcvs
);
1608 if (!stdi2dv_timings(sd
, &stdi
, timings
))
1611 v4l2_dbg(1, debug
, sd
, "%s: lcvs - 1 = %d\n", __func__
, stdi
.lcvs
);
1612 if (stdi2dv_timings(sd
, &stdi
, timings
)) {
1614 * The STDI block may measure wrong values, especially
1615 * for lcvs and lcf. If the driver can not find any
1616 * valid timing, the STDI block is restarted to measure
1617 * the video timings again. The function will return an
1618 * error, but the restart of STDI will generate a new
1619 * STDI interrupt and the format detection process will
1622 if (state
->restart_stdi_once
) {
1623 v4l2_dbg(1, debug
, sd
, "%s: restart STDI\n", __func__
);
1624 /* TODO restart STDI for Sync Channel 2 */
1625 /* enter one-shot mode */
1626 cp_write_clr_set(sd
, 0x86, 0x06, 0x00);
1627 /* trigger STDI restart */
1628 cp_write_clr_set(sd
, 0x86, 0x06, 0x04);
1629 /* reset to continuous mode */
1630 cp_write_clr_set(sd
, 0x86, 0x06, 0x02);
1631 state
->restart_stdi_once
= false;
1634 v4l2_dbg(1, debug
, sd
, "%s: format not supported\n", __func__
);
1637 state
->restart_stdi_once
= true;
1641 if (no_signal(sd
)) {
1642 v4l2_dbg(1, debug
, sd
, "%s: signal lost during readout\n", __func__
);
1643 memset(timings
, 0, sizeof(struct v4l2_dv_timings
));
1647 if ((is_analog_input(sd
) && bt
->pixelclock
> 170000000) ||
1648 (is_digital_input(sd
) && bt
->pixelclock
> 225000000)) {
1649 v4l2_dbg(1, debug
, sd
, "%s: pixelclock out of range %d\n",
1650 __func__
, (u32
)bt
->pixelclock
);
1655 v4l2_print_dv_timings(sd
->name
, "adv7604_query_dv_timings: ",
1661 static int adv7604_s_dv_timings(struct v4l2_subdev
*sd
,
1662 struct v4l2_dv_timings
*timings
)
1664 struct adv7604_state
*state
= to_state(sd
);
1665 struct v4l2_bt_timings
*bt
;
1671 if (v4l2_match_dv_timings(&state
->timings
, timings
, 0)) {
1672 v4l2_dbg(1, debug
, sd
, "%s: no change\n", __func__
);
1678 if ((is_analog_input(sd
) && bt
->pixelclock
> 170000000) ||
1679 (is_digital_input(sd
) && bt
->pixelclock
> 225000000)) {
1680 v4l2_dbg(1, debug
, sd
, "%s: pixelclock out of range %d\n",
1681 __func__
, (u32
)bt
->pixelclock
);
1685 adv7604_fill_optional_dv_timings_fields(sd
, timings
);
1687 state
->timings
= *timings
;
1689 cp_write_clr_set(sd
, 0x91, 0x40, bt
->interlaced
? 0x40 : 0x00);
1691 /* Use prim_mode and vid_std when available */
1692 err
= configure_predefined_video_timings(sd
, timings
);
1694 /* custom settings when the video format
1695 does not have prim_mode/vid_std */
1696 configure_custom_video_timings(sd
, bt
);
1699 set_rgb_quantization_range(sd
);
1702 v4l2_print_dv_timings(sd
->name
, "adv7604_s_dv_timings: ",
1707 static int adv7604_g_dv_timings(struct v4l2_subdev
*sd
,
1708 struct v4l2_dv_timings
*timings
)
1710 struct adv7604_state
*state
= to_state(sd
);
1712 *timings
= state
->timings
;
1716 static void adv7604_set_termination(struct v4l2_subdev
*sd
, bool enable
)
1718 hdmi_write(sd
, 0x01, enable
? 0x00 : 0x78);
1721 static void adv7611_set_termination(struct v4l2_subdev
*sd
, bool enable
)
1723 hdmi_write(sd
, 0x83, enable
? 0xfe : 0xff);
1726 static void enable_input(struct v4l2_subdev
*sd
)
1728 struct adv7604_state
*state
= to_state(sd
);
1730 if (is_analog_input(sd
)) {
1731 io_write(sd
, 0x15, 0xb0); /* Disable Tristate of Pins (no audio) */
1732 } else if (is_digital_input(sd
)) {
1733 hdmi_write_clr_set(sd
, 0x00, 0x03, state
->selected_input
);
1734 state
->info
->set_termination(sd
, true);
1735 io_write(sd
, 0x15, 0xa0); /* Disable Tristate of Pins */
1736 hdmi_write_clr_set(sd
, 0x1a, 0x10, 0x00); /* Unmute audio */
1738 v4l2_dbg(2, debug
, sd
, "%s: Unknown port %d selected\n",
1739 __func__
, state
->selected_input
);
1743 static void disable_input(struct v4l2_subdev
*sd
)
1745 struct adv7604_state
*state
= to_state(sd
);
1747 hdmi_write_clr_set(sd
, 0x1a, 0x10, 0x10); /* Mute audio */
1748 msleep(16); /* 512 samples with >= 32 kHz sample rate [REF_03, c. 7.16.10] */
1749 io_write(sd
, 0x15, 0xbe); /* Tristate all outputs from video core */
1750 state
->info
->set_termination(sd
, false);
1753 static void select_input(struct v4l2_subdev
*sd
)
1755 struct adv7604_state
*state
= to_state(sd
);
1756 const struct adv7604_chip_info
*info
= state
->info
;
1758 if (is_analog_input(sd
)) {
1759 adv7604_write_reg_seq(sd
, info
->recommended_settings
[0]);
1761 afe_write(sd
, 0x00, 0x08); /* power up ADC */
1762 afe_write(sd
, 0x01, 0x06); /* power up Analog Front End */
1763 afe_write(sd
, 0xc8, 0x00); /* phase control */
1764 } else if (is_digital_input(sd
)) {
1765 hdmi_write(sd
, 0x00, state
->selected_input
& 0x03);
1767 adv7604_write_reg_seq(sd
, info
->recommended_settings
[1]);
1769 if (adv7604_has_afe(state
)) {
1770 afe_write(sd
, 0x00, 0xff); /* power down ADC */
1771 afe_write(sd
, 0x01, 0xfe); /* power down Analog Front End */
1772 afe_write(sd
, 0xc8, 0x40); /* phase control */
1775 cp_write(sd
, 0x3e, 0x00); /* CP core pre-gain control */
1776 cp_write(sd
, 0xc3, 0x39); /* CP coast control. Graphics mode */
1777 cp_write(sd
, 0x40, 0x80); /* CP core pre-gain control. Graphics mode */
1779 v4l2_dbg(2, debug
, sd
, "%s: Unknown port %d selected\n",
1780 __func__
, state
->selected_input
);
1784 static int adv7604_s_routing(struct v4l2_subdev
*sd
,
1785 u32 input
, u32 output
, u32 config
)
1787 struct adv7604_state
*state
= to_state(sd
);
1789 v4l2_dbg(2, debug
, sd
, "%s: input %d, selected input %d",
1790 __func__
, input
, state
->selected_input
);
1792 if (input
== state
->selected_input
)
1795 if (input
> state
->info
->max_port
)
1798 state
->selected_input
= input
;
1809 static int adv7604_enum_mbus_code(struct v4l2_subdev
*sd
,
1810 struct v4l2_subdev_fh
*fh
,
1811 struct v4l2_subdev_mbus_code_enum
*code
)
1813 struct adv7604_state
*state
= to_state(sd
);
1815 if (code
->index
>= state
->info
->nformats
)
1818 code
->code
= state
->info
->formats
[code
->index
].code
;
1823 static void adv7604_fill_format(struct adv7604_state
*state
,
1824 struct v4l2_mbus_framefmt
*format
)
1826 memset(format
, 0, sizeof(*format
));
1828 format
->width
= state
->timings
.bt
.width
;
1829 format
->height
= state
->timings
.bt
.height
;
1830 format
->field
= V4L2_FIELD_NONE
;
1832 if (state
->timings
.bt
.standards
& V4L2_DV_BT_STD_CEA861
)
1833 format
->colorspace
= (state
->timings
.bt
.height
<= 576) ?
1834 V4L2_COLORSPACE_SMPTE170M
: V4L2_COLORSPACE_REC709
;
1838 * Compute the op_ch_sel value required to obtain on the bus the component order
1839 * corresponding to the selected format taking into account bus reordering
1840 * applied by the board at the output of the device.
1842 * The following table gives the op_ch_value from the format component order
1843 * (expressed as op_ch_sel value in column) and the bus reordering (expressed as
1844 * adv7604_bus_order value in row).
1846 * | GBR(0) GRB(1) BGR(2) RGB(3) BRG(4) RBG(5)
1847 * ----------+-------------------------------------------------
1848 * RGB (NOP) | GBR GRB BGR RGB BRG RBG
1849 * GRB (1-2) | BGR RGB GBR GRB RBG BRG
1850 * RBG (2-3) | GRB GBR BRG RBG BGR RGB
1851 * BGR (1-3) | RBG BRG RGB BGR GRB GBR
1852 * BRG (ROR) | BRG RBG GRB GBR RGB BGR
1853 * GBR (ROL) | RGB BGR RBG BRG GBR GRB
1855 static unsigned int adv7604_op_ch_sel(struct adv7604_state
*state
)
1857 #define _SEL(a,b,c,d,e,f) { \
1858 ADV7604_OP_CH_SEL_##a, ADV7604_OP_CH_SEL_##b, ADV7604_OP_CH_SEL_##c, \
1859 ADV7604_OP_CH_SEL_##d, ADV7604_OP_CH_SEL_##e, ADV7604_OP_CH_SEL_##f }
1860 #define _BUS(x) [ADV7604_BUS_ORDER_##x]
1862 static const unsigned int op_ch_sel
[6][6] = {
1863 _BUS(RGB
) /* NOP */ = _SEL(GBR
, GRB
, BGR
, RGB
, BRG
, RBG
),
1864 _BUS(GRB
) /* 1-2 */ = _SEL(BGR
, RGB
, GBR
, GRB
, RBG
, BRG
),
1865 _BUS(RBG
) /* 2-3 */ = _SEL(GRB
, GBR
, BRG
, RBG
, BGR
, RGB
),
1866 _BUS(BGR
) /* 1-3 */ = _SEL(RBG
, BRG
, RGB
, BGR
, GRB
, GBR
),
1867 _BUS(BRG
) /* ROR */ = _SEL(BRG
, RBG
, GRB
, GBR
, RGB
, BGR
),
1868 _BUS(GBR
) /* ROL */ = _SEL(RGB
, BGR
, RBG
, BRG
, GBR
, GRB
),
1871 return op_ch_sel
[state
->pdata
.bus_order
][state
->format
->op_ch_sel
>> 5];
1874 static void adv7604_setup_format(struct adv7604_state
*state
)
1876 struct v4l2_subdev
*sd
= &state
->sd
;
1878 io_write_clr_set(sd
, 0x02, 0x02,
1879 state
->format
->rgb_out
? ADV7604_RGB_OUT
: 0);
1880 io_write(sd
, 0x03, state
->format
->op_format_sel
|
1881 state
->pdata
.op_format_mode_sel
);
1882 io_write_clr_set(sd
, 0x04, 0xe0, adv7604_op_ch_sel(state
));
1883 io_write_clr_set(sd
, 0x05, 0x01,
1884 state
->format
->swap_cb_cr
? ADV7604_OP_SWAP_CB_CR
: 0);
1887 static int adv7604_get_format(struct v4l2_subdev
*sd
, struct v4l2_subdev_fh
*fh
,
1888 struct v4l2_subdev_format
*format
)
1890 struct adv7604_state
*state
= to_state(sd
);
1892 if (format
->pad
!= state
->source_pad
)
1895 adv7604_fill_format(state
, &format
->format
);
1897 if (format
->which
== V4L2_SUBDEV_FORMAT_TRY
) {
1898 struct v4l2_mbus_framefmt
*fmt
;
1900 fmt
= v4l2_subdev_get_try_format(fh
, format
->pad
);
1901 format
->format
.code
= fmt
->code
;
1903 format
->format
.code
= state
->format
->code
;
1909 static int adv7604_set_format(struct v4l2_subdev
*sd
, struct v4l2_subdev_fh
*fh
,
1910 struct v4l2_subdev_format
*format
)
1912 struct adv7604_state
*state
= to_state(sd
);
1913 const struct adv7604_format_info
*info
;
1915 if (format
->pad
!= state
->source_pad
)
1918 info
= adv7604_format_info(state
, format
->format
.code
);
1920 info
= adv7604_format_info(state
, V4L2_MBUS_FMT_YUYV8_2X8
);
1922 adv7604_fill_format(state
, &format
->format
);
1923 format
->format
.code
= info
->code
;
1925 if (format
->which
== V4L2_SUBDEV_FORMAT_TRY
) {
1926 struct v4l2_mbus_framefmt
*fmt
;
1928 fmt
= v4l2_subdev_get_try_format(fh
, format
->pad
);
1929 fmt
->code
= format
->format
.code
;
1931 state
->format
= info
;
1932 adv7604_setup_format(state
);
1938 static int adv7604_isr(struct v4l2_subdev
*sd
, u32 status
, bool *handled
)
1940 struct adv7604_state
*state
= to_state(sd
);
1941 const struct adv7604_chip_info
*info
= state
->info
;
1942 const u8 irq_reg_0x43
= io_read(sd
, 0x43);
1943 const u8 irq_reg_0x6b
= io_read(sd
, 0x6b);
1944 const u8 irq_reg_0x70
= io_read(sd
, 0x70);
1945 u8 fmt_change_digital
;
1950 io_write(sd
, 0x44, irq_reg_0x43
);
1952 io_write(sd
, 0x71, irq_reg_0x70
);
1954 io_write(sd
, 0x6c, irq_reg_0x6b
);
1956 v4l2_dbg(2, debug
, sd
, "%s: ", __func__
);
1959 fmt_change
= irq_reg_0x43
& 0x98;
1960 fmt_change_digital
= is_digital_input(sd
)
1961 ? irq_reg_0x6b
& info
->fmt_change_digital_mask
1964 if (fmt_change
|| fmt_change_digital
) {
1965 v4l2_dbg(1, debug
, sd
,
1966 "%s: fmt_change = 0x%x, fmt_change_digital = 0x%x\n",
1967 __func__
, fmt_change
, fmt_change_digital
);
1969 v4l2_subdev_notify(sd
, ADV7604_FMT_CHANGE
, NULL
);
1975 if (irq_reg_0x6b
& 0x01) {
1976 v4l2_dbg(1, debug
, sd
, "%s: irq %s mode\n", __func__
,
1977 (io_read(sd
, 0x6a) & 0x01) ? "HDMI" : "DVI");
1978 set_rgb_quantization_range(sd
);
1984 tx_5v
= io_read(sd
, 0x70) & info
->cable_det_mask
;
1986 v4l2_dbg(1, debug
, sd
, "%s: tx_5v: 0x%x\n", __func__
, tx_5v
);
1987 io_write(sd
, 0x71, tx_5v
);
1988 adv7604_s_detect_tx_5v_ctrl(sd
);
1995 static int adv7604_get_edid(struct v4l2_subdev
*sd
, struct v4l2_edid
*edid
)
1997 struct adv7604_state
*state
= to_state(sd
);
2000 if (edid
->pad
> ADV7604_PAD_HDMI_PORT_D
)
2002 if (edid
->blocks
== 0)
2004 if (edid
->blocks
> 2)
2006 if (edid
->start_block
> 1)
2008 if (edid
->start_block
== 1)
2011 if (edid
->blocks
> state
->edid
.blocks
)
2012 edid
->blocks
= state
->edid
.blocks
;
2014 switch (edid
->pad
) {
2015 case ADV7604_PAD_HDMI_PORT_A
:
2016 case ADV7604_PAD_HDMI_PORT_B
:
2017 case ADV7604_PAD_HDMI_PORT_C
:
2018 case ADV7604_PAD_HDMI_PORT_D
:
2019 if (state
->edid
.present
& (1 << edid
->pad
))
2020 data
= state
->edid
.edid
;
2030 data
+ edid
->start_block
* 128,
2031 edid
->blocks
* 128);
2035 static int get_edid_spa_location(const u8
*edid
)
2039 if ((edid
[0x7e] != 1) ||
2040 (edid
[0x80] != 0x02) ||
2041 (edid
[0x81] != 0x03)) {
2045 /* search Vendor Specific Data Block (tag 3) */
2046 d
= edid
[0x82] & 0x7f;
2052 u8 tag
= edid
[i
] >> 5;
2053 u8 len
= edid
[i
] & 0x1f;
2055 if ((tag
== 3) && (len
>= 5))
2063 static int adv7604_set_edid(struct v4l2_subdev
*sd
, struct v4l2_edid
*edid
)
2065 struct adv7604_state
*state
= to_state(sd
);
2066 const struct adv7604_chip_info
*info
= state
->info
;
2071 if (edid
->pad
> ADV7604_PAD_HDMI_PORT_D
)
2073 if (edid
->start_block
!= 0)
2075 if (edid
->blocks
== 0) {
2076 /* Disable hotplug and I2C access to EDID RAM from DDC port */
2077 state
->edid
.present
&= ~(1 << edid
->pad
);
2078 adv7604_set_hpd(state
, state
->edid
.present
);
2079 rep_write_clr_set(sd
, info
->edid_enable_reg
, 0x0f, state
->edid
.present
);
2081 /* Fall back to a 16:9 aspect ratio */
2082 state
->aspect_ratio
.numerator
= 16;
2083 state
->aspect_ratio
.denominator
= 9;
2085 if (!state
->edid
.present
)
2086 state
->edid
.blocks
= 0;
2088 v4l2_dbg(2, debug
, sd
, "%s: clear EDID pad %d, edid.present = 0x%x\n",
2089 __func__
, edid
->pad
, state
->edid
.present
);
2092 if (edid
->blocks
> 2) {
2097 v4l2_dbg(2, debug
, sd
, "%s: write EDID pad %d, edid.present = 0x%x\n",
2098 __func__
, edid
->pad
, state
->edid
.present
);
2100 /* Disable hotplug and I2C access to EDID RAM from DDC port */
2101 cancel_delayed_work_sync(&state
->delayed_work_enable_hotplug
);
2102 adv7604_set_hpd(state
, 0);
2103 rep_write_clr_set(sd
, info
->edid_enable_reg
, 0x0f, 0x00);
2105 spa_loc
= get_edid_spa_location(edid
->edid
);
2107 spa_loc
= 0xc0; /* Default value [REF_02, p. 116] */
2109 switch (edid
->pad
) {
2110 case ADV7604_PAD_HDMI_PORT_A
:
2111 state
->spa_port_a
[0] = edid
->edid
[spa_loc
];
2112 state
->spa_port_a
[1] = edid
->edid
[spa_loc
+ 1];
2114 case ADV7604_PAD_HDMI_PORT_B
:
2115 rep_write(sd
, 0x70, edid
->edid
[spa_loc
]);
2116 rep_write(sd
, 0x71, edid
->edid
[spa_loc
+ 1]);
2118 case ADV7604_PAD_HDMI_PORT_C
:
2119 rep_write(sd
, 0x72, edid
->edid
[spa_loc
]);
2120 rep_write(sd
, 0x73, edid
->edid
[spa_loc
+ 1]);
2122 case ADV7604_PAD_HDMI_PORT_D
:
2123 rep_write(sd
, 0x74, edid
->edid
[spa_loc
]);
2124 rep_write(sd
, 0x75, edid
->edid
[spa_loc
+ 1]);
2130 if (info
->type
== ADV7604
) {
2131 rep_write(sd
, 0x76, spa_loc
& 0xff);
2132 rep_write_clr_set(sd
, 0x77, 0x40, (spa_loc
& 0x100) >> 2);
2134 /* FIXME: Where is the SPA location LSB register ? */
2135 rep_write_clr_set(sd
, 0x71, 0x01, (spa_loc
& 0x100) >> 8);
2138 edid
->edid
[spa_loc
] = state
->spa_port_a
[0];
2139 edid
->edid
[spa_loc
+ 1] = state
->spa_port_a
[1];
2141 memcpy(state
->edid
.edid
, edid
->edid
, 128 * edid
->blocks
);
2142 state
->edid
.blocks
= edid
->blocks
;
2143 state
->aspect_ratio
= v4l2_calc_aspect_ratio(edid
->edid
[0x15],
2145 state
->edid
.present
|= 1 << edid
->pad
;
2147 err
= edid_write_block(sd
, 128 * edid
->blocks
, state
->edid
.edid
);
2149 v4l2_err(sd
, "error %d writing edid pad %d\n", err
, edid
->pad
);
2153 /* adv7604 calculates the checksums and enables I2C access to internal
2154 EDID RAM from DDC port. */
2155 rep_write_clr_set(sd
, info
->edid_enable_reg
, 0x0f, state
->edid
.present
);
2157 for (i
= 0; i
< 1000; i
++) {
2158 if (rep_read(sd
, info
->edid_status_reg
) & state
->edid
.present
)
2163 v4l2_err(sd
, "error enabling edid (0x%x)\n", state
->edid
.present
);
2168 /* enable hotplug after 100 ms */
2169 queue_delayed_work(state
->work_queues
,
2170 &state
->delayed_work_enable_hotplug
, HZ
/ 10);
2174 /*********** avi info frame CEA-861-E **************/
2176 static void print_avi_infoframe(struct v4l2_subdev
*sd
)
2184 v4l2_info(sd
, "receive DVI-D signal (AVI infoframe not supported)\n");
2187 if (!(io_read(sd
, 0x60) & 0x01)) {
2188 v4l2_info(sd
, "AVI infoframe not received\n");
2192 if (io_read(sd
, 0x83) & 0x01) {
2193 v4l2_info(sd
, "AVI infoframe checksum error has occurred earlier\n");
2194 io_write(sd
, 0x85, 0x01); /* clear AVI_INF_CKS_ERR_RAW */
2195 if (io_read(sd
, 0x83) & 0x01) {
2196 v4l2_info(sd
, "AVI infoframe checksum error still present\n");
2197 io_write(sd
, 0x85, 0x01); /* clear AVI_INF_CKS_ERR_RAW */
2201 avi_len
= infoframe_read(sd
, 0xe2);
2202 avi_ver
= infoframe_read(sd
, 0xe1);
2203 v4l2_info(sd
, "AVI infoframe version %d (%d byte)\n",
2206 if (avi_ver
!= 0x02)
2209 for (i
= 0; i
< 14; i
++)
2210 buf
[i
] = infoframe_read(sd
, i
);
2213 "\t%02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x\n",
2214 buf
[0], buf
[1], buf
[2], buf
[3], buf
[4], buf
[5], buf
[6], buf
[7],
2215 buf
[8], buf
[9], buf
[10], buf
[11], buf
[12], buf
[13]);
2218 static int adv7604_log_status(struct v4l2_subdev
*sd
)
2220 struct adv7604_state
*state
= to_state(sd
);
2221 const struct adv7604_chip_info
*info
= state
->info
;
2222 struct v4l2_dv_timings timings
;
2223 struct stdi_readback stdi
;
2224 u8 reg_io_0x02
= io_read(sd
, 0x02);
2228 static const char * const csc_coeff_sel_rb
[16] = {
2229 "bypassed", "YPbPr601 -> RGB", "reserved", "YPbPr709 -> RGB",
2230 "reserved", "RGB -> YPbPr601", "reserved", "RGB -> YPbPr709",
2231 "reserved", "YPbPr709 -> YPbPr601", "YPbPr601 -> YPbPr709",
2232 "reserved", "reserved", "reserved", "reserved", "manual"
2234 static const char * const input_color_space_txt
[16] = {
2235 "RGB limited range (16-235)", "RGB full range (0-255)",
2236 "YCbCr Bt.601 (16-235)", "YCbCr Bt.709 (16-235)",
2237 "xvYCC Bt.601", "xvYCC Bt.709",
2238 "YCbCr Bt.601 (0-255)", "YCbCr Bt.709 (0-255)",
2239 "invalid", "invalid", "invalid", "invalid", "invalid",
2240 "invalid", "invalid", "automatic"
2242 static const char * const rgb_quantization_range_txt
[] = {
2244 "RGB limited range (16-235)",
2245 "RGB full range (0-255)",
2247 static const char * const deep_color_mode_txt
[4] = {
2248 "8-bits per channel",
2249 "10-bits per channel",
2250 "12-bits per channel",
2251 "16-bits per channel (not supported)"
2254 v4l2_info(sd
, "-----Chip status-----\n");
2255 v4l2_info(sd
, "Chip power: %s\n", no_power(sd
) ? "off" : "on");
2256 edid_enabled
= rep_read(sd
, info
->edid_status_reg
);
2257 v4l2_info(sd
, "EDID enabled port A: %s, B: %s, C: %s, D: %s\n",
2258 ((edid_enabled
& 0x01) ? "Yes" : "No"),
2259 ((edid_enabled
& 0x02) ? "Yes" : "No"),
2260 ((edid_enabled
& 0x04) ? "Yes" : "No"),
2261 ((edid_enabled
& 0x08) ? "Yes" : "No"));
2262 v4l2_info(sd
, "CEC: %s\n", !!(cec_read(sd
, 0x2a) & 0x01) ?
2263 "enabled" : "disabled");
2265 v4l2_info(sd
, "-----Signal status-----\n");
2266 cable_det
= info
->read_cable_det(sd
);
2267 v4l2_info(sd
, "Cable detected (+5V power) port A: %s, B: %s, C: %s, D: %s\n",
2268 ((cable_det
& 0x01) ? "Yes" : "No"),
2269 ((cable_det
& 0x02) ? "Yes" : "No"),
2270 ((cable_det
& 0x04) ? "Yes" : "No"),
2271 ((cable_det
& 0x08) ? "Yes" : "No"));
2272 v4l2_info(sd
, "TMDS signal detected: %s\n",
2273 no_signal_tmds(sd
) ? "false" : "true");
2274 v4l2_info(sd
, "TMDS signal locked: %s\n",
2275 no_lock_tmds(sd
) ? "false" : "true");
2276 v4l2_info(sd
, "SSPD locked: %s\n", no_lock_sspd(sd
) ? "false" : "true");
2277 v4l2_info(sd
, "STDI locked: %s\n", no_lock_stdi(sd
) ? "false" : "true");
2278 v4l2_info(sd
, "CP locked: %s\n", no_lock_cp(sd
) ? "false" : "true");
2279 v4l2_info(sd
, "CP free run: %s\n",
2280 (!!(cp_read(sd
, 0xff) & 0x10) ? "on" : "off"));
2281 v4l2_info(sd
, "Prim-mode = 0x%x, video std = 0x%x, v_freq = 0x%x\n",
2282 io_read(sd
, 0x01) & 0x0f, io_read(sd
, 0x00) & 0x3f,
2283 (io_read(sd
, 0x01) & 0x70) >> 4);
2285 v4l2_info(sd
, "-----Video Timings-----\n");
2286 if (read_stdi(sd
, &stdi
))
2287 v4l2_info(sd
, "STDI: not locked\n");
2289 v4l2_info(sd
, "STDI: lcf (frame height - 1) = %d, bl = %d, lcvs (vsync) = %d, %s, %chsync, %cvsync\n",
2290 stdi
.lcf
, stdi
.bl
, stdi
.lcvs
,
2291 stdi
.interlaced
? "interlaced" : "progressive",
2292 stdi
.hs_pol
, stdi
.vs_pol
);
2293 if (adv7604_query_dv_timings(sd
, &timings
))
2294 v4l2_info(sd
, "No video detected\n");
2296 v4l2_print_dv_timings(sd
->name
, "Detected format: ",
2298 v4l2_print_dv_timings(sd
->name
, "Configured format: ",
2299 &state
->timings
, true);
2304 v4l2_info(sd
, "-----Color space-----\n");
2305 v4l2_info(sd
, "RGB quantization range ctrl: %s\n",
2306 rgb_quantization_range_txt
[state
->rgb_quantization_range
]);
2307 v4l2_info(sd
, "Input color space: %s\n",
2308 input_color_space_txt
[reg_io_0x02
>> 4]);
2309 v4l2_info(sd
, "Output color space: %s %s, saturator %s\n",
2310 (reg_io_0x02
& 0x02) ? "RGB" : "YCbCr",
2311 (reg_io_0x02
& 0x04) ? "(16-235)" : "(0-255)",
2312 ((reg_io_0x02
& 0x04) ^ (reg_io_0x02
& 0x01)) ?
2313 "enabled" : "disabled");
2314 v4l2_info(sd
, "Color space conversion: %s\n",
2315 csc_coeff_sel_rb
[cp_read(sd
, 0xfc) >> 4]);
2317 if (!is_digital_input(sd
))
2320 v4l2_info(sd
, "-----%s status-----\n", is_hdmi(sd
) ? "HDMI" : "DVI-D");
2321 v4l2_info(sd
, "Digital video port selected: %c\n",
2322 (hdmi_read(sd
, 0x00) & 0x03) + 'A');
2323 v4l2_info(sd
, "HDCP encrypted content: %s\n",
2324 (hdmi_read(sd
, 0x05) & 0x40) ? "true" : "false");
2325 v4l2_info(sd
, "HDCP keys read: %s%s\n",
2326 (hdmi_read(sd
, 0x04) & 0x20) ? "yes" : "no",
2327 (hdmi_read(sd
, 0x04) & 0x10) ? "ERROR" : "");
2329 bool audio_pll_locked
= hdmi_read(sd
, 0x04) & 0x01;
2330 bool audio_sample_packet_detect
= hdmi_read(sd
, 0x18) & 0x01;
2331 bool audio_mute
= io_read(sd
, 0x65) & 0x40;
2333 v4l2_info(sd
, "Audio: pll %s, samples %s, %s\n",
2334 audio_pll_locked
? "locked" : "not locked",
2335 audio_sample_packet_detect
? "detected" : "not detected",
2336 audio_mute
? "muted" : "enabled");
2337 if (audio_pll_locked
&& audio_sample_packet_detect
) {
2338 v4l2_info(sd
, "Audio format: %s\n",
2339 (hdmi_read(sd
, 0x07) & 0x20) ? "multi-channel" : "stereo");
2341 v4l2_info(sd
, "Audio CTS: %u\n", (hdmi_read(sd
, 0x5b) << 12) +
2342 (hdmi_read(sd
, 0x5c) << 8) +
2343 (hdmi_read(sd
, 0x5d) & 0xf0));
2344 v4l2_info(sd
, "Audio N: %u\n", ((hdmi_read(sd
, 0x5d) & 0x0f) << 16) +
2345 (hdmi_read(sd
, 0x5e) << 8) +
2346 hdmi_read(sd
, 0x5f));
2347 v4l2_info(sd
, "AV Mute: %s\n", (hdmi_read(sd
, 0x04) & 0x40) ? "on" : "off");
2349 v4l2_info(sd
, "Deep color mode: %s\n", deep_color_mode_txt
[(hdmi_read(sd
, 0x0b) & 0x60) >> 5]);
2351 print_avi_infoframe(sd
);
2357 /* ----------------------------------------------------------------------- */
2359 static const struct v4l2_ctrl_ops adv7604_ctrl_ops
= {
2360 .s_ctrl
= adv7604_s_ctrl
,
2363 static const struct v4l2_subdev_core_ops adv7604_core_ops
= {
2364 .log_status
= adv7604_log_status
,
2365 .interrupt_service_routine
= adv7604_isr
,
2366 #ifdef CONFIG_VIDEO_ADV_DEBUG
2367 .g_register
= adv7604_g_register
,
2368 .s_register
= adv7604_s_register
,
2372 static const struct v4l2_subdev_video_ops adv7604_video_ops
= {
2373 .s_routing
= adv7604_s_routing
,
2374 .g_input_status
= adv7604_g_input_status
,
2375 .s_dv_timings
= adv7604_s_dv_timings
,
2376 .g_dv_timings
= adv7604_g_dv_timings
,
2377 .query_dv_timings
= adv7604_query_dv_timings
,
2380 static const struct v4l2_subdev_pad_ops adv7604_pad_ops
= {
2381 .enum_mbus_code
= adv7604_enum_mbus_code
,
2382 .get_fmt
= adv7604_get_format
,
2383 .set_fmt
= adv7604_set_format
,
2384 .get_edid
= adv7604_get_edid
,
2385 .set_edid
= adv7604_set_edid
,
2386 .dv_timings_cap
= adv7604_dv_timings_cap
,
2387 .enum_dv_timings
= adv7604_enum_dv_timings
,
2390 static const struct v4l2_subdev_ops adv7604_ops
= {
2391 .core
= &adv7604_core_ops
,
2392 .video
= &adv7604_video_ops
,
2393 .pad
= &adv7604_pad_ops
,
2396 /* -------------------------- custom ctrls ---------------------------------- */
2398 static const struct v4l2_ctrl_config adv7604_ctrl_analog_sampling_phase
= {
2399 .ops
= &adv7604_ctrl_ops
,
2400 .id
= V4L2_CID_ADV_RX_ANALOG_SAMPLING_PHASE
,
2401 .name
= "Analog Sampling Phase",
2402 .type
= V4L2_CTRL_TYPE_INTEGER
,
2409 static const struct v4l2_ctrl_config adv7604_ctrl_free_run_color_manual
= {
2410 .ops
= &adv7604_ctrl_ops
,
2411 .id
= V4L2_CID_ADV_RX_FREE_RUN_COLOR_MANUAL
,
2412 .name
= "Free Running Color, Manual",
2413 .type
= V4L2_CTRL_TYPE_BOOLEAN
,
2420 static const struct v4l2_ctrl_config adv7604_ctrl_free_run_color
= {
2421 .ops
= &adv7604_ctrl_ops
,
2422 .id
= V4L2_CID_ADV_RX_FREE_RUN_COLOR
,
2423 .name
= "Free Running Color",
2424 .type
= V4L2_CTRL_TYPE_INTEGER
,
2431 /* ----------------------------------------------------------------------- */
2433 static int adv7604_core_init(struct v4l2_subdev
*sd
)
2435 struct adv7604_state
*state
= to_state(sd
);
2436 const struct adv7604_chip_info
*info
= state
->info
;
2437 struct adv7604_platform_data
*pdata
= &state
->pdata
;
2439 hdmi_write(sd
, 0x48,
2440 (pdata
->disable_pwrdnb
? 0x80 : 0) |
2441 (pdata
->disable_cable_det_rst
? 0x40 : 0));
2445 if (pdata
->default_input
>= 0 &&
2446 pdata
->default_input
< state
->source_pad
) {
2447 state
->selected_input
= pdata
->default_input
;
2453 io_write(sd
, 0x0c, 0x42); /* Power up part and power down VDP */
2454 io_write(sd
, 0x0b, 0x44); /* Power down ESDP block */
2455 cp_write(sd
, 0xcf, 0x01); /* Power down macrovision */
2458 io_write_clr_set(sd
, 0x02, 0x0f,
2459 pdata
->alt_gamma
<< 3 |
2460 pdata
->op_656_range
<< 2 |
2461 pdata
->alt_data_sat
<< 0);
2462 io_write_clr_set(sd
, 0x05, 0x0e, pdata
->blank_data
<< 3 |
2463 pdata
->insert_av_codes
<< 2 |
2464 pdata
->replicate_av_codes
<< 1);
2465 adv7604_setup_format(state
);
2467 cp_write(sd
, 0x69, 0x30); /* Enable CP CSC */
2469 /* VS, HS polarities */
2470 io_write(sd
, 0x06, 0xa0 | pdata
->inv_vs_pol
<< 2 |
2471 pdata
->inv_hs_pol
<< 1 | pdata
->inv_llc_pol
);
2473 /* Adjust drive strength */
2474 io_write(sd
, 0x14, 0x40 | pdata
->dr_str_data
<< 4 |
2475 pdata
->dr_str_clk
<< 2 |
2476 pdata
->dr_str_sync
);
2478 cp_write(sd
, 0xba, (pdata
->hdmi_free_run_mode
<< 1) | 0x01); /* HDMI free run */
2479 cp_write(sd
, 0xf3, 0xdc); /* Low threshold to enter/exit free run mode */
2480 cp_write(sd
, 0xf9, 0x23); /* STDI ch. 1 - LCVS change threshold -
2481 ADI recommended setting [REF_01, c. 2.3.3] */
2482 cp_write(sd
, 0x45, 0x23); /* STDI ch. 2 - LCVS change threshold -
2483 ADI recommended setting [REF_01, c. 2.3.3] */
2484 cp_write(sd
, 0xc9, 0x2d); /* use prim_mode and vid_std as free run resolution
2485 for digital formats */
2488 hdmi_write_clr_set(sd
, 0x15, 0x03, 0x03); /* Mute on FIFO over-/underflow [REF_01, c. 1.2.18] */
2489 hdmi_write_clr_set(sd
, 0x1a, 0x0e, 0x08); /* Wait 1 s before unmute */
2490 hdmi_write_clr_set(sd
, 0x68, 0x06, 0x06); /* FIFO reset on over-/underflow [REF_01, c. 1.2.19] */
2492 /* TODO from platform data */
2493 afe_write(sd
, 0xb5, 0x01); /* Setting MCLK to 256Fs */
2495 if (adv7604_has_afe(state
)) {
2496 afe_write(sd
, 0x02, pdata
->ain_sel
); /* Select analog input muxing mode */
2497 io_write_clr_set(sd
, 0x30, 1 << 4, pdata
->output_bus_lsb_to_msb
<< 4);
2501 io_write(sd
, 0x40, 0xc0 | pdata
->int1_config
); /* Configure INT1 */
2502 io_write(sd
, 0x46, 0x98); /* Enable SSPD, STDI and CP unlocked interrupts */
2503 io_write(sd
, 0x6e, info
->fmt_change_digital_mask
); /* Enable V_LOCKED and DE_REGEN_LCK interrupts */
2504 io_write(sd
, 0x73, info
->cable_det_mask
); /* Enable cable detection (+5v) interrupts */
2505 info
->setup_irqs(sd
);
2507 return v4l2_ctrl_handler_setup(sd
->ctrl_handler
);
2510 static void adv7604_setup_irqs(struct v4l2_subdev
*sd
)
2512 io_write(sd
, 0x41, 0xd7); /* STDI irq for any change, disable INT2 */
2515 static void adv7611_setup_irqs(struct v4l2_subdev
*sd
)
2517 io_write(sd
, 0x41, 0xd0); /* STDI irq for any change, disable INT2 */
2520 static void adv7604_unregister_clients(struct adv7604_state
*state
)
2524 for (i
= 1; i
< ARRAY_SIZE(state
->i2c_clients
); ++i
) {
2525 if (state
->i2c_clients
[i
])
2526 i2c_unregister_device(state
->i2c_clients
[i
]);
2530 static struct i2c_client
*adv7604_dummy_client(struct v4l2_subdev
*sd
,
2533 struct i2c_client
*client
= v4l2_get_subdevdata(sd
);
2536 io_write(sd
, io_reg
, addr
<< 1);
2537 return i2c_new_dummy(client
->adapter
, io_read(sd
, io_reg
) >> 1);
2540 static const struct adv7604_reg_seq adv7604_recommended_settings_afe
[] = {
2541 /* reset ADI recommended settings for HDMI: */
2542 /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 4. */
2543 { ADV7604_REG(ADV7604_PAGE_HDMI
, 0x0d), 0x04 }, /* HDMI filter optimization */
2544 { ADV7604_REG(ADV7604_PAGE_HDMI
, 0x0d), 0x04 }, /* HDMI filter optimization */
2545 { ADV7604_REG(ADV7604_PAGE_HDMI
, 0x3d), 0x00 }, /* DDC bus active pull-up control */
2546 { ADV7604_REG(ADV7604_PAGE_HDMI
, 0x3e), 0x74 }, /* TMDS PLL optimization */
2547 { ADV7604_REG(ADV7604_PAGE_HDMI
, 0x4e), 0x3b }, /* TMDS PLL optimization */
2548 { ADV7604_REG(ADV7604_PAGE_HDMI
, 0x57), 0x74 }, /* TMDS PLL optimization */
2549 { ADV7604_REG(ADV7604_PAGE_HDMI
, 0x58), 0x63 }, /* TMDS PLL optimization */
2550 { ADV7604_REG(ADV7604_PAGE_HDMI
, 0x8d), 0x18 }, /* equaliser */
2551 { ADV7604_REG(ADV7604_PAGE_HDMI
, 0x8e), 0x34 }, /* equaliser */
2552 { ADV7604_REG(ADV7604_PAGE_HDMI
, 0x93), 0x88 }, /* equaliser */
2553 { ADV7604_REG(ADV7604_PAGE_HDMI
, 0x94), 0x2e }, /* equaliser */
2554 { ADV7604_REG(ADV7604_PAGE_HDMI
, 0x96), 0x00 }, /* enable automatic EQ changing */
2556 /* set ADI recommended settings for digitizer */
2557 /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 17. */
2558 { ADV7604_REG(ADV7604_PAGE_AFE
, 0x12), 0x7b }, /* ADC noise shaping filter controls */
2559 { ADV7604_REG(ADV7604_PAGE_AFE
, 0x0c), 0x1f }, /* CP core gain controls */
2560 { ADV7604_REG(ADV7604_PAGE_CP
, 0x3e), 0x04 }, /* CP core pre-gain control */
2561 { ADV7604_REG(ADV7604_PAGE_CP
, 0xc3), 0x39 }, /* CP coast control. Graphics mode */
2562 { ADV7604_REG(ADV7604_PAGE_CP
, 0x40), 0x5c }, /* CP core pre-gain control. Graphics mode */
2564 { ADV7604_REG_SEQ_TERM
, 0 },
2567 static const struct adv7604_reg_seq adv7604_recommended_settings_hdmi
[] = {
2568 /* set ADI recommended settings for HDMI: */
2569 /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 4. */
2570 { ADV7604_REG(ADV7604_PAGE_HDMI
, 0x0d), 0x84 }, /* HDMI filter optimization */
2571 { ADV7604_REG(ADV7604_PAGE_HDMI
, 0x3d), 0x10 }, /* DDC bus active pull-up control */
2572 { ADV7604_REG(ADV7604_PAGE_HDMI
, 0x3e), 0x39 }, /* TMDS PLL optimization */
2573 { ADV7604_REG(ADV7604_PAGE_HDMI
, 0x4e), 0x3b }, /* TMDS PLL optimization */
2574 { ADV7604_REG(ADV7604_PAGE_HDMI
, 0x57), 0xb6 }, /* TMDS PLL optimization */
2575 { ADV7604_REG(ADV7604_PAGE_HDMI
, 0x58), 0x03 }, /* TMDS PLL optimization */
2576 { ADV7604_REG(ADV7604_PAGE_HDMI
, 0x8d), 0x18 }, /* equaliser */
2577 { ADV7604_REG(ADV7604_PAGE_HDMI
, 0x8e), 0x34 }, /* equaliser */
2578 { ADV7604_REG(ADV7604_PAGE_HDMI
, 0x93), 0x8b }, /* equaliser */
2579 { ADV7604_REG(ADV7604_PAGE_HDMI
, 0x94), 0x2d }, /* equaliser */
2580 { ADV7604_REG(ADV7604_PAGE_HDMI
, 0x96), 0x01 }, /* enable automatic EQ changing */
2582 /* reset ADI recommended settings for digitizer */
2583 /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 17. */
2584 { ADV7604_REG(ADV7604_PAGE_AFE
, 0x12), 0xfb }, /* ADC noise shaping filter controls */
2585 { ADV7604_REG(ADV7604_PAGE_AFE
, 0x0c), 0x0d }, /* CP core gain controls */
2587 { ADV7604_REG_SEQ_TERM
, 0 },
2590 static const struct adv7604_reg_seq adv7611_recommended_settings_hdmi
[] = {
2591 { ADV7604_REG(ADV7604_PAGE_CP
, 0x6c), 0x00 },
2592 { ADV7604_REG(ADV7604_PAGE_HDMI
, 0x6f), 0x0c },
2593 { ADV7604_REG(ADV7604_PAGE_HDMI
, 0x87), 0x70 },
2594 { ADV7604_REG(ADV7604_PAGE_HDMI
, 0x57), 0xda },
2595 { ADV7604_REG(ADV7604_PAGE_HDMI
, 0x58), 0x01 },
2596 { ADV7604_REG(ADV7604_PAGE_HDMI
, 0x03), 0x98 },
2597 { ADV7604_REG(ADV7604_PAGE_HDMI
, 0x4c), 0x44 },
2598 { ADV7604_REG(ADV7604_PAGE_HDMI
, 0x8d), 0x04 },
2599 { ADV7604_REG(ADV7604_PAGE_HDMI
, 0x8e), 0x1e },
2601 { ADV7604_REG_SEQ_TERM
, 0 },
2604 static const struct adv7604_chip_info adv7604_chip_info
[] = {
2608 .max_port
= ADV7604_PAD_VGA_COMP
,
2610 .edid_enable_reg
= 0x77,
2611 .edid_status_reg
= 0x7d,
2613 .tdms_lock_mask
= 0xe0,
2614 .cable_det_mask
= 0x1e,
2615 .fmt_change_digital_mask
= 0xc1,
2616 .formats
= adv7604_formats
,
2617 .nformats
= ARRAY_SIZE(adv7604_formats
),
2618 .set_termination
= adv7604_set_termination
,
2619 .setup_irqs
= adv7604_setup_irqs
,
2620 .read_hdmi_pixelclock
= adv7604_read_hdmi_pixelclock
,
2621 .read_cable_det
= adv7604_read_cable_det
,
2622 .recommended_settings
= {
2623 [0] = adv7604_recommended_settings_afe
,
2624 [1] = adv7604_recommended_settings_hdmi
,
2626 .num_recommended_settings
= {
2627 [0] = ARRAY_SIZE(adv7604_recommended_settings_afe
),
2628 [1] = ARRAY_SIZE(adv7604_recommended_settings_hdmi
),
2630 .page_mask
= BIT(ADV7604_PAGE_IO
) | BIT(ADV7604_PAGE_AVLINK
) |
2631 BIT(ADV7604_PAGE_CEC
) | BIT(ADV7604_PAGE_INFOFRAME
) |
2632 BIT(ADV7604_PAGE_ESDP
) | BIT(ADV7604_PAGE_DPP
) |
2633 BIT(ADV7604_PAGE_AFE
) | BIT(ADV7604_PAGE_REP
) |
2634 BIT(ADV7604_PAGE_EDID
) | BIT(ADV7604_PAGE_HDMI
) |
2635 BIT(ADV7604_PAGE_TEST
) | BIT(ADV7604_PAGE_CP
) |
2636 BIT(ADV7604_PAGE_VDP
),
2641 .max_port
= ADV7604_PAD_HDMI_PORT_A
,
2643 .edid_enable_reg
= 0x74,
2644 .edid_status_reg
= 0x76,
2646 .tdms_lock_mask
= 0x43,
2647 .cable_det_mask
= 0x01,
2648 .fmt_change_digital_mask
= 0x03,
2649 .formats
= adv7611_formats
,
2650 .nformats
= ARRAY_SIZE(adv7611_formats
),
2651 .set_termination
= adv7611_set_termination
,
2652 .setup_irqs
= adv7611_setup_irqs
,
2653 .read_hdmi_pixelclock
= adv7611_read_hdmi_pixelclock
,
2654 .read_cable_det
= adv7611_read_cable_det
,
2655 .recommended_settings
= {
2656 [1] = adv7611_recommended_settings_hdmi
,
2658 .num_recommended_settings
= {
2659 [1] = ARRAY_SIZE(adv7611_recommended_settings_hdmi
),
2661 .page_mask
= BIT(ADV7604_PAGE_IO
) | BIT(ADV7604_PAGE_CEC
) |
2662 BIT(ADV7604_PAGE_INFOFRAME
) | BIT(ADV7604_PAGE_AFE
) |
2663 BIT(ADV7604_PAGE_REP
) | BIT(ADV7604_PAGE_EDID
) |
2664 BIT(ADV7604_PAGE_HDMI
) | BIT(ADV7604_PAGE_CP
),
2668 static struct i2c_device_id adv7604_i2c_id
[] = {
2669 { "adv7604", (kernel_ulong_t
)&adv7604_chip_info
[ADV7604
] },
2670 { "adv7611", (kernel_ulong_t
)&adv7604_chip_info
[ADV7611
] },
2673 MODULE_DEVICE_TABLE(i2c
, adv7604_i2c_id
);
2675 static struct of_device_id adv7604_of_id
[] __maybe_unused
= {
2676 { .compatible
= "adi,adv7611", .data
= &adv7604_chip_info
[ADV7611
] },
2679 MODULE_DEVICE_TABLE(of
, adv7604_of_id
);
2681 static int adv7604_parse_dt(struct adv7604_state
*state
)
2683 struct v4l2_of_endpoint bus_cfg
;
2684 struct device_node
*endpoint
;
2685 struct device_node
*np
;
2688 np
= state
->i2c_clients
[ADV7604_PAGE_IO
]->dev
.of_node
;
2690 /* Parse the endpoint. */
2691 endpoint
= of_graph_get_next_endpoint(np
, NULL
);
2695 v4l2_of_parse_endpoint(endpoint
, &bus_cfg
);
2696 of_node_put(endpoint
);
2698 flags
= bus_cfg
.bus
.parallel
.flags
;
2700 if (flags
& V4L2_MBUS_HSYNC_ACTIVE_HIGH
)
2701 state
->pdata
.inv_hs_pol
= 1;
2703 if (flags
& V4L2_MBUS_VSYNC_ACTIVE_HIGH
)
2704 state
->pdata
.inv_vs_pol
= 1;
2706 if (flags
& V4L2_MBUS_PCLK_SAMPLE_RISING
)
2707 state
->pdata
.inv_llc_pol
= 1;
2709 if (bus_cfg
.bus_type
== V4L2_MBUS_BT656
) {
2710 state
->pdata
.insert_av_codes
= 1;
2711 state
->pdata
.op_656_range
= 1;
2714 /* Disable the interrupt for now as no DT-based board uses it. */
2715 state
->pdata
.int1_config
= ADV7604_INT1_CONFIG_DISABLED
;
2717 /* Use the default I2C addresses. */
2718 state
->pdata
.i2c_addresses
[ADV7604_PAGE_AVLINK
] = 0x42;
2719 state
->pdata
.i2c_addresses
[ADV7604_PAGE_CEC
] = 0x40;
2720 state
->pdata
.i2c_addresses
[ADV7604_PAGE_INFOFRAME
] = 0x3e;
2721 state
->pdata
.i2c_addresses
[ADV7604_PAGE_ESDP
] = 0x38;
2722 state
->pdata
.i2c_addresses
[ADV7604_PAGE_DPP
] = 0x3c;
2723 state
->pdata
.i2c_addresses
[ADV7604_PAGE_AFE
] = 0x26;
2724 state
->pdata
.i2c_addresses
[ADV7604_PAGE_REP
] = 0x32;
2725 state
->pdata
.i2c_addresses
[ADV7604_PAGE_EDID
] = 0x36;
2726 state
->pdata
.i2c_addresses
[ADV7604_PAGE_HDMI
] = 0x34;
2727 state
->pdata
.i2c_addresses
[ADV7604_PAGE_TEST
] = 0x30;
2728 state
->pdata
.i2c_addresses
[ADV7604_PAGE_CP
] = 0x22;
2729 state
->pdata
.i2c_addresses
[ADV7604_PAGE_VDP
] = 0x24;
2731 /* Hardcode the remaining platform data fields. */
2732 state
->pdata
.disable_pwrdnb
= 0;
2733 state
->pdata
.disable_cable_det_rst
= 0;
2734 state
->pdata
.default_input
= -1;
2735 state
->pdata
.blank_data
= 1;
2736 state
->pdata
.alt_data_sat
= 1;
2737 state
->pdata
.op_format_mode_sel
= ADV7604_OP_FORMAT_MODE0
;
2738 state
->pdata
.bus_order
= ADV7604_BUS_ORDER_RGB
;
2743 static int adv7604_probe(struct i2c_client
*client
,
2744 const struct i2c_device_id
*id
)
2746 static const struct v4l2_dv_timings cea640x480
=
2747 V4L2_DV_BT_CEA_640X480P59_94
;
2748 struct adv7604_state
*state
;
2749 struct v4l2_ctrl_handler
*hdl
;
2750 struct v4l2_subdev
*sd
;
2755 /* Check if the adapter supports the needed features */
2756 if (!i2c_check_functionality(client
->adapter
, I2C_FUNC_SMBUS_BYTE_DATA
))
2758 v4l_dbg(1, debug
, client
, "detecting adv7604 client on address 0x%x\n",
2761 state
= devm_kzalloc(&client
->dev
, sizeof(*state
), GFP_KERNEL
);
2763 v4l_err(client
, "Could not allocate adv7604_state memory!\n");
2767 state
->i2c_clients
[ADV7604_PAGE_IO
] = client
;
2769 /* initialize variables */
2770 state
->restart_stdi_once
= true;
2771 state
->selected_input
= ~0;
2773 if (IS_ENABLED(CONFIG_OF
) && client
->dev
.of_node
) {
2774 const struct of_device_id
*oid
;
2776 oid
= of_match_node(adv7604_of_id
, client
->dev
.of_node
);
2777 state
->info
= oid
->data
;
2779 err
= adv7604_parse_dt(state
);
2781 v4l_err(client
, "DT parsing error\n");
2784 } else if (client
->dev
.platform_data
) {
2785 struct adv7604_platform_data
*pdata
= client
->dev
.platform_data
;
2787 state
->info
= (const struct adv7604_chip_info
*)id
->driver_data
;
2788 state
->pdata
= *pdata
;
2790 v4l_err(client
, "No platform data!\n");
2794 /* Request GPIOs. */
2795 for (i
= 0; i
< state
->info
->num_dv_ports
; ++i
) {
2796 state
->hpd_gpio
[i
] =
2797 devm_gpiod_get_index(&client
->dev
, "hpd", i
);
2798 if (IS_ERR(state
->hpd_gpio
[i
]))
2801 gpiod_direction_output(state
->hpd_gpio
[i
], 0);
2803 v4l_info(client
, "Handling HPD %u GPIO\n", i
);
2806 state
->timings
= cea640x480
;
2807 state
->format
= adv7604_format_info(state
, V4L2_MBUS_FMT_YUYV8_2X8
);
2810 v4l2_i2c_subdev_init(sd
, client
, &adv7604_ops
);
2811 snprintf(sd
->name
, sizeof(sd
->name
), "%s %d-%04x",
2812 id
->name
, i2c_adapter_id(client
->adapter
),
2814 sd
->flags
|= V4L2_SUBDEV_FL_HAS_DEVNODE
;
2817 * Verify that the chip is present. On ADV7604 the RD_INFO register only
2818 * identifies the revision, while on ADV7611 it identifies the model as
2819 * well. Use the HDMI slave address on ADV7604 and RD_INFO on ADV7611.
2821 if (state
->info
->type
== ADV7604
) {
2822 val
= adv_smbus_read_byte_data_check(client
, 0xfb, false);
2824 v4l2_info(sd
, "not an adv7604 on address 0x%x\n",
2829 val
= (adv_smbus_read_byte_data_check(client
, 0xea, false) << 8)
2830 | (adv_smbus_read_byte_data_check(client
, 0xeb, false) << 0);
2831 if (val
!= 0x2051) {
2832 v4l2_info(sd
, "not an adv7611 on address 0x%x\n",
2838 /* control handlers */
2840 v4l2_ctrl_handler_init(hdl
, adv7604_has_afe(state
) ? 9 : 8);
2842 v4l2_ctrl_new_std(hdl
, &adv7604_ctrl_ops
,
2843 V4L2_CID_BRIGHTNESS
, -128, 127, 1, 0);
2844 v4l2_ctrl_new_std(hdl
, &adv7604_ctrl_ops
,
2845 V4L2_CID_CONTRAST
, 0, 255, 1, 128);
2846 v4l2_ctrl_new_std(hdl
, &adv7604_ctrl_ops
,
2847 V4L2_CID_SATURATION
, 0, 255, 1, 128);
2848 v4l2_ctrl_new_std(hdl
, &adv7604_ctrl_ops
,
2849 V4L2_CID_HUE
, 0, 128, 1, 0);
2851 /* private controls */
2852 state
->detect_tx_5v_ctrl
= v4l2_ctrl_new_std(hdl
, NULL
,
2853 V4L2_CID_DV_RX_POWER_PRESENT
, 0,
2854 (1 << state
->info
->num_dv_ports
) - 1, 0, 0);
2855 state
->rgb_quantization_range_ctrl
=
2856 v4l2_ctrl_new_std_menu(hdl
, &adv7604_ctrl_ops
,
2857 V4L2_CID_DV_RX_RGB_RANGE
, V4L2_DV_RGB_RANGE_FULL
,
2858 0, V4L2_DV_RGB_RANGE_AUTO
);
2860 /* custom controls */
2861 if (adv7604_has_afe(state
))
2862 state
->analog_sampling_phase_ctrl
=
2863 v4l2_ctrl_new_custom(hdl
, &adv7604_ctrl_analog_sampling_phase
, NULL
);
2864 state
->free_run_color_manual_ctrl
=
2865 v4l2_ctrl_new_custom(hdl
, &adv7604_ctrl_free_run_color_manual
, NULL
);
2866 state
->free_run_color_ctrl
=
2867 v4l2_ctrl_new_custom(hdl
, &adv7604_ctrl_free_run_color
, NULL
);
2869 sd
->ctrl_handler
= hdl
;
2874 state
->detect_tx_5v_ctrl
->is_private
= true;
2875 state
->rgb_quantization_range_ctrl
->is_private
= true;
2876 if (adv7604_has_afe(state
))
2877 state
->analog_sampling_phase_ctrl
->is_private
= true;
2878 state
->free_run_color_manual_ctrl
->is_private
= true;
2879 state
->free_run_color_ctrl
->is_private
= true;
2881 if (adv7604_s_detect_tx_5v_ctrl(sd
)) {
2886 for (i
= 1; i
< ADV7604_PAGE_MAX
; ++i
) {
2887 if (!(BIT(i
) & state
->info
->page_mask
))
2890 state
->i2c_clients
[i
] =
2891 adv7604_dummy_client(sd
, state
->pdata
.i2c_addresses
[i
],
2893 if (state
->i2c_clients
[i
] == NULL
) {
2895 v4l2_err(sd
, "failed to create i2c client %u\n", i
);
2901 state
->work_queues
= create_singlethread_workqueue(client
->name
);
2902 if (!state
->work_queues
) {
2903 v4l2_err(sd
, "Could not create work queue\n");
2908 INIT_DELAYED_WORK(&state
->delayed_work_enable_hotplug
,
2909 adv7604_delayed_work_enable_hotplug
);
2911 state
->source_pad
= state
->info
->num_dv_ports
2912 + (state
->info
->has_afe
? 2 : 0);
2913 for (i
= 0; i
< state
->source_pad
; ++i
)
2914 state
->pads
[i
].flags
= MEDIA_PAD_FL_SINK
;
2915 state
->pads
[state
->source_pad
].flags
= MEDIA_PAD_FL_SOURCE
;
2917 err
= media_entity_init(&sd
->entity
, state
->source_pad
+ 1,
2920 goto err_work_queues
;
2922 err
= adv7604_core_init(sd
);
2925 v4l2_info(sd
, "%s found @ 0x%x (%s)\n", client
->name
,
2926 client
->addr
<< 1, client
->adapter
->name
);
2928 err
= v4l2_async_register_subdev(sd
);
2935 media_entity_cleanup(&sd
->entity
);
2937 cancel_delayed_work(&state
->delayed_work_enable_hotplug
);
2938 destroy_workqueue(state
->work_queues
);
2940 adv7604_unregister_clients(state
);
2942 v4l2_ctrl_handler_free(hdl
);
2946 /* ----------------------------------------------------------------------- */
2948 static int adv7604_remove(struct i2c_client
*client
)
2950 struct v4l2_subdev
*sd
= i2c_get_clientdata(client
);
2951 struct adv7604_state
*state
= to_state(sd
);
2953 cancel_delayed_work(&state
->delayed_work_enable_hotplug
);
2954 destroy_workqueue(state
->work_queues
);
2955 v4l2_async_unregister_subdev(sd
);
2956 v4l2_device_unregister_subdev(sd
);
2957 media_entity_cleanup(&sd
->entity
);
2958 adv7604_unregister_clients(to_state(sd
));
2959 v4l2_ctrl_handler_free(sd
->ctrl_handler
);
2963 /* ----------------------------------------------------------------------- */
2965 static struct i2c_driver adv7604_driver
= {
2967 .owner
= THIS_MODULE
,
2969 .of_match_table
= of_match_ptr(adv7604_of_id
),
2971 .probe
= adv7604_probe
,
2972 .remove
= adv7604_remove
,
2973 .id_table
= adv7604_i2c_id
,
2976 module_i2c_driver(adv7604_driver
);