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sched: Remove double_rq_lock() from __migrate_task()
[linux/fpc-iii.git] / drivers / media / i2c / adv7842.c
blob0d554919cdd52726f52deda278414aa62bb6e47c
1 /*
2 * adv7842 - Analog Devices ADV7842 video decoder driver
3 *
4 * Copyright 2013 Cisco Systems, Inc. and/or its affiliates. All rights reserved.
5 *
6 * This program is free software; you may redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
11 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
12 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
13 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
14 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
15 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
16 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
17 * SOFTWARE.
18 *
19 */
20
21 /*
22 * References (c = chapter, p = page):
23 * REF_01 - Analog devices, ADV7842,
24 * Register Settings Recommendations, Rev. 1.9, April 2011
25 * REF_02 - Analog devices, Software User Guide, UG-206,
26 * ADV7842 I2C Register Maps, Rev. 0, November 2010
27 * REF_03 - Analog devices, Hardware User Guide, UG-214,
28 * ADV7842 Fast Switching 2:1 HDMI 1.4 Receiver with 3D-Comb
29 * Decoder and Digitizer , Rev. 0, January 2011
30 */
31
32
33 #include <linux/kernel.h>
34 #include <linux/module.h>
35 #include <linux/slab.h>
36 #include <linux/i2c.h>
37 #include <linux/delay.h>
38 #include <linux/videodev2.h>
39 #include <linux/workqueue.h>
40 #include <linux/v4l2-dv-timings.h>
41 #include <media/v4l2-device.h>
42 #include <media/v4l2-ctrls.h>
43 #include <media/v4l2-dv-timings.h>
44 #include <media/adv7842.h>
45
46 static int debug;
47 module_param(debug, int, 0644);
48 MODULE_PARM_DESC(debug, "debug level (0-2)");
49
50 MODULE_DESCRIPTION("Analog Devices ADV7842 video decoder driver");
51 MODULE_AUTHOR("Hans Verkuil <hans.verkuil@cisco.com>");
52 MODULE_AUTHOR("Martin Bugge <marbugge@cisco.com>");
53 MODULE_LICENSE("GPL");
54
55 /* ADV7842 system clock frequency */
56 #define ADV7842_fsc (28636360)
57
58 /*
59 **********************************************************************
60 *
61 * Arrays with configuration parameters for the ADV7842
62 *
63 **********************************************************************
64 */
65
66 struct adv7842_state {
67 struct adv7842_platform_data pdata;
68 struct v4l2_subdev sd;
69 struct media_pad pad;
70 struct v4l2_ctrl_handler hdl;
71 enum adv7842_mode mode;
72 struct v4l2_dv_timings timings;
73 enum adv7842_vid_std_select vid_std_select;
74 v4l2_std_id norm;
75 struct {
76 u8 edid[256];
77 u32 present;
78 } hdmi_edid;
79 struct {
80 u8 edid[256];
81 u32 present;
82 } vga_edid;
83 struct v4l2_fract aspect_ratio;
84 u32 rgb_quantization_range;
85 bool is_cea_format;
86 struct workqueue_struct *work_queues;
87 struct delayed_work delayed_work_enable_hotplug;
88 bool restart_stdi_once;
89 bool hdmi_port_a;
90
91 /* i2c clients */
92 struct i2c_client *i2c_sdp_io;
93 struct i2c_client *i2c_sdp;
94 struct i2c_client *i2c_cp;
95 struct i2c_client *i2c_vdp;
96 struct i2c_client *i2c_afe;
97 struct i2c_client *i2c_hdmi;
98 struct i2c_client *i2c_repeater;
99 struct i2c_client *i2c_edid;
100 struct i2c_client *i2c_infoframe;
101 struct i2c_client *i2c_cec;
102 struct i2c_client *i2c_avlink;
103
104 /* controls */
105 struct v4l2_ctrl *detect_tx_5v_ctrl;
106 struct v4l2_ctrl *analog_sampling_phase_ctrl;
107 struct v4l2_ctrl *free_run_color_ctrl_manual;
108 struct v4l2_ctrl *free_run_color_ctrl;
109 struct v4l2_ctrl *rgb_quantization_range_ctrl;
110 };
111
112 /* Unsupported timings. This device cannot support 720p30. */
113 static const struct v4l2_dv_timings adv7842_timings_exceptions[] = {
114 V4L2_DV_BT_CEA_1280X720P30,
115 { }
116 };
117
118 static bool adv7842_check_dv_timings(const struct v4l2_dv_timings *t, void *hdl)
119 {
120 int i;
121
122 for (i = 0; adv7842_timings_exceptions[i].bt.width; i++)
123 if (v4l2_match_dv_timings(t, adv7842_timings_exceptions + i, 0))
124 return false;
125 return true;
126 }
127
128 struct adv7842_video_standards {
129 struct v4l2_dv_timings timings;
130 u8 vid_std;
131 u8 v_freq;
132 };
133
134 /* sorted by number of lines */
135 static const struct adv7842_video_standards adv7842_prim_mode_comp[] = {
136 /* { V4L2_DV_BT_CEA_720X480P59_94, 0x0a, 0x00 }, TODO flickering */
137 { V4L2_DV_BT_CEA_720X576P50, 0x0b, 0x00 },
138 { V4L2_DV_BT_CEA_1280X720P50, 0x19, 0x01 },
139 { V4L2_DV_BT_CEA_1280X720P60, 0x19, 0x00 },
140 { V4L2_DV_BT_CEA_1920X1080P24, 0x1e, 0x04 },
141 { V4L2_DV_BT_CEA_1920X1080P25, 0x1e, 0x03 },
142 { V4L2_DV_BT_CEA_1920X1080P30, 0x1e, 0x02 },
143 { V4L2_DV_BT_CEA_1920X1080P50, 0x1e, 0x01 },
144 { V4L2_DV_BT_CEA_1920X1080P60, 0x1e, 0x00 },
145 /* TODO add 1920x1080P60_RB (CVT timing) */
146 { },
147 };
148
149 /* sorted by number of lines */
150 static const struct adv7842_video_standards adv7842_prim_mode_gr[] = {
151 { V4L2_DV_BT_DMT_640X480P60, 0x08, 0x00 },
152 { V4L2_DV_BT_DMT_640X480P72, 0x09, 0x00 },
153 { V4L2_DV_BT_DMT_640X480P75, 0x0a, 0x00 },
154 { V4L2_DV_BT_DMT_640X480P85, 0x0b, 0x00 },
155 { V4L2_DV_BT_DMT_800X600P56, 0x00, 0x00 },
156 { V4L2_DV_BT_DMT_800X600P60, 0x01, 0x00 },
157 { V4L2_DV_BT_DMT_800X600P72, 0x02, 0x00 },
158 { V4L2_DV_BT_DMT_800X600P75, 0x03, 0x00 },
159 { V4L2_DV_BT_DMT_800X600P85, 0x04, 0x00 },
160 { V4L2_DV_BT_DMT_1024X768P60, 0x0c, 0x00 },
161 { V4L2_DV_BT_DMT_1024X768P70, 0x0d, 0x00 },
162 { V4L2_DV_BT_DMT_1024X768P75, 0x0e, 0x00 },
163 { V4L2_DV_BT_DMT_1024X768P85, 0x0f, 0x00 },
164 { V4L2_DV_BT_DMT_1280X1024P60, 0x05, 0x00 },
165 { V4L2_DV_BT_DMT_1280X1024P75, 0x06, 0x00 },
166 { V4L2_DV_BT_DMT_1360X768P60, 0x12, 0x00 },
167 { V4L2_DV_BT_DMT_1366X768P60, 0x13, 0x00 },
168 { V4L2_DV_BT_DMT_1400X1050P60, 0x14, 0x00 },
169 { V4L2_DV_BT_DMT_1400X1050P75, 0x15, 0x00 },
170 { V4L2_DV_BT_DMT_1600X1200P60, 0x16, 0x00 }, /* TODO not tested */
171 /* TODO add 1600X1200P60_RB (not a DMT timing) */
172 { V4L2_DV_BT_DMT_1680X1050P60, 0x18, 0x00 },
173 { V4L2_DV_BT_DMT_1920X1200P60_RB, 0x19, 0x00 }, /* TODO not tested */
174 { },
175 };
176
177 /* sorted by number of lines */
178 static const struct adv7842_video_standards adv7842_prim_mode_hdmi_comp[] = {
179 { V4L2_DV_BT_CEA_720X480P59_94, 0x0a, 0x00 },
180 { V4L2_DV_BT_CEA_720X576P50, 0x0b, 0x00 },
181 { V4L2_DV_BT_CEA_1280X720P50, 0x13, 0x01 },
182 { V4L2_DV_BT_CEA_1280X720P60, 0x13, 0x00 },
183 { V4L2_DV_BT_CEA_1920X1080P24, 0x1e, 0x04 },
184 { V4L2_DV_BT_CEA_1920X1080P25, 0x1e, 0x03 },
185 { V4L2_DV_BT_CEA_1920X1080P30, 0x1e, 0x02 },
186 { V4L2_DV_BT_CEA_1920X1080P50, 0x1e, 0x01 },
187 { V4L2_DV_BT_CEA_1920X1080P60, 0x1e, 0x00 },
188 { },
189 };
190
191 /* sorted by number of lines */
192 static const struct adv7842_video_standards adv7842_prim_mode_hdmi_gr[] = {
193 { V4L2_DV_BT_DMT_640X480P60, 0x08, 0x00 },
194 { V4L2_DV_BT_DMT_640X480P72, 0x09, 0x00 },
195 { V4L2_DV_BT_DMT_640X480P75, 0x0a, 0x00 },
196 { V4L2_DV_BT_DMT_640X480P85, 0x0b, 0x00 },
197 { V4L2_DV_BT_DMT_800X600P56, 0x00, 0x00 },
198 { V4L2_DV_BT_DMT_800X600P60, 0x01, 0x00 },
199 { V4L2_DV_BT_DMT_800X600P72, 0x02, 0x00 },
200 { V4L2_DV_BT_DMT_800X600P75, 0x03, 0x00 },
201 { V4L2_DV_BT_DMT_800X600P85, 0x04, 0x00 },
202 { V4L2_DV_BT_DMT_1024X768P60, 0x0c, 0x00 },
203 { V4L2_DV_BT_DMT_1024X768P70, 0x0d, 0x00 },
204 { V4L2_DV_BT_DMT_1024X768P75, 0x0e, 0x00 },
205 { V4L2_DV_BT_DMT_1024X768P85, 0x0f, 0x00 },
206 { V4L2_DV_BT_DMT_1280X1024P60, 0x05, 0x00 },
207 { V4L2_DV_BT_DMT_1280X1024P75, 0x06, 0x00 },
208 { },
209 };
210
211 /* ----------------------------------------------------------------------- */
212
213 static inline struct adv7842_state *to_state(struct v4l2_subdev *sd)
214 {
215 return container_of(sd, struct adv7842_state, sd);
216 }
217
218 static inline struct v4l2_subdev *to_sd(struct v4l2_ctrl *ctrl)
219 {
220 return &container_of(ctrl->handler, struct adv7842_state, hdl)->sd;
221 }
222
223 static inline unsigned hblanking(const struct v4l2_bt_timings *t)
224 {
225 return V4L2_DV_BT_BLANKING_WIDTH(t);
226 }
227
228 static inline unsigned htotal(const struct v4l2_bt_timings *t)
229 {
230 return V4L2_DV_BT_FRAME_WIDTH(t);
231 }
232
233 static inline unsigned vblanking(const struct v4l2_bt_timings *t)
234 {
235 return V4L2_DV_BT_BLANKING_HEIGHT(t);
236 }
237
238 static inline unsigned vtotal(const struct v4l2_bt_timings *t)
239 {
240 return V4L2_DV_BT_FRAME_HEIGHT(t);
241 }
242
243
244 /* ----------------------------------------------------------------------- */
245
246 static s32 adv_smbus_read_byte_data_check(struct i2c_client *client,
247 u8 command, bool check)
248 {
249 union i2c_smbus_data data;
250
251 if (!i2c_smbus_xfer(client->adapter, client->addr, client->flags,
252 I2C_SMBUS_READ, command,
253 I2C_SMBUS_BYTE_DATA, &data))
254 return data.byte;
255 if (check)
256 v4l_err(client, "error reading %02x, %02x\n",
257 client->addr, command);
258 return -EIO;
259 }
260
261 static s32 adv_smbus_read_byte_data(struct i2c_client *client, u8 command)
262 {
263 int i;
264
265 for (i = 0; i < 3; i++) {
266 int ret = adv_smbus_read_byte_data_check(client, command, true);
267
268 if (ret >= 0) {
269 if (i)
270 v4l_err(client, "read ok after %d retries\n", i);
271 return ret;
272 }
273 }
274 v4l_err(client, "read failed\n");
275 return -EIO;
276 }
277
278 static s32 adv_smbus_write_byte_data(struct i2c_client *client,
279 u8 command, u8 value)
280 {
281 union i2c_smbus_data data;
282 int err;
283 int i;
284
285 data.byte = value;
286 for (i = 0; i < 3; i++) {
287 err = i2c_smbus_xfer(client->adapter, client->addr,
288 client->flags,
289 I2C_SMBUS_WRITE, command,
290 I2C_SMBUS_BYTE_DATA, &data);
291 if (!err)
292 break;
293 }
294 if (err < 0)
295 v4l_err(client, "error writing %02x, %02x, %02x\n",
296 client->addr, command, value);
297 return err;
298 }
299
300 static void adv_smbus_write_byte_no_check(struct i2c_client *client,
301 u8 command, u8 value)
302 {
303 union i2c_smbus_data data;
304 data.byte = value;
305
306 i2c_smbus_xfer(client->adapter, client->addr,
307 client->flags,
308 I2C_SMBUS_WRITE, command,
309 I2C_SMBUS_BYTE_DATA, &data);
310 }
311
312 static s32 adv_smbus_write_i2c_block_data(struct i2c_client *client,
313 u8 command, unsigned length, const u8 *values)
314 {
315 union i2c_smbus_data data;
316
317 if (length > I2C_SMBUS_BLOCK_MAX)
318 length = I2C_SMBUS_BLOCK_MAX;
319 data.block[0] = length;
320 memcpy(data.block + 1, values, length);
321 return i2c_smbus_xfer(client->adapter, client->addr, client->flags,
322 I2C_SMBUS_WRITE, command,
323 I2C_SMBUS_I2C_BLOCK_DATA, &data);
324 }
325
326 /* ----------------------------------------------------------------------- */
327
328 static inline int io_read(struct v4l2_subdev *sd, u8 reg)
329 {
330 struct i2c_client *client = v4l2_get_subdevdata(sd);
331
332 return adv_smbus_read_byte_data(client, reg);
333 }
334
335 static inline int io_write(struct v4l2_subdev *sd, u8 reg, u8 val)
336 {
337 struct i2c_client *client = v4l2_get_subdevdata(sd);
338
339 return adv_smbus_write_byte_data(client, reg, val);
340 }
341
342 static inline int io_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
343 {
344 return io_write(sd, reg, (io_read(sd, reg) & mask) | val);
345 }
346
347 static inline int avlink_read(struct v4l2_subdev *sd, u8 reg)
348 {
349 struct adv7842_state *state = to_state(sd);
350
351 return adv_smbus_read_byte_data(state->i2c_avlink, reg);
352 }
353
354 static inline int avlink_write(struct v4l2_subdev *sd, u8 reg, u8 val)
355 {
356 struct adv7842_state *state = to_state(sd);
357
358 return adv_smbus_write_byte_data(state->i2c_avlink, reg, val);
359 }
360
361 static inline int cec_read(struct v4l2_subdev *sd, u8 reg)
362 {
363 struct adv7842_state *state = to_state(sd);
364
365 return adv_smbus_read_byte_data(state->i2c_cec, reg);
366 }
367
368 static inline int cec_write(struct v4l2_subdev *sd, u8 reg, u8 val)
369 {
370 struct adv7842_state *state = to_state(sd);
371
372 return adv_smbus_write_byte_data(state->i2c_cec, reg, val);
373 }
374
375 static inline int cec_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
376 {
377 return cec_write(sd, reg, (cec_read(sd, reg) & mask) | val);
378 }
379
380 static inline int infoframe_read(struct v4l2_subdev *sd, u8 reg)
381 {
382 struct adv7842_state *state = to_state(sd);
383
384 return adv_smbus_read_byte_data(state->i2c_infoframe, reg);
385 }
386
387 static inline int infoframe_write(struct v4l2_subdev *sd, u8 reg, u8 val)
388 {
389 struct adv7842_state *state = to_state(sd);
390
391 return adv_smbus_write_byte_data(state->i2c_infoframe, reg, val);
392 }
393
394 static inline int sdp_io_read(struct v4l2_subdev *sd, u8 reg)
395 {
396 struct adv7842_state *state = to_state(sd);
397
398 return adv_smbus_read_byte_data(state->i2c_sdp_io, reg);
399 }
400
401 static inline int sdp_io_write(struct v4l2_subdev *sd, u8 reg, u8 val)
402 {
403 struct adv7842_state *state = to_state(sd);
404
405 return adv_smbus_write_byte_data(state->i2c_sdp_io, reg, val);
406 }
407
408 static inline int sdp_io_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
409 {
410 return sdp_io_write(sd, reg, (sdp_io_read(sd, reg) & mask) | val);
411 }
412
413 static inline int sdp_read(struct v4l2_subdev *sd, u8 reg)
414 {
415 struct adv7842_state *state = to_state(sd);
416
417 return adv_smbus_read_byte_data(state->i2c_sdp, reg);
418 }
419
420 static inline int sdp_write(struct v4l2_subdev *sd, u8 reg, u8 val)
421 {
422 struct adv7842_state *state = to_state(sd);
423
424 return adv_smbus_write_byte_data(state->i2c_sdp, reg, val);
425 }
426
427 static inline int sdp_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
428 {
429 return sdp_write(sd, reg, (sdp_read(sd, reg) & mask) | val);
430 }
431
432 static inline int afe_read(struct v4l2_subdev *sd, u8 reg)
433 {
434 struct adv7842_state *state = to_state(sd);
435
436 return adv_smbus_read_byte_data(state->i2c_afe, reg);
437 }
438
439 static inline int afe_write(struct v4l2_subdev *sd, u8 reg, u8 val)
440 {
441 struct adv7842_state *state = to_state(sd);
442
443 return adv_smbus_write_byte_data(state->i2c_afe, reg, val);
444 }
445
446 static inline int afe_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
447 {
448 return afe_write(sd, reg, (afe_read(sd, reg) & mask) | val);
449 }
450
451 static inline int rep_read(struct v4l2_subdev *sd, u8 reg)
452 {
453 struct adv7842_state *state = to_state(sd);
454
455 return adv_smbus_read_byte_data(state->i2c_repeater, reg);
456 }
457
458 static inline int rep_write(struct v4l2_subdev *sd, u8 reg, u8 val)
459 {
460 struct adv7842_state *state = to_state(sd);
461
462 return adv_smbus_write_byte_data(state->i2c_repeater, reg, val);
463 }
464
465 static inline int rep_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
466 {
467 return rep_write(sd, reg, (rep_read(sd, reg) & mask) | val);
468 }
469
470 static inline int edid_read(struct v4l2_subdev *sd, u8 reg)
471 {
472 struct adv7842_state *state = to_state(sd);
473
474 return adv_smbus_read_byte_data(state->i2c_edid, reg);
475 }
476
477 static inline int edid_write(struct v4l2_subdev *sd, u8 reg, u8 val)
478 {
479 struct adv7842_state *state = to_state(sd);
480
481 return adv_smbus_write_byte_data(state->i2c_edid, reg, val);
482 }
483
484 static inline int hdmi_read(struct v4l2_subdev *sd, u8 reg)
485 {
486 struct adv7842_state *state = to_state(sd);
487
488 return adv_smbus_read_byte_data(state->i2c_hdmi, reg);
489 }
490
491 static inline int hdmi_write(struct v4l2_subdev *sd, u8 reg, u8 val)
492 {
493 struct adv7842_state *state = to_state(sd);
494
495 return adv_smbus_write_byte_data(state->i2c_hdmi, reg, val);
496 }
497
498 static inline int hdmi_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
499 {
500 return hdmi_write(sd, reg, (hdmi_read(sd, reg) & mask) | val);
501 }
502
503 static inline int cp_read(struct v4l2_subdev *sd, u8 reg)
504 {
505 struct adv7842_state *state = to_state(sd);
506
507 return adv_smbus_read_byte_data(state->i2c_cp, reg);
508 }
509
510 static inline int cp_write(struct v4l2_subdev *sd, u8 reg, u8 val)
511 {
512 struct adv7842_state *state = to_state(sd);
513
514 return adv_smbus_write_byte_data(state->i2c_cp, reg, val);
515 }
516
517 static inline int cp_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
518 {
519 return cp_write(sd, reg, (cp_read(sd, reg) & mask) | val);
520 }
521
522 static inline int vdp_read(struct v4l2_subdev *sd, u8 reg)
523 {
524 struct adv7842_state *state = to_state(sd);
525
526 return adv_smbus_read_byte_data(state->i2c_vdp, reg);
527 }
528
529 static inline int vdp_write(struct v4l2_subdev *sd, u8 reg, u8 val)
530 {
531 struct adv7842_state *state = to_state(sd);
532
533 return adv_smbus_write_byte_data(state->i2c_vdp, reg, val);
534 }
535
536 static void main_reset(struct v4l2_subdev *sd)
537 {
538 struct i2c_client *client = v4l2_get_subdevdata(sd);
539
540 v4l2_dbg(1, debug, sd, "%s:\n", __func__);
541
542 adv_smbus_write_byte_no_check(client, 0xff, 0x80);
543
544 mdelay(5);
545 }
546
547 /* ----------------------------------------------------------------------- */
548
549 static inline bool is_analog_input(struct v4l2_subdev *sd)
550 {
551 struct adv7842_state *state = to_state(sd);
552
553 return ((state->mode == ADV7842_MODE_RGB) ||
554 (state->mode == ADV7842_MODE_COMP));
555 }
556
557 static inline bool is_digital_input(struct v4l2_subdev *sd)
558 {
559 struct adv7842_state *state = to_state(sd);
560
561 return state->mode == ADV7842_MODE_HDMI;
562 }
563
564 static const struct v4l2_dv_timings_cap adv7842_timings_cap_analog = {
565 .type = V4L2_DV_BT_656_1120,
566 /* keep this initialization for compatibility with GCC < 4.4.6 */
567 .reserved = { 0 },
568 V4L2_INIT_BT_TIMINGS(0, 1920, 0, 1200, 25000000, 170000000,
569 V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT |
570 V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT,
571 V4L2_DV_BT_CAP_PROGRESSIVE | V4L2_DV_BT_CAP_REDUCED_BLANKING |
572 V4L2_DV_BT_CAP_CUSTOM)
573 };
574
575 static const struct v4l2_dv_timings_cap adv7842_timings_cap_digital = {
576 .type = V4L2_DV_BT_656_1120,
577 /* keep this initialization for compatibility with GCC < 4.4.6 */
578 .reserved = { 0 },
579 V4L2_INIT_BT_TIMINGS(0, 1920, 0, 1200, 25000000, 225000000,
580 V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT |
581 V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT,
582 V4L2_DV_BT_CAP_PROGRESSIVE | V4L2_DV_BT_CAP_REDUCED_BLANKING |
583 V4L2_DV_BT_CAP_CUSTOM)
584 };
585
586 static inline const struct v4l2_dv_timings_cap *
587 adv7842_get_dv_timings_cap(struct v4l2_subdev *sd)
588 {
589 return is_digital_input(sd) ? &adv7842_timings_cap_digital :
590 &adv7842_timings_cap_analog;
591 }
592
593 /* ----------------------------------------------------------------------- */
594
595 static void adv7842_delayed_work_enable_hotplug(struct work_struct *work)
596 {
597 struct delayed_work *dwork = to_delayed_work(work);
598 struct adv7842_state *state = container_of(dwork,
599 struct adv7842_state, delayed_work_enable_hotplug);
600 struct v4l2_subdev *sd = &state->sd;
601 int present = state->hdmi_edid.present;
602 u8 mask = 0;
603
604 v4l2_dbg(2, debug, sd, "%s: enable hotplug on ports: 0x%x\n",
605 __func__, present);
606
607 if (present & (0x04 << ADV7842_EDID_PORT_A))
608 mask |= 0x20;
609 if (present & (0x04 << ADV7842_EDID_PORT_B))
610 mask |= 0x10;
611 io_write_and_or(sd, 0x20, 0xcf, mask);
612 }
613
614 static int edid_write_vga_segment(struct v4l2_subdev *sd)
615 {
616 struct i2c_client *client = v4l2_get_subdevdata(sd);
617 struct adv7842_state *state = to_state(sd);
618 const u8 *val = state->vga_edid.edid;
619 int err = 0;
620 int i;
621
622 v4l2_dbg(2, debug, sd, "%s: write EDID on VGA port\n", __func__);
623
624 /* HPA disable on port A and B */
625 io_write_and_or(sd, 0x20, 0xcf, 0x00);
626
627 /* Disable I2C access to internal EDID ram from VGA DDC port */
628 rep_write_and_or(sd, 0x7f, 0x7f, 0x00);
629
630 /* edid segment pointer '1' for VGA port */
631 rep_write_and_or(sd, 0x77, 0xef, 0x10);
632
633 for (i = 0; !err && i < 256; i += I2C_SMBUS_BLOCK_MAX)
634 err = adv_smbus_write_i2c_block_data(state->i2c_edid, i,
635 I2C_SMBUS_BLOCK_MAX, val + i);
636 if (err)
637 return err;
638
639 /* Calculates the checksums and enables I2C access
640 * to internal EDID ram from VGA DDC port.
641 */
642 rep_write_and_or(sd, 0x7f, 0x7f, 0x80);
643
644 for (i = 0; i < 1000; i++) {
645 if (rep_read(sd, 0x79) & 0x20)
646 break;
647 mdelay(1);
648 }
649 if (i == 1000) {
650 v4l_err(client, "error enabling edid on VGA port\n");
651 return -EIO;
652 }
653
654 /* enable hotplug after 200 ms */
655 queue_delayed_work(state->work_queues,
656 &state->delayed_work_enable_hotplug, HZ / 5);
657
658 return 0;
659 }
660
661 static int edid_spa_location(const u8 *edid)
662 {
663 u8 d;
664
665 /*
666 * TODO, improve and update for other CEA extensions
667 * currently only for 1 segment (256 bytes),
668 * i.e. 1 extension block and CEA revision 3.
669 */
670 if ((edid[0x7e] != 1) ||
671 (edid[0x80] != 0x02) ||
672 (edid[0x81] != 0x03)) {
673 return -EINVAL;
674 }
675 /*
676 * search Vendor Specific Data Block (tag 3)
677 */
678 d = edid[0x82] & 0x7f;
679 if (d > 4) {
680 int i = 0x84;
681 int end = 0x80 + d;
682 do {
683 u8 tag = edid[i]>>5;
684 u8 len = edid[i] & 0x1f;
685
686 if ((tag == 3) && (len >= 5))
687 return i + 4;
688 i += len + 1;
689 } while (i < end);
690 }
691 return -EINVAL;
692 }
693
694 static int edid_write_hdmi_segment(struct v4l2_subdev *sd, u8 port)
695 {
696 struct i2c_client *client = v4l2_get_subdevdata(sd);
697 struct adv7842_state *state = to_state(sd);
698 const u8 *val = state->hdmi_edid.edid;
699 int spa_loc = edid_spa_location(val);
700 int err = 0;
701 int i;
702
703 v4l2_dbg(2, debug, sd, "%s: write EDID on port %c (spa at 0x%x)\n",
704 __func__, (port == ADV7842_EDID_PORT_A) ? 'A' : 'B', spa_loc);
705
706 /* HPA disable on port A and B */
707 io_write_and_or(sd, 0x20, 0xcf, 0x00);
708
709 /* Disable I2C access to internal EDID ram from HDMI DDC ports */
710 rep_write_and_or(sd, 0x77, 0xf3, 0x00);
711
712 if (!state->hdmi_edid.present)
713 return 0;
714
715 /* edid segment pointer '0' for HDMI ports */
716 rep_write_and_or(sd, 0x77, 0xef, 0x00);
717
718 for (i = 0; !err && i < 256; i += I2C_SMBUS_BLOCK_MAX)
719 err = adv_smbus_write_i2c_block_data(state->i2c_edid, i,
720 I2C_SMBUS_BLOCK_MAX, val + i);
721 if (err)
722 return err;
723
724 if (spa_loc < 0)
725 spa_loc = 0xc0; /* Default value [REF_02, p. 199] */
726
727 if (port == ADV7842_EDID_PORT_A) {
728 rep_write(sd, 0x72, val[spa_loc]);
729 rep_write(sd, 0x73, val[spa_loc + 1]);
730 } else {
731 rep_write(sd, 0x74, val[spa_loc]);
732 rep_write(sd, 0x75, val[spa_loc + 1]);
733 }
734 rep_write(sd, 0x76, spa_loc & 0xff);
735 rep_write_and_or(sd, 0x77, 0xbf, (spa_loc >> 2) & 0x40);
736
737 /* Calculates the checksums and enables I2C access to internal
738 * EDID ram from HDMI DDC ports
739 */
740 rep_write_and_or(sd, 0x77, 0xf3, state->hdmi_edid.present);
741
742 for (i = 0; i < 1000; i++) {
743 if (rep_read(sd, 0x7d) & state->hdmi_edid.present)
744 break;
745 mdelay(1);
746 }
747 if (i == 1000) {
748 v4l_err(client, "error enabling edid on port %c\n",
749 (port == ADV7842_EDID_PORT_A) ? 'A' : 'B');
750 return -EIO;
751 }
752
753 /* enable hotplug after 200 ms */
754 queue_delayed_work(state->work_queues,
755 &state->delayed_work_enable_hotplug, HZ / 5);
756
757 return 0;
758 }
759
760 /* ----------------------------------------------------------------------- */
761
762 #ifdef CONFIG_VIDEO_ADV_DEBUG
763 static void adv7842_inv_register(struct v4l2_subdev *sd)
764 {
765 v4l2_info(sd, "0x000-0x0ff: IO Map\n");
766 v4l2_info(sd, "0x100-0x1ff: AVLink Map\n");
767 v4l2_info(sd, "0x200-0x2ff: CEC Map\n");
768 v4l2_info(sd, "0x300-0x3ff: InfoFrame Map\n");
769 v4l2_info(sd, "0x400-0x4ff: SDP_IO Map\n");
770 v4l2_info(sd, "0x500-0x5ff: SDP Map\n");
771 v4l2_info(sd, "0x600-0x6ff: AFE Map\n");
772 v4l2_info(sd, "0x700-0x7ff: Repeater Map\n");
773 v4l2_info(sd, "0x800-0x8ff: EDID Map\n");
774 v4l2_info(sd, "0x900-0x9ff: HDMI Map\n");
775 v4l2_info(sd, "0xa00-0xaff: CP Map\n");
776 v4l2_info(sd, "0xb00-0xbff: VDP Map\n");
777 }
778
779 static int adv7842_g_register(struct v4l2_subdev *sd,
780 struct v4l2_dbg_register *reg)
781 {
782 reg->size = 1;
783 switch (reg->reg >> 8) {
784 case 0:
785 reg->val = io_read(sd, reg->reg & 0xff);
786 break;
787 case 1:
788 reg->val = avlink_read(sd, reg->reg & 0xff);
789 break;
790 case 2:
791 reg->val = cec_read(sd, reg->reg & 0xff);
792 break;
793 case 3:
794 reg->val = infoframe_read(sd, reg->reg & 0xff);
795 break;
796 case 4:
797 reg->val = sdp_io_read(sd, reg->reg & 0xff);
798 break;
799 case 5:
800 reg->val = sdp_read(sd, reg->reg & 0xff);
801 break;
802 case 6:
803 reg->val = afe_read(sd, reg->reg & 0xff);
804 break;
805 case 7:
806 reg->val = rep_read(sd, reg->reg & 0xff);
807 break;
808 case 8:
809 reg->val = edid_read(sd, reg->reg & 0xff);
810 break;
811 case 9:
812 reg->val = hdmi_read(sd, reg->reg & 0xff);
813 break;
814 case 0xa:
815 reg->val = cp_read(sd, reg->reg & 0xff);
816 break;
817 case 0xb:
818 reg->val = vdp_read(sd, reg->reg & 0xff);
819 break;
820 default:
821 v4l2_info(sd, "Register %03llx not supported\n", reg->reg);
822 adv7842_inv_register(sd);
823 break;
824 }
825 return 0;
826 }
827
828 static int adv7842_s_register(struct v4l2_subdev *sd,
829 const struct v4l2_dbg_register *reg)
830 {
831 u8 val = reg->val & 0xff;
832
833 switch (reg->reg >> 8) {
834 case 0:
835 io_write(sd, reg->reg & 0xff, val);
836 break;
837 case 1:
838 avlink_write(sd, reg->reg & 0xff, val);
839 break;
840 case 2:
841 cec_write(sd, reg->reg & 0xff, val);
842 break;
843 case 3:
844 infoframe_write(sd, reg->reg & 0xff, val);
845 break;
846 case 4:
847 sdp_io_write(sd, reg->reg & 0xff, val);
848 break;
849 case 5:
850 sdp_write(sd, reg->reg & 0xff, val);
851 break;
852 case 6:
853 afe_write(sd, reg->reg & 0xff, val);
854 break;
855 case 7:
856 rep_write(sd, reg->reg & 0xff, val);
857 break;
858 case 8:
859 edid_write(sd, reg->reg & 0xff, val);
860 break;
861 case 9:
862 hdmi_write(sd, reg->reg & 0xff, val);
863 break;
864 case 0xa:
865 cp_write(sd, reg->reg & 0xff, val);
866 break;
867 case 0xb:
868 vdp_write(sd, reg->reg & 0xff, val);
869 break;
870 default:
871 v4l2_info(sd, "Register %03llx not supported\n", reg->reg);
872 adv7842_inv_register(sd);
873 break;
874 }
875 return 0;
876 }
877 #endif
878
879 static int adv7842_s_detect_tx_5v_ctrl(struct v4l2_subdev *sd)
880 {
881 struct adv7842_state *state = to_state(sd);
882 int prev = v4l2_ctrl_g_ctrl(state->detect_tx_5v_ctrl);
883 u8 reg_io_6f = io_read(sd, 0x6f);
884 int val = 0;
885
886 if (reg_io_6f & 0x02)
887 val |= 1; /* port A */
888 if (reg_io_6f & 0x01)
889 val |= 2; /* port B */
890
891 v4l2_dbg(1, debug, sd, "%s: 0x%x -> 0x%x\n", __func__, prev, val);
892
893 if (val != prev)
894 return v4l2_ctrl_s_ctrl(state->detect_tx_5v_ctrl, val);
895 return 0;
896 }
897
898 static int find_and_set_predefined_video_timings(struct v4l2_subdev *sd,
899 u8 prim_mode,
900 const struct adv7842_video_standards *predef_vid_timings,
901 const struct v4l2_dv_timings *timings)
902 {
903 int i;
904
905 for (i = 0; predef_vid_timings[i].timings.bt.width; i++) {
906 if (!v4l2_match_dv_timings(timings, &predef_vid_timings[i].timings,
907 is_digital_input(sd) ? 250000 : 1000000))
908 continue;
909 /* video std */
910 io_write(sd, 0x00, predef_vid_timings[i].vid_std);
911 /* v_freq and prim mode */
912 io_write(sd, 0x01, (predef_vid_timings[i].v_freq << 4) + prim_mode);
913 return 0;
914 }
915
916 return -1;
917 }
918
919 static int configure_predefined_video_timings(struct v4l2_subdev *sd,
920 struct v4l2_dv_timings *timings)
921 {
922 struct adv7842_state *state = to_state(sd);
923 int err;
924
925 v4l2_dbg(1, debug, sd, "%s\n", __func__);
926
927 /* reset to default values */
928 io_write(sd, 0x16, 0x43);
929 io_write(sd, 0x17, 0x5a);
930 /* disable embedded syncs for auto graphics mode */
931 cp_write_and_or(sd, 0x81, 0xef, 0x00);
932 cp_write(sd, 0x26, 0x00);
933 cp_write(sd, 0x27, 0x00);
934 cp_write(sd, 0x28, 0x00);
935 cp_write(sd, 0x29, 0x00);
936 cp_write(sd, 0x8f, 0x40);
937 cp_write(sd, 0x90, 0x00);
938 cp_write(sd, 0xa5, 0x00);
939 cp_write(sd, 0xa6, 0x00);
940 cp_write(sd, 0xa7, 0x00);
941 cp_write(sd, 0xab, 0x00);
942 cp_write(sd, 0xac, 0x00);
943
944 switch (state->mode) {
945 case ADV7842_MODE_COMP:
946 case ADV7842_MODE_RGB:
947 err = find_and_set_predefined_video_timings(sd,
948 0x01, adv7842_prim_mode_comp, timings);
949 if (err)
950 err = find_and_set_predefined_video_timings(sd,
951 0x02, adv7842_prim_mode_gr, timings);
952 break;
953 case ADV7842_MODE_HDMI:
954 err = find_and_set_predefined_video_timings(sd,
955 0x05, adv7842_prim_mode_hdmi_comp, timings);
956 if (err)
957 err = find_and_set_predefined_video_timings(sd,
958 0x06, adv7842_prim_mode_hdmi_gr, timings);
959 break;
960 default:
961 v4l2_dbg(2, debug, sd, "%s: Unknown mode %d\n",
962 __func__, state->mode);
963 err = -1;
964 break;
965 }
966
967
968 return err;
969 }
970
971 static void configure_custom_video_timings(struct v4l2_subdev *sd,
972 const struct v4l2_bt_timings *bt)
973 {
974 struct adv7842_state *state = to_state(sd);
975 struct i2c_client *client = v4l2_get_subdevdata(sd);
976 u32 width = htotal(bt);
977 u32 height = vtotal(bt);
978 u16 cp_start_sav = bt->hsync + bt->hbackporch - 4;
979 u16 cp_start_eav = width - bt->hfrontporch;
980 u16 cp_start_vbi = height - bt->vfrontporch + 1;
981 u16 cp_end_vbi = bt->vsync + bt->vbackporch + 1;
982 u16 ch1_fr_ll = (((u32)bt->pixelclock / 100) > 0) ?
983 ((width * (ADV7842_fsc / 100)) / ((u32)bt->pixelclock / 100)) : 0;
984 const u8 pll[2] = {
985 0xc0 | ((width >> 8) & 0x1f),
986 width & 0xff
987 };
988
989 v4l2_dbg(2, debug, sd, "%s\n", __func__);
990
991 switch (state->mode) {
992 case ADV7842_MODE_COMP:
993 case ADV7842_MODE_RGB:
994 /* auto graphics */
995 io_write(sd, 0x00, 0x07); /* video std */
996 io_write(sd, 0x01, 0x02); /* prim mode */
997 /* enable embedded syncs for auto graphics mode */
998 cp_write_and_or(sd, 0x81, 0xef, 0x10);
999
1000 /* Should only be set in auto-graphics mode [REF_02, p. 91-92] */
1001 /* setup PLL_DIV_MAN_EN and PLL_DIV_RATIO */
1002 /* IO-map reg. 0x16 and 0x17 should be written in sequence */
1003 if (adv_smbus_write_i2c_block_data(client, 0x16, 2, pll)) {
1004 v4l2_err(sd, "writing to reg 0x16 and 0x17 failed\n");
1005 break;
1006 }
1007
1008 /* active video - horizontal timing */
1009 cp_write(sd, 0x26, (cp_start_sav >> 8) & 0xf);
1010 cp_write(sd, 0x27, (cp_start_sav & 0xff));
1011 cp_write(sd, 0x28, (cp_start_eav >> 8) & 0xf);
1012 cp_write(sd, 0x29, (cp_start_eav & 0xff));
1013
1014 /* active video - vertical timing */
1015 cp_write(sd, 0xa5, (cp_start_vbi >> 4) & 0xff);
1016 cp_write(sd, 0xa6, ((cp_start_vbi & 0xf) << 4) |
1017 ((cp_end_vbi >> 8) & 0xf));
1018 cp_write(sd, 0xa7, cp_end_vbi & 0xff);
1019 break;
1020 case ADV7842_MODE_HDMI:
1021 /* set default prim_mode/vid_std for HDMI
1022 according to [REF_03, c. 4.2] */
1023 io_write(sd, 0x00, 0x02); /* video std */
1024 io_write(sd, 0x01, 0x06); /* prim mode */
1025 break;
1026 default:
1027 v4l2_dbg(2, debug, sd, "%s: Unknown mode %d\n",
1028 __func__, state->mode);
1029 break;
1030 }
1031
1032 cp_write(sd, 0x8f, (ch1_fr_ll >> 8) & 0x7);
1033 cp_write(sd, 0x90, ch1_fr_ll & 0xff);
1034 cp_write(sd, 0xab, (height >> 4) & 0xff);
1035 cp_write(sd, 0xac, (height & 0x0f) << 4);
1036 }
1037
1038 static void adv7842_set_offset(struct v4l2_subdev *sd, bool auto_offset, u16 offset_a, u16 offset_b, u16 offset_c)
1039 {
1040 struct adv7842_state *state = to_state(sd);
1041 u8 offset_buf[4];
1042
1043 if (auto_offset) {
1044 offset_a = 0x3ff;
1045 offset_b = 0x3ff;
1046 offset_c = 0x3ff;
1047 }
1048
1049 v4l2_dbg(2, debug, sd, "%s: %s offset: a = 0x%x, b = 0x%x, c = 0x%x\n",
1050 __func__, auto_offset ? "Auto" : "Manual",
1051 offset_a, offset_b, offset_c);
1052
1053 offset_buf[0]= (cp_read(sd, 0x77) & 0xc0) | ((offset_a & 0x3f0) >> 4);
1054 offset_buf[1] = ((offset_a & 0x00f) << 4) | ((offset_b & 0x3c0) >> 6);
1055 offset_buf[2] = ((offset_b & 0x03f) << 2) | ((offset_c & 0x300) >> 8);
1056 offset_buf[3] = offset_c & 0x0ff;
1057
1058 /* Registers must be written in this order with no i2c access in between */
1059 if (adv_smbus_write_i2c_block_data(state->i2c_cp, 0x77, 4, offset_buf))
1060 v4l2_err(sd, "%s: i2c error writing to CP reg 0x77, 0x78, 0x79, 0x7a\n", __func__);
1061 }
1062
1063 static void adv7842_set_gain(struct v4l2_subdev *sd, bool auto_gain, u16 gain_a, u16 gain_b, u16 gain_c)
1064 {
1065 struct adv7842_state *state = to_state(sd);
1066 u8 gain_buf[4];
1067 u8 gain_man = 1;
1068 u8 agc_mode_man = 1;
1069
1070 if (auto_gain) {
1071 gain_man = 0;
1072 agc_mode_man = 0;
1073 gain_a = 0x100;
1074 gain_b = 0x100;
1075 gain_c = 0x100;
1076 }
1077
1078 v4l2_dbg(2, debug, sd, "%s: %s gain: a = 0x%x, b = 0x%x, c = 0x%x\n",
1079 __func__, auto_gain ? "Auto" : "Manual",
1080 gain_a, gain_b, gain_c);
1081
1082 gain_buf[0] = ((gain_man << 7) | (agc_mode_man << 6) | ((gain_a & 0x3f0) >> 4));
1083 gain_buf[1] = (((gain_a & 0x00f) << 4) | ((gain_b & 0x3c0) >> 6));
1084 gain_buf[2] = (((gain_b & 0x03f) << 2) | ((gain_c & 0x300) >> 8));
1085 gain_buf[3] = ((gain_c & 0x0ff));
1086
1087 /* Registers must be written in this order with no i2c access in between */
1088 if (adv_smbus_write_i2c_block_data(state->i2c_cp, 0x73, 4, gain_buf))
1089 v4l2_err(sd, "%s: i2c error writing to CP reg 0x73, 0x74, 0x75, 0x76\n", __func__);
1090 }
1091
1092 static void set_rgb_quantization_range(struct v4l2_subdev *sd)
1093 {
1094 struct adv7842_state *state = to_state(sd);
1095 bool rgb_output = io_read(sd, 0x02) & 0x02;
1096 bool hdmi_signal = hdmi_read(sd, 0x05) & 0x80;
1097
1098 v4l2_dbg(2, debug, sd, "%s: RGB quantization range: %d, RGB out: %d, HDMI: %d\n",
1099 __func__, state->rgb_quantization_range,
1100 rgb_output, hdmi_signal);
1101
1102 adv7842_set_gain(sd, true, 0x0, 0x0, 0x0);
1103 adv7842_set_offset(sd, true, 0x0, 0x0, 0x0);
1104
1105 switch (state->rgb_quantization_range) {
1106 case V4L2_DV_RGB_RANGE_AUTO:
1107 if (state->mode == ADV7842_MODE_RGB) {
1108 /* Receiving analog RGB signal
1109 * Set RGB full range (0-255) */
1110 io_write_and_or(sd, 0x02, 0x0f, 0x10);
1111 break;
1112 }
1113
1114 if (state->mode == ADV7842_MODE_COMP) {
1115 /* Receiving analog YPbPr signal
1116 * Set automode */
1117 io_write_and_or(sd, 0x02, 0x0f, 0xf0);
1118 break;
1119 }
1120
1121 if (hdmi_signal) {
1122 /* Receiving HDMI signal
1123 * Set automode */
1124 io_write_and_or(sd, 0x02, 0x0f, 0xf0);
1125 break;
1126 }
1127
1128 /* Receiving DVI-D signal
1129 * ADV7842 selects RGB limited range regardless of
1130 * input format (CE/IT) in automatic mode */
1131 if (state->timings.bt.standards & V4L2_DV_BT_STD_CEA861) {
1132 /* RGB limited range (16-235) */
1133 io_write_and_or(sd, 0x02, 0x0f, 0x00);
1134 } else {
1135 /* RGB full range (0-255) */
1136 io_write_and_or(sd, 0x02, 0x0f, 0x10);
1137
1138 if (is_digital_input(sd) && rgb_output) {
1139 adv7842_set_offset(sd, false, 0x40, 0x40, 0x40);
1140 } else {
1141 adv7842_set_gain(sd, false, 0xe0, 0xe0, 0xe0);
1142 adv7842_set_offset(sd, false, 0x70, 0x70, 0x70);
1143 }
1144 }
1145 break;
1146 case V4L2_DV_RGB_RANGE_LIMITED:
1147 if (state->mode == ADV7842_MODE_COMP) {
1148 /* YCrCb limited range (16-235) */
1149 io_write_and_or(sd, 0x02, 0x0f, 0x20);
1150 break;
1151 }
1152
1153 /* RGB limited range (16-235) */
1154 io_write_and_or(sd, 0x02, 0x0f, 0x00);
1155
1156 break;
1157 case V4L2_DV_RGB_RANGE_FULL:
1158 if (state->mode == ADV7842_MODE_COMP) {
1159 /* YCrCb full range (0-255) */
1160 io_write_and_or(sd, 0x02, 0x0f, 0x60);
1161 break;
1162 }
1163
1164 /* RGB full range (0-255) */
1165 io_write_and_or(sd, 0x02, 0x0f, 0x10);
1166
1167 if (is_analog_input(sd) || hdmi_signal)
1168 break;
1169
1170 /* Adjust gain/offset for DVI-D signals only */
1171 if (rgb_output) {
1172 adv7842_set_offset(sd, false, 0x40, 0x40, 0x40);
1173 } else {
1174 adv7842_set_gain(sd, false, 0xe0, 0xe0, 0xe0);
1175 adv7842_set_offset(sd, false, 0x70, 0x70, 0x70);
1176 }
1177 break;
1178 }
1179 }
1180
1181 static int adv7842_s_ctrl(struct v4l2_ctrl *ctrl)
1182 {
1183 struct v4l2_subdev *sd = to_sd(ctrl);
1184 struct adv7842_state *state = to_state(sd);
1185
1186 /* TODO SDP ctrls
1187 contrast/brightness/hue/free run is acting a bit strange,
1188 not sure if sdp csc is correct.
1189 */
1190 switch (ctrl->id) {
1191 /* standard ctrls */
1192 case V4L2_CID_BRIGHTNESS:
1193 cp_write(sd, 0x3c, ctrl->val);
1194 sdp_write(sd, 0x14, ctrl->val);
1195 /* ignore lsb sdp 0x17[3:2] */
1196 return 0;
1197 case V4L2_CID_CONTRAST:
1198 cp_write(sd, 0x3a, ctrl->val);
1199 sdp_write(sd, 0x13, ctrl->val);
1200 /* ignore lsb sdp 0x17[1:0] */
1201 return 0;
1202 case V4L2_CID_SATURATION:
1203 cp_write(sd, 0x3b, ctrl->val);
1204 sdp_write(sd, 0x15, ctrl->val);
1205 /* ignore lsb sdp 0x17[5:4] */
1206 return 0;
1207 case V4L2_CID_HUE:
1208 cp_write(sd, 0x3d, ctrl->val);
1209 sdp_write(sd, 0x16, ctrl->val);
1210 /* ignore lsb sdp 0x17[7:6] */
1211 return 0;
1212 /* custom ctrls */
1213 case V4L2_CID_ADV_RX_ANALOG_SAMPLING_PHASE:
1214 afe_write(sd, 0xc8, ctrl->val);
1215 return 0;
1216 case V4L2_CID_ADV_RX_FREE_RUN_COLOR_MANUAL:
1217 cp_write_and_or(sd, 0xbf, ~0x04, (ctrl->val << 2));
1218 sdp_write_and_or(sd, 0xdd, ~0x04, (ctrl->val << 2));
1219 return 0;
1220 case V4L2_CID_ADV_RX_FREE_RUN_COLOR: {
1221 u8 R = (ctrl->val & 0xff0000) >> 16;
1222 u8 G = (ctrl->val & 0x00ff00) >> 8;
1223 u8 B = (ctrl->val & 0x0000ff);
1224 /* RGB -> YUV, numerical approximation */
1225 int Y = 66 * R + 129 * G + 25 * B;
1226 int U = -38 * R - 74 * G + 112 * B;
1227 int V = 112 * R - 94 * G - 18 * B;
1228
1229 /* Scale down to 8 bits with rounding */
1230 Y = (Y + 128) >> 8;
1231 U = (U + 128) >> 8;
1232 V = (V + 128) >> 8;
1233 /* make U,V positive */
1234 Y += 16;
1235 U += 128;
1236 V += 128;
1237
1238 v4l2_dbg(1, debug, sd, "R %x, G %x, B %x\n", R, G, B);
1239 v4l2_dbg(1, debug, sd, "Y %x, U %x, V %x\n", Y, U, V);
1240
1241 /* CP */
1242 cp_write(sd, 0xc1, R);
1243 cp_write(sd, 0xc0, G);
1244 cp_write(sd, 0xc2, B);
1245 /* SDP */
1246 sdp_write(sd, 0xde, Y);
1247 sdp_write(sd, 0xdf, (V & 0xf0) | ((U >> 4) & 0x0f));
1248 return 0;
1249 }
1250 case V4L2_CID_DV_RX_RGB_RANGE:
1251 state->rgb_quantization_range = ctrl->val;
1252 set_rgb_quantization_range(sd);
1253 return 0;
1254 }
1255 return -EINVAL;
1256 }
1257
1258 static inline bool no_power(struct v4l2_subdev *sd)
1259 {
1260 return io_read(sd, 0x0c) & 0x24;
1261 }
1262
1263 static inline bool no_cp_signal(struct v4l2_subdev *sd)
1264 {
1265 return ((cp_read(sd, 0xb5) & 0xd0) != 0xd0) || !(cp_read(sd, 0xb1) & 0x80);
1266 }
1267
1268 static inline bool is_hdmi(struct v4l2_subdev *sd)
1269 {
1270 return hdmi_read(sd, 0x05) & 0x80;
1271 }
1272
1273 static int adv7842_g_input_status(struct v4l2_subdev *sd, u32 *status)
1274 {
1275 struct adv7842_state *state = to_state(sd);
1276
1277 *status = 0;
1278
1279 if (io_read(sd, 0x0c) & 0x24)
1280 *status |= V4L2_IN_ST_NO_POWER;
1281
1282 if (state->mode == ADV7842_MODE_SDP) {
1283 /* status from SDP block */
1284 if (!(sdp_read(sd, 0x5A) & 0x01))
1285 *status |= V4L2_IN_ST_NO_SIGNAL;
1286
1287 v4l2_dbg(1, debug, sd, "%s: SDP status = 0x%x\n",
1288 __func__, *status);
1289 return 0;
1290 }
1291 /* status from CP block */
1292 if ((cp_read(sd, 0xb5) & 0xd0) != 0xd0 ||
1293 !(cp_read(sd, 0xb1) & 0x80))
1294 /* TODO channel 2 */
1295 *status |= V4L2_IN_ST_NO_SIGNAL;
1296
1297 if (is_digital_input(sd) && ((io_read(sd, 0x74) & 0x03) != 0x03))
1298 *status |= V4L2_IN_ST_NO_SIGNAL;
1299
1300 v4l2_dbg(1, debug, sd, "%s: CP status = 0x%x\n",
1301 __func__, *status);
1302
1303 return 0;
1304 }
1305
1306 struct stdi_readback {
1307 u16 bl, lcf, lcvs;
1308 u8 hs_pol, vs_pol;
1309 bool interlaced;
1310 };
1311
1312 static int stdi2dv_timings(struct v4l2_subdev *sd,
1313 struct stdi_readback *stdi,
1314 struct v4l2_dv_timings *timings)
1315 {
1316 struct adv7842_state *state = to_state(sd);
1317 u32 hfreq = (ADV7842_fsc * 8) / stdi->bl;
1318 u32 pix_clk;
1319 int i;
1320
1321 for (i = 0; v4l2_dv_timings_presets[i].bt.width; i++) {
1322 const struct v4l2_bt_timings *bt = &v4l2_dv_timings_presets[i].bt;
1323
1324 if (!v4l2_valid_dv_timings(&v4l2_dv_timings_presets[i],
1325 adv7842_get_dv_timings_cap(sd),
1326 adv7842_check_dv_timings, NULL))
1327 continue;
1328 if (vtotal(bt) != stdi->lcf + 1)
1329 continue;
1330 if (bt->vsync != stdi->lcvs)
1331 continue;
1332
1333 pix_clk = hfreq * htotal(bt);
1334
1335 if ((pix_clk < bt->pixelclock + 1000000) &&
1336 (pix_clk > bt->pixelclock - 1000000)) {
1337 *timings = v4l2_dv_timings_presets[i];
1338 return 0;
1339 }
1340 }
1341
1342 if (v4l2_detect_cvt(stdi->lcf + 1, hfreq, stdi->lcvs,
1343 (stdi->hs_pol == '+' ? V4L2_DV_HSYNC_POS_POL : 0) |
1344 (stdi->vs_pol == '+' ? V4L2_DV_VSYNC_POS_POL : 0),
1345 timings))
1346 return 0;
1347 if (v4l2_detect_gtf(stdi->lcf + 1, hfreq, stdi->lcvs,
1348 (stdi->hs_pol == '+' ? V4L2_DV_HSYNC_POS_POL : 0) |
1349 (stdi->vs_pol == '+' ? V4L2_DV_VSYNC_POS_POL : 0),
1350 state->aspect_ratio, timings))
1351 return 0;
1352
1353 v4l2_dbg(2, debug, sd,
1354 "%s: No format candidate found for lcvs = %d, lcf=%d, bl = %d, %chsync, %cvsync\n",
1355 __func__, stdi->lcvs, stdi->lcf, stdi->bl,
1356 stdi->hs_pol, stdi->vs_pol);
1357 return -1;
1358 }
1359
1360 static int read_stdi(struct v4l2_subdev *sd, struct stdi_readback *stdi)
1361 {
1362 u32 status;
1363
1364 adv7842_g_input_status(sd, &status);
1365 if (status & V4L2_IN_ST_NO_SIGNAL) {
1366 v4l2_dbg(2, debug, sd, "%s: no signal\n", __func__);
1367 return -ENOLINK;
1368 }
1369
1370 stdi->bl = ((cp_read(sd, 0xb1) & 0x3f) << 8) | cp_read(sd, 0xb2);
1371 stdi->lcf = ((cp_read(sd, 0xb3) & 0x7) << 8) | cp_read(sd, 0xb4);
1372 stdi->lcvs = cp_read(sd, 0xb3) >> 3;
1373
1374 if ((cp_read(sd, 0xb5) & 0x80) && ((cp_read(sd, 0xb5) & 0x03) == 0x01)) {
1375 stdi->hs_pol = ((cp_read(sd, 0xb5) & 0x10) ?
1376 ((cp_read(sd, 0xb5) & 0x08) ? '+' : '-') : 'x');
1377 stdi->vs_pol = ((cp_read(sd, 0xb5) & 0x40) ?
1378 ((cp_read(sd, 0xb5) & 0x20) ? '+' : '-') : 'x');
1379 } else {
1380 stdi->hs_pol = 'x';
1381 stdi->vs_pol = 'x';
1382 }
1383 stdi->interlaced = (cp_read(sd, 0xb1) & 0x40) ? true : false;
1384
1385 if (stdi->lcf < 239 || stdi->bl < 8 || stdi->bl == 0x3fff) {
1386 v4l2_dbg(2, debug, sd, "%s: invalid signal\n", __func__);
1387 return -ENOLINK;
1388 }
1389
1390 v4l2_dbg(2, debug, sd,
1391 "%s: lcf (frame height - 1) = %d, bl = %d, lcvs (vsync) = %d, %chsync, %cvsync, %s\n",
1392 __func__, stdi->lcf, stdi->bl, stdi->lcvs,
1393 stdi->hs_pol, stdi->vs_pol,
1394 stdi->interlaced ? "interlaced" : "progressive");
1395
1396 return 0;
1397 }
1398
1399 static int adv7842_enum_dv_timings(struct v4l2_subdev *sd,
1400 struct v4l2_enum_dv_timings *timings)
1401 {
1402 if (timings->pad != 0)
1403 return -EINVAL;
1404
1405 return v4l2_enum_dv_timings_cap(timings,
1406 adv7842_get_dv_timings_cap(sd), adv7842_check_dv_timings, NULL);
1407 }
1408
1409 static int adv7842_dv_timings_cap(struct v4l2_subdev *sd,
1410 struct v4l2_dv_timings_cap *cap)
1411 {
1412 if (cap->pad != 0)
1413 return -EINVAL;
1414
1415 *cap = *adv7842_get_dv_timings_cap(sd);
1416 return 0;
1417 }
1418
1419 /* Fill the optional fields .standards and .flags in struct v4l2_dv_timings
1420 if the format is listed in adv7842_timings[] */
1421 static void adv7842_fill_optional_dv_timings_fields(struct v4l2_subdev *sd,
1422 struct v4l2_dv_timings *timings)
1423 {
1424 v4l2_find_dv_timings_cap(timings, adv7842_get_dv_timings_cap(sd),
1425 is_digital_input(sd) ? 250000 : 1000000,
1426 adv7842_check_dv_timings, NULL);
1427 }
1428
1429 static int adv7842_query_dv_timings(struct v4l2_subdev *sd,
1430 struct v4l2_dv_timings *timings)
1431 {
1432 struct adv7842_state *state = to_state(sd);
1433 struct v4l2_bt_timings *bt = &timings->bt;
1434 struct stdi_readback stdi = { 0 };
1435
1436 v4l2_dbg(1, debug, sd, "%s:\n", __func__);
1437
1438 /* SDP block */
1439 if (state->mode == ADV7842_MODE_SDP)
1440 return -ENODATA;
1441
1442 /* read STDI */
1443 if (read_stdi(sd, &stdi)) {
1444 state->restart_stdi_once = true;
1445 v4l2_dbg(1, debug, sd, "%s: no valid signal\n", __func__);
1446 return -ENOLINK;
1447 }
1448 bt->interlaced = stdi.interlaced ?
1449 V4L2_DV_INTERLACED : V4L2_DV_PROGRESSIVE;
1450
1451 if (is_digital_input(sd)) {
1452 uint32_t freq;
1453
1454 timings->type = V4L2_DV_BT_656_1120;
1455
1456 bt->width = (hdmi_read(sd, 0x07) & 0x0f) * 256 + hdmi_read(sd, 0x08);
1457 bt->height = (hdmi_read(sd, 0x09) & 0x0f) * 256 + hdmi_read(sd, 0x0a);
1458 freq = ((hdmi_read(sd, 0x51) << 1) + (hdmi_read(sd, 0x52) >> 7)) * 1000000;
1459 freq += ((hdmi_read(sd, 0x52) & 0x7f) * 7813);
1460 if (is_hdmi(sd)) {
1461 /* adjust for deep color mode */
1462 freq = freq * 8 / (((hdmi_read(sd, 0x0b) & 0xc0) >> 6) * 2 + 8);
1463 }
1464 bt->pixelclock = freq;
1465 bt->hfrontporch = (hdmi_read(sd, 0x20) & 0x03) * 256 +
1466 hdmi_read(sd, 0x21);
1467 bt->hsync = (hdmi_read(sd, 0x22) & 0x03) * 256 +
1468 hdmi_read(sd, 0x23);
1469 bt->hbackporch = (hdmi_read(sd, 0x24) & 0x03) * 256 +
1470 hdmi_read(sd, 0x25);
1471 bt->vfrontporch = ((hdmi_read(sd, 0x2a) & 0x1f) * 256 +
1472 hdmi_read(sd, 0x2b)) / 2;
1473 bt->vsync = ((hdmi_read(sd, 0x2e) & 0x1f) * 256 +
1474 hdmi_read(sd, 0x2f)) / 2;
1475 bt->vbackporch = ((hdmi_read(sd, 0x32) & 0x1f) * 256 +
1476 hdmi_read(sd, 0x33)) / 2;
1477 bt->polarities = ((hdmi_read(sd, 0x05) & 0x10) ? V4L2_DV_VSYNC_POS_POL : 0) |
1478 ((hdmi_read(sd, 0x05) & 0x20) ? V4L2_DV_HSYNC_POS_POL : 0);
1479 if (bt->interlaced == V4L2_DV_INTERLACED) {
1480 bt->height += (hdmi_read(sd, 0x0b) & 0x0f) * 256 +
1481 hdmi_read(sd, 0x0c);
1482 bt->il_vfrontporch = ((hdmi_read(sd, 0x2c) & 0x1f) * 256 +
1483 hdmi_read(sd, 0x2d)) / 2;
1484 bt->il_vsync = ((hdmi_read(sd, 0x30) & 0x1f) * 256 +
1485 hdmi_read(sd, 0x31)) / 2;
1486 bt->vbackporch = ((hdmi_read(sd, 0x34) & 0x1f) * 256 +
1487 hdmi_read(sd, 0x35)) / 2;
1488 }
1489 adv7842_fill_optional_dv_timings_fields(sd, timings);
1490 } else {
1491 /* find format
1492 * Since LCVS values are inaccurate [REF_03, p. 339-340],
1493 * stdi2dv_timings() is called with lcvs +-1 if the first attempt fails.
1494 */
1495 if (!stdi2dv_timings(sd, &stdi, timings))
1496 goto found;
1497 stdi.lcvs += 1;
1498 v4l2_dbg(1, debug, sd, "%s: lcvs + 1 = %d\n", __func__, stdi.lcvs);
1499 if (!stdi2dv_timings(sd, &stdi, timings))
1500 goto found;
1501 stdi.lcvs -= 2;
1502 v4l2_dbg(1, debug, sd, "%s: lcvs - 1 = %d\n", __func__, stdi.lcvs);
1503 if (stdi2dv_timings(sd, &stdi, timings)) {
1504 /*
1505 * The STDI block may measure wrong values, especially
1506 * for lcvs and lcf. If the driver can not find any
1507 * valid timing, the STDI block is restarted to measure
1508 * the video timings again. The function will return an
1509 * error, but the restart of STDI will generate a new
1510 * STDI interrupt and the format detection process will
1511 * restart.
1512 */
1513 if (state->restart_stdi_once) {
1514 v4l2_dbg(1, debug, sd, "%s: restart STDI\n", __func__);
1515 /* TODO restart STDI for Sync Channel 2 */
1516 /* enter one-shot mode */
1517 cp_write_and_or(sd, 0x86, 0xf9, 0x00);
1518 /* trigger STDI restart */
1519 cp_write_and_or(sd, 0x86, 0xf9, 0x04);
1520 /* reset to continuous mode */
1521 cp_write_and_or(sd, 0x86, 0xf9, 0x02);
1522 state->restart_stdi_once = false;
1523 return -ENOLINK;
1524 }
1525 v4l2_dbg(1, debug, sd, "%s: format not supported\n", __func__);
1526 return -ERANGE;
1527 }
1528 state->restart_stdi_once = true;
1529 }
1530 found:
1531
1532 if (debug > 1)
1533 v4l2_print_dv_timings(sd->name, "adv7842_query_dv_timings:",
1534 timings, true);
1535 return 0;
1536 }
1537
1538 static int adv7842_s_dv_timings(struct v4l2_subdev *sd,
1539 struct v4l2_dv_timings *timings)
1540 {
1541 struct adv7842_state *state = to_state(sd);
1542 struct v4l2_bt_timings *bt;
1543 int err;
1544
1545 v4l2_dbg(1, debug, sd, "%s:\n", __func__);
1546
1547 if (state->mode == ADV7842_MODE_SDP)
1548 return -ENODATA;
1549
1550 if (v4l2_match_dv_timings(&state->timings, timings, 0)) {
1551 v4l2_dbg(1, debug, sd, "%s: no change\n", __func__);
1552 return 0;
1553 }
1554
1555 bt = &timings->bt;
1556
1557 if (!v4l2_valid_dv_timings(timings, adv7842_get_dv_timings_cap(sd),
1558 adv7842_check_dv_timings, NULL))
1559 return -ERANGE;
1560
1561 adv7842_fill_optional_dv_timings_fields(sd, timings);
1562
1563 state->timings = *timings;
1564
1565 cp_write(sd, 0x91, bt->interlaced ? 0x40 : 0x00);
1566
1567 /* Use prim_mode and vid_std when available */
1568 err = configure_predefined_video_timings(sd, timings);
1569 if (err) {
1570 /* custom settings when the video format
1571 does not have prim_mode/vid_std */
1572 configure_custom_video_timings(sd, bt);
1573 }
1574
1575 set_rgb_quantization_range(sd);
1576
1577
1578 if (debug > 1)
1579 v4l2_print_dv_timings(sd->name, "adv7842_s_dv_timings: ",
1580 timings, true);
1581 return 0;
1582 }
1583
1584 static int adv7842_g_dv_timings(struct v4l2_subdev *sd,
1585 struct v4l2_dv_timings *timings)
1586 {
1587 struct adv7842_state *state = to_state(sd);
1588
1589 if (state->mode == ADV7842_MODE_SDP)
1590 return -ENODATA;
1591 *timings = state->timings;
1592 return 0;
1593 }
1594
1595 static void enable_input(struct v4l2_subdev *sd)
1596 {
1597 struct adv7842_state *state = to_state(sd);
1598
1599 set_rgb_quantization_range(sd);
1600 switch (state->mode) {
1601 case ADV7842_MODE_SDP:
1602 case ADV7842_MODE_COMP:
1603 case ADV7842_MODE_RGB:
1604 io_write(sd, 0x15, 0xb0); /* Disable Tristate of Pins (no audio) */
1605 break;
1606 case ADV7842_MODE_HDMI:
1607 hdmi_write(sd, 0x01, 0x00); /* Enable HDMI clock terminators */
1608 io_write(sd, 0x15, 0xa0); /* Disable Tristate of Pins */
1609 hdmi_write_and_or(sd, 0x1a, 0xef, 0x00); /* Unmute audio */
1610 break;
1611 default:
1612 v4l2_dbg(2, debug, sd, "%s: Unknown mode %d\n",
1613 __func__, state->mode);
1614 break;
1615 }
1616 }
1617
1618 static void disable_input(struct v4l2_subdev *sd)
1619 {
1620 hdmi_write_and_or(sd, 0x1a, 0xef, 0x10); /* Mute audio [REF_01, c. 2.2.2] */
1621 msleep(16); /* 512 samples with >= 32 kHz sample rate [REF_03, c. 8.29] */
1622 io_write(sd, 0x15, 0xbe); /* Tristate all outputs from video core */
1623 hdmi_write(sd, 0x01, 0x78); /* Disable HDMI clock terminators */
1624 }
1625
1626 static void sdp_csc_coeff(struct v4l2_subdev *sd,
1627 const struct adv7842_sdp_csc_coeff *c)
1628 {
1629 /* csc auto/manual */
1630 sdp_io_write_and_or(sd, 0xe0, 0xbf, c->manual ? 0x00 : 0x40);
1631
1632 if (!c->manual)
1633 return;
1634
1635 /* csc scaling */
1636 sdp_io_write_and_or(sd, 0xe0, 0x7f, c->scaling == 2 ? 0x80 : 0x00);
1637
1638 /* A coeff */
1639 sdp_io_write_and_or(sd, 0xe0, 0xe0, c->A1 >> 8);
1640 sdp_io_write(sd, 0xe1, c->A1);
1641 sdp_io_write_and_or(sd, 0xe2, 0xe0, c->A2 >> 8);
1642 sdp_io_write(sd, 0xe3, c->A2);
1643 sdp_io_write_and_or(sd, 0xe4, 0xe0, c->A3 >> 8);
1644 sdp_io_write(sd, 0xe5, c->A3);
1645
1646 /* A scale */
1647 sdp_io_write_and_or(sd, 0xe6, 0x80, c->A4 >> 8);
1648 sdp_io_write(sd, 0xe7, c->A4);
1649
1650 /* B coeff */
1651 sdp_io_write_and_or(sd, 0xe8, 0xe0, c->B1 >> 8);
1652 sdp_io_write(sd, 0xe9, c->B1);
1653 sdp_io_write_and_or(sd, 0xea, 0xe0, c->B2 >> 8);
1654 sdp_io_write(sd, 0xeb, c->B2);
1655 sdp_io_write_and_or(sd, 0xec, 0xe0, c->B3 >> 8);
1656 sdp_io_write(sd, 0xed, c->B3);
1657
1658 /* B scale */
1659 sdp_io_write_and_or(sd, 0xee, 0x80, c->B4 >> 8);
1660 sdp_io_write(sd, 0xef, c->B4);
1661
1662 /* C coeff */
1663 sdp_io_write_and_or(sd, 0xf0, 0xe0, c->C1 >> 8);
1664 sdp_io_write(sd, 0xf1, c->C1);
1665 sdp_io_write_and_or(sd, 0xf2, 0xe0, c->C2 >> 8);
1666 sdp_io_write(sd, 0xf3, c->C2);
1667 sdp_io_write_and_or(sd, 0xf4, 0xe0, c->C3 >> 8);
1668 sdp_io_write(sd, 0xf5, c->C3);
1669
1670 /* C scale */
1671 sdp_io_write_and_or(sd, 0xf6, 0x80, c->C4 >> 8);
1672 sdp_io_write(sd, 0xf7, c->C4);
1673 }
1674
1675 static void select_input(struct v4l2_subdev *sd,
1676 enum adv7842_vid_std_select vid_std_select)
1677 {
1678 struct adv7842_state *state = to_state(sd);
1679
1680 switch (state->mode) {
1681 case ADV7842_MODE_SDP:
1682 io_write(sd, 0x00, vid_std_select); /* video std: CVBS or YC mode */
1683 io_write(sd, 0x01, 0); /* prim mode */
1684 /* enable embedded syncs for auto graphics mode */
1685 cp_write_and_or(sd, 0x81, 0xef, 0x10);
1686
1687 afe_write(sd, 0x00, 0x00); /* power up ADC */
1688 afe_write(sd, 0xc8, 0x00); /* phase control */
1689
1690 io_write(sd, 0xdd, 0x90); /* Manual 2x output clock */
1691 /* script says register 0xde, which don't exist in manual */
1692
1693 /* Manual analog input muxing mode, CVBS (6.4)*/
1694 afe_write_and_or(sd, 0x02, 0x7f, 0x80);
1695 if (vid_std_select == ADV7842_SDP_VID_STD_CVBS_SD_4x1) {
1696 afe_write(sd, 0x03, 0xa0); /* ADC0 to AIN10 (CVBS), ADC1 N/C*/
1697 afe_write(sd, 0x04, 0x00); /* ADC2 N/C,ADC3 N/C*/
1698 } else {
1699 afe_write(sd, 0x03, 0xa0); /* ADC0 to AIN10 (CVBS), ADC1 N/C*/
1700 afe_write(sd, 0x04, 0xc0); /* ADC2 to AIN12, ADC3 N/C*/
1701 }
1702 afe_write(sd, 0x0c, 0x1f); /* ADI recommend write */
1703 afe_write(sd, 0x12, 0x63); /* ADI recommend write */
1704
1705 sdp_io_write(sd, 0xb2, 0x60); /* Disable AV codes */
1706 sdp_io_write(sd, 0xc8, 0xe3); /* Disable Ancillary data */
1707
1708 /* SDP recommended settings */
1709 sdp_write(sd, 0x00, 0x3F); /* Autodetect PAL NTSC (not SECAM) */
1710 sdp_write(sd, 0x01, 0x00); /* Pedestal Off */
1711
1712 sdp_write(sd, 0x03, 0xE4); /* Manual VCR Gain Luma 0x40B */
1713 sdp_write(sd, 0x04, 0x0B); /* Manual Luma setting */
1714 sdp_write(sd, 0x05, 0xC3); /* Manual Chroma setting 0x3FE */
1715 sdp_write(sd, 0x06, 0xFE); /* Manual Chroma setting */
1716 sdp_write(sd, 0x12, 0x0D); /* Frame TBC,I_P, 3D comb enabled */
1717 sdp_write(sd, 0xA7, 0x00); /* ADI Recommended Write */
1718 sdp_io_write(sd, 0xB0, 0x00); /* Disable H and v blanking */
1719
1720 /* deinterlacer enabled and 3D comb */
1721 sdp_write_and_or(sd, 0x12, 0xf6, 0x09);
1722
1723 break;
1724
1725 case ADV7842_MODE_COMP:
1726 case ADV7842_MODE_RGB:
1727 /* Automatic analog input muxing mode */
1728 afe_write_and_or(sd, 0x02, 0x7f, 0x00);
1729 /* set mode and select free run resolution */
1730 io_write(sd, 0x00, vid_std_select); /* video std */
1731 io_write(sd, 0x01, 0x02); /* prim mode */
1732 cp_write_and_or(sd, 0x81, 0xef, 0x10); /* enable embedded syncs
1733 for auto graphics mode */
1734
1735 afe_write(sd, 0x00, 0x00); /* power up ADC */
1736 afe_write(sd, 0xc8, 0x00); /* phase control */
1737 if (state->mode == ADV7842_MODE_COMP) {
1738 /* force to YCrCb */
1739 io_write_and_or(sd, 0x02, 0x0f, 0x60);
1740 } else {
1741 /* force to RGB */
1742 io_write_and_or(sd, 0x02, 0x0f, 0x10);
1743 }
1744
1745 /* set ADI recommended settings for digitizer */
1746 /* "ADV7842 Register Settings Recommendations
1747 * (rev. 1.8, November 2010)" p. 9. */
1748 afe_write(sd, 0x0c, 0x1f); /* ADC Range improvement */
1749 afe_write(sd, 0x12, 0x63); /* ADC Range improvement */
1750
1751 /* set to default gain for RGB */
1752 cp_write(sd, 0x73, 0x10);
1753 cp_write(sd, 0x74, 0x04);
1754 cp_write(sd, 0x75, 0x01);
1755 cp_write(sd, 0x76, 0x00);
1756
1757 cp_write(sd, 0x3e, 0x04); /* CP core pre-gain control */
1758 cp_write(sd, 0xc3, 0x39); /* CP coast control. Graphics mode */
1759 cp_write(sd, 0x40, 0x5c); /* CP core pre-gain control. Graphics mode */
1760 break;
1761
1762 case ADV7842_MODE_HDMI:
1763 /* Automatic analog input muxing mode */
1764 afe_write_and_or(sd, 0x02, 0x7f, 0x00);
1765 /* set mode and select free run resolution */
1766 if (state->hdmi_port_a)
1767 hdmi_write(sd, 0x00, 0x02); /* select port A */
1768 else
1769 hdmi_write(sd, 0x00, 0x03); /* select port B */
1770 io_write(sd, 0x00, vid_std_select); /* video std */
1771 io_write(sd, 0x01, 5); /* prim mode */
1772 cp_write_and_or(sd, 0x81, 0xef, 0x00); /* disable embedded syncs
1773 for auto graphics mode */
1774
1775 /* set ADI recommended settings for HDMI: */
1776 /* "ADV7842 Register Settings Recommendations
1777 * (rev. 1.8, November 2010)" p. 3. */
1778 hdmi_write(sd, 0xc0, 0x00);
1779 hdmi_write(sd, 0x0d, 0x34); /* ADI recommended write */
1780 hdmi_write(sd, 0x3d, 0x10); /* ADI recommended write */
1781 hdmi_write(sd, 0x44, 0x85); /* TMDS PLL optimization */
1782 hdmi_write(sd, 0x46, 0x1f); /* ADI recommended write */
1783 hdmi_write(sd, 0x57, 0xb6); /* TMDS PLL optimization */
1784 hdmi_write(sd, 0x58, 0x03); /* TMDS PLL optimization */
1785 hdmi_write(sd, 0x60, 0x88); /* TMDS PLL optimization */
1786 hdmi_write(sd, 0x61, 0x88); /* TMDS PLL optimization */
1787 hdmi_write(sd, 0x6c, 0x18); /* Disable ISRC clearing bit,
1788 Improve robustness */
1789 hdmi_write(sd, 0x75, 0x10); /* DDC drive strength */
1790 hdmi_write(sd, 0x85, 0x1f); /* equaliser */
1791 hdmi_write(sd, 0x87, 0x70); /* ADI recommended write */
1792 hdmi_write(sd, 0x89, 0x04); /* equaliser */
1793 hdmi_write(sd, 0x8a, 0x1e); /* equaliser */
1794 hdmi_write(sd, 0x93, 0x04); /* equaliser */
1795 hdmi_write(sd, 0x94, 0x1e); /* equaliser */
1796 hdmi_write(sd, 0x99, 0xa1); /* ADI recommended write */
1797 hdmi_write(sd, 0x9b, 0x09); /* ADI recommended write */
1798 hdmi_write(sd, 0x9d, 0x02); /* equaliser */
1799
1800 afe_write(sd, 0x00, 0xff); /* power down ADC */
1801 afe_write(sd, 0xc8, 0x40); /* phase control */
1802
1803 /* set to default gain for HDMI */
1804 cp_write(sd, 0x73, 0x10);
1805 cp_write(sd, 0x74, 0x04);
1806 cp_write(sd, 0x75, 0x01);
1807 cp_write(sd, 0x76, 0x00);
1808
1809 /* reset ADI recommended settings for digitizer */
1810 /* "ADV7842 Register Settings Recommendations
1811 * (rev. 2.5, June 2010)" p. 17. */
1812 afe_write(sd, 0x12, 0xfb); /* ADC noise shaping filter controls */
1813 afe_write(sd, 0x0c, 0x0d); /* CP core gain controls */
1814 cp_write(sd, 0x3e, 0x00); /* CP core pre-gain control */
1815
1816 /* CP coast control */
1817 cp_write(sd, 0xc3, 0x33); /* Component mode */
1818
1819 /* color space conversion, autodetect color space */
1820 io_write_and_or(sd, 0x02, 0x0f, 0xf0);
1821 break;
1822
1823 default:
1824 v4l2_dbg(2, debug, sd, "%s: Unknown mode %d\n",
1825 __func__, state->mode);
1826 break;
1827 }
1828 }
1829
1830 static int adv7842_s_routing(struct v4l2_subdev *sd,
1831 u32 input, u32 output, u32 config)
1832 {
1833 struct adv7842_state *state = to_state(sd);
1834
1835 v4l2_dbg(2, debug, sd, "%s: input %d\n", __func__, input);
1836
1837 switch (input) {
1838 case ADV7842_SELECT_HDMI_PORT_A:
1839 state->mode = ADV7842_MODE_HDMI;
1840 state->vid_std_select = ADV7842_HDMI_COMP_VID_STD_HD_1250P;
1841 state->hdmi_port_a = true;
1842 break;
1843 case ADV7842_SELECT_HDMI_PORT_B:
1844 state->mode = ADV7842_MODE_HDMI;
1845 state->vid_std_select = ADV7842_HDMI_COMP_VID_STD_HD_1250P;
1846 state->hdmi_port_a = false;
1847 break;
1848 case ADV7842_SELECT_VGA_COMP:
1849 state->mode = ADV7842_MODE_COMP;
1850 state->vid_std_select = ADV7842_RGB_VID_STD_AUTO_GRAPH_MODE;
1851 break;
1852 case ADV7842_SELECT_VGA_RGB:
1853 state->mode = ADV7842_MODE_RGB;
1854 state->vid_std_select = ADV7842_RGB_VID_STD_AUTO_GRAPH_MODE;
1855 break;
1856 case ADV7842_SELECT_SDP_CVBS:
1857 state->mode = ADV7842_MODE_SDP;
1858 state->vid_std_select = ADV7842_SDP_VID_STD_CVBS_SD_4x1;
1859 break;
1860 case ADV7842_SELECT_SDP_YC:
1861 state->mode = ADV7842_MODE_SDP;
1862 state->vid_std_select = ADV7842_SDP_VID_STD_YC_SD4_x1;
1863 break;
1864 default:
1865 return -EINVAL;
1866 }
1867
1868 disable_input(sd);
1869 select_input(sd, state->vid_std_select);
1870 enable_input(sd);
1871
1872 v4l2_subdev_notify(sd, ADV7842_FMT_CHANGE, NULL);
1873
1874 return 0;
1875 }
1876
1877 static int adv7842_enum_mbus_fmt(struct v4l2_subdev *sd, unsigned int index,
1878 enum v4l2_mbus_pixelcode *code)
1879 {
1880 if (index)
1881 return -EINVAL;
1882 /* Good enough for now */
1883 *code = V4L2_MBUS_FMT_FIXED;
1884 return 0;
1885 }
1886
1887 static int adv7842_g_mbus_fmt(struct v4l2_subdev *sd,
1888 struct v4l2_mbus_framefmt *fmt)
1889 {
1890 struct adv7842_state *state = to_state(sd);
1891
1892 fmt->width = state->timings.bt.width;
1893 fmt->height = state->timings.bt.height;
1894 fmt->code = V4L2_MBUS_FMT_FIXED;
1895 fmt->field = V4L2_FIELD_NONE;
1896
1897 if (state->mode == ADV7842_MODE_SDP) {
1898 /* SPD block */
1899 if (!(sdp_read(sd, 0x5A) & 0x01))
1900 return -EINVAL;
1901 fmt->width = 720;
1902 /* valid signal */
1903 if (state->norm & V4L2_STD_525_60)
1904 fmt->height = 480;
1905 else
1906 fmt->height = 576;
1907 fmt->colorspace = V4L2_COLORSPACE_SMPTE170M;
1908 return 0;
1909 }
1910
1911 if (state->timings.bt.standards & V4L2_DV_BT_STD_CEA861) {
1912 fmt->colorspace = (state->timings.bt.height <= 576) ?
1913 V4L2_COLORSPACE_SMPTE170M : V4L2_COLORSPACE_REC709;
1914 }
1915 return 0;
1916 }
1917
1918 static void adv7842_irq_enable(struct v4l2_subdev *sd, bool enable)
1919 {
1920 if (enable) {
1921 /* Enable SSPD, STDI and CP locked/unlocked interrupts */
1922 io_write(sd, 0x46, 0x9c);
1923 /* ESDP_50HZ_DET interrupt */
1924 io_write(sd, 0x5a, 0x10);
1925 /* Enable CABLE_DET_A/B_ST (+5v) interrupt */
1926 io_write(sd, 0x73, 0x03);
1927 /* Enable V_LOCKED and DE_REGEN_LCK interrupts */
1928 io_write(sd, 0x78, 0x03);
1929 /* Enable SDP Standard Detection Change and SDP Video Detected */
1930 io_write(sd, 0xa0, 0x09);
1931 /* Enable HDMI_MODE interrupt */
1932 io_write(sd, 0x69, 0x08);
1933 } else {
1934 io_write(sd, 0x46, 0x0);
1935 io_write(sd, 0x5a, 0x0);
1936 io_write(sd, 0x73, 0x0);
1937 io_write(sd, 0x78, 0x0);
1938 io_write(sd, 0xa0, 0x0);
1939 io_write(sd, 0x69, 0x0);
1940 }
1941 }
1942
1943 static int adv7842_isr(struct v4l2_subdev *sd, u32 status, bool *handled)
1944 {
1945 struct adv7842_state *state = to_state(sd);
1946 u8 fmt_change_cp, fmt_change_digital, fmt_change_sdp;
1947 u8 irq_status[6];
1948
1949 adv7842_irq_enable(sd, false);
1950
1951 /* read status */
1952 irq_status[0] = io_read(sd, 0x43);
1953 irq_status[1] = io_read(sd, 0x57);
1954 irq_status[2] = io_read(sd, 0x70);
1955 irq_status[3] = io_read(sd, 0x75);
1956 irq_status[4] = io_read(sd, 0x9d);
1957 irq_status[5] = io_read(sd, 0x66);
1958
1959 /* and clear */
1960 if (irq_status[0])
1961 io_write(sd, 0x44, irq_status[0]);
1962 if (irq_status[1])
1963 io_write(sd, 0x58, irq_status[1]);
1964 if (irq_status[2])
1965 io_write(sd, 0x71, irq_status[2]);
1966 if (irq_status[3])
1967 io_write(sd, 0x76, irq_status[3]);
1968 if (irq_status[4])
1969 io_write(sd, 0x9e, irq_status[4]);
1970 if (irq_status[5])
1971 io_write(sd, 0x67, irq_status[5]);
1972
1973 adv7842_irq_enable(sd, true);
1974
1975 v4l2_dbg(1, debug, sd, "%s: irq %x, %x, %x, %x, %x, %x\n", __func__,
1976 irq_status[0], irq_status[1], irq_status[2],
1977 irq_status[3], irq_status[4], irq_status[5]);
1978
1979 /* format change CP */
1980 fmt_change_cp = irq_status[0] & 0x9c;
1981
1982 /* format change SDP */
1983 if (state->mode == ADV7842_MODE_SDP)
1984 fmt_change_sdp = (irq_status[1] & 0x30) | (irq_status[4] & 0x09);
1985 else
1986 fmt_change_sdp = 0;
1987
1988 /* digital format CP */
1989 if (is_digital_input(sd))
1990 fmt_change_digital = irq_status[3] & 0x03;
1991 else
1992 fmt_change_digital = 0;
1993
1994 /* format change */
1995 if (fmt_change_cp || fmt_change_digital || fmt_change_sdp) {
1996 v4l2_dbg(1, debug, sd,
1997 "%s: fmt_change_cp = 0x%x, fmt_change_digital = 0x%x, fmt_change_sdp = 0x%x\n",
1998 __func__, fmt_change_cp, fmt_change_digital,
1999 fmt_change_sdp);
2000 v4l2_subdev_notify(sd, ADV7842_FMT_CHANGE, NULL);
2001 if (handled)
2002 *handled = true;
2003 }
2004
2005 /* HDMI/DVI mode */
2006 if (irq_status[5] & 0x08) {
2007 v4l2_dbg(1, debug, sd, "%s: irq %s mode\n", __func__,
2008 (io_read(sd, 0x65) & 0x08) ? "HDMI" : "DVI");
2009 set_rgb_quantization_range(sd);
2010 if (handled)
2011 *handled = true;
2012 }
2013
2014 /* tx 5v detect */
2015 if (irq_status[2] & 0x3) {
2016 v4l2_dbg(1, debug, sd, "%s: irq tx_5v\n", __func__);
2017 adv7842_s_detect_tx_5v_ctrl(sd);
2018 if (handled)
2019 *handled = true;
2020 }
2021 return 0;
2022 }
2023
2024 static int adv7842_get_edid(struct v4l2_subdev *sd, struct v4l2_edid *edid)
2025 {
2026 struct adv7842_state *state = to_state(sd);
2027 u8 *data = NULL;
2028
2029 if (edid->pad > ADV7842_EDID_PORT_VGA)
2030 return -EINVAL;
2031 if (edid->blocks == 0)
2032 return -EINVAL;
2033 if (edid->blocks > 2)
2034 return -EINVAL;
2035 if (edid->start_block > 1)
2036 return -EINVAL;
2037 if (edid->start_block == 1)
2038 edid->blocks = 1;
2039
2040 switch (edid->pad) {
2041 case ADV7842_EDID_PORT_A:
2042 case ADV7842_EDID_PORT_B:
2043 if (state->hdmi_edid.present & (0x04 << edid->pad))
2044 data = state->hdmi_edid.edid;
2045 break;
2046 case ADV7842_EDID_PORT_VGA:
2047 if (state->vga_edid.present)
2048 data = state->vga_edid.edid;
2049 break;
2050 default:
2051 return -EINVAL;
2052 }
2053 if (!data)
2054 return -ENODATA;
2055
2056 memcpy(edid->edid,
2057 data + edid->start_block * 128,
2058 edid->blocks * 128);
2059 return 0;
2060 }
2061
2062 static int adv7842_set_edid(struct v4l2_subdev *sd, struct v4l2_edid *e)
2063 {
2064 struct adv7842_state *state = to_state(sd);
2065 int err = 0;
2066
2067 if (e->pad > ADV7842_EDID_PORT_VGA)
2068 return -EINVAL;
2069 if (e->start_block != 0)
2070 return -EINVAL;
2071 if (e->blocks > 2)
2072 return -E2BIG;
2073
2074 /* todo, per edid */
2075 state->aspect_ratio = v4l2_calc_aspect_ratio(e->edid[0x15],
2076 e->edid[0x16]);
2077
2078 switch (e->pad) {
2079 case ADV7842_EDID_PORT_VGA:
2080 memset(&state->vga_edid.edid, 0, 256);
2081 state->vga_edid.present = e->blocks ? 0x1 : 0x0;
2082 memcpy(&state->vga_edid.edid, e->edid, 128 * e->blocks);
2083 err = edid_write_vga_segment(sd);
2084 break;
2085 case ADV7842_EDID_PORT_A:
2086 case ADV7842_EDID_PORT_B:
2087 memset(&state->hdmi_edid.edid, 0, 256);
2088 if (e->blocks)
2089 state->hdmi_edid.present |= 0x04 << e->pad;
2090 else
2091 state->hdmi_edid.present &= ~(0x04 << e->pad);
2092 memcpy(&state->hdmi_edid.edid, e->edid, 128 * e->blocks);
2093 err = edid_write_hdmi_segment(sd, e->pad);
2094 break;
2095 default:
2096 return -EINVAL;
2097 }
2098 if (err < 0)
2099 v4l2_err(sd, "error %d writing edid on port %d\n", err, e->pad);
2100 return err;
2101 }
2102
2103 /*********** avi info frame CEA-861-E **************/
2104 /* TODO move to common library */
2105
2106 struct avi_info_frame {
2107 uint8_t f17;
2108 uint8_t y10;
2109 uint8_t a0;
2110 uint8_t b10;
2111 uint8_t s10;
2112 uint8_t c10;
2113 uint8_t m10;
2114 uint8_t r3210;
2115 uint8_t itc;
2116 uint8_t ec210;
2117 uint8_t q10;
2118 uint8_t sc10;
2119 uint8_t f47;
2120 uint8_t vic;
2121 uint8_t yq10;
2122 uint8_t cn10;
2123 uint8_t pr3210;
2124 uint16_t etb;
2125 uint16_t sbb;
2126 uint16_t elb;
2127 uint16_t srb;
2128 };
2129
2130 static const char *y10_txt[4] = {
2131 "RGB",
2132 "YCbCr 4:2:2",
2133 "YCbCr 4:4:4",
2134 "Future",
2135 };
2136
2137 static const char *c10_txt[4] = {
2138 "No Data",
2139 "SMPTE 170M",
2140 "ITU-R 709",
2141 "Extended Colorimetry information valied",
2142 };
2143
2144 static const char *itc_txt[2] = {
2145 "No Data",
2146 "IT content",
2147 };
2148
2149 static const char *ec210_txt[8] = {
2150 "xvYCC601",
2151 "xvYCC709",
2152 "sYCC601",
2153 "AdobeYCC601",
2154 "AdobeRGB",
2155 "5 reserved",
2156 "6 reserved",
2157 "7 reserved",
2158 };
2159
2160 static const char *q10_txt[4] = {
2161 "Default",
2162 "Limited Range",
2163 "Full Range",
2164 "Reserved",
2165 };
2166
2167 static void parse_avi_infoframe(struct v4l2_subdev *sd, uint8_t *buf,
2168 struct avi_info_frame *avi)
2169 {
2170 avi->f17 = (buf[1] >> 7) & 0x1;
2171 avi->y10 = (buf[1] >> 5) & 0x3;
2172 avi->a0 = (buf[1] >> 4) & 0x1;
2173 avi->b10 = (buf[1] >> 2) & 0x3;
2174 avi->s10 = buf[1] & 0x3;
2175 avi->c10 = (buf[2] >> 6) & 0x3;
2176 avi->m10 = (buf[2] >> 4) & 0x3;
2177 avi->r3210 = buf[2] & 0xf;
2178 avi->itc = (buf[3] >> 7) & 0x1;
2179 avi->ec210 = (buf[3] >> 4) & 0x7;
2180 avi->q10 = (buf[3] >> 2) & 0x3;
2181 avi->sc10 = buf[3] & 0x3;
2182 avi->f47 = (buf[4] >> 7) & 0x1;
2183 avi->vic = buf[4] & 0x7f;
2184 avi->yq10 = (buf[5] >> 6) & 0x3;
2185 avi->cn10 = (buf[5] >> 4) & 0x3;
2186 avi->pr3210 = buf[5] & 0xf;
2187 avi->etb = buf[6] + 256*buf[7];
2188 avi->sbb = buf[8] + 256*buf[9];
2189 avi->elb = buf[10] + 256*buf[11];
2190 avi->srb = buf[12] + 256*buf[13];
2191 }
2192
2193 static void print_avi_infoframe(struct v4l2_subdev *sd)
2194 {
2195 int i;
2196 uint8_t buf[14];
2197 u8 avi_len;
2198 u8 avi_ver;
2199 struct avi_info_frame avi;
2200
2201 if (!(hdmi_read(sd, 0x05) & 0x80)) {
2202 v4l2_info(sd, "receive DVI-D signal (AVI infoframe not supported)\n");
2203 return;
2204 }
2205 if (!(io_read(sd, 0x60) & 0x01)) {
2206 v4l2_info(sd, "AVI infoframe not received\n");
2207 return;
2208 }
2209
2210 if (io_read(sd, 0x88) & 0x10) {
2211 v4l2_info(sd, "AVI infoframe checksum error has occurred earlier\n");
2212 io_write(sd, 0x8a, 0x10); /* clear AVI_INF_CKS_ERR_RAW */
2213 if (io_read(sd, 0x88) & 0x10) {
2214 v4l2_info(sd, "AVI infoframe checksum error still present\n");
2215 io_write(sd, 0x8a, 0x10); /* clear AVI_INF_CKS_ERR_RAW */
2216 }
2217 }
2218
2219 avi_len = infoframe_read(sd, 0xe2);
2220 avi_ver = infoframe_read(sd, 0xe1);
2221 v4l2_info(sd, "AVI infoframe version %d (%d byte)\n",
2222 avi_ver, avi_len);
2223
2224 if (avi_ver != 0x02)
2225 return;
2226
2227 for (i = 0; i < 14; i++)
2228 buf[i] = infoframe_read(sd, i);
2229
2230 v4l2_info(sd, "\t%02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x\n",
2231 buf[0], buf[1], buf[2], buf[3], buf[4], buf[5], buf[6], buf[7],
2232 buf[8], buf[9], buf[10], buf[11], buf[12], buf[13]);
2233
2234 parse_avi_infoframe(sd, buf, &avi);
2235
2236 if (avi.vic)
2237 v4l2_info(sd, "\tVIC: %d\n", avi.vic);
2238 if (avi.itc)
2239 v4l2_info(sd, "\t%s\n", itc_txt[avi.itc]);
2240
2241 if (avi.y10)
2242 v4l2_info(sd, "\t%s %s\n", y10_txt[avi.y10], !avi.c10 ? "" :
2243 (avi.c10 == 0x3 ? ec210_txt[avi.ec210] : c10_txt[avi.c10]));
2244 else
2245 v4l2_info(sd, "\t%s %s\n", y10_txt[avi.y10], q10_txt[avi.q10]);
2246 }
2247
2248 static const char * const prim_mode_txt[] = {
2249 "SDP",
2250 "Component",
2251 "Graphics",
2252 "Reserved",
2253 "CVBS & HDMI AUDIO",
2254 "HDMI-Comp",
2255 "HDMI-GR",
2256 "Reserved",
2257 "Reserved",
2258 "Reserved",
2259 "Reserved",
2260 "Reserved",
2261 "Reserved",
2262 "Reserved",
2263 "Reserved",
2264 "Reserved",
2265 };
2266
2267 static int adv7842_sdp_log_status(struct v4l2_subdev *sd)
2268 {
2269 /* SDP (Standard definition processor) block */
2270 uint8_t sdp_signal_detected = sdp_read(sd, 0x5A) & 0x01;
2271
2272 v4l2_info(sd, "Chip powered %s\n", no_power(sd) ? "off" : "on");
2273 v4l2_info(sd, "Prim-mode = 0x%x, video std = 0x%x\n",
2274 io_read(sd, 0x01) & 0x0f, io_read(sd, 0x00) & 0x3f);
2275
2276 v4l2_info(sd, "SDP: free run: %s\n",
2277 (sdp_read(sd, 0x56) & 0x01) ? "on" : "off");
2278 v4l2_info(sd, "SDP: %s\n", sdp_signal_detected ?
2279 "valid SD/PR signal detected" : "invalid/no signal");
2280 if (sdp_signal_detected) {
2281 static const char * const sdp_std_txt[] = {
2282 "NTSC-M/J",
2283 "1?",
2284 "NTSC-443",
2285 "60HzSECAM",
2286 "PAL-M",
2287 "5?",
2288 "PAL-60",
2289 "7?", "8?", "9?", "a?", "b?",
2290 "PAL-CombN",
2291 "d?",
2292 "PAL-BGHID",
2293 "SECAM"
2294 };
2295 v4l2_info(sd, "SDP: standard %s\n",
2296 sdp_std_txt[sdp_read(sd, 0x52) & 0x0f]);
2297 v4l2_info(sd, "SDP: %s\n",
2298 (sdp_read(sd, 0x59) & 0x08) ? "50Hz" : "60Hz");
2299 v4l2_info(sd, "SDP: %s\n",
2300 (sdp_read(sd, 0x57) & 0x08) ? "Interlaced" : "Progressive");
2301 v4l2_info(sd, "SDP: deinterlacer %s\n",
2302 (sdp_read(sd, 0x12) & 0x08) ? "enabled" : "disabled");
2303 v4l2_info(sd, "SDP: csc %s mode\n",
2304 (sdp_io_read(sd, 0xe0) & 0x40) ? "auto" : "manual");
2305 }
2306 return 0;
2307 }
2308
2309 static int adv7842_cp_log_status(struct v4l2_subdev *sd)
2310 {
2311 /* CP block */
2312 struct adv7842_state *state = to_state(sd);
2313 struct v4l2_dv_timings timings;
2314 uint8_t reg_io_0x02 = io_read(sd, 0x02);
2315 uint8_t reg_io_0x21 = io_read(sd, 0x21);
2316 uint8_t reg_rep_0x77 = rep_read(sd, 0x77);
2317 uint8_t reg_rep_0x7d = rep_read(sd, 0x7d);
2318 bool audio_pll_locked = hdmi_read(sd, 0x04) & 0x01;
2319 bool audio_sample_packet_detect = hdmi_read(sd, 0x18) & 0x01;
2320 bool audio_mute = io_read(sd, 0x65) & 0x40;
2321
2322 static const char * const csc_coeff_sel_rb[16] = {
2323 "bypassed", "YPbPr601 -> RGB", "reserved", "YPbPr709 -> RGB",
2324 "reserved", "RGB -> YPbPr601", "reserved", "RGB -> YPbPr709",
2325 "reserved", "YPbPr709 -> YPbPr601", "YPbPr601 -> YPbPr709",
2326 "reserved", "reserved", "reserved", "reserved", "manual"
2327 };
2328 static const char * const input_color_space_txt[16] = {
2329 "RGB limited range (16-235)", "RGB full range (0-255)",
2330 "YCbCr Bt.601 (16-235)", "YCbCr Bt.709 (16-235)",
2331 "xvYCC Bt.601", "xvYCC Bt.709",
2332 "YCbCr Bt.601 (0-255)", "YCbCr Bt.709 (0-255)",
2333 "invalid", "invalid", "invalid", "invalid", "invalid",
2334 "invalid", "invalid", "automatic"
2335 };
2336 static const char * const rgb_quantization_range_txt[] = {
2337 "Automatic",
2338 "RGB limited range (16-235)",
2339 "RGB full range (0-255)",
2340 };
2341 static const char * const deep_color_mode_txt[4] = {
2342 "8-bits per channel",
2343 "10-bits per channel",
2344 "12-bits per channel",
2345 "16-bits per channel (not supported)"
2346 };
2347
2348 v4l2_info(sd, "-----Chip status-----\n");
2349 v4l2_info(sd, "Chip power: %s\n", no_power(sd) ? "off" : "on");
2350 v4l2_info(sd, "HDMI/DVI-D port selected: %s\n",
2351 state->hdmi_port_a ? "A" : "B");
2352 v4l2_info(sd, "EDID A %s, B %s\n",
2353 ((reg_rep_0x7d & 0x04) && (reg_rep_0x77 & 0x04)) ?
2354 "enabled" : "disabled",
2355 ((reg_rep_0x7d & 0x08) && (reg_rep_0x77 & 0x08)) ?
2356 "enabled" : "disabled");
2357 v4l2_info(sd, "HPD A %s, B %s\n",
2358 reg_io_0x21 & 0x02 ? "enabled" : "disabled",
2359 reg_io_0x21 & 0x01 ? "enabled" : "disabled");
2360 v4l2_info(sd, "CEC %s\n", !!(cec_read(sd, 0x2a) & 0x01) ?
2361 "enabled" : "disabled");
2362
2363 v4l2_info(sd, "-----Signal status-----\n");
2364 if (state->hdmi_port_a) {
2365 v4l2_info(sd, "Cable detected (+5V power): %s\n",
2366 io_read(sd, 0x6f) & 0x02 ? "true" : "false");
2367 v4l2_info(sd, "TMDS signal detected: %s\n",
2368 (io_read(sd, 0x6a) & 0x02) ? "true" : "false");
2369 v4l2_info(sd, "TMDS signal locked: %s\n",
2370 (io_read(sd, 0x6a) & 0x20) ? "true" : "false");
2371 } else {
2372 v4l2_info(sd, "Cable detected (+5V power):%s\n",
2373 io_read(sd, 0x6f) & 0x01 ? "true" : "false");
2374 v4l2_info(sd, "TMDS signal detected: %s\n",
2375 (io_read(sd, 0x6a) & 0x01) ? "true" : "false");
2376 v4l2_info(sd, "TMDS signal locked: %s\n",
2377 (io_read(sd, 0x6a) & 0x10) ? "true" : "false");
2378 }
2379 v4l2_info(sd, "CP free run: %s\n",
2380 (!!(cp_read(sd, 0xff) & 0x10) ? "on" : "off"));
2381 v4l2_info(sd, "Prim-mode = 0x%x, video std = 0x%x, v_freq = 0x%x\n",
2382 io_read(sd, 0x01) & 0x0f, io_read(sd, 0x00) & 0x3f,
2383 (io_read(sd, 0x01) & 0x70) >> 4);
2384
2385 v4l2_info(sd, "-----Video Timings-----\n");
2386 if (no_cp_signal(sd)) {
2387 v4l2_info(sd, "STDI: not locked\n");
2388 } else {
2389 uint32_t bl = ((cp_read(sd, 0xb1) & 0x3f) << 8) | cp_read(sd, 0xb2);
2390 uint32_t lcf = ((cp_read(sd, 0xb3) & 0x7) << 8) | cp_read(sd, 0xb4);
2391 uint32_t lcvs = cp_read(sd, 0xb3) >> 3;
2392 uint32_t fcl = ((cp_read(sd, 0xb8) & 0x1f) << 8) | cp_read(sd, 0xb9);
2393 char hs_pol = ((cp_read(sd, 0xb5) & 0x10) ?
2394 ((cp_read(sd, 0xb5) & 0x08) ? '+' : '-') : 'x');
2395 char vs_pol = ((cp_read(sd, 0xb5) & 0x40) ?
2396 ((cp_read(sd, 0xb5) & 0x20) ? '+' : '-') : 'x');
2397 v4l2_info(sd,
2398 "STDI: lcf (frame height - 1) = %d, bl = %d, lcvs (vsync) = %d, fcl = %d, %s, %chsync, %cvsync\n",
2399 lcf, bl, lcvs, fcl,
2400 (cp_read(sd, 0xb1) & 0x40) ?
2401 "interlaced" : "progressive",
2402 hs_pol, vs_pol);
2403 }
2404 if (adv7842_query_dv_timings(sd, &timings))
2405 v4l2_info(sd, "No video detected\n");
2406 else
2407 v4l2_print_dv_timings(sd->name, "Detected format: ",
2408 &timings, true);
2409 v4l2_print_dv_timings(sd->name, "Configured format: ",
2410 &state->timings, true);
2411
2412 if (no_cp_signal(sd))
2413 return 0;
2414
2415 v4l2_info(sd, "-----Color space-----\n");
2416 v4l2_info(sd, "RGB quantization range ctrl: %s\n",
2417 rgb_quantization_range_txt[state->rgb_quantization_range]);
2418 v4l2_info(sd, "Input color space: %s\n",
2419 input_color_space_txt[reg_io_0x02 >> 4]);
2420 v4l2_info(sd, "Output color space: %s %s, saturator %s\n",
2421 (reg_io_0x02 & 0x02) ? "RGB" : "YCbCr",
2422 (reg_io_0x02 & 0x04) ? "(16-235)" : "(0-255)",
2423 ((reg_io_0x02 & 0x04) ^ (reg_io_0x02 & 0x01)) ?
2424 "enabled" : "disabled");
2425 v4l2_info(sd, "Color space conversion: %s\n",
2426 csc_coeff_sel_rb[cp_read(sd, 0xf4) >> 4]);
2427
2428 if (!is_digital_input(sd))
2429 return 0;
2430
2431 v4l2_info(sd, "-----%s status-----\n", is_hdmi(sd) ? "HDMI" : "DVI-D");
2432 v4l2_info(sd, "HDCP encrypted content: %s\n",
2433 (hdmi_read(sd, 0x05) & 0x40) ? "true" : "false");
2434 v4l2_info(sd, "HDCP keys read: %s%s\n",
2435 (hdmi_read(sd, 0x04) & 0x20) ? "yes" : "no",
2436 (hdmi_read(sd, 0x04) & 0x10) ? "ERROR" : "");
2437 if (!is_hdmi(sd))
2438 return 0;
2439
2440 v4l2_info(sd, "Audio: pll %s, samples %s, %s\n",
2441 audio_pll_locked ? "locked" : "not locked",
2442 audio_sample_packet_detect ? "detected" : "not detected",
2443 audio_mute ? "muted" : "enabled");
2444 if (audio_pll_locked && audio_sample_packet_detect) {
2445 v4l2_info(sd, "Audio format: %s\n",
2446 (hdmi_read(sd, 0x07) & 0x40) ? "multi-channel" : "stereo");
2447 }
2448 v4l2_info(sd, "Audio CTS: %u\n", (hdmi_read(sd, 0x5b) << 12) +
2449 (hdmi_read(sd, 0x5c) << 8) +
2450 (hdmi_read(sd, 0x5d) & 0xf0));
2451 v4l2_info(sd, "Audio N: %u\n", ((hdmi_read(sd, 0x5d) & 0x0f) << 16) +
2452 (hdmi_read(sd, 0x5e) << 8) +
2453 hdmi_read(sd, 0x5f));
2454 v4l2_info(sd, "AV Mute: %s\n",
2455 (hdmi_read(sd, 0x04) & 0x40) ? "on" : "off");
2456 v4l2_info(sd, "Deep color mode: %s\n",
2457 deep_color_mode_txt[hdmi_read(sd, 0x0b) >> 6]);
2458
2459 print_avi_infoframe(sd);
2460 return 0;
2461 }
2462
2463 static int adv7842_log_status(struct v4l2_subdev *sd)
2464 {
2465 struct adv7842_state *state = to_state(sd);
2466
2467 if (state->mode == ADV7842_MODE_SDP)
2468 return adv7842_sdp_log_status(sd);
2469 return adv7842_cp_log_status(sd);
2470 }
2471
2472 static int adv7842_querystd(struct v4l2_subdev *sd, v4l2_std_id *std)
2473 {
2474 struct adv7842_state *state = to_state(sd);
2475
2476 v4l2_dbg(1, debug, sd, "%s:\n", __func__);
2477
2478 if (state->mode != ADV7842_MODE_SDP)
2479 return -ENODATA;
2480
2481 if (!(sdp_read(sd, 0x5A) & 0x01)) {
2482 *std = 0;
2483 v4l2_dbg(1, debug, sd, "%s: no valid signal\n", __func__);
2484 return 0;
2485 }
2486
2487 switch (sdp_read(sd, 0x52) & 0x0f) {
2488 case 0:
2489 /* NTSC-M/J */
2490 *std &= V4L2_STD_NTSC;
2491 break;
2492 case 2:
2493 /* NTSC-443 */
2494 *std &= V4L2_STD_NTSC_443;
2495 break;
2496 case 3:
2497 /* 60HzSECAM */
2498 *std &= V4L2_STD_SECAM;
2499 break;
2500 case 4:
2501 /* PAL-M */
2502 *std &= V4L2_STD_PAL_M;
2503 break;
2504 case 6:
2505 /* PAL-60 */
2506 *std &= V4L2_STD_PAL_60;
2507 break;
2508 case 0xc:
2509 /* PAL-CombN */
2510 *std &= V4L2_STD_PAL_Nc;
2511 break;
2512 case 0xe:
2513 /* PAL-BGHID */
2514 *std &= V4L2_STD_PAL;
2515 break;
2516 case 0xf:
2517 /* SECAM */
2518 *std &= V4L2_STD_SECAM;
2519 break;
2520 default:
2521 *std &= V4L2_STD_ALL;
2522 break;
2523 }
2524 return 0;
2525 }
2526
2527 static void adv7842_s_sdp_io(struct v4l2_subdev *sd, struct adv7842_sdp_io_sync_adjustment *s)
2528 {
2529 if (s && s->adjust) {
2530 sdp_io_write(sd, 0x94, (s->hs_beg >> 8) & 0xf);
2531 sdp_io_write(sd, 0x95, s->hs_beg & 0xff);
2532 sdp_io_write(sd, 0x96, (s->hs_width >> 8) & 0xf);
2533 sdp_io_write(sd, 0x97, s->hs_width & 0xff);
2534 sdp_io_write(sd, 0x98, (s->de_beg >> 8) & 0xf);
2535 sdp_io_write(sd, 0x99, s->de_beg & 0xff);
2536 sdp_io_write(sd, 0x9a, (s->de_end >> 8) & 0xf);
2537 sdp_io_write(sd, 0x9b, s->de_end & 0xff);
2538 sdp_io_write(sd, 0xa8, s->vs_beg_o);
2539 sdp_io_write(sd, 0xa9, s->vs_beg_e);
2540 sdp_io_write(sd, 0xaa, s->vs_end_o);
2541 sdp_io_write(sd, 0xab, s->vs_end_e);
2542 sdp_io_write(sd, 0xac, s->de_v_beg_o);
2543 sdp_io_write(sd, 0xad, s->de_v_beg_e);
2544 sdp_io_write(sd, 0xae, s->de_v_end_o);
2545 sdp_io_write(sd, 0xaf, s->de_v_end_e);
2546 } else {
2547 /* set to default */
2548 sdp_io_write(sd, 0x94, 0x00);
2549 sdp_io_write(sd, 0x95, 0x00);
2550 sdp_io_write(sd, 0x96, 0x00);
2551 sdp_io_write(sd, 0x97, 0x20);
2552 sdp_io_write(sd, 0x98, 0x00);
2553 sdp_io_write(sd, 0x99, 0x00);
2554 sdp_io_write(sd, 0x9a, 0x00);
2555 sdp_io_write(sd, 0x9b, 0x00);
2556 sdp_io_write(sd, 0xa8, 0x04);
2557 sdp_io_write(sd, 0xa9, 0x04);
2558 sdp_io_write(sd, 0xaa, 0x04);
2559 sdp_io_write(sd, 0xab, 0x04);
2560 sdp_io_write(sd, 0xac, 0x04);
2561 sdp_io_write(sd, 0xad, 0x04);
2562 sdp_io_write(sd, 0xae, 0x04);
2563 sdp_io_write(sd, 0xaf, 0x04);
2564 }
2565 }
2566
2567 static int adv7842_s_std(struct v4l2_subdev *sd, v4l2_std_id norm)
2568 {
2569 struct adv7842_state *state = to_state(sd);
2570 struct adv7842_platform_data *pdata = &state->pdata;
2571
2572 v4l2_dbg(1, debug, sd, "%s:\n", __func__);
2573
2574 if (state->mode != ADV7842_MODE_SDP)
2575 return -ENODATA;
2576
2577 if (norm & V4L2_STD_625_50)
2578 adv7842_s_sdp_io(sd, &pdata->sdp_io_sync_625);
2579 else if (norm & V4L2_STD_525_60)
2580 adv7842_s_sdp_io(sd, &pdata->sdp_io_sync_525);
2581 else
2582 adv7842_s_sdp_io(sd, NULL);
2583
2584 if (norm & V4L2_STD_ALL) {
2585 state->norm = norm;
2586 return 0;
2587 }
2588 return -EINVAL;
2589 }
2590
2591 static int adv7842_g_std(struct v4l2_subdev *sd, v4l2_std_id *norm)
2592 {
2593 struct adv7842_state *state = to_state(sd);
2594
2595 v4l2_dbg(1, debug, sd, "%s:\n", __func__);
2596
2597 if (state->mode != ADV7842_MODE_SDP)
2598 return -ENODATA;
2599
2600 *norm = state->norm;
2601 return 0;
2602 }
2603
2604 /* ----------------------------------------------------------------------- */
2605
2606 static int adv7842_core_init(struct v4l2_subdev *sd)
2607 {
2608 struct adv7842_state *state = to_state(sd);
2609 struct adv7842_platform_data *pdata = &state->pdata;
2610 hdmi_write(sd, 0x48,
2611 (pdata->disable_pwrdnb ? 0x80 : 0) |
2612 (pdata->disable_cable_det_rst ? 0x40 : 0));
2613
2614 disable_input(sd);
2615
2616 /*
2617 * Disable I2C access to internal EDID ram from HDMI DDC ports
2618 * Disable auto edid enable when leaving powerdown mode
2619 */
2620 rep_write_and_or(sd, 0x77, 0xd3, 0x20);
2621
2622 /* power */
2623 io_write(sd, 0x0c, 0x42); /* Power up part and power down VDP */
2624 io_write(sd, 0x15, 0x80); /* Power up pads */
2625
2626 /* video format */
2627 io_write(sd, 0x02,
2628 0xf0 |
2629 pdata->alt_gamma << 3 |
2630 pdata->op_656_range << 2 |
2631 pdata->rgb_out << 1 |
2632 pdata->alt_data_sat << 0);
2633 io_write(sd, 0x03, pdata->op_format_sel);
2634 io_write_and_or(sd, 0x04, 0x1f, pdata->op_ch_sel << 5);
2635 io_write_and_or(sd, 0x05, 0xf0, pdata->blank_data << 3 |
2636 pdata->insert_av_codes << 2 |
2637 pdata->replicate_av_codes << 1 |
2638 pdata->invert_cbcr << 0);
2639
2640 /* HDMI audio */
2641 hdmi_write_and_or(sd, 0x1a, 0xf1, 0x08); /* Wait 1 s before unmute */
2642
2643 /* Drive strength */
2644 io_write_and_or(sd, 0x14, 0xc0,
2645 pdata->dr_str_data << 4 |
2646 pdata->dr_str_clk << 2 |
2647 pdata->dr_str_sync);
2648
2649 /* HDMI free run */
2650 cp_write_and_or(sd, 0xba, 0xfc, pdata->hdmi_free_run_enable |
2651 (pdata->hdmi_free_run_mode << 1));
2652
2653 /* SPD free run */
2654 sdp_write_and_or(sd, 0xdd, 0xf0, pdata->sdp_free_run_force |
2655 (pdata->sdp_free_run_cbar_en << 1) |
2656 (pdata->sdp_free_run_man_col_en << 2) |
2657 (pdata->sdp_free_run_auto << 3));
2658
2659 /* TODO from platform data */
2660 cp_write(sd, 0x69, 0x14); /* Enable CP CSC */
2661 io_write(sd, 0x06, 0xa6); /* positive VS and HS and DE */
2662 cp_write(sd, 0xf3, 0xdc); /* Low threshold to enter/exit free run mode */
2663 afe_write(sd, 0xb5, 0x01); /* Setting MCLK to 256Fs */
2664
2665 afe_write(sd, 0x02, pdata->ain_sel); /* Select analog input muxing mode */
2666 io_write_and_or(sd, 0x30, ~(1 << 4), pdata->output_bus_lsb_to_msb << 4);
2667
2668 sdp_csc_coeff(sd, &pdata->sdp_csc_coeff);
2669
2670 /* todo, improve settings for sdram */
2671 if (pdata->sd_ram_size >= 128) {
2672 sdp_write(sd, 0x12, 0x0d); /* Frame TBC,3D comb enabled */
2673 if (pdata->sd_ram_ddr) {
2674 /* SDP setup for the AD eval board */
2675 sdp_io_write(sd, 0x6f, 0x00); /* DDR mode */
2676 sdp_io_write(sd, 0x75, 0x0a); /* 128 MB memory size */
2677 sdp_io_write(sd, 0x7a, 0xa5); /* Timing Adjustment */
2678 sdp_io_write(sd, 0x7b, 0x8f); /* Timing Adjustment */
2679 sdp_io_write(sd, 0x60, 0x01); /* SDRAM reset */
2680 } else {
2681 sdp_io_write(sd, 0x75, 0x0a); /* 64 MB memory size ?*/
2682 sdp_io_write(sd, 0x74, 0x00); /* must be zero for sdr sdram */
2683 sdp_io_write(sd, 0x79, 0x33); /* CAS latency to 3,
2684 depends on memory */
2685 sdp_io_write(sd, 0x6f, 0x01); /* SDR mode */
2686 sdp_io_write(sd, 0x7a, 0xa5); /* Timing Adjustment */
2687 sdp_io_write(sd, 0x7b, 0x8f); /* Timing Adjustment */
2688 sdp_io_write(sd, 0x60, 0x01); /* SDRAM reset */
2689 }
2690 } else {
2691 /*
2692 * Manual UG-214, rev 0 is bit confusing on this bit
2693 * but a '1' disables any signal if the Ram is active.
2694 */
2695 sdp_io_write(sd, 0x29, 0x10); /* Tristate memory interface */
2696 }
2697
2698 select_input(sd, pdata->vid_std_select);
2699
2700 enable_input(sd);
2701
2702 if (pdata->hpa_auto) {
2703 /* HPA auto, HPA 0.5s after Edid set and Cable detect */
2704 hdmi_write(sd, 0x69, 0x5c);
2705 } else {
2706 /* HPA manual */
2707 hdmi_write(sd, 0x69, 0xa3);
2708 /* HPA disable on port A and B */
2709 io_write_and_or(sd, 0x20, 0xcf, 0x00);
2710 }
2711
2712 /* LLC */
2713 io_write(sd, 0x19, 0x80 | pdata->llc_dll_phase);
2714 io_write(sd, 0x33, 0x40);
2715
2716 /* interrupts */
2717 io_write(sd, 0x40, 0xf2); /* Configure INT1 */
2718
2719 adv7842_irq_enable(sd, true);
2720
2721 return v4l2_ctrl_handler_setup(sd->ctrl_handler);
2722 }
2723
2724 /* ----------------------------------------------------------------------- */
2725
2726 static int adv7842_ddr_ram_test(struct v4l2_subdev *sd)
2727 {
2728 /*
2729 * From ADV784x external Memory test.pdf
2730 *
2731 * Reset must just been performed before running test.
2732 * Recommended to reset after test.
2733 */
2734 int i;
2735 int pass = 0;
2736 int fail = 0;
2737 int complete = 0;
2738
2739 io_write(sd, 0x00, 0x01); /* Program SDP 4x1 */
2740 io_write(sd, 0x01, 0x00); /* Program SDP mode */
2741 afe_write(sd, 0x80, 0x92); /* SDP Recommeneded Write */
2742 afe_write(sd, 0x9B, 0x01); /* SDP Recommeneded Write ADV7844ES1 */
2743 afe_write(sd, 0x9C, 0x60); /* SDP Recommeneded Write ADV7844ES1 */
2744 afe_write(sd, 0x9E, 0x02); /* SDP Recommeneded Write ADV7844ES1 */
2745 afe_write(sd, 0xA0, 0x0B); /* SDP Recommeneded Write ADV7844ES1 */
2746 afe_write(sd, 0xC3, 0x02); /* Memory BIST Initialisation */
2747 io_write(sd, 0x0C, 0x40); /* Power up ADV7844 */
2748 io_write(sd, 0x15, 0xBA); /* Enable outputs */
2749 sdp_write(sd, 0x12, 0x00); /* Disable 3D comb, Frame TBC & 3DNR */
2750 io_write(sd, 0xFF, 0x04); /* Reset memory controller */
2751
2752 mdelay(5);
2753
2754 sdp_write(sd, 0x12, 0x00); /* Disable 3D Comb, Frame TBC & 3DNR */
2755 sdp_io_write(sd, 0x2A, 0x01); /* Memory BIST Initialisation */
2756 sdp_io_write(sd, 0x7c, 0x19); /* Memory BIST Initialisation */
2757 sdp_io_write(sd, 0x80, 0x87); /* Memory BIST Initialisation */
2758 sdp_io_write(sd, 0x81, 0x4a); /* Memory BIST Initialisation */
2759 sdp_io_write(sd, 0x82, 0x2c); /* Memory BIST Initialisation */
2760 sdp_io_write(sd, 0x83, 0x0e); /* Memory BIST Initialisation */
2761 sdp_io_write(sd, 0x84, 0x94); /* Memory BIST Initialisation */
2762 sdp_io_write(sd, 0x85, 0x62); /* Memory BIST Initialisation */
2763 sdp_io_write(sd, 0x7d, 0x00); /* Memory BIST Initialisation */
2764 sdp_io_write(sd, 0x7e, 0x1a); /* Memory BIST Initialisation */
2765
2766 mdelay(5);
2767
2768 sdp_io_write(sd, 0xd9, 0xd5); /* Enable BIST Test */
2769 sdp_write(sd, 0x12, 0x05); /* Enable FRAME TBC & 3D COMB */
2770
2771 mdelay(20);
2772
2773 for (i = 0; i < 10; i++) {
2774 u8 result = sdp_io_read(sd, 0xdb);
2775 if (result & 0x10) {
2776 complete++;
2777 if (result & 0x20)
2778 fail++;
2779 else
2780 pass++;
2781 }
2782 mdelay(20);
2783 }
2784
2785 v4l2_dbg(1, debug, sd,
2786 "Ram Test: completed %d of %d: pass %d, fail %d\n",
2787 complete, i, pass, fail);
2788
2789 if (!complete || fail)
2790 return -EIO;
2791 return 0;
2792 }
2793
2794 static void adv7842_rewrite_i2c_addresses(struct v4l2_subdev *sd,
2795 struct adv7842_platform_data *pdata)
2796 {
2797 io_write(sd, 0xf1, pdata->i2c_sdp << 1);
2798 io_write(sd, 0xf2, pdata->i2c_sdp_io << 1);
2799 io_write(sd, 0xf3, pdata->i2c_avlink << 1);
2800 io_write(sd, 0xf4, pdata->i2c_cec << 1);
2801 io_write(sd, 0xf5, pdata->i2c_infoframe << 1);
2802
2803 io_write(sd, 0xf8, pdata->i2c_afe << 1);
2804 io_write(sd, 0xf9, pdata->i2c_repeater << 1);
2805 io_write(sd, 0xfa, pdata->i2c_edid << 1);
2806 io_write(sd, 0xfb, pdata->i2c_hdmi << 1);
2807
2808 io_write(sd, 0xfd, pdata->i2c_cp << 1);
2809 io_write(sd, 0xfe, pdata->i2c_vdp << 1);
2810 }
2811
2812 static int adv7842_command_ram_test(struct v4l2_subdev *sd)
2813 {
2814 struct i2c_client *client = v4l2_get_subdevdata(sd);
2815 struct adv7842_state *state = to_state(sd);
2816 struct adv7842_platform_data *pdata = client->dev.platform_data;
2817 struct v4l2_dv_timings timings;
2818 int ret = 0;
2819
2820 if (!pdata)
2821 return -ENODEV;
2822
2823 if (!pdata->sd_ram_size || !pdata->sd_ram_ddr) {
2824 v4l2_info(sd, "no sdram or no ddr sdram\n");
2825 return -EINVAL;
2826 }
2827
2828 main_reset(sd);
2829
2830 adv7842_rewrite_i2c_addresses(sd, pdata);
2831
2832 /* run ram test */
2833 ret = adv7842_ddr_ram_test(sd);
2834
2835 main_reset(sd);
2836
2837 adv7842_rewrite_i2c_addresses(sd, pdata);
2838
2839 /* and re-init chip and state */
2840 adv7842_core_init(sd);
2841
2842 disable_input(sd);
2843
2844 select_input(sd, state->vid_std_select);
2845
2846 enable_input(sd);
2847
2848 edid_write_vga_segment(sd);
2849 edid_write_hdmi_segment(sd, ADV7842_EDID_PORT_A);
2850 edid_write_hdmi_segment(sd, ADV7842_EDID_PORT_B);
2851
2852 timings = state->timings;
2853
2854 memset(&state->timings, 0, sizeof(struct v4l2_dv_timings));
2855
2856 adv7842_s_dv_timings(sd, &timings);
2857
2858 return ret;
2859 }
2860
2861 static long adv7842_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
2862 {
2863 switch (cmd) {
2864 case ADV7842_CMD_RAM_TEST:
2865 return adv7842_command_ram_test(sd);
2866 }
2867 return -ENOTTY;
2868 }
2869
2870 /* ----------------------------------------------------------------------- */
2871
2872 static const struct v4l2_ctrl_ops adv7842_ctrl_ops = {
2873 .s_ctrl = adv7842_s_ctrl,
2874 };
2875
2876 static const struct v4l2_subdev_core_ops adv7842_core_ops = {
2877 .log_status = adv7842_log_status,
2878 .ioctl = adv7842_ioctl,
2879 .interrupt_service_routine = adv7842_isr,
2880 #ifdef CONFIG_VIDEO_ADV_DEBUG
2881 .g_register = adv7842_g_register,
2882 .s_register = adv7842_s_register,
2883 #endif
2884 };
2885
2886 static const struct v4l2_subdev_video_ops adv7842_video_ops = {
2887 .g_std = adv7842_g_std,
2888 .s_std = adv7842_s_std,
2889 .s_routing = adv7842_s_routing,
2890 .querystd = adv7842_querystd,
2891 .g_input_status = adv7842_g_input_status,
2892 .s_dv_timings = adv7842_s_dv_timings,
2893 .g_dv_timings = adv7842_g_dv_timings,
2894 .query_dv_timings = adv7842_query_dv_timings,
2895 .enum_mbus_fmt = adv7842_enum_mbus_fmt,
2896 .g_mbus_fmt = adv7842_g_mbus_fmt,
2897 .try_mbus_fmt = adv7842_g_mbus_fmt,
2898 .s_mbus_fmt = adv7842_g_mbus_fmt,
2899 };
2900
2901 static const struct v4l2_subdev_pad_ops adv7842_pad_ops = {
2902 .get_edid = adv7842_get_edid,
2903 .set_edid = adv7842_set_edid,
2904 .enum_dv_timings = adv7842_enum_dv_timings,
2905 .dv_timings_cap = adv7842_dv_timings_cap,
2906 };
2907
2908 static const struct v4l2_subdev_ops adv7842_ops = {
2909 .core = &adv7842_core_ops,
2910 .video = &adv7842_video_ops,
2911 .pad = &adv7842_pad_ops,
2912 };
2913
2914 /* -------------------------- custom ctrls ---------------------------------- */
2915
2916 static const struct v4l2_ctrl_config adv7842_ctrl_analog_sampling_phase = {
2917 .ops = &adv7842_ctrl_ops,
2918 .id = V4L2_CID_ADV_RX_ANALOG_SAMPLING_PHASE,
2919 .name = "Analog Sampling Phase",
2920 .type = V4L2_CTRL_TYPE_INTEGER,
2921 .min = 0,
2922 .max = 0x1f,
2923 .step = 1,
2924 .def = 0,
2925 };
2926
2927 static const struct v4l2_ctrl_config adv7842_ctrl_free_run_color_manual = {
2928 .ops = &adv7842_ctrl_ops,
2929 .id = V4L2_CID_ADV_RX_FREE_RUN_COLOR_MANUAL,
2930 .name = "Free Running Color, Manual",
2931 .type = V4L2_CTRL_TYPE_BOOLEAN,
2932 .max = 1,
2933 .step = 1,
2934 .def = 1,
2935 };
2936
2937 static const struct v4l2_ctrl_config adv7842_ctrl_free_run_color = {
2938 .ops = &adv7842_ctrl_ops,
2939 .id = V4L2_CID_ADV_RX_FREE_RUN_COLOR,
2940 .name = "Free Running Color",
2941 .type = V4L2_CTRL_TYPE_INTEGER,
2942 .max = 0xffffff,
2943 .step = 0x1,
2944 };
2945
2946
2947 static void adv7842_unregister_clients(struct v4l2_subdev *sd)
2948 {
2949 struct adv7842_state *state = to_state(sd);
2950 if (state->i2c_avlink)
2951 i2c_unregister_device(state->i2c_avlink);
2952 if (state->i2c_cec)
2953 i2c_unregister_device(state->i2c_cec);
2954 if (state->i2c_infoframe)
2955 i2c_unregister_device(state->i2c_infoframe);
2956 if (state->i2c_sdp_io)
2957 i2c_unregister_device(state->i2c_sdp_io);
2958 if (state->i2c_sdp)
2959 i2c_unregister_device(state->i2c_sdp);
2960 if (state->i2c_afe)
2961 i2c_unregister_device(state->i2c_afe);
2962 if (state->i2c_repeater)
2963 i2c_unregister_device(state->i2c_repeater);
2964 if (state->i2c_edid)
2965 i2c_unregister_device(state->i2c_edid);
2966 if (state->i2c_hdmi)
2967 i2c_unregister_device(state->i2c_hdmi);
2968 if (state->i2c_cp)
2969 i2c_unregister_device(state->i2c_cp);
2970 if (state->i2c_vdp)
2971 i2c_unregister_device(state->i2c_vdp);
2972
2973 state->i2c_avlink = NULL;
2974 state->i2c_cec = NULL;
2975 state->i2c_infoframe = NULL;
2976 state->i2c_sdp_io = NULL;
2977 state->i2c_sdp = NULL;
2978 state->i2c_afe = NULL;
2979 state->i2c_repeater = NULL;
2980 state->i2c_edid = NULL;
2981 state->i2c_hdmi = NULL;
2982 state->i2c_cp = NULL;
2983 state->i2c_vdp = NULL;
2984 }
2985
2986 static struct i2c_client *adv7842_dummy_client(struct v4l2_subdev *sd, const char *desc,
2987 u8 addr, u8 io_reg)
2988 {
2989 struct i2c_client *client = v4l2_get_subdevdata(sd);
2990 struct i2c_client *cp;
2991
2992 io_write(sd, io_reg, addr << 1);
2993
2994 if (addr == 0) {
2995 v4l2_err(sd, "no %s i2c addr configured\n", desc);
2996 return NULL;
2997 }
2998
2999 cp = i2c_new_dummy(client->adapter, io_read(sd, io_reg) >> 1);
3000 if (!cp)
3001 v4l2_err(sd, "register %s on i2c addr 0x%x failed\n", desc, addr);
3002
3003 return cp;
3004 }
3005
3006 static int adv7842_register_clients(struct v4l2_subdev *sd)
3007 {
3008 struct adv7842_state *state = to_state(sd);
3009 struct adv7842_platform_data *pdata = &state->pdata;
3010
3011 state->i2c_avlink = adv7842_dummy_client(sd, "avlink", pdata->i2c_avlink, 0xf3);
3012 state->i2c_cec = adv7842_dummy_client(sd, "cec", pdata->i2c_cec, 0xf4);
3013 state->i2c_infoframe = adv7842_dummy_client(sd, "infoframe", pdata->i2c_infoframe, 0xf5);
3014 state->i2c_sdp_io = adv7842_dummy_client(sd, "sdp_io", pdata->i2c_sdp_io, 0xf2);
3015 state->i2c_sdp = adv7842_dummy_client(sd, "sdp", pdata->i2c_sdp, 0xf1);
3016 state->i2c_afe = adv7842_dummy_client(sd, "afe", pdata->i2c_afe, 0xf8);
3017 state->i2c_repeater = adv7842_dummy_client(sd, "repeater", pdata->i2c_repeater, 0xf9);
3018 state->i2c_edid = adv7842_dummy_client(sd, "edid", pdata->i2c_edid, 0xfa);
3019 state->i2c_hdmi = adv7842_dummy_client(sd, "hdmi", pdata->i2c_hdmi, 0xfb);
3020 state->i2c_cp = adv7842_dummy_client(sd, "cp", pdata->i2c_cp, 0xfd);
3021 state->i2c_vdp = adv7842_dummy_client(sd, "vdp", pdata->i2c_vdp, 0xfe);
3022
3023 if (!state->i2c_avlink ||
3024 !state->i2c_cec ||
3025 !state->i2c_infoframe ||
3026 !state->i2c_sdp_io ||
3027 !state->i2c_sdp ||
3028 !state->i2c_afe ||
3029 !state->i2c_repeater ||
3030 !state->i2c_edid ||
3031 !state->i2c_hdmi ||
3032 !state->i2c_cp ||
3033 !state->i2c_vdp)
3034 return -1;
3035
3036 return 0;
3037 }
3038
3039 static int adv7842_probe(struct i2c_client *client,
3040 const struct i2c_device_id *id)
3041 {
3042 struct adv7842_state *state;
3043 static const struct v4l2_dv_timings cea640x480 =
3044 V4L2_DV_BT_CEA_640X480P59_94;
3045 struct adv7842_platform_data *pdata = client->dev.platform_data;
3046 struct v4l2_ctrl_handler *hdl;
3047 struct v4l2_subdev *sd;
3048 u16 rev;
3049 int err;
3050
3051 /* Check if the adapter supports the needed features */
3052 if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA))
3053 return -EIO;
3054
3055 v4l_dbg(1, debug, client, "detecting adv7842 client on address 0x%x\n",
3056 client->addr << 1);
3057
3058 if (!pdata) {
3059 v4l_err(client, "No platform data!\n");
3060 return -ENODEV;
3061 }
3062
3063 state = devm_kzalloc(&client->dev, sizeof(struct adv7842_state), GFP_KERNEL);
3064 if (!state) {
3065 v4l_err(client, "Could not allocate adv7842_state memory!\n");
3066 return -ENOMEM;
3067 }
3068
3069 /* platform data */
3070 state->pdata = *pdata;
3071 state->timings = cea640x480;
3072
3073 sd = &state->sd;
3074 v4l2_i2c_subdev_init(sd, client, &adv7842_ops);
3075 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
3076 state->mode = pdata->mode;
3077
3078 state->hdmi_port_a = pdata->input == ADV7842_SELECT_HDMI_PORT_A;
3079 state->restart_stdi_once = true;
3080
3081 /* i2c access to adv7842? */
3082 rev = adv_smbus_read_byte_data_check(client, 0xea, false) << 8 |
3083 adv_smbus_read_byte_data_check(client, 0xeb, false);
3084 if (rev != 0x2012) {
3085 v4l2_info(sd, "got rev=0x%04x on first read attempt\n", rev);
3086 rev = adv_smbus_read_byte_data_check(client, 0xea, false) << 8 |
3087 adv_smbus_read_byte_data_check(client, 0xeb, false);
3088 }
3089 if (rev != 0x2012) {
3090 v4l2_info(sd, "not an adv7842 on address 0x%x (rev=0x%04x)\n",
3091 client->addr << 1, rev);
3092 return -ENODEV;
3093 }
3094
3095 if (pdata->chip_reset)
3096 main_reset(sd);
3097
3098 /* control handlers */
3099 hdl = &state->hdl;
3100 v4l2_ctrl_handler_init(hdl, 6);
3101
3102 /* add in ascending ID order */
3103 v4l2_ctrl_new_std(hdl, &adv7842_ctrl_ops,
3104 V4L2_CID_BRIGHTNESS, -128, 127, 1, 0);
3105 v4l2_ctrl_new_std(hdl, &adv7842_ctrl_ops,
3106 V4L2_CID_CONTRAST, 0, 255, 1, 128);
3107 v4l2_ctrl_new_std(hdl, &adv7842_ctrl_ops,
3108 V4L2_CID_SATURATION, 0, 255, 1, 128);
3109 v4l2_ctrl_new_std(hdl, &adv7842_ctrl_ops,
3110 V4L2_CID_HUE, 0, 128, 1, 0);
3111
3112 /* custom controls */
3113 state->detect_tx_5v_ctrl = v4l2_ctrl_new_std(hdl, NULL,
3114 V4L2_CID_DV_RX_POWER_PRESENT, 0, 3, 0, 0);
3115 state->analog_sampling_phase_ctrl = v4l2_ctrl_new_custom(hdl,
3116 &adv7842_ctrl_analog_sampling_phase, NULL);
3117 state->free_run_color_ctrl_manual = v4l2_ctrl_new_custom(hdl,
3118 &adv7842_ctrl_free_run_color_manual, NULL);
3119 state->free_run_color_ctrl = v4l2_ctrl_new_custom(hdl,
3120 &adv7842_ctrl_free_run_color, NULL);
3121 state->rgb_quantization_range_ctrl =
3122 v4l2_ctrl_new_std_menu(hdl, &adv7842_ctrl_ops,
3123 V4L2_CID_DV_RX_RGB_RANGE, V4L2_DV_RGB_RANGE_FULL,
3124 0, V4L2_DV_RGB_RANGE_AUTO);
3125 sd->ctrl_handler = hdl;
3126 if (hdl->error) {
3127 err = hdl->error;
3128 goto err_hdl;
3129 }
3130 state->detect_tx_5v_ctrl->is_private = true;
3131 state->rgb_quantization_range_ctrl->is_private = true;
3132 state->analog_sampling_phase_ctrl->is_private = true;
3133 state->free_run_color_ctrl_manual->is_private = true;
3134 state->free_run_color_ctrl->is_private = true;
3135
3136 if (adv7842_s_detect_tx_5v_ctrl(sd)) {
3137 err = -ENODEV;
3138 goto err_hdl;
3139 }
3140
3141 if (adv7842_register_clients(sd) < 0) {
3142 err = -ENOMEM;
3143 v4l2_err(sd, "failed to create all i2c clients\n");
3144 goto err_i2c;
3145 }
3146
3147 /* work queues */
3148 state->work_queues = create_singlethread_workqueue(client->name);
3149 if (!state->work_queues) {
3150 v4l2_err(sd, "Could not create work queue\n");
3151 err = -ENOMEM;
3152 goto err_i2c;
3153 }
3154
3155 INIT_DELAYED_WORK(&state->delayed_work_enable_hotplug,
3156 adv7842_delayed_work_enable_hotplug);
3157
3158 state->pad.flags = MEDIA_PAD_FL_SOURCE;
3159 err = media_entity_init(&sd->entity, 1, &state->pad, 0);
3160 if (err)
3161 goto err_work_queues;
3162
3163 err = adv7842_core_init(sd);
3164 if (err)
3165 goto err_entity;
3166
3167 v4l2_info(sd, "%s found @ 0x%x (%s)\n", client->name,
3168 client->addr << 1, client->adapter->name);
3169 return 0;
3170
3171 err_entity:
3172 media_entity_cleanup(&sd->entity);
3173 err_work_queues:
3174 cancel_delayed_work(&state->delayed_work_enable_hotplug);
3175 destroy_workqueue(state->work_queues);
3176 err_i2c:
3177 adv7842_unregister_clients(sd);
3178 err_hdl:
3179 v4l2_ctrl_handler_free(hdl);
3180 return err;
3181 }
3182
3183 /* ----------------------------------------------------------------------- */
3184
3185 static int adv7842_remove(struct i2c_client *client)
3186 {
3187 struct v4l2_subdev *sd = i2c_get_clientdata(client);
3188 struct adv7842_state *state = to_state(sd);
3189
3190 adv7842_irq_enable(sd, false);
3191
3192 cancel_delayed_work(&state->delayed_work_enable_hotplug);
3193 destroy_workqueue(state->work_queues);
3194 v4l2_device_unregister_subdev(sd);
3195 media_entity_cleanup(&sd->entity);
3196 adv7842_unregister_clients(sd);
3197 v4l2_ctrl_handler_free(sd->ctrl_handler);
3198 return 0;
3199 }
3200
3201 /* ----------------------------------------------------------------------- */
3202
3203 static struct i2c_device_id adv7842_id[] = {
3204 { "adv7842", 0 },
3205 { }
3206 };
3207 MODULE_DEVICE_TABLE(i2c, adv7842_id);
3208
3209 /* ----------------------------------------------------------------------- */
3210
3211 static struct i2c_driver adv7842_driver = {
3212 .driver = {
3213 .owner = THIS_MODULE,
3214 .name = "adv7842",
3215 },
3216 .probe = adv7842_probe,
3217 .remove = adv7842_remove,
3218 .id_table = adv7842_id,
3219 };
3220
3221 module_i2c_driver(adv7842_driver);
Linux with added FPC-III support