2 * saa7191.c - Philips SAA7191 video decoder driver
4 * Copyright (C) 2003 Ladislav Michl <ladis@linux-mips.org>
5 * Copyright (C) 2004,2005 Mikael Nousiainen <tmnousia@cc.hut.fi>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
12 #include <linux/delay.h>
13 #include <linux/errno.h>
15 #include <linux/init.h>
16 #include <linux/kernel.h>
17 #include <linux/major.h>
18 #include <linux/module.h>
20 #include <linux/slab.h>
22 #include <linux/videodev2.h>
23 #include <linux/i2c.h>
24 #include <media/v4l2-device.h>
28 #define SAA7191_MODULE_VERSION "0.0.5"
30 MODULE_DESCRIPTION("Philips SAA7191 video decoder driver");
31 MODULE_VERSION(SAA7191_MODULE_VERSION
);
32 MODULE_AUTHOR("Mikael Nousiainen <tmnousia@cc.hut.fi>");
33 MODULE_LICENSE("GPL");
36 // #define SAA7191_DEBUG
39 #define dprintk(x...) printk("SAA7191: " x);
44 #define SAA7191_SYNC_COUNT 30
45 #define SAA7191_SYNC_DELAY 100 /* milliseconds */
48 struct v4l2_subdev sd
;
50 /* the register values are stored here as the actual
51 * I2C-registers are write-only */
58 static inline struct saa7191
*to_saa7191(struct v4l2_subdev
*sd
)
60 return container_of(sd
, struct saa7191
, sd
);
63 static const u8 initseq
[] = {
66 0x50, /* (0x50) SAA7191_REG_IDEL */
68 /* 50 Hz signal timing */
69 0x30, /* (0x30) SAA7191_REG_HSYB */
70 0x00, /* (0x00) SAA7191_REG_HSYS */
71 0xe8, /* (0xe8) SAA7191_REG_HCLB */
72 0xb6, /* (0xb6) SAA7191_REG_HCLS */
73 0xf4, /* (0xf4) SAA7191_REG_HPHI */
76 SAA7191_LUMA_APER_1
, /* (0x01) SAA7191_REG_LUMA - CVBS mode */
77 0x00, /* (0x00) SAA7191_REG_HUEC */
78 0xf8, /* (0xf8) SAA7191_REG_CKTQ */
79 0xf8, /* (0xf8) SAA7191_REG_CKTS */
80 0x90, /* (0x90) SAA7191_REG_PLSE */
81 0x90, /* (0x90) SAA7191_REG_SESE */
82 0x00, /* (0x00) SAA7191_REG_GAIN */
83 SAA7191_STDC_NFEN
| SAA7191_STDC_HRMV
, /* (0x0c) SAA7191_REG_STDC
85 * slow time constant */
86 SAA7191_IOCK_OEDC
| SAA7191_IOCK_OEHS
| SAA7191_IOCK_OEVS
87 | SAA7191_IOCK_OEDY
, /* (0x78) SAA7191_REG_IOCK
88 * - chroma from CVBS, GPSW1 & 2 off */
89 SAA7191_CTL3_AUFD
| SAA7191_CTL3_SCEN
| SAA7191_CTL3_OFTS
90 | SAA7191_CTL3_YDEL0
, /* (0x99) SAA7191_REG_CTL3
91 * - automatic field detection */
92 0x00, /* (0x00) SAA7191_REG_CTL4 */
93 0x2c, /* (0x2c) SAA7191_REG_CHCV - PAL nominal value */
97 /* 60 Hz signal timing */
98 0x34, /* (0x34) SAA7191_REG_HS6B */
99 0x0a, /* (0x0a) SAA7191_REG_HS6S */
100 0xf4, /* (0xf4) SAA7191_REG_HC6B */
101 0xce, /* (0xce) SAA7191_REG_HC6S */
102 0xf4, /* (0xf4) SAA7191_REG_HP6I */
105 /* SAA7191 register handling */
107 static u8
saa7191_read_reg(struct v4l2_subdev
*sd
, u8 reg
)
109 return to_saa7191(sd
)->reg
[reg
];
112 static int saa7191_read_status(struct v4l2_subdev
*sd
, u8
*value
)
114 struct i2c_client
*client
= v4l2_get_subdevdata(sd
);
117 ret
= i2c_master_recv(client
, value
, 1);
119 printk(KERN_ERR
"SAA7191: saa7191_read_status(): read failed\n");
127 static int saa7191_write_reg(struct v4l2_subdev
*sd
, u8 reg
, u8 value
)
129 struct i2c_client
*client
= v4l2_get_subdevdata(sd
);
131 to_saa7191(sd
)->reg
[reg
] = value
;
132 return i2c_smbus_write_byte_data(client
, reg
, value
);
135 /* the first byte of data must be the first subaddress number (register) */
136 static int saa7191_write_block(struct v4l2_subdev
*sd
,
137 u8 length
, const u8
*data
)
139 struct i2c_client
*client
= v4l2_get_subdevdata(sd
);
140 struct saa7191
*decoder
= to_saa7191(sd
);
144 for (i
= 0; i
< (length
- 1); i
++) {
145 decoder
->reg
[data
[0] + i
] = data
[i
+ 1];
148 ret
= i2c_master_send(client
, data
, length
);
150 printk(KERN_ERR
"SAA7191: saa7191_write_block(): "
158 /* Helper functions */
160 static int saa7191_s_routing(struct v4l2_subdev
*sd
,
161 u32 input
, u32 output
, u32 config
)
163 struct saa7191
*decoder
= to_saa7191(sd
);
164 u8 luma
= saa7191_read_reg(sd
, SAA7191_REG_LUMA
);
165 u8 iock
= saa7191_read_reg(sd
, SAA7191_REG_IOCK
);
169 case SAA7191_INPUT_COMPOSITE
: /* Set Composite input */
170 iock
&= ~(SAA7191_IOCK_CHRS
| SAA7191_IOCK_GPSW1
171 | SAA7191_IOCK_GPSW2
);
172 /* Chrominance trap active */
173 luma
&= ~SAA7191_LUMA_BYPS
;
175 case SAA7191_INPUT_SVIDEO
: /* Set S-Video input */
176 iock
|= SAA7191_IOCK_CHRS
| SAA7191_IOCK_GPSW2
;
177 /* Chrominance trap bypassed */
178 luma
|= SAA7191_LUMA_BYPS
;
184 err
= saa7191_write_reg(sd
, SAA7191_REG_LUMA
, luma
);
187 err
= saa7191_write_reg(sd
, SAA7191_REG_IOCK
, iock
);
191 decoder
->input
= input
;
196 static int saa7191_s_std(struct v4l2_subdev
*sd
, v4l2_std_id norm
)
198 struct saa7191
*decoder
= to_saa7191(sd
);
199 u8 stdc
= saa7191_read_reg(sd
, SAA7191_REG_STDC
);
200 u8 ctl3
= saa7191_read_reg(sd
, SAA7191_REG_CTL3
);
201 u8 chcv
= saa7191_read_reg(sd
, SAA7191_REG_CHCV
);
204 if (norm
& V4L2_STD_PAL
) {
205 stdc
&= ~SAA7191_STDC_SECS
;
206 ctl3
&= ~(SAA7191_CTL3_AUFD
| SAA7191_CTL3_FSEL
);
207 chcv
= SAA7191_CHCV_PAL
;
208 } else if (norm
& V4L2_STD_NTSC
) {
209 stdc
&= ~SAA7191_STDC_SECS
;
210 ctl3
&= ~SAA7191_CTL3_AUFD
;
211 ctl3
|= SAA7191_CTL3_FSEL
;
212 chcv
= SAA7191_CHCV_NTSC
;
213 } else if (norm
& V4L2_STD_SECAM
) {
214 stdc
|= SAA7191_STDC_SECS
;
215 ctl3
&= ~(SAA7191_CTL3_AUFD
| SAA7191_CTL3_FSEL
);
216 chcv
= SAA7191_CHCV_PAL
;
221 err
= saa7191_write_reg(sd
, SAA7191_REG_CTL3
, ctl3
);
224 err
= saa7191_write_reg(sd
, SAA7191_REG_STDC
, stdc
);
227 err
= saa7191_write_reg(sd
, SAA7191_REG_CHCV
, chcv
);
231 decoder
->norm
= norm
;
233 dprintk("ctl3: %02x stdc: %02x chcv: %02x\n", ctl3
,
235 dprintk("norm: %llx\n", norm
);
240 static int saa7191_wait_for_signal(struct v4l2_subdev
*sd
, u8
*status
)
244 dprintk("Checking for signal...\n");
246 for (i
= 0; i
< SAA7191_SYNC_COUNT
; i
++) {
247 if (saa7191_read_status(sd
, status
))
250 if (((*status
) & SAA7191_STATUS_HLCK
) == 0) {
251 dprintk("Signal found\n");
255 msleep(SAA7191_SYNC_DELAY
);
258 dprintk("No signal\n");
263 static int saa7191_querystd(struct v4l2_subdev
*sd
, v4l2_std_id
*norm
)
265 struct saa7191
*decoder
= to_saa7191(sd
);
266 u8 stdc
= saa7191_read_reg(sd
, SAA7191_REG_STDC
);
267 u8 ctl3
= saa7191_read_reg(sd
, SAA7191_REG_CTL3
);
269 v4l2_std_id old_norm
= decoder
->norm
;
272 dprintk("SAA7191 extended signal auto-detection...\n");
274 *norm
&= V4L2_STD_NTSC
| V4L2_STD_PAL
| V4L2_STD_SECAM
;
275 stdc
&= ~SAA7191_STDC_SECS
;
276 ctl3
&= ~(SAA7191_CTL3_FSEL
);
278 err
= saa7191_write_reg(sd
, SAA7191_REG_STDC
, stdc
);
283 err
= saa7191_write_reg(sd
, SAA7191_REG_CTL3
, ctl3
);
289 ctl3
|= SAA7191_CTL3_AUFD
;
290 err
= saa7191_write_reg(sd
, SAA7191_REG_CTL3
, ctl3
);
296 msleep(SAA7191_SYNC_DELAY
);
298 err
= saa7191_wait_for_signal(sd
, &status
);
302 if (status
& SAA7191_STATUS_FIDT
) {
303 /* 60Hz signal -> NTSC */
304 dprintk("60Hz signal: NTSC\n");
305 *norm
&= V4L2_STD_NTSC
;
310 dprintk("50Hz signal: Trying PAL...\n");
313 err
= saa7191_s_std(sd
, V4L2_STD_PAL
);
317 msleep(SAA7191_SYNC_DELAY
);
319 err
= saa7191_wait_for_signal(sd
, &status
);
324 if (status
& SAA7191_STATUS_FIDT
) {
325 dprintk("No 50Hz signal\n");
326 saa7191_s_std(sd
, old_norm
);
327 *norm
= V4L2_STD_UNKNOWN
;
331 if (status
& SAA7191_STATUS_CODE
) {
333 *norm
&= V4L2_STD_PAL
;
334 return saa7191_s_std(sd
, old_norm
);
337 dprintk("No color detected with PAL - Trying SECAM...\n");
339 /* no color detected ? -> try SECAM */
340 err
= saa7191_s_std(sd
, V4L2_STD_SECAM
);
344 msleep(SAA7191_SYNC_DELAY
);
346 err
= saa7191_wait_for_signal(sd
, &status
);
351 if (status
& SAA7191_STATUS_FIDT
) {
352 dprintk("No 50Hz signal\n");
353 *norm
= V4L2_STD_UNKNOWN
;
357 if (status
& SAA7191_STATUS_CODE
) {
358 /* Color detected -> SECAM */
360 *norm
&= V4L2_STD_SECAM
;
361 return saa7191_s_std(sd
, old_norm
);
364 dprintk("No color detected with SECAM - Going back to PAL.\n");
365 *norm
= V4L2_STD_UNKNOWN
;
368 return saa7191_s_std(sd
, old_norm
);
371 static int saa7191_autodetect_norm(struct v4l2_subdev
*sd
)
375 dprintk("SAA7191 signal auto-detection...\n");
377 dprintk("Reading status...\n");
379 if (saa7191_read_status(sd
, &status
))
382 dprintk("Checking for signal...\n");
385 if (status
& SAA7191_STATUS_HLCK
) {
386 dprintk("No signal\n");
390 dprintk("Signal found\n");
392 if (status
& SAA7191_STATUS_FIDT
) {
393 /* 60hz signal -> NTSC */
395 return saa7191_s_std(sd
, V4L2_STD_NTSC
);
397 /* 50hz signal -> PAL */
399 return saa7191_s_std(sd
, V4L2_STD_PAL
);
403 static int saa7191_g_ctrl(struct v4l2_subdev
*sd
, struct v4l2_control
*ctrl
)
409 case SAA7191_CONTROL_BANDPASS
:
410 case SAA7191_CONTROL_BANDPASS_WEIGHT
:
411 case SAA7191_CONTROL_CORING
:
412 reg
= saa7191_read_reg(sd
, SAA7191_REG_LUMA
);
414 case SAA7191_CONTROL_BANDPASS
:
415 ctrl
->value
= ((s32
)reg
& SAA7191_LUMA_BPSS_MASK
)
416 >> SAA7191_LUMA_BPSS_SHIFT
;
418 case SAA7191_CONTROL_BANDPASS_WEIGHT
:
419 ctrl
->value
= ((s32
)reg
& SAA7191_LUMA_APER_MASK
)
420 >> SAA7191_LUMA_APER_SHIFT
;
422 case SAA7191_CONTROL_CORING
:
423 ctrl
->value
= ((s32
)reg
& SAA7191_LUMA_CORI_MASK
)
424 >> SAA7191_LUMA_CORI_SHIFT
;
428 case SAA7191_CONTROL_FORCE_COLOUR
:
429 case SAA7191_CONTROL_CHROMA_GAIN
:
430 reg
= saa7191_read_reg(sd
, SAA7191_REG_GAIN
);
431 if (ctrl
->id
== SAA7191_CONTROL_FORCE_COLOUR
)
432 ctrl
->value
= ((s32
)reg
& SAA7191_GAIN_COLO
) ? 1 : 0;
434 ctrl
->value
= ((s32
)reg
& SAA7191_GAIN_LFIS_MASK
)
435 >> SAA7191_GAIN_LFIS_SHIFT
;
438 reg
= saa7191_read_reg(sd
, SAA7191_REG_HUEC
);
443 ctrl
->value
= (s32
)reg
;
445 case SAA7191_CONTROL_VTRC
:
446 reg
= saa7191_read_reg(sd
, SAA7191_REG_STDC
);
447 ctrl
->value
= ((s32
)reg
& SAA7191_STDC_VTRC
) ? 1 : 0;
449 case SAA7191_CONTROL_LUMA_DELAY
:
450 reg
= saa7191_read_reg(sd
, SAA7191_REG_CTL3
);
451 ctrl
->value
= ((s32
)reg
& SAA7191_CTL3_YDEL_MASK
)
452 >> SAA7191_CTL3_YDEL_SHIFT
;
453 if (ctrl
->value
>= 4)
456 case SAA7191_CONTROL_VNR
:
457 reg
= saa7191_read_reg(sd
, SAA7191_REG_CTL4
);
458 ctrl
->value
= ((s32
)reg
& SAA7191_CTL4_VNOI_MASK
)
459 >> SAA7191_CTL4_VNOI_SHIFT
;
468 static int saa7191_s_ctrl(struct v4l2_subdev
*sd
, struct v4l2_control
*ctrl
)
474 case SAA7191_CONTROL_BANDPASS
:
475 case SAA7191_CONTROL_BANDPASS_WEIGHT
:
476 case SAA7191_CONTROL_CORING
:
477 reg
= saa7191_read_reg(sd
, SAA7191_REG_LUMA
);
479 case SAA7191_CONTROL_BANDPASS
:
480 reg
&= ~SAA7191_LUMA_BPSS_MASK
;
481 reg
|= (ctrl
->value
<< SAA7191_LUMA_BPSS_SHIFT
)
482 & SAA7191_LUMA_BPSS_MASK
;
484 case SAA7191_CONTROL_BANDPASS_WEIGHT
:
485 reg
&= ~SAA7191_LUMA_APER_MASK
;
486 reg
|= (ctrl
->value
<< SAA7191_LUMA_APER_SHIFT
)
487 & SAA7191_LUMA_APER_MASK
;
489 case SAA7191_CONTROL_CORING
:
490 reg
&= ~SAA7191_LUMA_CORI_MASK
;
491 reg
|= (ctrl
->value
<< SAA7191_LUMA_CORI_SHIFT
)
492 & SAA7191_LUMA_CORI_MASK
;
495 ret
= saa7191_write_reg(sd
, SAA7191_REG_LUMA
, reg
);
497 case SAA7191_CONTROL_FORCE_COLOUR
:
498 case SAA7191_CONTROL_CHROMA_GAIN
:
499 reg
= saa7191_read_reg(sd
, SAA7191_REG_GAIN
);
500 if (ctrl
->id
== SAA7191_CONTROL_FORCE_COLOUR
) {
502 reg
|= SAA7191_GAIN_COLO
;
504 reg
&= ~SAA7191_GAIN_COLO
;
506 reg
&= ~SAA7191_GAIN_LFIS_MASK
;
507 reg
|= (ctrl
->value
<< SAA7191_GAIN_LFIS_SHIFT
)
508 & SAA7191_GAIN_LFIS_MASK
;
510 ret
= saa7191_write_reg(sd
, SAA7191_REG_GAIN
, reg
);
513 reg
= ctrl
->value
& 0xff;
518 ret
= saa7191_write_reg(sd
, SAA7191_REG_HUEC
, reg
);
520 case SAA7191_CONTROL_VTRC
:
521 reg
= saa7191_read_reg(sd
, SAA7191_REG_STDC
);
523 reg
|= SAA7191_STDC_VTRC
;
525 reg
&= ~SAA7191_STDC_VTRC
;
526 ret
= saa7191_write_reg(sd
, SAA7191_REG_STDC
, reg
);
528 case SAA7191_CONTROL_LUMA_DELAY
: {
529 s32 value
= ctrl
->value
;
532 reg
= saa7191_read_reg(sd
, SAA7191_REG_CTL3
);
533 reg
&= ~SAA7191_CTL3_YDEL_MASK
;
534 reg
|= (value
<< SAA7191_CTL3_YDEL_SHIFT
)
535 & SAA7191_CTL3_YDEL_MASK
;
536 ret
= saa7191_write_reg(sd
, SAA7191_REG_CTL3
, reg
);
539 case SAA7191_CONTROL_VNR
:
540 reg
= saa7191_read_reg(sd
, SAA7191_REG_CTL4
);
541 reg
&= ~SAA7191_CTL4_VNOI_MASK
;
542 reg
|= (ctrl
->value
<< SAA7191_CTL4_VNOI_SHIFT
)
543 & SAA7191_CTL4_VNOI_MASK
;
544 ret
= saa7191_write_reg(sd
, SAA7191_REG_CTL4
, reg
);
555 static int saa7191_g_input_status(struct v4l2_subdev
*sd
, u32
*status
)
558 int res
= V4L2_IN_ST_NO_SIGNAL
;
560 if (saa7191_read_status(sd
, &status_reg
))
562 if ((status_reg
& SAA7191_STATUS_HLCK
) == 0)
564 if (!(status_reg
& SAA7191_STATUS_CODE
))
565 res
|= V4L2_IN_ST_NO_COLOR
;
571 /* ----------------------------------------------------------------------- */
573 static const struct v4l2_subdev_core_ops saa7191_core_ops
= {
574 .g_ctrl
= saa7191_g_ctrl
,
575 .s_ctrl
= saa7191_s_ctrl
,
578 static const struct v4l2_subdev_video_ops saa7191_video_ops
= {
579 .s_std
= saa7191_s_std
,
580 .s_routing
= saa7191_s_routing
,
581 .querystd
= saa7191_querystd
,
582 .g_input_status
= saa7191_g_input_status
,
585 static const struct v4l2_subdev_ops saa7191_ops
= {
586 .core
= &saa7191_core_ops
,
587 .video
= &saa7191_video_ops
,
590 static int saa7191_probe(struct i2c_client
*client
,
591 const struct i2c_device_id
*id
)
594 struct saa7191
*decoder
;
595 struct v4l2_subdev
*sd
;
597 v4l_info(client
, "chip found @ 0x%x (%s)\n",
598 client
->addr
<< 1, client
->adapter
->name
);
600 decoder
= devm_kzalloc(&client
->dev
, sizeof(*decoder
), GFP_KERNEL
);
605 v4l2_i2c_subdev_init(sd
, client
, &saa7191_ops
);
607 err
= saa7191_write_block(sd
, sizeof(initseq
), initseq
);
609 printk(KERN_ERR
"SAA7191 initialization failed\n");
613 printk(KERN_INFO
"SAA7191 initialized\n");
615 decoder
->input
= SAA7191_INPUT_COMPOSITE
;
616 decoder
->norm
= V4L2_STD_PAL
;
618 err
= saa7191_autodetect_norm(sd
);
619 if (err
&& (err
!= -EBUSY
))
620 printk(KERN_ERR
"SAA7191: Signal auto-detection failed\n");
625 static int saa7191_remove(struct i2c_client
*client
)
627 struct v4l2_subdev
*sd
= i2c_get_clientdata(client
);
629 v4l2_device_unregister_subdev(sd
);
633 static const struct i2c_device_id saa7191_id
[] = {
637 MODULE_DEVICE_TABLE(i2c
, saa7191_id
);
639 static struct i2c_driver saa7191_driver
= {
641 .owner
= THIS_MODULE
,
644 .probe
= saa7191_probe
,
645 .remove
= saa7191_remove
,
646 .id_table
= saa7191_id
,
649 module_i2c_driver(saa7191_driver
);