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sched: Remove double_rq_lock() from __migrate_task()
[linux/fpc-iii.git] / drivers / net / ethernet / amd / amd8111e.c
blob068dc7cad5fa3c511c34b034c006add6284bb097
1
2 /* Advanced Micro Devices Inc. AMD8111E Linux Network Driver
3 * Copyright (C) 2004 Advanced Micro Devices
4 *
5 *
6 * Copyright 2001,2002 Jeff Garzik <jgarzik@mandrakesoft.com> [ 8139cp.c,tg3.c ]
7 * Copyright (C) 2001, 2002 David S. Miller (davem@redhat.com)[ tg3.c]
8 * Copyright 1996-1999 Thomas Bogendoerfer [ pcnet32.c ]
9 * Derived from the lance driver written 1993,1994,1995 by Donald Becker.
10 * Copyright 1993 United States Government as represented by the
11 * Director, National Security Agency.[ pcnet32.c ]
12 * Carsten Langgaard, carstenl@mips.com [ pcnet32.c ]
13 * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
14 *
15 *
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License as published by
18 * the Free Software Foundation; either version 2 of the License, or
19 * (at your option) any later version.
20 *
21 * This program is distributed in the hope that it will be useful,
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 * GNU General Public License for more details.
25 *
26 * You should have received a copy of the GNU General Public License
27 * along with this program; if not, see <http://www.gnu.org/licenses/>.
28
29 Module Name:
30
31 amd8111e.c
32
33 Abstract:
34
35 AMD8111 based 10/100 Ethernet Controller Driver.
36
37 Environment:
38
39 Kernel Mode
40
41 Revision History:
42 3.0.0
43 Initial Revision.
44 3.0.1
45 1. Dynamic interrupt coalescing.
46 2. Removed prev_stats.
47 3. MII support.
48 4. Dynamic IPG support
49 3.0.2 05/29/2003
50 1. Bug fix: Fixed failure to send jumbo packets larger than 4k.
51 2. Bug fix: Fixed VLAN support failure.
52 3. Bug fix: Fixed receive interrupt coalescing bug.
53 4. Dynamic IPG support is disabled by default.
54 3.0.3 06/05/2003
55 1. Bug fix: Fixed failure to close the interface if SMP is enabled.
56 3.0.4 12/09/2003
57 1. Added set_mac_address routine for bonding driver support.
58 2. Tested the driver for bonding support
59 3. Bug fix: Fixed mismach in actual receive buffer lenth and lenth
60 indicated to the h/w.
61 4. Modified amd8111e_rx() routine to receive all the received packets
62 in the first interrupt.
63 5. Bug fix: Corrected rx_errors reported in get_stats() function.
64 3.0.5 03/22/2004
65 1. Added NAPI support
66
67 */
68
69
70 #include <linux/module.h>
71 #include <linux/kernel.h>
72 #include <linux/types.h>
73 #include <linux/compiler.h>
74 #include <linux/delay.h>
75 #include <linux/interrupt.h>
76 #include <linux/ioport.h>
77 #include <linux/pci.h>
78 #include <linux/netdevice.h>
79 #include <linux/etherdevice.h>
80 #include <linux/skbuff.h>
81 #include <linux/ethtool.h>
82 #include <linux/mii.h>
83 #include <linux/if_vlan.h>
84 #include <linux/ctype.h>
85 #include <linux/crc32.h>
86 #include <linux/dma-mapping.h>
87
88 #include <asm/io.h>
89 #include <asm/byteorder.h>
90 #include <asm/uaccess.h>
91
92 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
93 #define AMD8111E_VLAN_TAG_USED 1
94 #else
95 #define AMD8111E_VLAN_TAG_USED 0
96 #endif
97
98 #include "amd8111e.h"
99 #define MODULE_NAME "amd8111e"
100 #define MODULE_VERS "3.0.7"
101 MODULE_AUTHOR("Advanced Micro Devices, Inc.");
102 MODULE_DESCRIPTION ("AMD8111 based 10/100 Ethernet Controller. Driver Version "MODULE_VERS);
103 MODULE_LICENSE("GPL");
104 MODULE_DEVICE_TABLE(pci, amd8111e_pci_tbl);
105 module_param_array(speed_duplex, int, NULL, 0);
106 MODULE_PARM_DESC(speed_duplex, "Set device speed and duplex modes, 0: Auto Negotiate, 1: 10Mbps Half Duplex, 2: 10Mbps Full Duplex, 3: 100Mbps Half Duplex, 4: 100Mbps Full Duplex");
107 module_param_array(coalesce, bool, NULL, 0);
108 MODULE_PARM_DESC(coalesce, "Enable or Disable interrupt coalescing, 1: Enable, 0: Disable");
109 module_param_array(dynamic_ipg, bool, NULL, 0);
110 MODULE_PARM_DESC(dynamic_ipg, "Enable or Disable dynamic IPG, 1: Enable, 0: Disable");
111
112 static DEFINE_PCI_DEVICE_TABLE(amd8111e_pci_tbl) = {
113
114 { PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD8111E_7462,
115 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
116 { 0, }
117
118 };
119 /*
120 This function will read the PHY registers.
121 */
122 static int amd8111e_read_phy(struct amd8111e_priv* lp, int phy_id, int reg, u32* val)
123 {
124 void __iomem *mmio = lp->mmio;
125 unsigned int reg_val;
126 unsigned int repeat= REPEAT_CNT;
127
128 reg_val = readl(mmio + PHY_ACCESS);
129 while (reg_val & PHY_CMD_ACTIVE)
130 reg_val = readl( mmio + PHY_ACCESS );
131
132 writel( PHY_RD_CMD | ((phy_id & 0x1f) << 21) |
133 ((reg & 0x1f) << 16), mmio +PHY_ACCESS);
134 do{
135 reg_val = readl(mmio + PHY_ACCESS);
136 udelay(30); /* It takes 30 us to read/write data */
137 } while (--repeat && (reg_val & PHY_CMD_ACTIVE));
138 if(reg_val & PHY_RD_ERR)
139 goto err_phy_read;
140
141 *val = reg_val & 0xffff;
142 return 0;
143 err_phy_read:
144 *val = 0;
145 return -EINVAL;
146
147 }
148
149 /*
150 This function will write into PHY registers.
151 */
152 static int amd8111e_write_phy(struct amd8111e_priv* lp,int phy_id, int reg, u32 val)
153 {
154 unsigned int repeat = REPEAT_CNT;
155 void __iomem *mmio = lp->mmio;
156 unsigned int reg_val;
157
158 reg_val = readl(mmio + PHY_ACCESS);
159 while (reg_val & PHY_CMD_ACTIVE)
160 reg_val = readl( mmio + PHY_ACCESS );
161
162 writel( PHY_WR_CMD | ((phy_id & 0x1f) << 21) |
163 ((reg & 0x1f) << 16)|val, mmio + PHY_ACCESS);
164
165 do{
166 reg_val = readl(mmio + PHY_ACCESS);
167 udelay(30); /* It takes 30 us to read/write the data */
168 } while (--repeat && (reg_val & PHY_CMD_ACTIVE));
169
170 if(reg_val & PHY_RD_ERR)
171 goto err_phy_write;
172
173 return 0;
174
175 err_phy_write:
176 return -EINVAL;
177
178 }
179 /*
180 This is the mii register read function provided to the mii interface.
181 */
182 static int amd8111e_mdio_read(struct net_device * dev, int phy_id, int reg_num)
183 {
184 struct amd8111e_priv* lp = netdev_priv(dev);
185 unsigned int reg_val;
186
187 amd8111e_read_phy(lp,phy_id,reg_num,&reg_val);
188 return reg_val;
189
190 }
191
192 /*
193 This is the mii register write function provided to the mii interface.
194 */
195 static void amd8111e_mdio_write(struct net_device * dev, int phy_id, int reg_num, int val)
196 {
197 struct amd8111e_priv* lp = netdev_priv(dev);
198
199 amd8111e_write_phy(lp, phy_id, reg_num, val);
200 }
201
202 /*
203 This function will set PHY speed. During initialization sets the original speed to 100 full.
204 */
205 static void amd8111e_set_ext_phy(struct net_device *dev)
206 {
207 struct amd8111e_priv *lp = netdev_priv(dev);
208 u32 bmcr,advert,tmp;
209
210 /* Determine mii register values to set the speed */
211 advert = amd8111e_mdio_read(dev, lp->ext_phy_addr, MII_ADVERTISE);
212 tmp = advert & ~(ADVERTISE_ALL | ADVERTISE_100BASE4);
213 switch (lp->ext_phy_option){
214
215 default:
216 case SPEED_AUTONEG: /* advertise all values */
217 tmp |= ( ADVERTISE_10HALF|ADVERTISE_10FULL|
218 ADVERTISE_100HALF|ADVERTISE_100FULL) ;
219 break;
220 case SPEED10_HALF:
221 tmp |= ADVERTISE_10HALF;
222 break;
223 case SPEED10_FULL:
224 tmp |= ADVERTISE_10FULL;
225 break;
226 case SPEED100_HALF:
227 tmp |= ADVERTISE_100HALF;
228 break;
229 case SPEED100_FULL:
230 tmp |= ADVERTISE_100FULL;
231 break;
232 }
233
234 if(advert != tmp)
235 amd8111e_mdio_write(dev, lp->ext_phy_addr, MII_ADVERTISE, tmp);
236 /* Restart auto negotiation */
237 bmcr = amd8111e_mdio_read(dev, lp->ext_phy_addr, MII_BMCR);
238 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
239 amd8111e_mdio_write(dev, lp->ext_phy_addr, MII_BMCR, bmcr);
240
241 }
242
243 /*
244 This function will unmap skb->data space and will free
245 all transmit and receive skbuffs.
246 */
247 static int amd8111e_free_skbs(struct net_device *dev)
248 {
249 struct amd8111e_priv *lp = netdev_priv(dev);
250 struct sk_buff* rx_skbuff;
251 int i;
252
253 /* Freeing transmit skbs */
254 for(i = 0; i < NUM_TX_BUFFERS; i++){
255 if(lp->tx_skbuff[i]){
256 pci_unmap_single(lp->pci_dev,lp->tx_dma_addr[i], lp->tx_skbuff[i]->len,PCI_DMA_TODEVICE);
257 dev_kfree_skb (lp->tx_skbuff[i]);
258 lp->tx_skbuff[i] = NULL;
259 lp->tx_dma_addr[i] = 0;
260 }
261 }
262 /* Freeing previously allocated receive buffers */
263 for (i = 0; i < NUM_RX_BUFFERS; i++){
264 rx_skbuff = lp->rx_skbuff[i];
265 if(rx_skbuff != NULL){
266 pci_unmap_single(lp->pci_dev,lp->rx_dma_addr[i],
267 lp->rx_buff_len - 2,PCI_DMA_FROMDEVICE);
268 dev_kfree_skb(lp->rx_skbuff[i]);
269 lp->rx_skbuff[i] = NULL;
270 lp->rx_dma_addr[i] = 0;
271 }
272 }
273
274 return 0;
275 }
276
277 /*
278 This will set the receive buffer length corresponding to the mtu size of networkinterface.
279 */
280 static inline void amd8111e_set_rx_buff_len(struct net_device* dev)
281 {
282 struct amd8111e_priv* lp = netdev_priv(dev);
283 unsigned int mtu = dev->mtu;
284
285 if (mtu > ETH_DATA_LEN){
286 /* MTU + ethernet header + FCS
287 + optional VLAN tag + skb reserve space 2 */
288
289 lp->rx_buff_len = mtu + ETH_HLEN + 10;
290 lp->options |= OPTION_JUMBO_ENABLE;
291 } else{
292 lp->rx_buff_len = PKT_BUFF_SZ;
293 lp->options &= ~OPTION_JUMBO_ENABLE;
294 }
295 }
296
297 /*
298 This function will free all the previously allocated buffers, determine new receive buffer length and will allocate new receive buffers. This function also allocates and initializes both the transmitter and receive hardware descriptors.
299 */
300 static int amd8111e_init_ring(struct net_device *dev)
301 {
302 struct amd8111e_priv *lp = netdev_priv(dev);
303 int i;
304
305 lp->rx_idx = lp->tx_idx = 0;
306 lp->tx_complete_idx = 0;
307 lp->tx_ring_idx = 0;
308
309
310 if(lp->opened)
311 /* Free previously allocated transmit and receive skbs */
312 amd8111e_free_skbs(dev);
313
314 else{
315 /* allocate the tx and rx descriptors */
316 if((lp->tx_ring = pci_alloc_consistent(lp->pci_dev,
317 sizeof(struct amd8111e_tx_dr)*NUM_TX_RING_DR,
318 &lp->tx_ring_dma_addr)) == NULL)
319
320 goto err_no_mem;
321
322 if((lp->rx_ring = pci_alloc_consistent(lp->pci_dev,
323 sizeof(struct amd8111e_rx_dr)*NUM_RX_RING_DR,
324 &lp->rx_ring_dma_addr)) == NULL)
325
326 goto err_free_tx_ring;
327
328 }
329 /* Set new receive buff size */
330 amd8111e_set_rx_buff_len(dev);
331
332 /* Allocating receive skbs */
333 for (i = 0; i < NUM_RX_BUFFERS; i++) {
334
335 lp->rx_skbuff[i] = netdev_alloc_skb(dev, lp->rx_buff_len);
336 if (!lp->rx_skbuff[i]) {
337 /* Release previos allocated skbs */
338 for(--i; i >= 0 ;i--)
339 dev_kfree_skb(lp->rx_skbuff[i]);
340 goto err_free_rx_ring;
341 }
342 skb_reserve(lp->rx_skbuff[i],2);
343 }
344 /* Initilaizing receive descriptors */
345 for (i = 0; i < NUM_RX_BUFFERS; i++) {
346 lp->rx_dma_addr[i] = pci_map_single(lp->pci_dev,
347 lp->rx_skbuff[i]->data,lp->rx_buff_len-2, PCI_DMA_FROMDEVICE);
348
349 lp->rx_ring[i].buff_phy_addr = cpu_to_le32(lp->rx_dma_addr[i]);
350 lp->rx_ring[i].buff_count = cpu_to_le16(lp->rx_buff_len-2);
351 wmb();
352 lp->rx_ring[i].rx_flags = cpu_to_le16(OWN_BIT);
353 }
354
355 /* Initializing transmit descriptors */
356 for (i = 0; i < NUM_TX_RING_DR; i++) {
357 lp->tx_ring[i].buff_phy_addr = 0;
358 lp->tx_ring[i].tx_flags = 0;
359 lp->tx_ring[i].buff_count = 0;
360 }
361
362 return 0;
363
364 err_free_rx_ring:
365
366 pci_free_consistent(lp->pci_dev,
367 sizeof(struct amd8111e_rx_dr)*NUM_RX_RING_DR,lp->rx_ring,
368 lp->rx_ring_dma_addr);
369
370 err_free_tx_ring:
371
372 pci_free_consistent(lp->pci_dev,
373 sizeof(struct amd8111e_tx_dr)*NUM_TX_RING_DR,lp->tx_ring,
374 lp->tx_ring_dma_addr);
375
376 err_no_mem:
377 return -ENOMEM;
378 }
379 /* This function will set the interrupt coalescing according to the input arguments */
380 static int amd8111e_set_coalesce(struct net_device * dev, enum coal_mode cmod)
381 {
382 unsigned int timeout;
383 unsigned int event_count;
384
385 struct amd8111e_priv *lp = netdev_priv(dev);
386 void __iomem *mmio = lp->mmio;
387 struct amd8111e_coalesce_conf * coal_conf = &lp->coal_conf;
388
389
390 switch(cmod)
391 {
392 case RX_INTR_COAL :
393 timeout = coal_conf->rx_timeout;
394 event_count = coal_conf->rx_event_count;
395 if( timeout > MAX_TIMEOUT ||
396 event_count > MAX_EVENT_COUNT )
397 return -EINVAL;
398
399 timeout = timeout * DELAY_TIMER_CONV;
400 writel(VAL0|STINTEN, mmio+INTEN0);
401 writel((u32)DLY_INT_A_R0|( event_count<< 16 )|timeout,
402 mmio+DLY_INT_A);
403 break;
404
405 case TX_INTR_COAL :
406 timeout = coal_conf->tx_timeout;
407 event_count = coal_conf->tx_event_count;
408 if( timeout > MAX_TIMEOUT ||
409 event_count > MAX_EVENT_COUNT )
410 return -EINVAL;
411
412
413 timeout = timeout * DELAY_TIMER_CONV;
414 writel(VAL0|STINTEN,mmio+INTEN0);
415 writel((u32)DLY_INT_B_T0|( event_count<< 16 )|timeout,
416 mmio+DLY_INT_B);
417 break;
418
419 case DISABLE_COAL:
420 writel(0,mmio+STVAL);
421 writel(STINTEN, mmio+INTEN0);
422 writel(0, mmio +DLY_INT_B);
423 writel(0, mmio+DLY_INT_A);
424 break;
425 case ENABLE_COAL:
426 /* Start the timer */
427 writel((u32)SOFT_TIMER_FREQ, mmio+STVAL); /* 0.5 sec */
428 writel(VAL0|STINTEN, mmio+INTEN0);
429 break;
430 default:
431 break;
432
433 }
434 return 0;
435
436 }
437
438 /*
439 This function initializes the device registers and starts the device.
440 */
441 static int amd8111e_restart(struct net_device *dev)
442 {
443 struct amd8111e_priv *lp = netdev_priv(dev);
444 void __iomem *mmio = lp->mmio;
445 int i,reg_val;
446
447 /* stop the chip */
448 writel(RUN, mmio + CMD0);
449
450 if(amd8111e_init_ring(dev))
451 return -ENOMEM;
452
453 /* enable the port manager and set auto negotiation always */
454 writel((u32) VAL1|EN_PMGR, mmio + CMD3 );
455 writel((u32)XPHYANE|XPHYRST , mmio + CTRL2);
456
457 amd8111e_set_ext_phy(dev);
458
459 /* set control registers */
460 reg_val = readl(mmio + CTRL1);
461 reg_val &= ~XMTSP_MASK;
462 writel( reg_val| XMTSP_128 | CACHE_ALIGN, mmio + CTRL1 );
463
464 /* enable interrupt */
465 writel( APINT5EN | APINT4EN | APINT3EN | APINT2EN | APINT1EN |
466 APINT0EN | MIIPDTINTEN | MCCIINTEN | MCCINTEN | MREINTEN |
467 SPNDINTEN | MPINTEN | SINTEN | STINTEN, mmio + INTEN0);
468
469 writel(VAL3 | LCINTEN | VAL1 | TINTEN0 | VAL0 | RINTEN0, mmio + INTEN0);
470
471 /* initialize tx and rx ring base addresses */
472 writel((u32)lp->tx_ring_dma_addr,mmio + XMT_RING_BASE_ADDR0);
473 writel((u32)lp->rx_ring_dma_addr,mmio+ RCV_RING_BASE_ADDR0);
474
475 writew((u32)NUM_TX_RING_DR, mmio + XMT_RING_LEN0);
476 writew((u16)NUM_RX_RING_DR, mmio + RCV_RING_LEN0);
477
478 /* set default IPG to 96 */
479 writew((u32)DEFAULT_IPG,mmio+IPG);
480 writew((u32)(DEFAULT_IPG-IFS1_DELTA), mmio + IFS1);
481
482 if(lp->options & OPTION_JUMBO_ENABLE){
483 writel((u32)VAL2|JUMBO, mmio + CMD3);
484 /* Reset REX_UFLO */
485 writel( REX_UFLO, mmio + CMD2);
486 /* Should not set REX_UFLO for jumbo frames */
487 writel( VAL0 | APAD_XMT|REX_RTRY , mmio + CMD2);
488 }else{
489 writel( VAL0 | APAD_XMT | REX_RTRY|REX_UFLO, mmio + CMD2);
490 writel((u32)JUMBO, mmio + CMD3);
491 }
492
493 #if AMD8111E_VLAN_TAG_USED
494 writel((u32) VAL2|VSIZE|VL_TAG_DEL, mmio + CMD3);
495 #endif
496 writel( VAL0 | APAD_XMT | REX_RTRY, mmio + CMD2 );
497
498 /* Setting the MAC address to the device */
499 for (i = 0; i < ETH_ALEN; i++)
500 writeb( dev->dev_addr[i], mmio + PADR + i );
501
502 /* Enable interrupt coalesce */
503 if(lp->options & OPTION_INTR_COAL_ENABLE){
504 printk(KERN_INFO "%s: Interrupt Coalescing Enabled.\n",
505 dev->name);
506 amd8111e_set_coalesce(dev,ENABLE_COAL);
507 }
508
509 /* set RUN bit to start the chip */
510 writel(VAL2 | RDMD0, mmio + CMD0);
511 writel(VAL0 | INTREN | RUN, mmio + CMD0);
512
513 /* To avoid PCI posting bug */
514 readl(mmio+CMD0);
515 return 0;
516 }
517 /*
518 This function clears necessary the device registers.
519 */
520 static void amd8111e_init_hw_default( struct amd8111e_priv* lp)
521 {
522 unsigned int reg_val;
523 unsigned int logic_filter[2] ={0,};
524 void __iomem *mmio = lp->mmio;
525
526
527 /* stop the chip */
528 writel(RUN, mmio + CMD0);
529
530 /* AUTOPOLL0 Register *//*TBD default value is 8100 in FPS */
531 writew( 0x8100 | lp->ext_phy_addr, mmio + AUTOPOLL0);
532
533 /* Clear RCV_RING_BASE_ADDR */
534 writel(0, mmio + RCV_RING_BASE_ADDR0);
535
536 /* Clear XMT_RING_BASE_ADDR */
537 writel(0, mmio + XMT_RING_BASE_ADDR0);
538 writel(0, mmio + XMT_RING_BASE_ADDR1);
539 writel(0, mmio + XMT_RING_BASE_ADDR2);
540 writel(0, mmio + XMT_RING_BASE_ADDR3);
541
542 /* Clear CMD0 */
543 writel(CMD0_CLEAR,mmio + CMD0);
544
545 /* Clear CMD2 */
546 writel(CMD2_CLEAR, mmio +CMD2);
547
548 /* Clear CMD7 */
549 writel(CMD7_CLEAR , mmio + CMD7);
550
551 /* Clear DLY_INT_A and DLY_INT_B */
552 writel(0x0, mmio + DLY_INT_A);
553 writel(0x0, mmio + DLY_INT_B);
554
555 /* Clear FLOW_CONTROL */
556 writel(0x0, mmio + FLOW_CONTROL);
557
558 /* Clear INT0 write 1 to clear register */
559 reg_val = readl(mmio + INT0);
560 writel(reg_val, mmio + INT0);
561
562 /* Clear STVAL */
563 writel(0x0, mmio + STVAL);
564
565 /* Clear INTEN0 */
566 writel( INTEN0_CLEAR, mmio + INTEN0);
567
568 /* Clear LADRF */
569 writel(0x0 , mmio + LADRF);
570
571 /* Set SRAM_SIZE & SRAM_BOUNDARY registers */
572 writel( 0x80010,mmio + SRAM_SIZE);
573
574 /* Clear RCV_RING0_LEN */
575 writel(0x0, mmio + RCV_RING_LEN0);
576
577 /* Clear XMT_RING0/1/2/3_LEN */
578 writel(0x0, mmio + XMT_RING_LEN0);
579 writel(0x0, mmio + XMT_RING_LEN1);
580 writel(0x0, mmio + XMT_RING_LEN2);
581 writel(0x0, mmio + XMT_RING_LEN3);
582
583 /* Clear XMT_RING_LIMIT */
584 writel(0x0, mmio + XMT_RING_LIMIT);
585
586 /* Clear MIB */
587 writew(MIB_CLEAR, mmio + MIB_ADDR);
588
589 /* Clear LARF */
590 amd8111e_writeq(*(u64*)logic_filter,mmio+LADRF);
591
592 /* SRAM_SIZE register */
593 reg_val = readl(mmio + SRAM_SIZE);
594
595 if(lp->options & OPTION_JUMBO_ENABLE)
596 writel( VAL2|JUMBO, mmio + CMD3);
597 #if AMD8111E_VLAN_TAG_USED
598 writel(VAL2|VSIZE|VL_TAG_DEL, mmio + CMD3 );
599 #endif
600 /* Set default value to CTRL1 Register */
601 writel(CTRL1_DEFAULT, mmio + CTRL1);
602
603 /* To avoid PCI posting bug */
604 readl(mmio + CMD2);
605
606 }
607
608 /*
609 This function disables the interrupt and clears all the pending
610 interrupts in INT0
611 */
612 static void amd8111e_disable_interrupt(struct amd8111e_priv* lp)
613 {
614 u32 intr0;
615
616 /* Disable interrupt */
617 writel(INTREN, lp->mmio + CMD0);
618
619 /* Clear INT0 */
620 intr0 = readl(lp->mmio + INT0);
621 writel(intr0, lp->mmio + INT0);
622
623 /* To avoid PCI posting bug */
624 readl(lp->mmio + INT0);
625
626 }
627
628 /*
629 This function stops the chip.
630 */
631 static void amd8111e_stop_chip(struct amd8111e_priv* lp)
632 {
633 writel(RUN, lp->mmio + CMD0);
634
635 /* To avoid PCI posting bug */
636 readl(lp->mmio + CMD0);
637 }
638
639 /*
640 This function frees the transmiter and receiver descriptor rings.
641 */
642 static void amd8111e_free_ring(struct amd8111e_priv* lp)
643 {
644 /* Free transmit and receive descriptor rings */
645 if(lp->rx_ring){
646 pci_free_consistent(lp->pci_dev,
647 sizeof(struct amd8111e_rx_dr)*NUM_RX_RING_DR,
648 lp->rx_ring, lp->rx_ring_dma_addr);
649 lp->rx_ring = NULL;
650 }
651
652 if(lp->tx_ring){
653 pci_free_consistent(lp->pci_dev,
654 sizeof(struct amd8111e_tx_dr)*NUM_TX_RING_DR,
655 lp->tx_ring, lp->tx_ring_dma_addr);
656
657 lp->tx_ring = NULL;
658 }
659
660 }
661
662 /*
663 This function will free all the transmit skbs that are actually transmitted by the device. It will check the ownership of the skb before freeing the skb.
664 */
665 static int amd8111e_tx(struct net_device *dev)
666 {
667 struct amd8111e_priv* lp = netdev_priv(dev);
668 int tx_index = lp->tx_complete_idx & TX_RING_DR_MOD_MASK;
669 int status;
670 /* Complete all the transmit packet */
671 while (lp->tx_complete_idx != lp->tx_idx){
672 tx_index = lp->tx_complete_idx & TX_RING_DR_MOD_MASK;
673 status = le16_to_cpu(lp->tx_ring[tx_index].tx_flags);
674
675 if(status & OWN_BIT)
676 break; /* It still hasn't been Txed */
677
678 lp->tx_ring[tx_index].buff_phy_addr = 0;
679
680 /* We must free the original skb */
681 if (lp->tx_skbuff[tx_index]) {
682 pci_unmap_single(lp->pci_dev, lp->tx_dma_addr[tx_index],
683 lp->tx_skbuff[tx_index]->len,
684 PCI_DMA_TODEVICE);
685 dev_kfree_skb_irq (lp->tx_skbuff[tx_index]);
686 lp->tx_skbuff[tx_index] = NULL;
687 lp->tx_dma_addr[tx_index] = 0;
688 }
689 lp->tx_complete_idx++;
690 /*COAL update tx coalescing parameters */
691 lp->coal_conf.tx_packets++;
692 lp->coal_conf.tx_bytes +=
693 le16_to_cpu(lp->tx_ring[tx_index].buff_count);
694
695 if (netif_queue_stopped(dev) &&
696 lp->tx_complete_idx > lp->tx_idx - NUM_TX_BUFFERS +2){
697 /* The ring is no longer full, clear tbusy. */
698 /* lp->tx_full = 0; */
699 netif_wake_queue (dev);
700 }
701 }
702 return 0;
703 }
704
705 /* This function handles the driver receive operation in polling mode */
706 static int amd8111e_rx_poll(struct napi_struct *napi, int budget)
707 {
708 struct amd8111e_priv *lp = container_of(napi, struct amd8111e_priv, napi);
709 struct net_device *dev = lp->amd8111e_net_dev;
710 int rx_index = lp->rx_idx & RX_RING_DR_MOD_MASK;
711 void __iomem *mmio = lp->mmio;
712 struct sk_buff *skb,*new_skb;
713 int min_pkt_len, status;
714 unsigned int intr0;
715 int num_rx_pkt = 0;
716 short pkt_len;
717 #if AMD8111E_VLAN_TAG_USED
718 short vtag;
719 #endif
720 int rx_pkt_limit = budget;
721 unsigned long flags;
722
723 if (rx_pkt_limit <= 0)
724 goto rx_not_empty;
725
726 do{
727 /* process receive packets until we use the quota*/
728 /* If we own the next entry, it's a new packet. Send it up. */
729 while(1) {
730 status = le16_to_cpu(lp->rx_ring[rx_index].rx_flags);
731 if (status & OWN_BIT)
732 break;
733
734 /*
735 * There is a tricky error noted by John Murphy,
736 * <murf@perftech.com> to Russ Nelson: Even with
737 * full-sized * buffers it's possible for a
738 * jabber packet to use two buffers, with only
739 * the last correctly noting the error.
740 */
741
742 if(status & ERR_BIT) {
743 /* reseting flags */
744 lp->rx_ring[rx_index].rx_flags &= RESET_RX_FLAGS;
745 goto err_next_pkt;
746 }
747 /* check for STP and ENP */
748 if(!((status & STP_BIT) && (status & ENP_BIT))){
749 /* reseting flags */
750 lp->rx_ring[rx_index].rx_flags &= RESET_RX_FLAGS;
751 goto err_next_pkt;
752 }
753 pkt_len = le16_to_cpu(lp->rx_ring[rx_index].msg_count) - 4;
754
755 #if AMD8111E_VLAN_TAG_USED
756 vtag = status & TT_MASK;
757 /*MAC will strip vlan tag*/
758 if (vtag != 0)
759 min_pkt_len =MIN_PKT_LEN - 4;
760 else
761 #endif
762 min_pkt_len =MIN_PKT_LEN;
763
764 if (pkt_len < min_pkt_len) {
765 lp->rx_ring[rx_index].rx_flags &= RESET_RX_FLAGS;
766 lp->drv_rx_errors++;
767 goto err_next_pkt;
768 }
769 if(--rx_pkt_limit < 0)
770 goto rx_not_empty;
771 new_skb = netdev_alloc_skb(dev, lp->rx_buff_len);
772 if (!new_skb) {
773 /* if allocation fail,
774 ignore that pkt and go to next one */
775 lp->rx_ring[rx_index].rx_flags &= RESET_RX_FLAGS;
776 lp->drv_rx_errors++;
777 goto err_next_pkt;
778 }
779
780 skb_reserve(new_skb, 2);
781 skb = lp->rx_skbuff[rx_index];
782 pci_unmap_single(lp->pci_dev,lp->rx_dma_addr[rx_index],
783 lp->rx_buff_len-2, PCI_DMA_FROMDEVICE);
784 skb_put(skb, pkt_len);
785 lp->rx_skbuff[rx_index] = new_skb;
786 lp->rx_dma_addr[rx_index] = pci_map_single(lp->pci_dev,
787 new_skb->data,
788 lp->rx_buff_len-2,
789 PCI_DMA_FROMDEVICE);
790
791 skb->protocol = eth_type_trans(skb, dev);
792
793 #if AMD8111E_VLAN_TAG_USED
794 if (vtag == TT_VLAN_TAGGED){
795 u16 vlan_tag = le16_to_cpu(lp->rx_ring[rx_index].tag_ctrl_info);
796 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vlan_tag);
797 }
798 #endif
799 netif_receive_skb(skb);
800 /*COAL update rx coalescing parameters*/
801 lp->coal_conf.rx_packets++;
802 lp->coal_conf.rx_bytes += pkt_len;
803 num_rx_pkt++;
804
805 err_next_pkt:
806 lp->rx_ring[rx_index].buff_phy_addr
807 = cpu_to_le32(lp->rx_dma_addr[rx_index]);
808 lp->rx_ring[rx_index].buff_count =
809 cpu_to_le16(lp->rx_buff_len-2);
810 wmb();
811 lp->rx_ring[rx_index].rx_flags |= cpu_to_le16(OWN_BIT);
812 rx_index = (++lp->rx_idx) & RX_RING_DR_MOD_MASK;
813 }
814 /* Check the interrupt status register for more packets in the
815 mean time. Process them since we have not used up our quota.*/
816
817 intr0 = readl(mmio + INT0);
818 /*Ack receive packets */
819 writel(intr0 & RINT0,mmio + INT0);
820
821 } while(intr0 & RINT0);
822
823 if (rx_pkt_limit > 0) {
824 /* Receive descriptor is empty now */
825 spin_lock_irqsave(&lp->lock, flags);
826 __napi_complete(napi);
827 writel(VAL0|RINTEN0, mmio + INTEN0);
828 writel(VAL2 | RDMD0, mmio + CMD0);
829 spin_unlock_irqrestore(&lp->lock, flags);
830 }
831
832 rx_not_empty:
833 return num_rx_pkt;
834 }
835
836 /*
837 This function will indicate the link status to the kernel.
838 */
839 static int amd8111e_link_change(struct net_device* dev)
840 {
841 struct amd8111e_priv *lp = netdev_priv(dev);
842 int status0,speed;
843
844 /* read the link change */
845 status0 = readl(lp->mmio + STAT0);
846
847 if(status0 & LINK_STATS){
848 if(status0 & AUTONEG_COMPLETE)
849 lp->link_config.autoneg = AUTONEG_ENABLE;
850 else
851 lp->link_config.autoneg = AUTONEG_DISABLE;
852
853 if(status0 & FULL_DPLX)
854 lp->link_config.duplex = DUPLEX_FULL;
855 else
856 lp->link_config.duplex = DUPLEX_HALF;
857 speed = (status0 & SPEED_MASK) >> 7;
858 if(speed == PHY_SPEED_10)
859 lp->link_config.speed = SPEED_10;
860 else if(speed == PHY_SPEED_100)
861 lp->link_config.speed = SPEED_100;
862
863 printk(KERN_INFO "%s: Link is Up. Speed is %s Mbps %s Duplex\n", dev->name,
864 (lp->link_config.speed == SPEED_100) ? "100": "10",
865 (lp->link_config.duplex == DUPLEX_FULL)? "Full": "Half");
866 netif_carrier_on(dev);
867 }
868 else{
869 lp->link_config.speed = SPEED_INVALID;
870 lp->link_config.duplex = DUPLEX_INVALID;
871 lp->link_config.autoneg = AUTONEG_INVALID;
872 printk(KERN_INFO "%s: Link is Down.\n",dev->name);
873 netif_carrier_off(dev);
874 }
875
876 return 0;
877 }
878 /*
879 This function reads the mib counters.
880 */
881 static int amd8111e_read_mib(void __iomem *mmio, u8 MIB_COUNTER)
882 {
883 unsigned int status;
884 unsigned int data;
885 unsigned int repeat = REPEAT_CNT;
886
887 writew( MIB_RD_CMD | MIB_COUNTER, mmio + MIB_ADDR);
888 do {
889 status = readw(mmio + MIB_ADDR);
890 udelay(2); /* controller takes MAX 2 us to get mib data */
891 }
892 while (--repeat && (status & MIB_CMD_ACTIVE));
893
894 data = readl(mmio + MIB_DATA);
895 return data;
896 }
897
898 /*
899 * This function reads the mib registers and returns the hardware statistics.
900 * It updates previous internal driver statistics with new values.
901 */
902 static struct net_device_stats *amd8111e_get_stats(struct net_device *dev)
903 {
904 struct amd8111e_priv *lp = netdev_priv(dev);
905 void __iomem *mmio = lp->mmio;
906 unsigned long flags;
907 struct net_device_stats *new_stats = &dev->stats;
908
909 if (!lp->opened)
910 return new_stats;
911 spin_lock_irqsave (&lp->lock, flags);
912
913 /* stats.rx_packets */
914 new_stats->rx_packets = amd8111e_read_mib(mmio, rcv_broadcast_pkts)+
915 amd8111e_read_mib(mmio, rcv_multicast_pkts)+
916 amd8111e_read_mib(mmio, rcv_unicast_pkts);
917
918 /* stats.tx_packets */
919 new_stats->tx_packets = amd8111e_read_mib(mmio, xmt_packets);
920
921 /*stats.rx_bytes */
922 new_stats->rx_bytes = amd8111e_read_mib(mmio, rcv_octets);
923
924 /* stats.tx_bytes */
925 new_stats->tx_bytes = amd8111e_read_mib(mmio, xmt_octets);
926
927 /* stats.rx_errors */
928 /* hw errors + errors driver reported */
929 new_stats->rx_errors = amd8111e_read_mib(mmio, rcv_undersize_pkts)+
930 amd8111e_read_mib(mmio, rcv_fragments)+
931 amd8111e_read_mib(mmio, rcv_jabbers)+
932 amd8111e_read_mib(mmio, rcv_alignment_errors)+
933 amd8111e_read_mib(mmio, rcv_fcs_errors)+
934 amd8111e_read_mib(mmio, rcv_miss_pkts)+
935 lp->drv_rx_errors;
936
937 /* stats.tx_errors */
938 new_stats->tx_errors = amd8111e_read_mib(mmio, xmt_underrun_pkts);
939
940 /* stats.rx_dropped*/
941 new_stats->rx_dropped = amd8111e_read_mib(mmio, rcv_miss_pkts);
942
943 /* stats.tx_dropped*/
944 new_stats->tx_dropped = amd8111e_read_mib(mmio, xmt_underrun_pkts);
945
946 /* stats.multicast*/
947 new_stats->multicast = amd8111e_read_mib(mmio, rcv_multicast_pkts);
948
949 /* stats.collisions*/
950 new_stats->collisions = amd8111e_read_mib(mmio, xmt_collisions);
951
952 /* stats.rx_length_errors*/
953 new_stats->rx_length_errors =
954 amd8111e_read_mib(mmio, rcv_undersize_pkts)+
955 amd8111e_read_mib(mmio, rcv_oversize_pkts);
956
957 /* stats.rx_over_errors*/
958 new_stats->rx_over_errors = amd8111e_read_mib(mmio, rcv_miss_pkts);
959
960 /* stats.rx_crc_errors*/
961 new_stats->rx_crc_errors = amd8111e_read_mib(mmio, rcv_fcs_errors);
962
963 /* stats.rx_frame_errors*/
964 new_stats->rx_frame_errors =
965 amd8111e_read_mib(mmio, rcv_alignment_errors);
966
967 /* stats.rx_fifo_errors */
968 new_stats->rx_fifo_errors = amd8111e_read_mib(mmio, rcv_miss_pkts);
969
970 /* stats.rx_missed_errors */
971 new_stats->rx_missed_errors = amd8111e_read_mib(mmio, rcv_miss_pkts);
972
973 /* stats.tx_aborted_errors*/
974 new_stats->tx_aborted_errors =
975 amd8111e_read_mib(mmio, xmt_excessive_collision);
976
977 /* stats.tx_carrier_errors*/
978 new_stats->tx_carrier_errors =
979 amd8111e_read_mib(mmio, xmt_loss_carrier);
980
981 /* stats.tx_fifo_errors*/
982 new_stats->tx_fifo_errors = amd8111e_read_mib(mmio, xmt_underrun_pkts);
983
984 /* stats.tx_window_errors*/
985 new_stats->tx_window_errors =
986 amd8111e_read_mib(mmio, xmt_late_collision);
987
988 /* Reset the mibs for collecting new statistics */
989 /* writew(MIB_CLEAR, mmio + MIB_ADDR);*/
990
991 spin_unlock_irqrestore (&lp->lock, flags);
992
993 return new_stats;
994 }
995 /* This function recalculate the interrupt coalescing mode on every interrupt
996 according to the datarate and the packet rate.
997 */
998 static int amd8111e_calc_coalesce(struct net_device *dev)
999 {
1000 struct amd8111e_priv *lp = netdev_priv(dev);
1001 struct amd8111e_coalesce_conf * coal_conf = &lp->coal_conf;
1002 int tx_pkt_rate;
1003 int rx_pkt_rate;
1004 int tx_data_rate;
1005 int rx_data_rate;
1006 int rx_pkt_size;
1007 int tx_pkt_size;
1008
1009 tx_pkt_rate = coal_conf->tx_packets - coal_conf->tx_prev_packets;
1010 coal_conf->tx_prev_packets = coal_conf->tx_packets;
1011
1012 tx_data_rate = coal_conf->tx_bytes - coal_conf->tx_prev_bytes;
1013 coal_conf->tx_prev_bytes = coal_conf->tx_bytes;
1014
1015 rx_pkt_rate = coal_conf->rx_packets - coal_conf->rx_prev_packets;
1016 coal_conf->rx_prev_packets = coal_conf->rx_packets;
1017
1018 rx_data_rate = coal_conf->rx_bytes - coal_conf->rx_prev_bytes;
1019 coal_conf->rx_prev_bytes = coal_conf->rx_bytes;
1020
1021 if(rx_pkt_rate < 800){
1022 if(coal_conf->rx_coal_type != NO_COALESCE){
1023
1024 coal_conf->rx_timeout = 0x0;
1025 coal_conf->rx_event_count = 0;
1026 amd8111e_set_coalesce(dev,RX_INTR_COAL);
1027 coal_conf->rx_coal_type = NO_COALESCE;
1028 }
1029 }
1030 else{
1031
1032 rx_pkt_size = rx_data_rate/rx_pkt_rate;
1033 if (rx_pkt_size < 128){
1034 if(coal_conf->rx_coal_type != NO_COALESCE){
1035
1036 coal_conf->rx_timeout = 0;
1037 coal_conf->rx_event_count = 0;
1038 amd8111e_set_coalesce(dev,RX_INTR_COAL);
1039 coal_conf->rx_coal_type = NO_COALESCE;
1040 }
1041
1042 }
1043 else if ( (rx_pkt_size >= 128) && (rx_pkt_size < 512) ){
1044
1045 if(coal_conf->rx_coal_type != LOW_COALESCE){
1046 coal_conf->rx_timeout = 1;
1047 coal_conf->rx_event_count = 4;
1048 amd8111e_set_coalesce(dev,RX_INTR_COAL);
1049 coal_conf->rx_coal_type = LOW_COALESCE;
1050 }
1051 }
1052 else if ((rx_pkt_size >= 512) && (rx_pkt_size < 1024)){
1053
1054 if(coal_conf->rx_coal_type != MEDIUM_COALESCE){
1055 coal_conf->rx_timeout = 1;
1056 coal_conf->rx_event_count = 4;
1057 amd8111e_set_coalesce(dev,RX_INTR_COAL);
1058 coal_conf->rx_coal_type = MEDIUM_COALESCE;
1059 }
1060
1061 }
1062 else if(rx_pkt_size >= 1024){
1063 if(coal_conf->rx_coal_type != HIGH_COALESCE){
1064 coal_conf->rx_timeout = 2;
1065 coal_conf->rx_event_count = 3;
1066 amd8111e_set_coalesce(dev,RX_INTR_COAL);
1067 coal_conf->rx_coal_type = HIGH_COALESCE;
1068 }
1069 }
1070 }
1071 /* NOW FOR TX INTR COALESC */
1072 if(tx_pkt_rate < 800){
1073 if(coal_conf->tx_coal_type != NO_COALESCE){
1074
1075 coal_conf->tx_timeout = 0x0;
1076 coal_conf->tx_event_count = 0;
1077 amd8111e_set_coalesce(dev,TX_INTR_COAL);
1078 coal_conf->tx_coal_type = NO_COALESCE;
1079 }
1080 }
1081 else{
1082
1083 tx_pkt_size = tx_data_rate/tx_pkt_rate;
1084 if (tx_pkt_size < 128){
1085
1086 if(coal_conf->tx_coal_type != NO_COALESCE){
1087
1088 coal_conf->tx_timeout = 0;
1089 coal_conf->tx_event_count = 0;
1090 amd8111e_set_coalesce(dev,TX_INTR_COAL);
1091 coal_conf->tx_coal_type = NO_COALESCE;
1092 }
1093
1094 }
1095 else if ( (tx_pkt_size >= 128) && (tx_pkt_size < 512) ){
1096
1097 if(coal_conf->tx_coal_type != LOW_COALESCE){
1098 coal_conf->tx_timeout = 1;
1099 coal_conf->tx_event_count = 2;
1100 amd8111e_set_coalesce(dev,TX_INTR_COAL);
1101 coal_conf->tx_coal_type = LOW_COALESCE;
1102
1103 }
1104 }
1105 else if ((tx_pkt_size >= 512) && (tx_pkt_size < 1024)){
1106
1107 if(coal_conf->tx_coal_type != MEDIUM_COALESCE){
1108 coal_conf->tx_timeout = 2;
1109 coal_conf->tx_event_count = 5;
1110 amd8111e_set_coalesce(dev,TX_INTR_COAL);
1111 coal_conf->tx_coal_type = MEDIUM_COALESCE;
1112 }
1113
1114 }
1115 else if(tx_pkt_size >= 1024){
1116 if (tx_pkt_size >= 1024){
1117 if(coal_conf->tx_coal_type != HIGH_COALESCE){
1118 coal_conf->tx_timeout = 4;
1119 coal_conf->tx_event_count = 8;
1120 amd8111e_set_coalesce(dev,TX_INTR_COAL);
1121 coal_conf->tx_coal_type = HIGH_COALESCE;
1122 }
1123 }
1124 }
1125 }
1126 return 0;
1127
1128 }
1129 /*
1130 This is device interrupt function. It handles transmit, receive,link change and hardware timer interrupts.
1131 */
1132 static irqreturn_t amd8111e_interrupt(int irq, void *dev_id)
1133 {
1134
1135 struct net_device * dev = (struct net_device *) dev_id;
1136 struct amd8111e_priv *lp = netdev_priv(dev);
1137 void __iomem *mmio = lp->mmio;
1138 unsigned int intr0, intren0;
1139 unsigned int handled = 1;
1140
1141 if(unlikely(dev == NULL))
1142 return IRQ_NONE;
1143
1144 spin_lock(&lp->lock);
1145
1146 /* disabling interrupt */
1147 writel(INTREN, mmio + CMD0);
1148
1149 /* Read interrupt status */
1150 intr0 = readl(mmio + INT0);
1151 intren0 = readl(mmio + INTEN0);
1152
1153 /* Process all the INT event until INTR bit is clear. */
1154
1155 if (!(intr0 & INTR)){
1156 handled = 0;
1157 goto err_no_interrupt;
1158 }
1159
1160 /* Current driver processes 4 interrupts : RINT,TINT,LCINT,STINT */
1161 writel(intr0, mmio + INT0);
1162
1163 /* Check if Receive Interrupt has occurred. */
1164 if (intr0 & RINT0) {
1165 if (napi_schedule_prep(&lp->napi)) {
1166 /* Disable receive interupts */
1167 writel(RINTEN0, mmio + INTEN0);
1168 /* Schedule a polling routine */
1169 __napi_schedule(&lp->napi);
1170 } else if (intren0 & RINTEN0) {
1171 printk("************Driver bug! interrupt while in poll\n");
1172 /* Fix by disable receive interrupts */
1173 writel(RINTEN0, mmio + INTEN0);
1174 }
1175 }
1176
1177 /* Check if Transmit Interrupt has occurred. */
1178 if (intr0 & TINT0)
1179 amd8111e_tx(dev);
1180
1181 /* Check if Link Change Interrupt has occurred. */
1182 if (intr0 & LCINT)
1183 amd8111e_link_change(dev);
1184
1185 /* Check if Hardware Timer Interrupt has occurred. */
1186 if (intr0 & STINT)
1187 amd8111e_calc_coalesce(dev);
1188
1189 err_no_interrupt:
1190 writel( VAL0 | INTREN,mmio + CMD0);
1191
1192 spin_unlock(&lp->lock);
1193
1194 return IRQ_RETVAL(handled);
1195 }
1196
1197 #ifdef CONFIG_NET_POLL_CONTROLLER
1198 static void amd8111e_poll(struct net_device *dev)
1199 {
1200 unsigned long flags;
1201 local_irq_save(flags);
1202 amd8111e_interrupt(0, dev);
1203 local_irq_restore(flags);
1204 }
1205 #endif
1206
1207
1208 /*
1209 This function closes the network interface and updates the statistics so that most recent statistics will be available after the interface is down.
1210 */
1211 static int amd8111e_close(struct net_device * dev)
1212 {
1213 struct amd8111e_priv *lp = netdev_priv(dev);
1214 netif_stop_queue(dev);
1215
1216 napi_disable(&lp->napi);
1217
1218 spin_lock_irq(&lp->lock);
1219
1220 amd8111e_disable_interrupt(lp);
1221 amd8111e_stop_chip(lp);
1222
1223 /* Free transmit and receive skbs */
1224 amd8111e_free_skbs(lp->amd8111e_net_dev);
1225
1226 netif_carrier_off(lp->amd8111e_net_dev);
1227
1228 /* Delete ipg timer */
1229 if(lp->options & OPTION_DYN_IPG_ENABLE)
1230 del_timer_sync(&lp->ipg_data.ipg_timer);
1231
1232 spin_unlock_irq(&lp->lock);
1233 free_irq(dev->irq, dev);
1234 amd8111e_free_ring(lp);
1235
1236 /* Update the statistics before closing */
1237 amd8111e_get_stats(dev);
1238 lp->opened = 0;
1239 return 0;
1240 }
1241 /* This function opens new interface.It requests irq for the device, initializes the device,buffers and descriptors, and starts the device.
1242 */
1243 static int amd8111e_open(struct net_device * dev )
1244 {
1245 struct amd8111e_priv *lp = netdev_priv(dev);
1246
1247 if(dev->irq ==0 || request_irq(dev->irq, amd8111e_interrupt, IRQF_SHARED,
1248 dev->name, dev))
1249 return -EAGAIN;
1250
1251 napi_enable(&lp->napi);
1252
1253 spin_lock_irq(&lp->lock);
1254
1255 amd8111e_init_hw_default(lp);
1256
1257 if(amd8111e_restart(dev)){
1258 spin_unlock_irq(&lp->lock);
1259 napi_disable(&lp->napi);
1260 if (dev->irq)
1261 free_irq(dev->irq, dev);
1262 return -ENOMEM;
1263 }
1264 /* Start ipg timer */
1265 if(lp->options & OPTION_DYN_IPG_ENABLE){
1266 add_timer(&lp->ipg_data.ipg_timer);
1267 printk(KERN_INFO "%s: Dynamic IPG Enabled.\n",dev->name);
1268 }
1269
1270 lp->opened = 1;
1271
1272 spin_unlock_irq(&lp->lock);
1273
1274 netif_start_queue(dev);
1275
1276 return 0;
1277 }
1278 /*
1279 This function checks if there is any transmit descriptors available to queue more packet.
1280 */
1281 static int amd8111e_tx_queue_avail(struct amd8111e_priv* lp )
1282 {
1283 int tx_index = lp->tx_idx & TX_BUFF_MOD_MASK;
1284 if (lp->tx_skbuff[tx_index])
1285 return -1;
1286 else
1287 return 0;
1288
1289 }
1290 /*
1291 This function will queue the transmit packets to the descriptors and will trigger the send operation. It also initializes the transmit descriptors with buffer physical address, byte count, ownership to hardware etc.
1292 */
1293
1294 static netdev_tx_t amd8111e_start_xmit(struct sk_buff *skb,
1295 struct net_device * dev)
1296 {
1297 struct amd8111e_priv *lp = netdev_priv(dev);
1298 int tx_index;
1299 unsigned long flags;
1300
1301 spin_lock_irqsave(&lp->lock, flags);
1302
1303 tx_index = lp->tx_idx & TX_RING_DR_MOD_MASK;
1304
1305 lp->tx_ring[tx_index].buff_count = cpu_to_le16(skb->len);
1306
1307 lp->tx_skbuff[tx_index] = skb;
1308 lp->tx_ring[tx_index].tx_flags = 0;
1309
1310 #if AMD8111E_VLAN_TAG_USED
1311 if (vlan_tx_tag_present(skb)) {
1312 lp->tx_ring[tx_index].tag_ctrl_cmd |=
1313 cpu_to_le16(TCC_VLAN_INSERT);
1314 lp->tx_ring[tx_index].tag_ctrl_info =
1315 cpu_to_le16(vlan_tx_tag_get(skb));
1316
1317 }
1318 #endif
1319 lp->tx_dma_addr[tx_index] =
1320 pci_map_single(lp->pci_dev, skb->data, skb->len, PCI_DMA_TODEVICE);
1321 lp->tx_ring[tx_index].buff_phy_addr =
1322 cpu_to_le32(lp->tx_dma_addr[tx_index]);
1323
1324 /* Set FCS and LTINT bits */
1325 wmb();
1326 lp->tx_ring[tx_index].tx_flags |=
1327 cpu_to_le16(OWN_BIT | STP_BIT | ENP_BIT|ADD_FCS_BIT|LTINT_BIT);
1328
1329 lp->tx_idx++;
1330
1331 /* Trigger an immediate send poll. */
1332 writel( VAL1 | TDMD0, lp->mmio + CMD0);
1333 writel( VAL2 | RDMD0,lp->mmio + CMD0);
1334
1335 if(amd8111e_tx_queue_avail(lp) < 0){
1336 netif_stop_queue(dev);
1337 }
1338 spin_unlock_irqrestore(&lp->lock, flags);
1339 return NETDEV_TX_OK;
1340 }
1341 /*
1342 This function returns all the memory mapped registers of the device.
1343 */
1344 static void amd8111e_read_regs(struct amd8111e_priv *lp, u32 *buf)
1345 {
1346 void __iomem *mmio = lp->mmio;
1347 /* Read only necessary registers */
1348 buf[0] = readl(mmio + XMT_RING_BASE_ADDR0);
1349 buf[1] = readl(mmio + XMT_RING_LEN0);
1350 buf[2] = readl(mmio + RCV_RING_BASE_ADDR0);
1351 buf[3] = readl(mmio + RCV_RING_LEN0);
1352 buf[4] = readl(mmio + CMD0);
1353 buf[5] = readl(mmio + CMD2);
1354 buf[6] = readl(mmio + CMD3);
1355 buf[7] = readl(mmio + CMD7);
1356 buf[8] = readl(mmio + INT0);
1357 buf[9] = readl(mmio + INTEN0);
1358 buf[10] = readl(mmio + LADRF);
1359 buf[11] = readl(mmio + LADRF+4);
1360 buf[12] = readl(mmio + STAT0);
1361 }
1362
1363
1364 /*
1365 This function sets promiscuos mode, all-multi mode or the multicast address
1366 list to the device.
1367 */
1368 static void amd8111e_set_multicast_list(struct net_device *dev)
1369 {
1370 struct netdev_hw_addr *ha;
1371 struct amd8111e_priv *lp = netdev_priv(dev);
1372 u32 mc_filter[2] ;
1373 int bit_num;
1374
1375 if(dev->flags & IFF_PROMISC){
1376 writel( VAL2 | PROM, lp->mmio + CMD2);
1377 return;
1378 }
1379 else
1380 writel( PROM, lp->mmio + CMD2);
1381 if (dev->flags & IFF_ALLMULTI ||
1382 netdev_mc_count(dev) > MAX_FILTER_SIZE) {
1383 /* get all multicast packet */
1384 mc_filter[1] = mc_filter[0] = 0xffffffff;
1385 lp->options |= OPTION_MULTICAST_ENABLE;
1386 amd8111e_writeq(*(u64*)mc_filter,lp->mmio + LADRF);
1387 return;
1388 }
1389 if (netdev_mc_empty(dev)) {
1390 /* get only own packets */
1391 mc_filter[1] = mc_filter[0] = 0;
1392 lp->options &= ~OPTION_MULTICAST_ENABLE;
1393 amd8111e_writeq(*(u64*)mc_filter,lp->mmio + LADRF);
1394 /* disable promiscuous mode */
1395 writel(PROM, lp->mmio + CMD2);
1396 return;
1397 }
1398 /* load all the multicast addresses in the logic filter */
1399 lp->options |= OPTION_MULTICAST_ENABLE;
1400 mc_filter[1] = mc_filter[0] = 0;
1401 netdev_for_each_mc_addr(ha, dev) {
1402 bit_num = (ether_crc_le(ETH_ALEN, ha->addr) >> 26) & 0x3f;
1403 mc_filter[bit_num >> 5] |= 1 << (bit_num & 31);
1404 }
1405 amd8111e_writeq(*(u64*)mc_filter,lp->mmio+ LADRF);
1406
1407 /* To eliminate PCI posting bug */
1408 readl(lp->mmio + CMD2);
1409
1410 }
1411
1412 static void amd8111e_get_drvinfo(struct net_device* dev, struct ethtool_drvinfo *info)
1413 {
1414 struct amd8111e_priv *lp = netdev_priv(dev);
1415 struct pci_dev *pci_dev = lp->pci_dev;
1416 strlcpy(info->driver, MODULE_NAME, sizeof(info->driver));
1417 strlcpy(info->version, MODULE_VERS, sizeof(info->version));
1418 snprintf(info->fw_version, sizeof(info->fw_version),
1419 "%u", chip_version);
1420 strlcpy(info->bus_info, pci_name(pci_dev), sizeof(info->bus_info));
1421 }
1422
1423 static int amd8111e_get_regs_len(struct net_device *dev)
1424 {
1425 return AMD8111E_REG_DUMP_LEN;
1426 }
1427
1428 static void amd8111e_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *buf)
1429 {
1430 struct amd8111e_priv *lp = netdev_priv(dev);
1431 regs->version = 0;
1432 amd8111e_read_regs(lp, buf);
1433 }
1434
1435 static int amd8111e_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
1436 {
1437 struct amd8111e_priv *lp = netdev_priv(dev);
1438 spin_lock_irq(&lp->lock);
1439 mii_ethtool_gset(&lp->mii_if, ecmd);
1440 spin_unlock_irq(&lp->lock);
1441 return 0;
1442 }
1443
1444 static int amd8111e_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
1445 {
1446 struct amd8111e_priv *lp = netdev_priv(dev);
1447 int res;
1448 spin_lock_irq(&lp->lock);
1449 res = mii_ethtool_sset(&lp->mii_if, ecmd);
1450 spin_unlock_irq(&lp->lock);
1451 return res;
1452 }
1453
1454 static int amd8111e_nway_reset(struct net_device *dev)
1455 {
1456 struct amd8111e_priv *lp = netdev_priv(dev);
1457 return mii_nway_restart(&lp->mii_if);
1458 }
1459
1460 static u32 amd8111e_get_link(struct net_device *dev)
1461 {
1462 struct amd8111e_priv *lp = netdev_priv(dev);
1463 return mii_link_ok(&lp->mii_if);
1464 }
1465
1466 static void amd8111e_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol_info)
1467 {
1468 struct amd8111e_priv *lp = netdev_priv(dev);
1469 wol_info->supported = WAKE_MAGIC|WAKE_PHY;
1470 if (lp->options & OPTION_WOL_ENABLE)
1471 wol_info->wolopts = WAKE_MAGIC;
1472 }
1473
1474 static int amd8111e_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol_info)
1475 {
1476 struct amd8111e_priv *lp = netdev_priv(dev);
1477 if (wol_info->wolopts & ~(WAKE_MAGIC|WAKE_PHY))
1478 return -EINVAL;
1479 spin_lock_irq(&lp->lock);
1480 if (wol_info->wolopts & WAKE_MAGIC)
1481 lp->options |=
1482 (OPTION_WOL_ENABLE | OPTION_WAKE_MAGIC_ENABLE);
1483 else if(wol_info->wolopts & WAKE_PHY)
1484 lp->options |=
1485 (OPTION_WOL_ENABLE | OPTION_WAKE_PHY_ENABLE);
1486 else
1487 lp->options &= ~OPTION_WOL_ENABLE;
1488 spin_unlock_irq(&lp->lock);
1489 return 0;
1490 }
1491
1492 static const struct ethtool_ops ops = {
1493 .get_drvinfo = amd8111e_get_drvinfo,
1494 .get_regs_len = amd8111e_get_regs_len,
1495 .get_regs = amd8111e_get_regs,
1496 .get_settings = amd8111e_get_settings,
1497 .set_settings = amd8111e_set_settings,
1498 .nway_reset = amd8111e_nway_reset,
1499 .get_link = amd8111e_get_link,
1500 .get_wol = amd8111e_get_wol,
1501 .set_wol = amd8111e_set_wol,
1502 };
1503
1504 /*
1505 This function handles all the ethtool ioctls. It gives driver info, gets/sets driver speed, gets memory mapped register values, forces auto negotiation, sets/gets WOL options for ethtool application.
1506 */
1507
1508 static int amd8111e_ioctl(struct net_device * dev , struct ifreq *ifr, int cmd)
1509 {
1510 struct mii_ioctl_data *data = if_mii(ifr);
1511 struct amd8111e_priv *lp = netdev_priv(dev);
1512 int err;
1513 u32 mii_regval;
1514
1515 switch(cmd) {
1516 case SIOCGMIIPHY:
1517 data->phy_id = lp->ext_phy_addr;
1518
1519 /* fallthru */
1520 case SIOCGMIIREG:
1521
1522 spin_lock_irq(&lp->lock);
1523 err = amd8111e_read_phy(lp, data->phy_id,
1524 data->reg_num & PHY_REG_ADDR_MASK, &mii_regval);
1525 spin_unlock_irq(&lp->lock);
1526
1527 data->val_out = mii_regval;
1528 return err;
1529
1530 case SIOCSMIIREG:
1531
1532 spin_lock_irq(&lp->lock);
1533 err = amd8111e_write_phy(lp, data->phy_id,
1534 data->reg_num & PHY_REG_ADDR_MASK, data->val_in);
1535 spin_unlock_irq(&lp->lock);
1536
1537 return err;
1538
1539 default:
1540 /* do nothing */
1541 break;
1542 }
1543 return -EOPNOTSUPP;
1544 }
1545 static int amd8111e_set_mac_address(struct net_device *dev, void *p)
1546 {
1547 struct amd8111e_priv *lp = netdev_priv(dev);
1548 int i;
1549 struct sockaddr *addr = p;
1550
1551 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
1552 spin_lock_irq(&lp->lock);
1553 /* Setting the MAC address to the device */
1554 for (i = 0; i < ETH_ALEN; i++)
1555 writeb( dev->dev_addr[i], lp->mmio + PADR + i );
1556
1557 spin_unlock_irq(&lp->lock);
1558
1559 return 0;
1560 }
1561
1562 /*
1563 This function changes the mtu of the device. It restarts the device to initialize the descriptor with new receive buffers.
1564 */
1565 static int amd8111e_change_mtu(struct net_device *dev, int new_mtu)
1566 {
1567 struct amd8111e_priv *lp = netdev_priv(dev);
1568 int err;
1569
1570 if ((new_mtu < AMD8111E_MIN_MTU) || (new_mtu > AMD8111E_MAX_MTU))
1571 return -EINVAL;
1572
1573 if (!netif_running(dev)) {
1574 /* new_mtu will be used
1575 when device starts netxt time */
1576 dev->mtu = new_mtu;
1577 return 0;
1578 }
1579
1580 spin_lock_irq(&lp->lock);
1581
1582 /* stop the chip */
1583 writel(RUN, lp->mmio + CMD0);
1584
1585 dev->mtu = new_mtu;
1586
1587 err = amd8111e_restart(dev);
1588 spin_unlock_irq(&lp->lock);
1589 if(!err)
1590 netif_start_queue(dev);
1591 return err;
1592 }
1593
1594 static int amd8111e_enable_magicpkt(struct amd8111e_priv* lp)
1595 {
1596 writel( VAL1|MPPLBA, lp->mmio + CMD3);
1597 writel( VAL0|MPEN_SW, lp->mmio + CMD7);
1598
1599 /* To eliminate PCI posting bug */
1600 readl(lp->mmio + CMD7);
1601 return 0;
1602 }
1603
1604 static int amd8111e_enable_link_change(struct amd8111e_priv* lp)
1605 {
1606
1607 /* Adapter is already stoped/suspended/interrupt-disabled */
1608 writel(VAL0|LCMODE_SW,lp->mmio + CMD7);
1609
1610 /* To eliminate PCI posting bug */
1611 readl(lp->mmio + CMD7);
1612 return 0;
1613 }
1614
1615 /*
1616 * This function is called when a packet transmission fails to complete
1617 * within a reasonable period, on the assumption that an interrupt have
1618 * failed or the interface is locked up. This function will reinitialize
1619 * the hardware.
1620 */
1621 static void amd8111e_tx_timeout(struct net_device *dev)
1622 {
1623 struct amd8111e_priv* lp = netdev_priv(dev);
1624 int err;
1625
1626 printk(KERN_ERR "%s: transmit timed out, resetting\n",
1627 dev->name);
1628 spin_lock_irq(&lp->lock);
1629 err = amd8111e_restart(dev);
1630 spin_unlock_irq(&lp->lock);
1631 if(!err)
1632 netif_wake_queue(dev);
1633 }
1634 static int amd8111e_suspend(struct pci_dev *pci_dev, pm_message_t state)
1635 {
1636 struct net_device *dev = pci_get_drvdata(pci_dev);
1637 struct amd8111e_priv *lp = netdev_priv(dev);
1638
1639 if (!netif_running(dev))
1640 return 0;
1641
1642 /* disable the interrupt */
1643 spin_lock_irq(&lp->lock);
1644 amd8111e_disable_interrupt(lp);
1645 spin_unlock_irq(&lp->lock);
1646
1647 netif_device_detach(dev);
1648
1649 /* stop chip */
1650 spin_lock_irq(&lp->lock);
1651 if(lp->options & OPTION_DYN_IPG_ENABLE)
1652 del_timer_sync(&lp->ipg_data.ipg_timer);
1653 amd8111e_stop_chip(lp);
1654 spin_unlock_irq(&lp->lock);
1655
1656 if(lp->options & OPTION_WOL_ENABLE){
1657 /* enable wol */
1658 if(lp->options & OPTION_WAKE_MAGIC_ENABLE)
1659 amd8111e_enable_magicpkt(lp);
1660 if(lp->options & OPTION_WAKE_PHY_ENABLE)
1661 amd8111e_enable_link_change(lp);
1662
1663 pci_enable_wake(pci_dev, PCI_D3hot, 1);
1664 pci_enable_wake(pci_dev, PCI_D3cold, 1);
1665
1666 }
1667 else{
1668 pci_enable_wake(pci_dev, PCI_D3hot, 0);
1669 pci_enable_wake(pci_dev, PCI_D3cold, 0);
1670 }
1671
1672 pci_save_state(pci_dev);
1673 pci_set_power_state(pci_dev, PCI_D3hot);
1674
1675 return 0;
1676 }
1677 static int amd8111e_resume(struct pci_dev *pci_dev)
1678 {
1679 struct net_device *dev = pci_get_drvdata(pci_dev);
1680 struct amd8111e_priv *lp = netdev_priv(dev);
1681
1682 if (!netif_running(dev))
1683 return 0;
1684
1685 pci_set_power_state(pci_dev, PCI_D0);
1686 pci_restore_state(pci_dev);
1687
1688 pci_enable_wake(pci_dev, PCI_D3hot, 0);
1689 pci_enable_wake(pci_dev, PCI_D3cold, 0); /* D3 cold */
1690
1691 netif_device_attach(dev);
1692
1693 spin_lock_irq(&lp->lock);
1694 amd8111e_restart(dev);
1695 /* Restart ipg timer */
1696 if(lp->options & OPTION_DYN_IPG_ENABLE)
1697 mod_timer(&lp->ipg_data.ipg_timer,
1698 jiffies + IPG_CONVERGE_JIFFIES);
1699 spin_unlock_irq(&lp->lock);
1700
1701 return 0;
1702 }
1703
1704
1705 static void amd8111e_remove_one(struct pci_dev *pdev)
1706 {
1707 struct net_device *dev = pci_get_drvdata(pdev);
1708 if (dev) {
1709 unregister_netdev(dev);
1710 iounmap(((struct amd8111e_priv *)netdev_priv(dev))->mmio);
1711 free_netdev(dev);
1712 pci_release_regions(pdev);
1713 pci_disable_device(pdev);
1714 }
1715 }
1716 static void amd8111e_config_ipg(struct net_device* dev)
1717 {
1718 struct amd8111e_priv *lp = netdev_priv(dev);
1719 struct ipg_info* ipg_data = &lp->ipg_data;
1720 void __iomem *mmio = lp->mmio;
1721 unsigned int prev_col_cnt = ipg_data->col_cnt;
1722 unsigned int total_col_cnt;
1723 unsigned int tmp_ipg;
1724
1725 if(lp->link_config.duplex == DUPLEX_FULL){
1726 ipg_data->ipg = DEFAULT_IPG;
1727 return;
1728 }
1729
1730 if(ipg_data->ipg_state == SSTATE){
1731
1732 if(ipg_data->timer_tick == IPG_STABLE_TIME){
1733
1734 ipg_data->timer_tick = 0;
1735 ipg_data->ipg = MIN_IPG - IPG_STEP;
1736 ipg_data->current_ipg = MIN_IPG;
1737 ipg_data->diff_col_cnt = 0xFFFFFFFF;
1738 ipg_data->ipg_state = CSTATE;
1739 }
1740 else
1741 ipg_data->timer_tick++;
1742 }
1743
1744 if(ipg_data->ipg_state == CSTATE){
1745
1746 /* Get the current collision count */
1747
1748 total_col_cnt = ipg_data->col_cnt =
1749 amd8111e_read_mib(mmio, xmt_collisions);
1750
1751 if ((total_col_cnt - prev_col_cnt) <
1752 (ipg_data->diff_col_cnt)){
1753
1754 ipg_data->diff_col_cnt =
1755 total_col_cnt - prev_col_cnt ;
1756
1757 ipg_data->ipg = ipg_data->current_ipg;
1758 }
1759
1760 ipg_data->current_ipg += IPG_STEP;
1761
1762 if (ipg_data->current_ipg <= MAX_IPG)
1763 tmp_ipg = ipg_data->current_ipg;
1764 else{
1765 tmp_ipg = ipg_data->ipg;
1766 ipg_data->ipg_state = SSTATE;
1767 }
1768 writew((u32)tmp_ipg, mmio + IPG);
1769 writew((u32)(tmp_ipg - IFS1_DELTA), mmio + IFS1);
1770 }
1771 mod_timer(&lp->ipg_data.ipg_timer, jiffies + IPG_CONVERGE_JIFFIES);
1772 return;
1773
1774 }
1775
1776 static void amd8111e_probe_ext_phy(struct net_device *dev)
1777 {
1778 struct amd8111e_priv *lp = netdev_priv(dev);
1779 int i;
1780
1781 for (i = 0x1e; i >= 0; i--) {
1782 u32 id1, id2;
1783
1784 if (amd8111e_read_phy(lp, i, MII_PHYSID1, &id1))
1785 continue;
1786 if (amd8111e_read_phy(lp, i, MII_PHYSID2, &id2))
1787 continue;
1788 lp->ext_phy_id = (id1 << 16) | id2;
1789 lp->ext_phy_addr = i;
1790 return;
1791 }
1792 lp->ext_phy_id = 0;
1793 lp->ext_phy_addr = 1;
1794 }
1795
1796 static const struct net_device_ops amd8111e_netdev_ops = {
1797 .ndo_open = amd8111e_open,
1798 .ndo_stop = amd8111e_close,
1799 .ndo_start_xmit = amd8111e_start_xmit,
1800 .ndo_tx_timeout = amd8111e_tx_timeout,
1801 .ndo_get_stats = amd8111e_get_stats,
1802 .ndo_set_rx_mode = amd8111e_set_multicast_list,
1803 .ndo_validate_addr = eth_validate_addr,
1804 .ndo_set_mac_address = amd8111e_set_mac_address,
1805 .ndo_do_ioctl = amd8111e_ioctl,
1806 .ndo_change_mtu = amd8111e_change_mtu,
1807 #ifdef CONFIG_NET_POLL_CONTROLLER
1808 .ndo_poll_controller = amd8111e_poll,
1809 #endif
1810 };
1811
1812 static int amd8111e_probe_one(struct pci_dev *pdev,
1813 const struct pci_device_id *ent)
1814 {
1815 int err, i;
1816 unsigned long reg_addr,reg_len;
1817 struct amd8111e_priv* lp;
1818 struct net_device* dev;
1819
1820 err = pci_enable_device(pdev);
1821 if(err){
1822 printk(KERN_ERR "amd8111e: Cannot enable new PCI device, "
1823 "exiting.\n");
1824 return err;
1825 }
1826
1827 if(!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)){
1828 printk(KERN_ERR "amd8111e: Cannot find PCI base address, "
1829 "exiting.\n");
1830 err = -ENODEV;
1831 goto err_disable_pdev;
1832 }
1833
1834 err = pci_request_regions(pdev, MODULE_NAME);
1835 if(err){
1836 printk(KERN_ERR "amd8111e: Cannot obtain PCI resources, "
1837 "exiting.\n");
1838 goto err_disable_pdev;
1839 }
1840
1841 pci_set_master(pdev);
1842
1843 /* Find power-management capability. */
1844 if (!pdev->pm_cap) {
1845 printk(KERN_ERR "amd8111e: No Power Management capability, "
1846 "exiting.\n");
1847 err = -ENODEV;
1848 goto err_free_reg;
1849 }
1850
1851 /* Initialize DMA */
1852 if (pci_set_dma_mask(pdev, DMA_BIT_MASK(32)) < 0) {
1853 printk(KERN_ERR "amd8111e: DMA not supported,"
1854 "exiting.\n");
1855 err = -ENODEV;
1856 goto err_free_reg;
1857 }
1858
1859 reg_addr = pci_resource_start(pdev, 0);
1860 reg_len = pci_resource_len(pdev, 0);
1861
1862 dev = alloc_etherdev(sizeof(struct amd8111e_priv));
1863 if (!dev) {
1864 err = -ENOMEM;
1865 goto err_free_reg;
1866 }
1867
1868 SET_NETDEV_DEV(dev, &pdev->dev);
1869
1870 #if AMD8111E_VLAN_TAG_USED
1871 dev->features |= NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX ;
1872 #endif
1873
1874 lp = netdev_priv(dev);
1875 lp->pci_dev = pdev;
1876 lp->amd8111e_net_dev = dev;
1877 lp->pm_cap = pdev->pm_cap;
1878
1879 spin_lock_init(&lp->lock);
1880
1881 lp->mmio = ioremap(reg_addr, reg_len);
1882 if (!lp->mmio) {
1883 printk(KERN_ERR "amd8111e: Cannot map device registers, "
1884 "exiting\n");
1885 err = -ENOMEM;
1886 goto err_free_dev;
1887 }
1888
1889 /* Initializing MAC address */
1890 for (i = 0; i < ETH_ALEN; i++)
1891 dev->dev_addr[i] = readb(lp->mmio + PADR + i);
1892
1893 /* Setting user defined parametrs */
1894 lp->ext_phy_option = speed_duplex[card_idx];
1895 if(coalesce[card_idx])
1896 lp->options |= OPTION_INTR_COAL_ENABLE;
1897 if(dynamic_ipg[card_idx++])
1898 lp->options |= OPTION_DYN_IPG_ENABLE;
1899
1900
1901 /* Initialize driver entry points */
1902 dev->netdev_ops = &amd8111e_netdev_ops;
1903 dev->ethtool_ops = &ops;
1904 dev->irq =pdev->irq;
1905 dev->watchdog_timeo = AMD8111E_TX_TIMEOUT;
1906 netif_napi_add(dev, &lp->napi, amd8111e_rx_poll, 32);
1907
1908 #if AMD8111E_VLAN_TAG_USED
1909 dev->features |= NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX;
1910 #endif
1911 /* Probe the external PHY */
1912 amd8111e_probe_ext_phy(dev);
1913
1914 /* setting mii default values */
1915 lp->mii_if.dev = dev;
1916 lp->mii_if.mdio_read = amd8111e_mdio_read;
1917 lp->mii_if.mdio_write = amd8111e_mdio_write;
1918 lp->mii_if.phy_id = lp->ext_phy_addr;
1919
1920 /* Set receive buffer length and set jumbo option*/
1921 amd8111e_set_rx_buff_len(dev);
1922
1923
1924 err = register_netdev(dev);
1925 if (err) {
1926 printk(KERN_ERR "amd8111e: Cannot register net device, "
1927 "exiting.\n");
1928 goto err_iounmap;
1929 }
1930
1931 pci_set_drvdata(pdev, dev);
1932
1933 /* Initialize software ipg timer */
1934 if(lp->options & OPTION_DYN_IPG_ENABLE){
1935 init_timer(&lp->ipg_data.ipg_timer);
1936 lp->ipg_data.ipg_timer.data = (unsigned long) dev;
1937 lp->ipg_data.ipg_timer.function = (void *)&amd8111e_config_ipg;
1938 lp->ipg_data.ipg_timer.expires = jiffies +
1939 IPG_CONVERGE_JIFFIES;
1940 lp->ipg_data.ipg = DEFAULT_IPG;
1941 lp->ipg_data.ipg_state = CSTATE;
1942 }
1943
1944 /* display driver and device information */
1945
1946 chip_version = (readl(lp->mmio + CHIPID) & 0xf0000000)>>28;
1947 printk(KERN_INFO "%s: AMD-8111e Driver Version: %s\n",
1948 dev->name,MODULE_VERS);
1949 printk(KERN_INFO "%s: [ Rev %x ] PCI 10/100BaseT Ethernet %pM\n",
1950 dev->name, chip_version, dev->dev_addr);
1951 if (lp->ext_phy_id)
1952 printk(KERN_INFO "%s: Found MII PHY ID 0x%08x at address 0x%02x\n",
1953 dev->name, lp->ext_phy_id, lp->ext_phy_addr);
1954 else
1955 printk(KERN_INFO "%s: Couldn't detect MII PHY, assuming address 0x01\n",
1956 dev->name);
1957 return 0;
1958 err_iounmap:
1959 iounmap(lp->mmio);
1960
1961 err_free_dev:
1962 free_netdev(dev);
1963
1964 err_free_reg:
1965 pci_release_regions(pdev);
1966
1967 err_disable_pdev:
1968 pci_disable_device(pdev);
1969 return err;
1970
1971 }
1972
1973 static struct pci_driver amd8111e_driver = {
1974 .name = MODULE_NAME,
1975 .id_table = amd8111e_pci_tbl,
1976 .probe = amd8111e_probe_one,
1977 .remove = amd8111e_remove_one,
1978 .suspend = amd8111e_suspend,
1979 .resume = amd8111e_resume
1980 };
1981
1982 module_pci_driver(amd8111e_driver);
Linux with added FPC-III support