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staging: xgifb: vb_setmode: make XGI_SetXG27FPBits() static
[linux/fpc-iii.git] / sound / soc / codecs / wm8350.c
blob35f3ad83dfb6670013652772268385b75cda481a
1 /*
2 * wm8350.c -- WM8350 ALSA SoC audio driver
3 *
4 * Copyright (C) 2007, 2008 Wolfson Microelectronics PLC.
5 *
6 * Author: Liam Girdwood <lrg@slimlogic.co.uk>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13 #include <linux/module.h>
14 #include <linux/moduleparam.h>
15 #include <linux/init.h>
16 #include <linux/slab.h>
17 #include <linux/delay.h>
18 #include <linux/pm.h>
19 #include <linux/platform_device.h>
20 #include <linux/mfd/wm8350/audio.h>
21 #include <linux/mfd/wm8350/core.h>
22 #include <linux/regulator/consumer.h>
23 #include <sound/core.h>
24 #include <sound/pcm.h>
25 #include <sound/pcm_params.h>
26 #include <sound/soc.h>
27 #include <sound/initval.h>
28 #include <sound/tlv.h>
29 #include <trace/events/asoc.h>
30
31 #include "wm8350.h"
32
33 #define WM8350_OUTn_0dB 0x39
34
35 #define WM8350_RAMP_NONE 0
36 #define WM8350_RAMP_UP 1
37 #define WM8350_RAMP_DOWN 2
38
39 /* We only include the analogue supplies here; the digital supplies
40 * need to be available well before this driver can be probed.
41 */
42 static const char *supply_names[] = {
43 "AVDD",
44 "HPVDD",
45 };
46
47 struct wm8350_output {
48 u16 active;
49 u16 left_vol;
50 u16 right_vol;
51 u16 ramp;
52 u16 mute;
53 };
54
55 struct wm8350_jack_data {
56 struct snd_soc_jack *jack;
57 struct delayed_work work;
58 int report;
59 int short_report;
60 };
61
62 struct wm8350_data {
63 struct snd_soc_codec codec;
64 struct wm8350_output out1;
65 struct wm8350_output out2;
66 struct wm8350_jack_data hpl;
67 struct wm8350_jack_data hpr;
68 struct wm8350_jack_data mic;
69 struct regulator_bulk_data supplies[ARRAY_SIZE(supply_names)];
70 int fll_freq_out;
71 int fll_freq_in;
72 };
73
74 static unsigned int wm8350_codec_cache_read(struct snd_soc_codec *codec,
75 unsigned int reg)
76 {
77 struct wm8350 *wm8350 = codec->control_data;
78 return wm8350->reg_cache[reg];
79 }
80
81 static unsigned int wm8350_codec_read(struct snd_soc_codec *codec,
82 unsigned int reg)
83 {
84 struct wm8350 *wm8350 = codec->control_data;
85 return wm8350_reg_read(wm8350, reg);
86 }
87
88 static int wm8350_codec_write(struct snd_soc_codec *codec, unsigned int reg,
89 unsigned int value)
90 {
91 struct wm8350 *wm8350 = codec->control_data;
92 return wm8350_reg_write(wm8350, reg, value);
93 }
94
95 /*
96 * Ramp OUT1 PGA volume to minimise pops at stream startup and shutdown.
97 */
98 static inline int wm8350_out1_ramp_step(struct snd_soc_codec *codec)
99 {
100 struct wm8350_data *wm8350_data = snd_soc_codec_get_drvdata(codec);
101 struct wm8350_output *out1 = &wm8350_data->out1;
102 struct wm8350 *wm8350 = codec->control_data;
103 int left_complete = 0, right_complete = 0;
104 u16 reg, val;
105
106 /* left channel */
107 reg = wm8350_reg_read(wm8350, WM8350_LOUT1_VOLUME);
108 val = (reg & WM8350_OUT1L_VOL_MASK) >> WM8350_OUT1L_VOL_SHIFT;
109
110 if (out1->ramp == WM8350_RAMP_UP) {
111 /* ramp step up */
112 if (val < out1->left_vol) {
113 val++;
114 reg &= ~WM8350_OUT1L_VOL_MASK;
115 wm8350_reg_write(wm8350, WM8350_LOUT1_VOLUME,
116 reg | (val << WM8350_OUT1L_VOL_SHIFT));
117 } else
118 left_complete = 1;
119 } else if (out1->ramp == WM8350_RAMP_DOWN) {
120 /* ramp step down */
121 if (val > 0) {
122 val--;
123 reg &= ~WM8350_OUT1L_VOL_MASK;
124 wm8350_reg_write(wm8350, WM8350_LOUT1_VOLUME,
125 reg | (val << WM8350_OUT1L_VOL_SHIFT));
126 } else
127 left_complete = 1;
128 } else
129 return 1;
130
131 /* right channel */
132 reg = wm8350_reg_read(wm8350, WM8350_ROUT1_VOLUME);
133 val = (reg & WM8350_OUT1R_VOL_MASK) >> WM8350_OUT1R_VOL_SHIFT;
134 if (out1->ramp == WM8350_RAMP_UP) {
135 /* ramp step up */
136 if (val < out1->right_vol) {
137 val++;
138 reg &= ~WM8350_OUT1R_VOL_MASK;
139 wm8350_reg_write(wm8350, WM8350_ROUT1_VOLUME,
140 reg | (val << WM8350_OUT1R_VOL_SHIFT));
141 } else
142 right_complete = 1;
143 } else if (out1->ramp == WM8350_RAMP_DOWN) {
144 /* ramp step down */
145 if (val > 0) {
146 val--;
147 reg &= ~WM8350_OUT1R_VOL_MASK;
148 wm8350_reg_write(wm8350, WM8350_ROUT1_VOLUME,
149 reg | (val << WM8350_OUT1R_VOL_SHIFT));
150 } else
151 right_complete = 1;
152 }
153
154 /* only hit the update bit if either volume has changed this step */
155 if (!left_complete || !right_complete)
156 wm8350_set_bits(wm8350, WM8350_LOUT1_VOLUME, WM8350_OUT1_VU);
157
158 return left_complete & right_complete;
159 }
160
161 /*
162 * Ramp OUT2 PGA volume to minimise pops at stream startup and shutdown.
163 */
164 static inline int wm8350_out2_ramp_step(struct snd_soc_codec *codec)
165 {
166 struct wm8350_data *wm8350_data = snd_soc_codec_get_drvdata(codec);
167 struct wm8350_output *out2 = &wm8350_data->out2;
168 struct wm8350 *wm8350 = codec->control_data;
169 int left_complete = 0, right_complete = 0;
170 u16 reg, val;
171
172 /* left channel */
173 reg = wm8350_reg_read(wm8350, WM8350_LOUT2_VOLUME);
174 val = (reg & WM8350_OUT2L_VOL_MASK) >> WM8350_OUT1L_VOL_SHIFT;
175 if (out2->ramp == WM8350_RAMP_UP) {
176 /* ramp step up */
177 if (val < out2->left_vol) {
178 val++;
179 reg &= ~WM8350_OUT2L_VOL_MASK;
180 wm8350_reg_write(wm8350, WM8350_LOUT2_VOLUME,
181 reg | (val << WM8350_OUT1L_VOL_SHIFT));
182 } else
183 left_complete = 1;
184 } else if (out2->ramp == WM8350_RAMP_DOWN) {
185 /* ramp step down */
186 if (val > 0) {
187 val--;
188 reg &= ~WM8350_OUT2L_VOL_MASK;
189 wm8350_reg_write(wm8350, WM8350_LOUT2_VOLUME,
190 reg | (val << WM8350_OUT1L_VOL_SHIFT));
191 } else
192 left_complete = 1;
193 } else
194 return 1;
195
196 /* right channel */
197 reg = wm8350_reg_read(wm8350, WM8350_ROUT2_VOLUME);
198 val = (reg & WM8350_OUT2R_VOL_MASK) >> WM8350_OUT1R_VOL_SHIFT;
199 if (out2->ramp == WM8350_RAMP_UP) {
200 /* ramp step up */
201 if (val < out2->right_vol) {
202 val++;
203 reg &= ~WM8350_OUT2R_VOL_MASK;
204 wm8350_reg_write(wm8350, WM8350_ROUT2_VOLUME,
205 reg | (val << WM8350_OUT1R_VOL_SHIFT));
206 } else
207 right_complete = 1;
208 } else if (out2->ramp == WM8350_RAMP_DOWN) {
209 /* ramp step down */
210 if (val > 0) {
211 val--;
212 reg &= ~WM8350_OUT2R_VOL_MASK;
213 wm8350_reg_write(wm8350, WM8350_ROUT2_VOLUME,
214 reg | (val << WM8350_OUT1R_VOL_SHIFT));
215 } else
216 right_complete = 1;
217 }
218
219 /* only hit the update bit if either volume has changed this step */
220 if (!left_complete || !right_complete)
221 wm8350_set_bits(wm8350, WM8350_LOUT2_VOLUME, WM8350_OUT2_VU);
222
223 return left_complete & right_complete;
224 }
225
226 /*
227 * This work ramps both output PGAs at stream start/stop time to
228 * minimise pop associated with DAPM power switching.
229 * It's best to enable Zero Cross when ramping occurs to minimise any
230 * zipper noises.
231 */
232 static void wm8350_pga_work(struct work_struct *work)
233 {
234 struct snd_soc_dapm_context *dapm =
235 container_of(work, struct snd_soc_dapm_context, delayed_work.work);
236 struct snd_soc_codec *codec = dapm->codec;
237 struct wm8350_data *wm8350_data = snd_soc_codec_get_drvdata(codec);
238 struct wm8350_output *out1 = &wm8350_data->out1,
239 *out2 = &wm8350_data->out2;
240 int i, out1_complete, out2_complete;
241
242 /* do we need to ramp at all ? */
243 if (out1->ramp == WM8350_RAMP_NONE && out2->ramp == WM8350_RAMP_NONE)
244 return;
245
246 /* PGA volumes have 6 bits of resolution to ramp */
247 for (i = 0; i <= 63; i++) {
248 out1_complete = 1, out2_complete = 1;
249 if (out1->ramp != WM8350_RAMP_NONE)
250 out1_complete = wm8350_out1_ramp_step(codec);
251 if (out2->ramp != WM8350_RAMP_NONE)
252 out2_complete = wm8350_out2_ramp_step(codec);
253
254 /* ramp finished ? */
255 if (out1_complete && out2_complete)
256 break;
257
258 /* we need to delay longer on the up ramp */
259 if (out1->ramp == WM8350_RAMP_UP ||
260 out2->ramp == WM8350_RAMP_UP) {
261 /* delay is longer over 0dB as increases are larger */
262 if (i >= WM8350_OUTn_0dB)
263 schedule_timeout_interruptible(msecs_to_jiffies
264 (2));
265 else
266 schedule_timeout_interruptible(msecs_to_jiffies
267 (1));
268 } else
269 udelay(50); /* doesn't matter if we delay longer */
270 }
271
272 out1->ramp = WM8350_RAMP_NONE;
273 out2->ramp = WM8350_RAMP_NONE;
274 }
275
276 /*
277 * WM8350 Controls
278 */
279
280 static int pga_event(struct snd_soc_dapm_widget *w,
281 struct snd_kcontrol *kcontrol, int event)
282 {
283 struct snd_soc_codec *codec = w->codec;
284 struct wm8350_data *wm8350_data = snd_soc_codec_get_drvdata(codec);
285 struct wm8350_output *out;
286
287 switch (w->shift) {
288 case 0:
289 case 1:
290 out = &wm8350_data->out1;
291 break;
292 case 2:
293 case 3:
294 out = &wm8350_data->out2;
295 break;
296
297 default:
298 BUG();
299 return -1;
300 }
301
302 switch (event) {
303 case SND_SOC_DAPM_POST_PMU:
304 out->ramp = WM8350_RAMP_UP;
305 out->active = 1;
306
307 if (!delayed_work_pending(&codec->dapm.delayed_work))
308 schedule_delayed_work(&codec->dapm.delayed_work,
309 msecs_to_jiffies(1));
310 break;
311
312 case SND_SOC_DAPM_PRE_PMD:
313 out->ramp = WM8350_RAMP_DOWN;
314 out->active = 0;
315
316 if (!delayed_work_pending(&codec->dapm.delayed_work))
317 schedule_delayed_work(&codec->dapm.delayed_work,
318 msecs_to_jiffies(1));
319 break;
320 }
321
322 return 0;
323 }
324
325 static int wm8350_put_volsw_2r_vu(struct snd_kcontrol *kcontrol,
326 struct snd_ctl_elem_value *ucontrol)
327 {
328 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
329 struct wm8350_data *wm8350_priv = snd_soc_codec_get_drvdata(codec);
330 struct wm8350_output *out = NULL;
331 struct soc_mixer_control *mc =
332 (struct soc_mixer_control *)kcontrol->private_value;
333 int ret;
334 unsigned int reg = mc->reg;
335 u16 val;
336
337 /* For OUT1 and OUT2 we shadow the values and only actually write
338 * them out when active in order to ensure the amplifier comes on
339 * as quietly as possible. */
340 switch (reg) {
341 case WM8350_LOUT1_VOLUME:
342 out = &wm8350_priv->out1;
343 break;
344 case WM8350_LOUT2_VOLUME:
345 out = &wm8350_priv->out2;
346 break;
347 default:
348 break;
349 }
350
351 if (out) {
352 out->left_vol = ucontrol->value.integer.value[0];
353 out->right_vol = ucontrol->value.integer.value[1];
354 if (!out->active)
355 return 1;
356 }
357
358 ret = snd_soc_put_volsw(kcontrol, ucontrol);
359 if (ret < 0)
360 return ret;
361
362 /* now hit the volume update bits (always bit 8) */
363 val = wm8350_codec_read(codec, reg);
364 wm8350_codec_write(codec, reg, val | WM8350_OUT1_VU);
365 return 1;
366 }
367
368 static int wm8350_get_volsw_2r(struct snd_kcontrol *kcontrol,
369 struct snd_ctl_elem_value *ucontrol)
370 {
371 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
372 struct wm8350_data *wm8350_priv = snd_soc_codec_get_drvdata(codec);
373 struct wm8350_output *out1 = &wm8350_priv->out1;
374 struct wm8350_output *out2 = &wm8350_priv->out2;
375 struct soc_mixer_control *mc =
376 (struct soc_mixer_control *)kcontrol->private_value;
377 unsigned int reg = mc->reg;
378
379 /* If these are cached registers use the cache */
380 switch (reg) {
381 case WM8350_LOUT1_VOLUME:
382 ucontrol->value.integer.value[0] = out1->left_vol;
383 ucontrol->value.integer.value[1] = out1->right_vol;
384 return 0;
385
386 case WM8350_LOUT2_VOLUME:
387 ucontrol->value.integer.value[0] = out2->left_vol;
388 ucontrol->value.integer.value[1] = out2->right_vol;
389 return 0;
390
391 default:
392 break;
393 }
394
395 return snd_soc_get_volsw(kcontrol, ucontrol);
396 }
397
398 static const char *wm8350_deemp[] = { "None", "32kHz", "44.1kHz", "48kHz" };
399 static const char *wm8350_pol[] = { "Normal", "Inv R", "Inv L", "Inv L & R" };
400 static const char *wm8350_dacmutem[] = { "Normal", "Soft" };
401 static const char *wm8350_dacmutes[] = { "Fast", "Slow" };
402 static const char *wm8350_adcfilter[] = { "None", "High Pass" };
403 static const char *wm8350_adchp[] = { "44.1kHz", "8kHz", "16kHz", "32kHz" };
404 static const char *wm8350_lr[] = { "Left", "Right" };
405
406 static const struct soc_enum wm8350_enum[] = {
407 SOC_ENUM_SINGLE(WM8350_DAC_CONTROL, 4, 4, wm8350_deemp),
408 SOC_ENUM_SINGLE(WM8350_DAC_CONTROL, 0, 4, wm8350_pol),
409 SOC_ENUM_SINGLE(WM8350_DAC_MUTE_VOLUME, 14, 2, wm8350_dacmutem),
410 SOC_ENUM_SINGLE(WM8350_DAC_MUTE_VOLUME, 13, 2, wm8350_dacmutes),
411 SOC_ENUM_SINGLE(WM8350_ADC_CONTROL, 15, 2, wm8350_adcfilter),
412 SOC_ENUM_SINGLE(WM8350_ADC_CONTROL, 8, 4, wm8350_adchp),
413 SOC_ENUM_SINGLE(WM8350_ADC_CONTROL, 0, 4, wm8350_pol),
414 SOC_ENUM_SINGLE(WM8350_INPUT_MIXER_VOLUME, 15, 2, wm8350_lr),
415 };
416
417 static DECLARE_TLV_DB_SCALE(pre_amp_tlv, -1200, 3525, 0);
418 static DECLARE_TLV_DB_SCALE(out_pga_tlv, -5700, 600, 0);
419 static DECLARE_TLV_DB_SCALE(dac_pcm_tlv, -7163, 36, 1);
420 static DECLARE_TLV_DB_SCALE(adc_pcm_tlv, -12700, 50, 1);
421 static DECLARE_TLV_DB_SCALE(out_mix_tlv, -1500, 300, 1);
422
423 static const unsigned int capture_sd_tlv[] = {
424 TLV_DB_RANGE_HEAD(2),
425 0, 12, TLV_DB_SCALE_ITEM(-3600, 300, 1),
426 13, 15, TLV_DB_SCALE_ITEM(0, 0, 0),
427 };
428
429 static const struct snd_kcontrol_new wm8350_snd_controls[] = {
430 SOC_ENUM("Playback Deemphasis", wm8350_enum[0]),
431 SOC_ENUM("Playback DAC Inversion", wm8350_enum[1]),
432 SOC_DOUBLE_R_EXT_TLV("Playback PCM Volume",
433 WM8350_DAC_DIGITAL_VOLUME_L,
434 WM8350_DAC_DIGITAL_VOLUME_R,
435 0, 255, 0, wm8350_get_volsw_2r,
436 wm8350_put_volsw_2r_vu, dac_pcm_tlv),
437 SOC_ENUM("Playback PCM Mute Function", wm8350_enum[2]),
438 SOC_ENUM("Playback PCM Mute Speed", wm8350_enum[3]),
439 SOC_ENUM("Capture PCM Filter", wm8350_enum[4]),
440 SOC_ENUM("Capture PCM HP Filter", wm8350_enum[5]),
441 SOC_ENUM("Capture ADC Inversion", wm8350_enum[6]),
442 SOC_DOUBLE_R_EXT_TLV("Capture PCM Volume",
443 WM8350_ADC_DIGITAL_VOLUME_L,
444 WM8350_ADC_DIGITAL_VOLUME_R,
445 0, 255, 0, wm8350_get_volsw_2r,
446 wm8350_put_volsw_2r_vu, adc_pcm_tlv),
447 SOC_DOUBLE_TLV("Capture Sidetone Volume",
448 WM8350_ADC_DIVIDER,
449 8, 4, 15, 1, capture_sd_tlv),
450 SOC_DOUBLE_R_EXT_TLV("Capture Volume",
451 WM8350_LEFT_INPUT_VOLUME,
452 WM8350_RIGHT_INPUT_VOLUME,
453 2, 63, 0, wm8350_get_volsw_2r,
454 wm8350_put_volsw_2r_vu, pre_amp_tlv),
455 SOC_DOUBLE_R("Capture ZC Switch",
456 WM8350_LEFT_INPUT_VOLUME,
457 WM8350_RIGHT_INPUT_VOLUME, 13, 1, 0),
458 SOC_SINGLE_TLV("Left Input Left Sidetone Volume",
459 WM8350_OUTPUT_LEFT_MIXER_VOLUME, 1, 7, 0, out_mix_tlv),
460 SOC_SINGLE_TLV("Left Input Right Sidetone Volume",
461 WM8350_OUTPUT_LEFT_MIXER_VOLUME,
462 5, 7, 0, out_mix_tlv),
463 SOC_SINGLE_TLV("Left Input Bypass Volume",
464 WM8350_OUTPUT_LEFT_MIXER_VOLUME,
465 9, 7, 0, out_mix_tlv),
466 SOC_SINGLE_TLV("Right Input Left Sidetone Volume",
467 WM8350_OUTPUT_RIGHT_MIXER_VOLUME,
468 1, 7, 0, out_mix_tlv),
469 SOC_SINGLE_TLV("Right Input Right Sidetone Volume",
470 WM8350_OUTPUT_RIGHT_MIXER_VOLUME,
471 5, 7, 0, out_mix_tlv),
472 SOC_SINGLE_TLV("Right Input Bypass Volume",
473 WM8350_OUTPUT_RIGHT_MIXER_VOLUME,
474 13, 7, 0, out_mix_tlv),
475 SOC_SINGLE("Left Input Mixer +20dB Switch",
476 WM8350_INPUT_MIXER_VOLUME_L, 0, 1, 0),
477 SOC_SINGLE("Right Input Mixer +20dB Switch",
478 WM8350_INPUT_MIXER_VOLUME_R, 0, 1, 0),
479 SOC_SINGLE_TLV("Out4 Capture Volume",
480 WM8350_INPUT_MIXER_VOLUME,
481 1, 7, 0, out_mix_tlv),
482 SOC_DOUBLE_R_EXT_TLV("Out1 Playback Volume",
483 WM8350_LOUT1_VOLUME,
484 WM8350_ROUT1_VOLUME,
485 2, 63, 0, wm8350_get_volsw_2r,
486 wm8350_put_volsw_2r_vu, out_pga_tlv),
487 SOC_DOUBLE_R("Out1 Playback ZC Switch",
488 WM8350_LOUT1_VOLUME,
489 WM8350_ROUT1_VOLUME, 13, 1, 0),
490 SOC_DOUBLE_R_EXT_TLV("Out2 Playback Volume",
491 WM8350_LOUT2_VOLUME,
492 WM8350_ROUT2_VOLUME,
493 2, 63, 0, wm8350_get_volsw_2r,
494 wm8350_put_volsw_2r_vu, out_pga_tlv),
495 SOC_DOUBLE_R("Out2 Playback ZC Switch", WM8350_LOUT2_VOLUME,
496 WM8350_ROUT2_VOLUME, 13, 1, 0),
497 SOC_SINGLE("Out2 Right Invert Switch", WM8350_ROUT2_VOLUME, 10, 1, 0),
498 SOC_SINGLE_TLV("Out2 Beep Volume", WM8350_BEEP_VOLUME,
499 5, 7, 0, out_mix_tlv),
500
501 SOC_DOUBLE_R("Out1 Playback Switch",
502 WM8350_LOUT1_VOLUME,
503 WM8350_ROUT1_VOLUME,
504 14, 1, 1),
505 SOC_DOUBLE_R("Out2 Playback Switch",
506 WM8350_LOUT2_VOLUME,
507 WM8350_ROUT2_VOLUME,
508 14, 1, 1),
509 };
510
511 /*
512 * DAPM Controls
513 */
514
515 /* Left Playback Mixer */
516 static const struct snd_kcontrol_new wm8350_left_play_mixer_controls[] = {
517 SOC_DAPM_SINGLE("Playback Switch",
518 WM8350_LEFT_MIXER_CONTROL, 11, 1, 0),
519 SOC_DAPM_SINGLE("Left Bypass Switch",
520 WM8350_LEFT_MIXER_CONTROL, 2, 1, 0),
521 SOC_DAPM_SINGLE("Right Playback Switch",
522 WM8350_LEFT_MIXER_CONTROL, 12, 1, 0),
523 SOC_DAPM_SINGLE("Left Sidetone Switch",
524 WM8350_LEFT_MIXER_CONTROL, 0, 1, 0),
525 SOC_DAPM_SINGLE("Right Sidetone Switch",
526 WM8350_LEFT_MIXER_CONTROL, 1, 1, 0),
527 };
528
529 /* Right Playback Mixer */
530 static const struct snd_kcontrol_new wm8350_right_play_mixer_controls[] = {
531 SOC_DAPM_SINGLE("Playback Switch",
532 WM8350_RIGHT_MIXER_CONTROL, 12, 1, 0),
533 SOC_DAPM_SINGLE("Right Bypass Switch",
534 WM8350_RIGHT_MIXER_CONTROL, 3, 1, 0),
535 SOC_DAPM_SINGLE("Left Playback Switch",
536 WM8350_RIGHT_MIXER_CONTROL, 11, 1, 0),
537 SOC_DAPM_SINGLE("Left Sidetone Switch",
538 WM8350_RIGHT_MIXER_CONTROL, 0, 1, 0),
539 SOC_DAPM_SINGLE("Right Sidetone Switch",
540 WM8350_RIGHT_MIXER_CONTROL, 1, 1, 0),
541 };
542
543 /* Out4 Mixer */
544 static const struct snd_kcontrol_new wm8350_out4_mixer_controls[] = {
545 SOC_DAPM_SINGLE("Right Playback Switch",
546 WM8350_OUT4_MIXER_CONTROL, 12, 1, 0),
547 SOC_DAPM_SINGLE("Left Playback Switch",
548 WM8350_OUT4_MIXER_CONTROL, 11, 1, 0),
549 SOC_DAPM_SINGLE("Right Capture Switch",
550 WM8350_OUT4_MIXER_CONTROL, 9, 1, 0),
551 SOC_DAPM_SINGLE("Out3 Playback Switch",
552 WM8350_OUT4_MIXER_CONTROL, 2, 1, 0),
553 SOC_DAPM_SINGLE("Right Mixer Switch",
554 WM8350_OUT4_MIXER_CONTROL, 1, 1, 0),
555 SOC_DAPM_SINGLE("Left Mixer Switch",
556 WM8350_OUT4_MIXER_CONTROL, 0, 1, 0),
557 };
558
559 /* Out3 Mixer */
560 static const struct snd_kcontrol_new wm8350_out3_mixer_controls[] = {
561 SOC_DAPM_SINGLE("Left Playback Switch",
562 WM8350_OUT3_MIXER_CONTROL, 11, 1, 0),
563 SOC_DAPM_SINGLE("Left Capture Switch",
564 WM8350_OUT3_MIXER_CONTROL, 8, 1, 0),
565 SOC_DAPM_SINGLE("Out4 Playback Switch",
566 WM8350_OUT3_MIXER_CONTROL, 3, 1, 0),
567 SOC_DAPM_SINGLE("Left Mixer Switch",
568 WM8350_OUT3_MIXER_CONTROL, 0, 1, 0),
569 };
570
571 /* Left Input Mixer */
572 static const struct snd_kcontrol_new wm8350_left_capt_mixer_controls[] = {
573 SOC_DAPM_SINGLE_TLV("L2 Capture Volume",
574 WM8350_INPUT_MIXER_VOLUME_L, 1, 7, 0, out_mix_tlv),
575 SOC_DAPM_SINGLE_TLV("L3 Capture Volume",
576 WM8350_INPUT_MIXER_VOLUME_L, 9, 7, 0, out_mix_tlv),
577 SOC_DAPM_SINGLE("PGA Capture Switch",
578 WM8350_LEFT_INPUT_VOLUME, 14, 1, 1),
579 };
580
581 /* Right Input Mixer */
582 static const struct snd_kcontrol_new wm8350_right_capt_mixer_controls[] = {
583 SOC_DAPM_SINGLE_TLV("L2 Capture Volume",
584 WM8350_INPUT_MIXER_VOLUME_R, 5, 7, 0, out_mix_tlv),
585 SOC_DAPM_SINGLE_TLV("L3 Capture Volume",
586 WM8350_INPUT_MIXER_VOLUME_R, 13, 7, 0, out_mix_tlv),
587 SOC_DAPM_SINGLE("PGA Capture Switch",
588 WM8350_RIGHT_INPUT_VOLUME, 14, 1, 1),
589 };
590
591 /* Left Mic Mixer */
592 static const struct snd_kcontrol_new wm8350_left_mic_mixer_controls[] = {
593 SOC_DAPM_SINGLE("INN Capture Switch", WM8350_INPUT_CONTROL, 1, 1, 0),
594 SOC_DAPM_SINGLE("INP Capture Switch", WM8350_INPUT_CONTROL, 0, 1, 0),
595 SOC_DAPM_SINGLE("IN2 Capture Switch", WM8350_INPUT_CONTROL, 2, 1, 0),
596 };
597
598 /* Right Mic Mixer */
599 static const struct snd_kcontrol_new wm8350_right_mic_mixer_controls[] = {
600 SOC_DAPM_SINGLE("INN Capture Switch", WM8350_INPUT_CONTROL, 9, 1, 0),
601 SOC_DAPM_SINGLE("INP Capture Switch", WM8350_INPUT_CONTROL, 8, 1, 0),
602 SOC_DAPM_SINGLE("IN2 Capture Switch", WM8350_INPUT_CONTROL, 10, 1, 0),
603 };
604
605 /* Beep Switch */
606 static const struct snd_kcontrol_new wm8350_beep_switch_controls =
607 SOC_DAPM_SINGLE("Switch", WM8350_BEEP_VOLUME, 15, 1, 1);
608
609 /* Out4 Capture Mux */
610 static const struct snd_kcontrol_new wm8350_out4_capture_controls =
611 SOC_DAPM_ENUM("Route", wm8350_enum[7]);
612
613 static const struct snd_soc_dapm_widget wm8350_dapm_widgets[] = {
614
615 SND_SOC_DAPM_PGA("IN3R PGA", WM8350_POWER_MGMT_2, 11, 0, NULL, 0),
616 SND_SOC_DAPM_PGA("IN3L PGA", WM8350_POWER_MGMT_2, 10, 0, NULL, 0),
617 SND_SOC_DAPM_PGA_E("Right Out2 PGA", WM8350_POWER_MGMT_3, 3, 0, NULL,
618 0, pga_event,
619 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
620 SND_SOC_DAPM_PGA_E("Left Out2 PGA", WM8350_POWER_MGMT_3, 2, 0, NULL, 0,
621 pga_event,
622 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
623 SND_SOC_DAPM_PGA_E("Right Out1 PGA", WM8350_POWER_MGMT_3, 1, 0, NULL,
624 0, pga_event,
625 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
626 SND_SOC_DAPM_PGA_E("Left Out1 PGA", WM8350_POWER_MGMT_3, 0, 0, NULL, 0,
627 pga_event,
628 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
629
630 SND_SOC_DAPM_MIXER("Right Capture Mixer", WM8350_POWER_MGMT_2,
631 7, 0, &wm8350_right_capt_mixer_controls[0],
632 ARRAY_SIZE(wm8350_right_capt_mixer_controls)),
633
634 SND_SOC_DAPM_MIXER("Left Capture Mixer", WM8350_POWER_MGMT_2,
635 6, 0, &wm8350_left_capt_mixer_controls[0],
636 ARRAY_SIZE(wm8350_left_capt_mixer_controls)),
637
638 SND_SOC_DAPM_MIXER("Out4 Mixer", WM8350_POWER_MGMT_2, 5, 0,
639 &wm8350_out4_mixer_controls[0],
640 ARRAY_SIZE(wm8350_out4_mixer_controls)),
641
642 SND_SOC_DAPM_MIXER("Out3 Mixer", WM8350_POWER_MGMT_2, 4, 0,
643 &wm8350_out3_mixer_controls[0],
644 ARRAY_SIZE(wm8350_out3_mixer_controls)),
645
646 SND_SOC_DAPM_MIXER("Right Playback Mixer", WM8350_POWER_MGMT_2, 1, 0,
647 &wm8350_right_play_mixer_controls[0],
648 ARRAY_SIZE(wm8350_right_play_mixer_controls)),
649
650 SND_SOC_DAPM_MIXER("Left Playback Mixer", WM8350_POWER_MGMT_2, 0, 0,
651 &wm8350_left_play_mixer_controls[0],
652 ARRAY_SIZE(wm8350_left_play_mixer_controls)),
653
654 SND_SOC_DAPM_MIXER("Left Mic Mixer", WM8350_POWER_MGMT_2, 8, 0,
655 &wm8350_left_mic_mixer_controls[0],
656 ARRAY_SIZE(wm8350_left_mic_mixer_controls)),
657
658 SND_SOC_DAPM_MIXER("Right Mic Mixer", WM8350_POWER_MGMT_2, 9, 0,
659 &wm8350_right_mic_mixer_controls[0],
660 ARRAY_SIZE(wm8350_right_mic_mixer_controls)),
661
662 /* virtual mixer for Beep and Out2R */
663 SND_SOC_DAPM_MIXER("Out2 Mixer", SND_SOC_NOPM, 0, 0, NULL, 0),
664
665 SND_SOC_DAPM_SWITCH("Beep", WM8350_POWER_MGMT_3, 7, 0,
666 &wm8350_beep_switch_controls),
667
668 SND_SOC_DAPM_ADC("Right ADC", "Right Capture",
669 WM8350_POWER_MGMT_4, 3, 0),
670 SND_SOC_DAPM_ADC("Left ADC", "Left Capture",
671 WM8350_POWER_MGMT_4, 2, 0),
672 SND_SOC_DAPM_DAC("Right DAC", "Right Playback",
673 WM8350_POWER_MGMT_4, 5, 0),
674 SND_SOC_DAPM_DAC("Left DAC", "Left Playback",
675 WM8350_POWER_MGMT_4, 4, 0),
676
677 SND_SOC_DAPM_MICBIAS("Mic Bias", WM8350_POWER_MGMT_1, 4, 0),
678
679 SND_SOC_DAPM_MUX("Out4 Capture Channel", SND_SOC_NOPM, 0, 0,
680 &wm8350_out4_capture_controls),
681
682 SND_SOC_DAPM_OUTPUT("OUT1R"),
683 SND_SOC_DAPM_OUTPUT("OUT1L"),
684 SND_SOC_DAPM_OUTPUT("OUT2R"),
685 SND_SOC_DAPM_OUTPUT("OUT2L"),
686 SND_SOC_DAPM_OUTPUT("OUT3"),
687 SND_SOC_DAPM_OUTPUT("OUT4"),
688
689 SND_SOC_DAPM_INPUT("IN1RN"),
690 SND_SOC_DAPM_INPUT("IN1RP"),
691 SND_SOC_DAPM_INPUT("IN2R"),
692 SND_SOC_DAPM_INPUT("IN1LP"),
693 SND_SOC_DAPM_INPUT("IN1LN"),
694 SND_SOC_DAPM_INPUT("IN2L"),
695 SND_SOC_DAPM_INPUT("IN3R"),
696 SND_SOC_DAPM_INPUT("IN3L"),
697 };
698
699 static const struct snd_soc_dapm_route audio_map[] = {
700
701 /* left playback mixer */
702 {"Left Playback Mixer", "Playback Switch", "Left DAC"},
703 {"Left Playback Mixer", "Left Bypass Switch", "IN3L PGA"},
704 {"Left Playback Mixer", "Right Playback Switch", "Right DAC"},
705 {"Left Playback Mixer", "Left Sidetone Switch", "Left Mic Mixer"},
706 {"Left Playback Mixer", "Right Sidetone Switch", "Right Mic Mixer"},
707
708 /* right playback mixer */
709 {"Right Playback Mixer", "Playback Switch", "Right DAC"},
710 {"Right Playback Mixer", "Right Bypass Switch", "IN3R PGA"},
711 {"Right Playback Mixer", "Left Playback Switch", "Left DAC"},
712 {"Right Playback Mixer", "Left Sidetone Switch", "Left Mic Mixer"},
713 {"Right Playback Mixer", "Right Sidetone Switch", "Right Mic Mixer"},
714
715 /* out4 playback mixer */
716 {"Out4 Mixer", "Right Playback Switch", "Right DAC"},
717 {"Out4 Mixer", "Left Playback Switch", "Left DAC"},
718 {"Out4 Mixer", "Right Capture Switch", "Right Capture Mixer"},
719 {"Out4 Mixer", "Out3 Playback Switch", "Out3 Mixer"},
720 {"Out4 Mixer", "Right Mixer Switch", "Right Playback Mixer"},
721 {"Out4 Mixer", "Left Mixer Switch", "Left Playback Mixer"},
722 {"OUT4", NULL, "Out4 Mixer"},
723
724 /* out3 playback mixer */
725 {"Out3 Mixer", "Left Playback Switch", "Left DAC"},
726 {"Out3 Mixer", "Left Capture Switch", "Left Capture Mixer"},
727 {"Out3 Mixer", "Left Mixer Switch", "Left Playback Mixer"},
728 {"Out3 Mixer", "Out4 Playback Switch", "Out4 Mixer"},
729 {"OUT3", NULL, "Out3 Mixer"},
730
731 /* out2 */
732 {"Right Out2 PGA", NULL, "Right Playback Mixer"},
733 {"Left Out2 PGA", NULL, "Left Playback Mixer"},
734 {"OUT2L", NULL, "Left Out2 PGA"},
735 {"OUT2R", NULL, "Right Out2 PGA"},
736
737 /* out1 */
738 {"Right Out1 PGA", NULL, "Right Playback Mixer"},
739 {"Left Out1 PGA", NULL, "Left Playback Mixer"},
740 {"OUT1L", NULL, "Left Out1 PGA"},
741 {"OUT1R", NULL, "Right Out1 PGA"},
742
743 /* ADCs */
744 {"Left ADC", NULL, "Left Capture Mixer"},
745 {"Right ADC", NULL, "Right Capture Mixer"},
746
747 /* Left capture mixer */
748 {"Left Capture Mixer", "L2 Capture Volume", "IN2L"},
749 {"Left Capture Mixer", "L3 Capture Volume", "IN3L PGA"},
750 {"Left Capture Mixer", "PGA Capture Switch", "Left Mic Mixer"},
751 {"Left Capture Mixer", NULL, "Out4 Capture Channel"},
752
753 /* Right capture mixer */
754 {"Right Capture Mixer", "L2 Capture Volume", "IN2R"},
755 {"Right Capture Mixer", "L3 Capture Volume", "IN3R PGA"},
756 {"Right Capture Mixer", "PGA Capture Switch", "Right Mic Mixer"},
757 {"Right Capture Mixer", NULL, "Out4 Capture Channel"},
758
759 /* L3 Inputs */
760 {"IN3L PGA", NULL, "IN3L"},
761 {"IN3R PGA", NULL, "IN3R"},
762
763 /* Left Mic mixer */
764 {"Left Mic Mixer", "INN Capture Switch", "IN1LN"},
765 {"Left Mic Mixer", "INP Capture Switch", "IN1LP"},
766 {"Left Mic Mixer", "IN2 Capture Switch", "IN2L"},
767
768 /* Right Mic mixer */
769 {"Right Mic Mixer", "INN Capture Switch", "IN1RN"},
770 {"Right Mic Mixer", "INP Capture Switch", "IN1RP"},
771 {"Right Mic Mixer", "IN2 Capture Switch", "IN2R"},
772
773 /* out 4 capture */
774 {"Out4 Capture Channel", NULL, "Out4 Mixer"},
775
776 /* Beep */
777 {"Beep", NULL, "IN3R PGA"},
778 };
779
780 static int wm8350_add_widgets(struct snd_soc_codec *codec)
781 {
782 struct snd_soc_dapm_context *dapm = &codec->dapm;
783 int ret;
784
785 ret = snd_soc_dapm_new_controls(dapm,
786 wm8350_dapm_widgets,
787 ARRAY_SIZE(wm8350_dapm_widgets));
788 if (ret != 0) {
789 dev_err(codec->dev, "dapm control register failed\n");
790 return ret;
791 }
792
793 /* set up audio paths */
794 ret = snd_soc_dapm_add_routes(dapm, audio_map, ARRAY_SIZE(audio_map));
795 if (ret != 0) {
796 dev_err(codec->dev, "DAPM route register failed\n");
797 return ret;
798 }
799
800 return 0;
801 }
802
803 static int wm8350_set_dai_sysclk(struct snd_soc_dai *codec_dai,
804 int clk_id, unsigned int freq, int dir)
805 {
806 struct snd_soc_codec *codec = codec_dai->codec;
807 struct wm8350 *wm8350 = codec->control_data;
808 u16 fll_4;
809
810 switch (clk_id) {
811 case WM8350_MCLK_SEL_MCLK:
812 wm8350_clear_bits(wm8350, WM8350_CLOCK_CONTROL_1,
813 WM8350_MCLK_SEL);
814 break;
815 case WM8350_MCLK_SEL_PLL_MCLK:
816 case WM8350_MCLK_SEL_PLL_DAC:
817 case WM8350_MCLK_SEL_PLL_ADC:
818 case WM8350_MCLK_SEL_PLL_32K:
819 wm8350_set_bits(wm8350, WM8350_CLOCK_CONTROL_1,
820 WM8350_MCLK_SEL);
821 fll_4 = wm8350_codec_read(codec, WM8350_FLL_CONTROL_4) &
822 ~WM8350_FLL_CLK_SRC_MASK;
823 wm8350_codec_write(codec, WM8350_FLL_CONTROL_4, fll_4 | clk_id);
824 break;
825 }
826
827 /* MCLK direction */
828 if (dir == SND_SOC_CLOCK_OUT)
829 wm8350_set_bits(wm8350, WM8350_CLOCK_CONTROL_2,
830 WM8350_MCLK_DIR);
831 else
832 wm8350_clear_bits(wm8350, WM8350_CLOCK_CONTROL_2,
833 WM8350_MCLK_DIR);
834
835 return 0;
836 }
837
838 static int wm8350_set_clkdiv(struct snd_soc_dai *codec_dai, int div_id, int div)
839 {
840 struct snd_soc_codec *codec = codec_dai->codec;
841 u16 val;
842
843 switch (div_id) {
844 case WM8350_ADC_CLKDIV:
845 val = wm8350_codec_read(codec, WM8350_ADC_DIVIDER) &
846 ~WM8350_ADC_CLKDIV_MASK;
847 wm8350_codec_write(codec, WM8350_ADC_DIVIDER, val | div);
848 break;
849 case WM8350_DAC_CLKDIV:
850 val = wm8350_codec_read(codec, WM8350_DAC_CLOCK_CONTROL) &
851 ~WM8350_DAC_CLKDIV_MASK;
852 wm8350_codec_write(codec, WM8350_DAC_CLOCK_CONTROL, val | div);
853 break;
854 case WM8350_BCLK_CLKDIV:
855 val = wm8350_codec_read(codec, WM8350_CLOCK_CONTROL_1) &
856 ~WM8350_BCLK_DIV_MASK;
857 wm8350_codec_write(codec, WM8350_CLOCK_CONTROL_1, val | div);
858 break;
859 case WM8350_OPCLK_CLKDIV:
860 val = wm8350_codec_read(codec, WM8350_CLOCK_CONTROL_1) &
861 ~WM8350_OPCLK_DIV_MASK;
862 wm8350_codec_write(codec, WM8350_CLOCK_CONTROL_1, val | div);
863 break;
864 case WM8350_SYS_CLKDIV:
865 val = wm8350_codec_read(codec, WM8350_CLOCK_CONTROL_1) &
866 ~WM8350_MCLK_DIV_MASK;
867 wm8350_codec_write(codec, WM8350_CLOCK_CONTROL_1, val | div);
868 break;
869 case WM8350_DACLR_CLKDIV:
870 val = wm8350_codec_read(codec, WM8350_DAC_LR_RATE) &
871 ~WM8350_DACLRC_RATE_MASK;
872 wm8350_codec_write(codec, WM8350_DAC_LR_RATE, val | div);
873 break;
874 case WM8350_ADCLR_CLKDIV:
875 val = wm8350_codec_read(codec, WM8350_ADC_LR_RATE) &
876 ~WM8350_ADCLRC_RATE_MASK;
877 wm8350_codec_write(codec, WM8350_ADC_LR_RATE, val | div);
878 break;
879 default:
880 return -EINVAL;
881 }
882
883 return 0;
884 }
885
886 static int wm8350_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
887 {
888 struct snd_soc_codec *codec = codec_dai->codec;
889 u16 iface = wm8350_codec_read(codec, WM8350_AI_FORMATING) &
890 ~(WM8350_AIF_BCLK_INV | WM8350_AIF_LRCLK_INV | WM8350_AIF_FMT_MASK);
891 u16 master = wm8350_codec_read(codec, WM8350_AI_DAC_CONTROL) &
892 ~WM8350_BCLK_MSTR;
893 u16 dac_lrc = wm8350_codec_read(codec, WM8350_DAC_LR_RATE) &
894 ~WM8350_DACLRC_ENA;
895 u16 adc_lrc = wm8350_codec_read(codec, WM8350_ADC_LR_RATE) &
896 ~WM8350_ADCLRC_ENA;
897
898 /* set master/slave audio interface */
899 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
900 case SND_SOC_DAIFMT_CBM_CFM:
901 master |= WM8350_BCLK_MSTR;
902 dac_lrc |= WM8350_DACLRC_ENA;
903 adc_lrc |= WM8350_ADCLRC_ENA;
904 break;
905 case SND_SOC_DAIFMT_CBS_CFS:
906 break;
907 default:
908 return -EINVAL;
909 }
910
911 /* interface format */
912 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
913 case SND_SOC_DAIFMT_I2S:
914 iface |= 0x2 << 8;
915 break;
916 case SND_SOC_DAIFMT_RIGHT_J:
917 break;
918 case SND_SOC_DAIFMT_LEFT_J:
919 iface |= 0x1 << 8;
920 break;
921 case SND_SOC_DAIFMT_DSP_A:
922 iface |= 0x3 << 8;
923 break;
924 case SND_SOC_DAIFMT_DSP_B:
925 iface |= 0x3 << 8 | WM8350_AIF_LRCLK_INV;
926 break;
927 default:
928 return -EINVAL;
929 }
930
931 /* clock inversion */
932 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
933 case SND_SOC_DAIFMT_NB_NF:
934 break;
935 case SND_SOC_DAIFMT_IB_IF:
936 iface |= WM8350_AIF_LRCLK_INV | WM8350_AIF_BCLK_INV;
937 break;
938 case SND_SOC_DAIFMT_IB_NF:
939 iface |= WM8350_AIF_BCLK_INV;
940 break;
941 case SND_SOC_DAIFMT_NB_IF:
942 iface |= WM8350_AIF_LRCLK_INV;
943 break;
944 default:
945 return -EINVAL;
946 }
947
948 wm8350_codec_write(codec, WM8350_AI_FORMATING, iface);
949 wm8350_codec_write(codec, WM8350_AI_DAC_CONTROL, master);
950 wm8350_codec_write(codec, WM8350_DAC_LR_RATE, dac_lrc);
951 wm8350_codec_write(codec, WM8350_ADC_LR_RATE, adc_lrc);
952 return 0;
953 }
954
955 static int wm8350_pcm_trigger(struct snd_pcm_substream *substream,
956 int cmd, struct snd_soc_dai *codec_dai)
957 {
958 struct snd_soc_codec *codec = codec_dai->codec;
959 int master = wm8350_codec_cache_read(codec, WM8350_AI_DAC_CONTROL) &
960 WM8350_BCLK_MSTR;
961 int enabled = 0;
962
963 /* Check that the DACs or ADCs are enabled since they are
964 * required for LRC in master mode. The DACs or ADCs need a
965 * valid audio path i.e. pin -> ADC or DAC -> pin before
966 * the LRC will be enabled in master mode. */
967 if (!master || cmd != SNDRV_PCM_TRIGGER_START)
968 return 0;
969
970 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
971 enabled = wm8350_codec_cache_read(codec, WM8350_POWER_MGMT_4) &
972 (WM8350_ADCR_ENA | WM8350_ADCL_ENA);
973 } else {
974 enabled = wm8350_codec_cache_read(codec, WM8350_POWER_MGMT_4) &
975 (WM8350_DACR_ENA | WM8350_DACL_ENA);
976 }
977
978 if (!enabled) {
979 dev_err(codec->dev,
980 "%s: invalid audio path - no clocks available\n",
981 __func__);
982 return -EINVAL;
983 }
984 return 0;
985 }
986
987 static int wm8350_pcm_hw_params(struct snd_pcm_substream *substream,
988 struct snd_pcm_hw_params *params,
989 struct snd_soc_dai *codec_dai)
990 {
991 struct snd_soc_codec *codec = codec_dai->codec;
992 struct wm8350 *wm8350 = codec->control_data;
993 u16 iface = wm8350_codec_read(codec, WM8350_AI_FORMATING) &
994 ~WM8350_AIF_WL_MASK;
995
996 /* bit size */
997 switch (params_format(params)) {
998 case SNDRV_PCM_FORMAT_S16_LE:
999 break;
1000 case SNDRV_PCM_FORMAT_S20_3LE:
1001 iface |= 0x1 << 10;
1002 break;
1003 case SNDRV_PCM_FORMAT_S24_LE:
1004 iface |= 0x2 << 10;
1005 break;
1006 case SNDRV_PCM_FORMAT_S32_LE:
1007 iface |= 0x3 << 10;
1008 break;
1009 }
1010
1011 wm8350_codec_write(codec, WM8350_AI_FORMATING, iface);
1012
1013 /* The sloping stopband filter is recommended for use with
1014 * lower sample rates to improve performance.
1015 */
1016 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1017 if (params_rate(params) < 24000)
1018 wm8350_set_bits(wm8350, WM8350_DAC_MUTE_VOLUME,
1019 WM8350_DAC_SB_FILT);
1020 else
1021 wm8350_clear_bits(wm8350, WM8350_DAC_MUTE_VOLUME,
1022 WM8350_DAC_SB_FILT);
1023 }
1024
1025 return 0;
1026 }
1027
1028 static int wm8350_mute(struct snd_soc_dai *dai, int mute)
1029 {
1030 struct snd_soc_codec *codec = dai->codec;
1031 struct wm8350 *wm8350 = codec->control_data;
1032
1033 if (mute)
1034 wm8350_set_bits(wm8350, WM8350_DAC_MUTE, WM8350_DAC_MUTE_ENA);
1035 else
1036 wm8350_clear_bits(wm8350, WM8350_DAC_MUTE, WM8350_DAC_MUTE_ENA);
1037 return 0;
1038 }
1039
1040 /* FLL divisors */
1041 struct _fll_div {
1042 int div; /* FLL_OUTDIV */
1043 int n;
1044 int k;
1045 int ratio; /* FLL_FRATIO */
1046 };
1047
1048 /* The size in bits of the fll divide multiplied by 10
1049 * to allow rounding later */
1050 #define FIXED_FLL_SIZE ((1 << 16) * 10)
1051
1052 static inline int fll_factors(struct _fll_div *fll_div, unsigned int input,
1053 unsigned int output)
1054 {
1055 u64 Kpart;
1056 unsigned int t1, t2, K, Nmod;
1057
1058 if (output >= 2815250 && output <= 3125000)
1059 fll_div->div = 0x4;
1060 else if (output >= 5625000 && output <= 6250000)
1061 fll_div->div = 0x3;
1062 else if (output >= 11250000 && output <= 12500000)
1063 fll_div->div = 0x2;
1064 else if (output >= 22500000 && output <= 25000000)
1065 fll_div->div = 0x1;
1066 else {
1067 printk(KERN_ERR "wm8350: fll freq %d out of range\n", output);
1068 return -EINVAL;
1069 }
1070
1071 if (input > 48000)
1072 fll_div->ratio = 1;
1073 else
1074 fll_div->ratio = 8;
1075
1076 t1 = output * (1 << (fll_div->div + 1));
1077 t2 = input * fll_div->ratio;
1078
1079 fll_div->n = t1 / t2;
1080 Nmod = t1 % t2;
1081
1082 if (Nmod) {
1083 Kpart = FIXED_FLL_SIZE * (long long)Nmod;
1084 do_div(Kpart, t2);
1085 K = Kpart & 0xFFFFFFFF;
1086
1087 /* Check if we need to round */
1088 if ((K % 10) >= 5)
1089 K += 5;
1090
1091 /* Move down to proper range now rounding is done */
1092 K /= 10;
1093 fll_div->k = K;
1094 } else
1095 fll_div->k = 0;
1096
1097 return 0;
1098 }
1099
1100 static int wm8350_set_fll(struct snd_soc_dai *codec_dai,
1101 int pll_id, int source, unsigned int freq_in,
1102 unsigned int freq_out)
1103 {
1104 struct snd_soc_codec *codec = codec_dai->codec;
1105 struct wm8350 *wm8350 = codec->control_data;
1106 struct wm8350_data *priv = snd_soc_codec_get_drvdata(codec);
1107 struct _fll_div fll_div;
1108 int ret = 0;
1109 u16 fll_1, fll_4;
1110
1111 if (freq_in == priv->fll_freq_in && freq_out == priv->fll_freq_out)
1112 return 0;
1113
1114 /* power down FLL - we need to do this for reconfiguration */
1115 wm8350_clear_bits(wm8350, WM8350_POWER_MGMT_4,
1116 WM8350_FLL_ENA | WM8350_FLL_OSC_ENA);
1117
1118 if (freq_out == 0 || freq_in == 0)
1119 return ret;
1120
1121 ret = fll_factors(&fll_div, freq_in, freq_out);
1122 if (ret < 0)
1123 return ret;
1124 dev_dbg(wm8350->dev,
1125 "FLL in %u FLL out %u N 0x%x K 0x%x div %d ratio %d",
1126 freq_in, freq_out, fll_div.n, fll_div.k, fll_div.div,
1127 fll_div.ratio);
1128
1129 /* set up N.K & dividers */
1130 fll_1 = wm8350_codec_read(codec, WM8350_FLL_CONTROL_1) &
1131 ~(WM8350_FLL_OUTDIV_MASK | WM8350_FLL_RSP_RATE_MASK | 0xc000);
1132 wm8350_codec_write(codec, WM8350_FLL_CONTROL_1,
1133 fll_1 | (fll_div.div << 8) | 0x50);
1134 wm8350_codec_write(codec, WM8350_FLL_CONTROL_2,
1135 (fll_div.ratio << 11) | (fll_div.
1136 n & WM8350_FLL_N_MASK));
1137 wm8350_codec_write(codec, WM8350_FLL_CONTROL_3, fll_div.k);
1138 fll_4 = wm8350_codec_read(codec, WM8350_FLL_CONTROL_4) &
1139 ~(WM8350_FLL_FRAC | WM8350_FLL_SLOW_LOCK_REF);
1140 wm8350_codec_write(codec, WM8350_FLL_CONTROL_4,
1141 fll_4 | (fll_div.k ? WM8350_FLL_FRAC : 0) |
1142 (fll_div.ratio == 8 ? WM8350_FLL_SLOW_LOCK_REF : 0));
1143
1144 /* power FLL on */
1145 wm8350_set_bits(wm8350, WM8350_POWER_MGMT_4, WM8350_FLL_OSC_ENA);
1146 wm8350_set_bits(wm8350, WM8350_POWER_MGMT_4, WM8350_FLL_ENA);
1147
1148 priv->fll_freq_out = freq_out;
1149 priv->fll_freq_in = freq_in;
1150
1151 return 0;
1152 }
1153
1154 static int wm8350_set_bias_level(struct snd_soc_codec *codec,
1155 enum snd_soc_bias_level level)
1156 {
1157 struct wm8350 *wm8350 = codec->control_data;
1158 struct wm8350_data *priv = snd_soc_codec_get_drvdata(codec);
1159 struct wm8350_audio_platform_data *platform =
1160 wm8350->codec.platform_data;
1161 u16 pm1;
1162 int ret;
1163
1164 switch (level) {
1165 case SND_SOC_BIAS_ON:
1166 pm1 = wm8350_reg_read(wm8350, WM8350_POWER_MGMT_1) &
1167 ~(WM8350_VMID_MASK | WM8350_CODEC_ISEL_MASK);
1168 wm8350_reg_write(wm8350, WM8350_POWER_MGMT_1,
1169 pm1 | WM8350_VMID_50K |
1170 platform->codec_current_on << 14);
1171 break;
1172
1173 case SND_SOC_BIAS_PREPARE:
1174 pm1 = wm8350_reg_read(wm8350, WM8350_POWER_MGMT_1);
1175 pm1 &= ~WM8350_VMID_MASK;
1176 wm8350_reg_write(wm8350, WM8350_POWER_MGMT_1,
1177 pm1 | WM8350_VMID_50K);
1178 break;
1179
1180 case SND_SOC_BIAS_STANDBY:
1181 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
1182 ret = regulator_bulk_enable(ARRAY_SIZE(priv->supplies),
1183 priv->supplies);
1184 if (ret != 0)
1185 return ret;
1186
1187 /* Enable the system clock */
1188 wm8350_set_bits(wm8350, WM8350_POWER_MGMT_4,
1189 WM8350_SYSCLK_ENA);
1190
1191 /* mute DAC & outputs */
1192 wm8350_set_bits(wm8350, WM8350_DAC_MUTE,
1193 WM8350_DAC_MUTE_ENA);
1194
1195 /* discharge cap memory */
1196 wm8350_reg_write(wm8350, WM8350_ANTI_POP_CONTROL,
1197 platform->dis_out1 |
1198 (platform->dis_out2 << 2) |
1199 (platform->dis_out3 << 4) |
1200 (platform->dis_out4 << 6));
1201
1202 /* wait for discharge */
1203 schedule_timeout_interruptible(msecs_to_jiffies
1204 (platform->
1205 cap_discharge_msecs));
1206
1207 /* enable antipop */
1208 wm8350_reg_write(wm8350, WM8350_ANTI_POP_CONTROL,
1209 (platform->vmid_s_curve << 8));
1210
1211 /* ramp up vmid */
1212 wm8350_reg_write(wm8350, WM8350_POWER_MGMT_1,
1213 (platform->
1214 codec_current_charge << 14) |
1215 WM8350_VMID_5K | WM8350_VMIDEN |
1216 WM8350_VBUFEN);
1217
1218 /* wait for vmid */
1219 schedule_timeout_interruptible(msecs_to_jiffies
1220 (platform->
1221 vmid_charge_msecs));
1222
1223 /* turn on vmid 300k */
1224 pm1 = wm8350_reg_read(wm8350, WM8350_POWER_MGMT_1) &
1225 ~(WM8350_VMID_MASK | WM8350_CODEC_ISEL_MASK);
1226 pm1 |= WM8350_VMID_300K |
1227 (platform->codec_current_standby << 14);
1228 wm8350_reg_write(wm8350, WM8350_POWER_MGMT_1,
1229 pm1);
1230
1231
1232 /* enable analogue bias */
1233 pm1 |= WM8350_BIASEN;
1234 wm8350_reg_write(wm8350, WM8350_POWER_MGMT_1, pm1);
1235
1236 /* disable antipop */
1237 wm8350_reg_write(wm8350, WM8350_ANTI_POP_CONTROL, 0);
1238
1239 } else {
1240 /* turn on vmid 300k and reduce current */
1241 pm1 = wm8350_reg_read(wm8350, WM8350_POWER_MGMT_1) &
1242 ~(WM8350_VMID_MASK | WM8350_CODEC_ISEL_MASK);
1243 wm8350_reg_write(wm8350, WM8350_POWER_MGMT_1,
1244 pm1 | WM8350_VMID_300K |
1245 (platform->
1246 codec_current_standby << 14));
1247
1248 }
1249 break;
1250
1251 case SND_SOC_BIAS_OFF:
1252
1253 /* mute DAC & enable outputs */
1254 wm8350_set_bits(wm8350, WM8350_DAC_MUTE, WM8350_DAC_MUTE_ENA);
1255
1256 wm8350_set_bits(wm8350, WM8350_POWER_MGMT_3,
1257 WM8350_OUT1L_ENA | WM8350_OUT1R_ENA |
1258 WM8350_OUT2L_ENA | WM8350_OUT2R_ENA);
1259
1260 /* enable anti pop S curve */
1261 wm8350_reg_write(wm8350, WM8350_ANTI_POP_CONTROL,
1262 (platform->vmid_s_curve << 8));
1263
1264 /* turn off vmid */
1265 pm1 = wm8350_reg_read(wm8350, WM8350_POWER_MGMT_1) &
1266 ~WM8350_VMIDEN;
1267 wm8350_reg_write(wm8350, WM8350_POWER_MGMT_1, pm1);
1268
1269 /* wait */
1270 schedule_timeout_interruptible(msecs_to_jiffies
1271 (platform->
1272 vmid_discharge_msecs));
1273
1274 wm8350_reg_write(wm8350, WM8350_ANTI_POP_CONTROL,
1275 (platform->vmid_s_curve << 8) |
1276 platform->dis_out1 |
1277 (platform->dis_out2 << 2) |
1278 (platform->dis_out3 << 4) |
1279 (platform->dis_out4 << 6));
1280
1281 /* turn off VBuf and drain */
1282 pm1 = wm8350_reg_read(wm8350, WM8350_POWER_MGMT_1) &
1283 ~(WM8350_VBUFEN | WM8350_VMID_MASK);
1284 wm8350_reg_write(wm8350, WM8350_POWER_MGMT_1,
1285 pm1 | WM8350_OUTPUT_DRAIN_EN);
1286
1287 /* wait */
1288 schedule_timeout_interruptible(msecs_to_jiffies
1289 (platform->drain_msecs));
1290
1291 pm1 &= ~WM8350_BIASEN;
1292 wm8350_reg_write(wm8350, WM8350_POWER_MGMT_1, pm1);
1293
1294 /* disable anti-pop */
1295 wm8350_reg_write(wm8350, WM8350_ANTI_POP_CONTROL, 0);
1296
1297 wm8350_clear_bits(wm8350, WM8350_LOUT1_VOLUME,
1298 WM8350_OUT1L_ENA);
1299 wm8350_clear_bits(wm8350, WM8350_ROUT1_VOLUME,
1300 WM8350_OUT1R_ENA);
1301 wm8350_clear_bits(wm8350, WM8350_LOUT2_VOLUME,
1302 WM8350_OUT2L_ENA);
1303 wm8350_clear_bits(wm8350, WM8350_ROUT2_VOLUME,
1304 WM8350_OUT2R_ENA);
1305
1306 /* disable clock gen */
1307 wm8350_clear_bits(wm8350, WM8350_POWER_MGMT_4,
1308 WM8350_SYSCLK_ENA);
1309
1310 regulator_bulk_disable(ARRAY_SIZE(priv->supplies),
1311 priv->supplies);
1312 break;
1313 }
1314 codec->dapm.bias_level = level;
1315 return 0;
1316 }
1317
1318 static int wm8350_suspend(struct snd_soc_codec *codec, pm_message_t state)
1319 {
1320 wm8350_set_bias_level(codec, SND_SOC_BIAS_OFF);
1321 return 0;
1322 }
1323
1324 static int wm8350_resume(struct snd_soc_codec *codec)
1325 {
1326 wm8350_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1327
1328 return 0;
1329 }
1330
1331 static void wm8350_hp_work(struct wm8350_data *priv,
1332 struct wm8350_jack_data *jack,
1333 u16 mask)
1334 {
1335 struct wm8350 *wm8350 = priv->codec.control_data;
1336 u16 reg;
1337 int report;
1338
1339 reg = wm8350_reg_read(wm8350, WM8350_JACK_PIN_STATUS);
1340 if (reg & mask)
1341 report = jack->report;
1342 else
1343 report = 0;
1344
1345 snd_soc_jack_report(jack->jack, report, jack->report);
1346
1347 }
1348
1349 static void wm8350_hpl_work(struct work_struct *work)
1350 {
1351 struct wm8350_data *priv =
1352 container_of(work, struct wm8350_data, hpl.work.work);
1353
1354 wm8350_hp_work(priv, &priv->hpl, WM8350_JACK_L_LVL);
1355 }
1356
1357 static void wm8350_hpr_work(struct work_struct *work)
1358 {
1359 struct wm8350_data *priv =
1360 container_of(work, struct wm8350_data, hpr.work.work);
1361
1362 wm8350_hp_work(priv, &priv->hpr, WM8350_JACK_R_LVL);
1363 }
1364
1365 static irqreturn_t wm8350_hp_jack_handler(int irq, void *data)
1366 {
1367 struct wm8350_data *priv = data;
1368 struct wm8350 *wm8350 = priv->codec.control_data;
1369 struct wm8350_jack_data *jack = NULL;
1370
1371 switch (irq - wm8350->irq_base) {
1372 case WM8350_IRQ_CODEC_JCK_DET_L:
1373 #ifndef CONFIG_SND_SOC_WM8350_MODULE
1374 trace_snd_soc_jack_irq("WM8350 HPL");
1375 #endif
1376 jack = &priv->hpl;
1377 break;
1378
1379 case WM8350_IRQ_CODEC_JCK_DET_R:
1380 #ifndef CONFIG_SND_SOC_WM8350_MODULE
1381 trace_snd_soc_jack_irq("WM8350 HPR");
1382 #endif
1383 jack = &priv->hpr;
1384 break;
1385
1386 default:
1387 BUG();
1388 }
1389
1390 if (device_may_wakeup(wm8350->dev))
1391 pm_wakeup_event(wm8350->dev, 250);
1392
1393 schedule_delayed_work(&jack->work, 200);
1394
1395 return IRQ_HANDLED;
1396 }
1397
1398 /**
1399 * wm8350_hp_jack_detect - Enable headphone jack detection.
1400 *
1401 * @codec: WM8350 codec
1402 * @which: left or right jack detect signal
1403 * @jack: jack to report detection events on
1404 * @report: value to report
1405 *
1406 * Enables the headphone jack detection of the WM8350. If no report
1407 * is specified then detection is disabled.
1408 */
1409 int wm8350_hp_jack_detect(struct snd_soc_codec *codec, enum wm8350_jack which,
1410 struct snd_soc_jack *jack, int report)
1411 {
1412 struct wm8350_data *priv = snd_soc_codec_get_drvdata(codec);
1413 struct wm8350 *wm8350 = codec->control_data;
1414 int irq;
1415 int ena;
1416
1417 switch (which) {
1418 case WM8350_JDL:
1419 priv->hpl.jack = jack;
1420 priv->hpl.report = report;
1421 irq = WM8350_IRQ_CODEC_JCK_DET_L;
1422 ena = WM8350_JDL_ENA;
1423 break;
1424
1425 case WM8350_JDR:
1426 priv->hpr.jack = jack;
1427 priv->hpr.report = report;
1428 irq = WM8350_IRQ_CODEC_JCK_DET_R;
1429 ena = WM8350_JDR_ENA;
1430 break;
1431
1432 default:
1433 return -EINVAL;
1434 }
1435
1436 if (report) {
1437 wm8350_set_bits(wm8350, WM8350_POWER_MGMT_4, WM8350_TOCLK_ENA);
1438 wm8350_set_bits(wm8350, WM8350_JACK_DETECT, ena);
1439 } else {
1440 wm8350_clear_bits(wm8350, WM8350_JACK_DETECT, ena);
1441 }
1442
1443 /* Sync status */
1444 wm8350_hp_jack_handler(irq + wm8350->irq_base, priv);
1445
1446 return 0;
1447 }
1448 EXPORT_SYMBOL_GPL(wm8350_hp_jack_detect);
1449
1450 static irqreturn_t wm8350_mic_handler(int irq, void *data)
1451 {
1452 struct wm8350_data *priv = data;
1453 struct wm8350 *wm8350 = priv->codec.control_data;
1454 u16 reg;
1455 int report = 0;
1456
1457 #ifndef CONFIG_SND_SOC_WM8350_MODULE
1458 trace_snd_soc_jack_irq("WM8350 mic");
1459 #endif
1460
1461 reg = wm8350_reg_read(wm8350, WM8350_JACK_PIN_STATUS);
1462 if (reg & WM8350_JACK_MICSCD_LVL)
1463 report |= priv->mic.short_report;
1464 if (reg & WM8350_JACK_MICSD_LVL)
1465 report |= priv->mic.report;
1466
1467 snd_soc_jack_report(priv->mic.jack, report,
1468 priv->mic.report | priv->mic.short_report);
1469
1470 return IRQ_HANDLED;
1471 }
1472
1473 /**
1474 * wm8350_mic_jack_detect - Enable microphone jack detection.
1475 *
1476 * @codec: WM8350 codec
1477 * @jack: jack to report detection events on
1478 * @detect_report: value to report when presence detected
1479 * @short_report: value to report when microphone short detected
1480 *
1481 * Enables the microphone jack detection of the WM8350. If both reports
1482 * are specified as zero then detection is disabled.
1483 */
1484 int wm8350_mic_jack_detect(struct snd_soc_codec *codec,
1485 struct snd_soc_jack *jack,
1486 int detect_report, int short_report)
1487 {
1488 struct wm8350_data *priv = snd_soc_codec_get_drvdata(codec);
1489 struct wm8350 *wm8350 = codec->control_data;
1490
1491 priv->mic.jack = jack;
1492 priv->mic.report = detect_report;
1493 priv->mic.short_report = short_report;
1494
1495 if (detect_report || short_report) {
1496 wm8350_set_bits(wm8350, WM8350_POWER_MGMT_4, WM8350_TOCLK_ENA);
1497 wm8350_set_bits(wm8350, WM8350_POWER_MGMT_1,
1498 WM8350_MIC_DET_ENA);
1499 } else {
1500 wm8350_clear_bits(wm8350, WM8350_POWER_MGMT_1,
1501 WM8350_MIC_DET_ENA);
1502 }
1503
1504 return 0;
1505 }
1506 EXPORT_SYMBOL_GPL(wm8350_mic_jack_detect);
1507
1508 #define WM8350_RATES (SNDRV_PCM_RATE_8000_96000)
1509
1510 #define WM8350_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
1511 SNDRV_PCM_FMTBIT_S20_3LE |\
1512 SNDRV_PCM_FMTBIT_S24_LE)
1513
1514 static struct snd_soc_dai_ops wm8350_dai_ops = {
1515 .hw_params = wm8350_pcm_hw_params,
1516 .digital_mute = wm8350_mute,
1517 .trigger = wm8350_pcm_trigger,
1518 .set_fmt = wm8350_set_dai_fmt,
1519 .set_sysclk = wm8350_set_dai_sysclk,
1520 .set_pll = wm8350_set_fll,
1521 .set_clkdiv = wm8350_set_clkdiv,
1522 };
1523
1524 static struct snd_soc_dai_driver wm8350_dai = {
1525 .name = "wm8350-hifi",
1526 .playback = {
1527 .stream_name = "Playback",
1528 .channels_min = 1,
1529 .channels_max = 2,
1530 .rates = WM8350_RATES,
1531 .formats = WM8350_FORMATS,
1532 },
1533 .capture = {
1534 .stream_name = "Capture",
1535 .channels_min = 1,
1536 .channels_max = 2,
1537 .rates = WM8350_RATES,
1538 .formats = WM8350_FORMATS,
1539 },
1540 .ops = &wm8350_dai_ops,
1541 };
1542
1543 static int wm8350_codec_probe(struct snd_soc_codec *codec)
1544 {
1545 struct wm8350 *wm8350 = dev_get_platdata(codec->dev);
1546 struct wm8350_data *priv;
1547 struct wm8350_output *out1;
1548 struct wm8350_output *out2;
1549 int ret, i;
1550
1551 if (wm8350->codec.platform_data == NULL) {
1552 dev_err(codec->dev, "No audio platform data supplied\n");
1553 return -EINVAL;
1554 }
1555
1556 priv = kzalloc(sizeof(struct wm8350_data), GFP_KERNEL);
1557 if (priv == NULL)
1558 return -ENOMEM;
1559 snd_soc_codec_set_drvdata(codec, priv);
1560
1561 for (i = 0; i < ARRAY_SIZE(supply_names); i++)
1562 priv->supplies[i].supply = supply_names[i];
1563
1564 ret = regulator_bulk_get(wm8350->dev, ARRAY_SIZE(priv->supplies),
1565 priv->supplies);
1566 if (ret != 0)
1567 goto err_priv;
1568
1569 wm8350->codec.codec = codec;
1570 codec->control_data = wm8350;
1571
1572 /* Put the codec into reset if it wasn't already */
1573 wm8350_clear_bits(wm8350, WM8350_POWER_MGMT_5, WM8350_CODEC_ENA);
1574
1575 INIT_DELAYED_WORK(&codec->dapm.delayed_work, wm8350_pga_work);
1576 INIT_DELAYED_WORK(&priv->hpl.work, wm8350_hpl_work);
1577 INIT_DELAYED_WORK(&priv->hpr.work, wm8350_hpr_work);
1578
1579 /* Enable the codec */
1580 wm8350_set_bits(wm8350, WM8350_POWER_MGMT_5, WM8350_CODEC_ENA);
1581
1582 /* Enable robust clocking mode in ADC */
1583 wm8350_codec_write(codec, WM8350_SECURITY, 0xa7);
1584 wm8350_codec_write(codec, 0xde, 0x13);
1585 wm8350_codec_write(codec, WM8350_SECURITY, 0);
1586
1587 /* read OUT1 & OUT2 volumes */
1588 out1 = &priv->out1;
1589 out2 = &priv->out2;
1590 out1->left_vol = (wm8350_reg_read(wm8350, WM8350_LOUT1_VOLUME) &
1591 WM8350_OUT1L_VOL_MASK) >> WM8350_OUT1L_VOL_SHIFT;
1592 out1->right_vol = (wm8350_reg_read(wm8350, WM8350_ROUT1_VOLUME) &
1593 WM8350_OUT1R_VOL_MASK) >> WM8350_OUT1R_VOL_SHIFT;
1594 out2->left_vol = (wm8350_reg_read(wm8350, WM8350_LOUT2_VOLUME) &
1595 WM8350_OUT2L_VOL_MASK) >> WM8350_OUT1L_VOL_SHIFT;
1596 out2->right_vol = (wm8350_reg_read(wm8350, WM8350_ROUT2_VOLUME) &
1597 WM8350_OUT2R_VOL_MASK) >> WM8350_OUT1R_VOL_SHIFT;
1598 wm8350_reg_write(wm8350, WM8350_LOUT1_VOLUME, 0);
1599 wm8350_reg_write(wm8350, WM8350_ROUT1_VOLUME, 0);
1600 wm8350_reg_write(wm8350, WM8350_LOUT2_VOLUME, 0);
1601 wm8350_reg_write(wm8350, WM8350_ROUT2_VOLUME, 0);
1602
1603 /* Latch VU bits & mute */
1604 wm8350_set_bits(wm8350, WM8350_LOUT1_VOLUME,
1605 WM8350_OUT1_VU | WM8350_OUT1L_MUTE);
1606 wm8350_set_bits(wm8350, WM8350_LOUT2_VOLUME,
1607 WM8350_OUT2_VU | WM8350_OUT2L_MUTE);
1608 wm8350_set_bits(wm8350, WM8350_ROUT1_VOLUME,
1609 WM8350_OUT1_VU | WM8350_OUT1R_MUTE);
1610 wm8350_set_bits(wm8350, WM8350_ROUT2_VOLUME,
1611 WM8350_OUT2_VU | WM8350_OUT2R_MUTE);
1612
1613 /* Make sure AIF tristating is disabled by default */
1614 wm8350_clear_bits(wm8350, WM8350_AI_FORMATING, WM8350_AIF_TRI);
1615
1616 /* Make sure we've got a sane companding setup too */
1617 wm8350_clear_bits(wm8350, WM8350_ADC_DAC_COMP,
1618 WM8350_DAC_COMP | WM8350_LOOPBACK);
1619
1620 /* Make sure jack detect is disabled to start off with */
1621 wm8350_clear_bits(wm8350, WM8350_JACK_DETECT,
1622 WM8350_JDL_ENA | WM8350_JDR_ENA);
1623
1624 wm8350_register_irq(wm8350, WM8350_IRQ_CODEC_JCK_DET_L,
1625 wm8350_hp_jack_handler, 0, "Left jack detect",
1626 priv);
1627 wm8350_register_irq(wm8350, WM8350_IRQ_CODEC_JCK_DET_R,
1628 wm8350_hp_jack_handler, 0, "Right jack detect",
1629 priv);
1630 wm8350_register_irq(wm8350, WM8350_IRQ_CODEC_MICSCD,
1631 wm8350_mic_handler, 0, "Microphone short", priv);
1632 wm8350_register_irq(wm8350, WM8350_IRQ_CODEC_MICD,
1633 wm8350_mic_handler, 0, "Microphone detect", priv);
1634
1635
1636 snd_soc_add_controls(codec, wm8350_snd_controls,
1637 ARRAY_SIZE(wm8350_snd_controls));
1638 wm8350_add_widgets(codec);
1639
1640 wm8350_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1641
1642 return 0;
1643
1644 err_priv:
1645 kfree(priv);
1646 return ret;
1647 }
1648
1649 static int wm8350_codec_remove(struct snd_soc_codec *codec)
1650 {
1651 struct wm8350_data *priv = snd_soc_codec_get_drvdata(codec);
1652 struct wm8350 *wm8350 = dev_get_platdata(codec->dev);
1653
1654 wm8350_clear_bits(wm8350, WM8350_JACK_DETECT,
1655 WM8350_JDL_ENA | WM8350_JDR_ENA);
1656 wm8350_clear_bits(wm8350, WM8350_POWER_MGMT_4, WM8350_TOCLK_ENA);
1657
1658 wm8350_free_irq(wm8350, WM8350_IRQ_CODEC_MICD, priv);
1659 wm8350_free_irq(wm8350, WM8350_IRQ_CODEC_MICSCD, priv);
1660 wm8350_free_irq(wm8350, WM8350_IRQ_CODEC_JCK_DET_L, priv);
1661 wm8350_free_irq(wm8350, WM8350_IRQ_CODEC_JCK_DET_R, priv);
1662
1663 priv->hpl.jack = NULL;
1664 priv->hpr.jack = NULL;
1665 priv->mic.jack = NULL;
1666
1667 cancel_delayed_work_sync(&priv->hpl.work);
1668 cancel_delayed_work_sync(&priv->hpr.work);
1669
1670 /* if there was any work waiting then we run it now and
1671 * wait for its completion */
1672 flush_delayed_work_sync(&codec->dapm.delayed_work);
1673
1674 wm8350_set_bias_level(codec, SND_SOC_BIAS_OFF);
1675
1676 wm8350_clear_bits(wm8350, WM8350_POWER_MGMT_5, WM8350_CODEC_ENA);
1677
1678 regulator_bulk_free(ARRAY_SIZE(priv->supplies), priv->supplies);
1679 kfree(priv);
1680 return 0;
1681 }
1682
1683 static struct snd_soc_codec_driver soc_codec_dev_wm8350 = {
1684 .probe = wm8350_codec_probe,
1685 .remove = wm8350_codec_remove,
1686 .suspend = wm8350_suspend,
1687 .resume = wm8350_resume,
1688 .read = wm8350_codec_read,
1689 .write = wm8350_codec_write,
1690 .set_bias_level = wm8350_set_bias_level,
1691 };
1692
1693 static int __devinit wm8350_probe(struct platform_device *pdev)
1694 {
1695 return snd_soc_register_codec(&pdev->dev, &soc_codec_dev_wm8350,
1696 &wm8350_dai, 1);
1697 }
1698
1699 static int __devexit wm8350_remove(struct platform_device *pdev)
1700 {
1701 snd_soc_unregister_codec(&pdev->dev);
1702 return 0;
1703 }
1704
1705 static struct platform_driver wm8350_codec_driver = {
1706 .driver = {
1707 .name = "wm8350-codec",
1708 .owner = THIS_MODULE,
1709 },
1710 .probe = wm8350_probe,
1711 .remove = __devexit_p(wm8350_remove),
1712 };
1713
1714 static __init int wm8350_init(void)
1715 {
1716 return platform_driver_register(&wm8350_codec_driver);
1717 }
1718 module_init(wm8350_init);
1719
1720 static __exit void wm8350_exit(void)
1721 {
1722 platform_driver_unregister(&wm8350_codec_driver);
1723 }
1724 module_exit(wm8350_exit);
1725
1726 MODULE_DESCRIPTION("ASoC WM8350 driver");
1727 MODULE_AUTHOR("Liam Girdwood");
1728 MODULE_LICENSE("GPL");
1729 MODULE_ALIAS("platform:wm8350-codec");
Linux with added FPC-III support