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staging: xgifb: vb_setmode: make XGI_SetXG27FPBits() static
[linux/fpc-iii.git] / sound / soc / codecs / wm9081.c
blob3cd35a02c28c7164f525f00f7375ac5ef4d6bbb1
1 /*
2 * wm9081.c -- WM9081 ALSA SoC Audio driver
3 *
4 * Author: Mark Brown
5 *
6 * Copyright 2009 Wolfson Microelectronics plc
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 */
13
14 #include <linux/module.h>
15 #include <linux/moduleparam.h>
16 #include <linux/init.h>
17 #include <linux/delay.h>
18 #include <linux/device.h>
19 #include <linux/pm.h>
20 #include <linux/i2c.h>
21 #include <linux/platform_device.h>
22 #include <linux/slab.h>
23 #include <sound/core.h>
24 #include <sound/pcm.h>
25 #include <sound/pcm_params.h>
26 #include <sound/soc.h>
27 #include <sound/initval.h>
28 #include <sound/tlv.h>
29
30 #include <sound/wm9081.h>
31 #include "wm9081.h"
32
33 static u16 wm9081_reg_defaults[] = {
34 0x0000, /* R0 - Software Reset */
35 0x0000, /* R1 */
36 0x00B9, /* R2 - Analogue Lineout */
37 0x00B9, /* R3 - Analogue Speaker PGA */
38 0x0001, /* R4 - VMID Control */
39 0x0068, /* R5 - Bias Control 1 */
40 0x0000, /* R6 */
41 0x0000, /* R7 - Analogue Mixer */
42 0x0000, /* R8 - Anti Pop Control */
43 0x01DB, /* R9 - Analogue Speaker 1 */
44 0x0018, /* R10 - Analogue Speaker 2 */
45 0x0180, /* R11 - Power Management */
46 0x0000, /* R12 - Clock Control 1 */
47 0x0038, /* R13 - Clock Control 2 */
48 0x4000, /* R14 - Clock Control 3 */
49 0x0000, /* R15 */
50 0x0000, /* R16 - FLL Control 1 */
51 0x0200, /* R17 - FLL Control 2 */
52 0x0000, /* R18 - FLL Control 3 */
53 0x0204, /* R19 - FLL Control 4 */
54 0x0000, /* R20 - FLL Control 5 */
55 0x0000, /* R21 */
56 0x0000, /* R22 - Audio Interface 1 */
57 0x0002, /* R23 - Audio Interface 2 */
58 0x0008, /* R24 - Audio Interface 3 */
59 0x0022, /* R25 - Audio Interface 4 */
60 0x0000, /* R26 - Interrupt Status */
61 0x0006, /* R27 - Interrupt Status Mask */
62 0x0000, /* R28 - Interrupt Polarity */
63 0x0000, /* R29 - Interrupt Control */
64 0x00C0, /* R30 - DAC Digital 1 */
65 0x0008, /* R31 - DAC Digital 2 */
66 0x09AF, /* R32 - DRC 1 */
67 0x4201, /* R33 - DRC 2 */
68 0x0000, /* R34 - DRC 3 */
69 0x0000, /* R35 - DRC 4 */
70 0x0000, /* R36 */
71 0x0000, /* R37 */
72 0x0000, /* R38 - Write Sequencer 1 */
73 0x0000, /* R39 - Write Sequencer 2 */
74 0x0002, /* R40 - MW Slave 1 */
75 0x0000, /* R41 */
76 0x0000, /* R42 - EQ 1 */
77 0x0000, /* R43 - EQ 2 */
78 0x0FCA, /* R44 - EQ 3 */
79 0x0400, /* R45 - EQ 4 */
80 0x00B8, /* R46 - EQ 5 */
81 0x1EB5, /* R47 - EQ 6 */
82 0xF145, /* R48 - EQ 7 */
83 0x0B75, /* R49 - EQ 8 */
84 0x01C5, /* R50 - EQ 9 */
85 0x169E, /* R51 - EQ 10 */
86 0xF829, /* R52 - EQ 11 */
87 0x07AD, /* R53 - EQ 12 */
88 0x1103, /* R54 - EQ 13 */
89 0x1C58, /* R55 - EQ 14 */
90 0xF373, /* R56 - EQ 15 */
91 0x0A54, /* R57 - EQ 16 */
92 0x0558, /* R58 - EQ 17 */
93 0x0564, /* R59 - EQ 18 */
94 0x0559, /* R60 - EQ 19 */
95 0x4000, /* R61 - EQ 20 */
96 };
97
98 static struct {
99 int ratio;
100 int clk_sys_rate;
101 } clk_sys_rates[] = {
102 { 64, 0 },
103 { 128, 1 },
104 { 192, 2 },
105 { 256, 3 },
106 { 384, 4 },
107 { 512, 5 },
108 { 768, 6 },
109 { 1024, 7 },
110 { 1408, 8 },
111 { 1536, 9 },
112 };
113
114 static struct {
115 int rate;
116 int sample_rate;
117 } sample_rates[] = {
118 { 8000, 0 },
119 { 11025, 1 },
120 { 12000, 2 },
121 { 16000, 3 },
122 { 22050, 4 },
123 { 24000, 5 },
124 { 32000, 6 },
125 { 44100, 7 },
126 { 48000, 8 },
127 { 88200, 9 },
128 { 96000, 10 },
129 };
130
131 static struct {
132 int div; /* *10 due to .5s */
133 int bclk_div;
134 } bclk_divs[] = {
135 { 10, 0 },
136 { 15, 1 },
137 { 20, 2 },
138 { 30, 3 },
139 { 40, 4 },
140 { 50, 5 },
141 { 55, 6 },
142 { 60, 7 },
143 { 80, 8 },
144 { 100, 9 },
145 { 110, 10 },
146 { 120, 11 },
147 { 160, 12 },
148 { 200, 13 },
149 { 220, 14 },
150 { 240, 15 },
151 { 250, 16 },
152 { 300, 17 },
153 { 320, 18 },
154 { 440, 19 },
155 { 480, 20 },
156 };
157
158 struct wm9081_priv {
159 enum snd_soc_control_type control_type;
160 int sysclk_source;
161 int mclk_rate;
162 int sysclk_rate;
163 int fs;
164 int bclk;
165 int master;
166 int fll_fref;
167 int fll_fout;
168 int tdm_width;
169 struct wm9081_pdata pdata;
170 };
171
172 static int wm9081_volatile_register(struct snd_soc_codec *codec, unsigned int reg)
173 {
174 switch (reg) {
175 case WM9081_SOFTWARE_RESET:
176 case WM9081_INTERRUPT_STATUS:
177 return 1;
178 default:
179 return 0;
180 }
181 }
182
183 static int wm9081_reset(struct snd_soc_codec *codec)
184 {
185 return snd_soc_write(codec, WM9081_SOFTWARE_RESET, 0);
186 }
187
188 static const DECLARE_TLV_DB_SCALE(drc_in_tlv, -4500, 75, 0);
189 static const DECLARE_TLV_DB_SCALE(drc_out_tlv, -2250, 75, 0);
190 static const DECLARE_TLV_DB_SCALE(drc_min_tlv, -1800, 600, 0);
191 static unsigned int drc_max_tlv[] = {
192 TLV_DB_RANGE_HEAD(4),
193 0, 0, TLV_DB_SCALE_ITEM(1200, 0, 0),
194 1, 1, TLV_DB_SCALE_ITEM(1800, 0, 0),
195 2, 2, TLV_DB_SCALE_ITEM(2400, 0, 0),
196 3, 3, TLV_DB_SCALE_ITEM(3600, 0, 0),
197 };
198 static const DECLARE_TLV_DB_SCALE(drc_qr_tlv, 1200, 600, 0);
199 static const DECLARE_TLV_DB_SCALE(drc_startup_tlv, -300, 50, 0);
200
201 static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
202
203 static const DECLARE_TLV_DB_SCALE(in_tlv, -600, 600, 0);
204 static const DECLARE_TLV_DB_SCALE(dac_tlv, -7200, 75, 1);
205 static const DECLARE_TLV_DB_SCALE(out_tlv, -5700, 100, 0);
206
207 static const char *drc_high_text[] = {
208 "1",
209 "1/2",
210 "1/4",
211 "1/8",
212 "1/16",
213 "0",
214 };
215
216 static const struct soc_enum drc_high =
217 SOC_ENUM_SINGLE(WM9081_DRC_3, 3, 6, drc_high_text);
218
219 static const char *drc_low_text[] = {
220 "1",
221 "1/2",
222 "1/4",
223 "1/8",
224 "0",
225 };
226
227 static const struct soc_enum drc_low =
228 SOC_ENUM_SINGLE(WM9081_DRC_3, 0, 5, drc_low_text);
229
230 static const char *drc_atk_text[] = {
231 "181us",
232 "181us",
233 "363us",
234 "726us",
235 "1.45ms",
236 "2.9ms",
237 "5.8ms",
238 "11.6ms",
239 "23.2ms",
240 "46.4ms",
241 "92.8ms",
242 "185.6ms",
243 };
244
245 static const struct soc_enum drc_atk =
246 SOC_ENUM_SINGLE(WM9081_DRC_2, 12, 12, drc_atk_text);
247
248 static const char *drc_dcy_text[] = {
249 "186ms",
250 "372ms",
251 "743ms",
252 "1.49s",
253 "2.97s",
254 "5.94s",
255 "11.89s",
256 "23.78s",
257 "47.56s",
258 };
259
260 static const struct soc_enum drc_dcy =
261 SOC_ENUM_SINGLE(WM9081_DRC_2, 8, 9, drc_dcy_text);
262
263 static const char *drc_qr_dcy_text[] = {
264 "0.725ms",
265 "1.45ms",
266 "5.8ms",
267 };
268
269 static const struct soc_enum drc_qr_dcy =
270 SOC_ENUM_SINGLE(WM9081_DRC_2, 4, 3, drc_qr_dcy_text);
271
272 static const char *dac_deemph_text[] = {
273 "None",
274 "32kHz",
275 "44.1kHz",
276 "48kHz",
277 };
278
279 static const struct soc_enum dac_deemph =
280 SOC_ENUM_SINGLE(WM9081_DAC_DIGITAL_2, 1, 4, dac_deemph_text);
281
282 static const char *speaker_mode_text[] = {
283 "Class D",
284 "Class AB",
285 };
286
287 static const struct soc_enum speaker_mode =
288 SOC_ENUM_SINGLE(WM9081_ANALOGUE_SPEAKER_2, 6, 2, speaker_mode_text);
289
290 static int speaker_mode_get(struct snd_kcontrol *kcontrol,
291 struct snd_ctl_elem_value *ucontrol)
292 {
293 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
294 unsigned int reg;
295
296 reg = snd_soc_read(codec, WM9081_ANALOGUE_SPEAKER_2);
297 if (reg & WM9081_SPK_MODE)
298 ucontrol->value.integer.value[0] = 1;
299 else
300 ucontrol->value.integer.value[0] = 0;
301
302 return 0;
303 }
304
305 /*
306 * Stop any attempts to change speaker mode while the speaker is enabled.
307 *
308 * We also have some special anti-pop controls dependent on speaker
309 * mode which must be changed along with the mode.
310 */
311 static int speaker_mode_put(struct snd_kcontrol *kcontrol,
312 struct snd_ctl_elem_value *ucontrol)
313 {
314 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
315 unsigned int reg_pwr = snd_soc_read(codec, WM9081_POWER_MANAGEMENT);
316 unsigned int reg2 = snd_soc_read(codec, WM9081_ANALOGUE_SPEAKER_2);
317
318 /* Are we changing anything? */
319 if (ucontrol->value.integer.value[0] ==
320 ((reg2 & WM9081_SPK_MODE) != 0))
321 return 0;
322
323 /* Don't try to change modes while enabled */
324 if (reg_pwr & WM9081_SPK_ENA)
325 return -EINVAL;
326
327 if (ucontrol->value.integer.value[0]) {
328 /* Class AB */
329 reg2 &= ~(WM9081_SPK_INV_MUTE | WM9081_OUT_SPK_CTRL);
330 reg2 |= WM9081_SPK_MODE;
331 } else {
332 /* Class D */
333 reg2 |= WM9081_SPK_INV_MUTE | WM9081_OUT_SPK_CTRL;
334 reg2 &= ~WM9081_SPK_MODE;
335 }
336
337 snd_soc_write(codec, WM9081_ANALOGUE_SPEAKER_2, reg2);
338
339 return 0;
340 }
341
342 static const struct snd_kcontrol_new wm9081_snd_controls[] = {
343 SOC_SINGLE_TLV("IN1 Volume", WM9081_ANALOGUE_MIXER, 1, 1, 1, in_tlv),
344 SOC_SINGLE_TLV("IN2 Volume", WM9081_ANALOGUE_MIXER, 3, 1, 1, in_tlv),
345
346 SOC_SINGLE_TLV("Playback Volume", WM9081_DAC_DIGITAL_1, 1, 96, 0, dac_tlv),
347
348 SOC_SINGLE("LINEOUT Switch", WM9081_ANALOGUE_LINEOUT, 7, 1, 1),
349 SOC_SINGLE("LINEOUT ZC Switch", WM9081_ANALOGUE_LINEOUT, 6, 1, 0),
350 SOC_SINGLE_TLV("LINEOUT Volume", WM9081_ANALOGUE_LINEOUT, 0, 63, 0, out_tlv),
351
352 SOC_SINGLE("DRC Switch", WM9081_DRC_1, 15, 1, 0),
353 SOC_ENUM("DRC High Slope", drc_high),
354 SOC_ENUM("DRC Low Slope", drc_low),
355 SOC_SINGLE_TLV("DRC Input Volume", WM9081_DRC_4, 5, 60, 1, drc_in_tlv),
356 SOC_SINGLE_TLV("DRC Output Volume", WM9081_DRC_4, 0, 30, 1, drc_out_tlv),
357 SOC_SINGLE_TLV("DRC Minimum Volume", WM9081_DRC_2, 2, 3, 1, drc_min_tlv),
358 SOC_SINGLE_TLV("DRC Maximum Volume", WM9081_DRC_2, 0, 3, 0, drc_max_tlv),
359 SOC_ENUM("DRC Attack", drc_atk),
360 SOC_ENUM("DRC Decay", drc_dcy),
361 SOC_SINGLE("DRC Quick Release Switch", WM9081_DRC_1, 2, 1, 0),
362 SOC_SINGLE_TLV("DRC Quick Release Volume", WM9081_DRC_2, 6, 3, 0, drc_qr_tlv),
363 SOC_ENUM("DRC Quick Release Decay", drc_qr_dcy),
364 SOC_SINGLE_TLV("DRC Startup Volume", WM9081_DRC_1, 6, 18, 0, drc_startup_tlv),
365
366 SOC_SINGLE("EQ Switch", WM9081_EQ_1, 0, 1, 0),
367
368 SOC_SINGLE("Speaker DC Volume", WM9081_ANALOGUE_SPEAKER_1, 3, 5, 0),
369 SOC_SINGLE("Speaker AC Volume", WM9081_ANALOGUE_SPEAKER_1, 0, 5, 0),
370 SOC_SINGLE("Speaker Switch", WM9081_ANALOGUE_SPEAKER_PGA, 7, 1, 1),
371 SOC_SINGLE("Speaker ZC Switch", WM9081_ANALOGUE_SPEAKER_PGA, 6, 1, 0),
372 SOC_SINGLE_TLV("Speaker Volume", WM9081_ANALOGUE_SPEAKER_PGA, 0, 63, 0,
373 out_tlv),
374 SOC_ENUM("DAC Deemphasis", dac_deemph),
375 SOC_ENUM_EXT("Speaker Mode", speaker_mode, speaker_mode_get, speaker_mode_put),
376 };
377
378 static const struct snd_kcontrol_new wm9081_eq_controls[] = {
379 SOC_SINGLE_TLV("EQ1 Volume", WM9081_EQ_1, 11, 24, 0, eq_tlv),
380 SOC_SINGLE_TLV("EQ2 Volume", WM9081_EQ_1, 6, 24, 0, eq_tlv),
381 SOC_SINGLE_TLV("EQ3 Volume", WM9081_EQ_1, 1, 24, 0, eq_tlv),
382 SOC_SINGLE_TLV("EQ4 Volume", WM9081_EQ_2, 11, 24, 0, eq_tlv),
383 SOC_SINGLE_TLV("EQ5 Volume", WM9081_EQ_2, 6, 24, 0, eq_tlv),
384 };
385
386 static const struct snd_kcontrol_new mixer[] = {
387 SOC_DAPM_SINGLE("IN1 Switch", WM9081_ANALOGUE_MIXER, 0, 1, 0),
388 SOC_DAPM_SINGLE("IN2 Switch", WM9081_ANALOGUE_MIXER, 2, 1, 0),
389 SOC_DAPM_SINGLE("Playback Switch", WM9081_ANALOGUE_MIXER, 4, 1, 0),
390 };
391
392 struct _fll_div {
393 u16 fll_fratio;
394 u16 fll_outdiv;
395 u16 fll_clk_ref_div;
396 u16 n;
397 u16 k;
398 };
399
400 /* The size in bits of the FLL divide multiplied by 10
401 * to allow rounding later */
402 #define FIXED_FLL_SIZE ((1 << 16) * 10)
403
404 static struct {
405 unsigned int min;
406 unsigned int max;
407 u16 fll_fratio;
408 int ratio;
409 } fll_fratios[] = {
410 { 0, 64000, 4, 16 },
411 { 64000, 128000, 3, 8 },
412 { 128000, 256000, 2, 4 },
413 { 256000, 1000000, 1, 2 },
414 { 1000000, 13500000, 0, 1 },
415 };
416
417 static int fll_factors(struct _fll_div *fll_div, unsigned int Fref,
418 unsigned int Fout)
419 {
420 u64 Kpart;
421 unsigned int K, Ndiv, Nmod, target;
422 unsigned int div;
423 int i;
424
425 /* Fref must be <=13.5MHz */
426 div = 1;
427 while ((Fref / div) > 13500000) {
428 div *= 2;
429
430 if (div > 8) {
431 pr_err("Can't scale %dMHz input down to <=13.5MHz\n",
432 Fref);
433 return -EINVAL;
434 }
435 }
436 fll_div->fll_clk_ref_div = div / 2;
437
438 pr_debug("Fref=%u Fout=%u\n", Fref, Fout);
439
440 /* Apply the division for our remaining calculations */
441 Fref /= div;
442
443 /* Fvco should be 90-100MHz; don't check the upper bound */
444 div = 0;
445 target = Fout * 2;
446 while (target < 90000000) {
447 div++;
448 target *= 2;
449 if (div > 7) {
450 pr_err("Unable to find FLL_OUTDIV for Fout=%uHz\n",
451 Fout);
452 return -EINVAL;
453 }
454 }
455 fll_div->fll_outdiv = div;
456
457 pr_debug("Fvco=%dHz\n", target);
458
459 /* Find an appropriate FLL_FRATIO and factor it out of the target */
460 for (i = 0; i < ARRAY_SIZE(fll_fratios); i++) {
461 if (fll_fratios[i].min <= Fref && Fref <= fll_fratios[i].max) {
462 fll_div->fll_fratio = fll_fratios[i].fll_fratio;
463 target /= fll_fratios[i].ratio;
464 break;
465 }
466 }
467 if (i == ARRAY_SIZE(fll_fratios)) {
468 pr_err("Unable to find FLL_FRATIO for Fref=%uHz\n", Fref);
469 return -EINVAL;
470 }
471
472 /* Now, calculate N.K */
473 Ndiv = target / Fref;
474
475 fll_div->n = Ndiv;
476 Nmod = target % Fref;
477 pr_debug("Nmod=%d\n", Nmod);
478
479 /* Calculate fractional part - scale up so we can round. */
480 Kpart = FIXED_FLL_SIZE * (long long)Nmod;
481
482 do_div(Kpart, Fref);
483
484 K = Kpart & 0xFFFFFFFF;
485
486 if ((K % 10) >= 5)
487 K += 5;
488
489 /* Move down to proper range now rounding is done */
490 fll_div->k = K / 10;
491
492 pr_debug("N=%x K=%x FLL_FRATIO=%x FLL_OUTDIV=%x FLL_CLK_REF_DIV=%x\n",
493 fll_div->n, fll_div->k,
494 fll_div->fll_fratio, fll_div->fll_outdiv,
495 fll_div->fll_clk_ref_div);
496
497 return 0;
498 }
499
500 static int wm9081_set_fll(struct snd_soc_codec *codec, int fll_id,
501 unsigned int Fref, unsigned int Fout)
502 {
503 struct wm9081_priv *wm9081 = snd_soc_codec_get_drvdata(codec);
504 u16 reg1, reg4, reg5;
505 struct _fll_div fll_div;
506 int ret;
507 int clk_sys_reg;
508
509 /* Any change? */
510 if (Fref == wm9081->fll_fref && Fout == wm9081->fll_fout)
511 return 0;
512
513 /* Disable the FLL */
514 if (Fout == 0) {
515 dev_dbg(codec->dev, "FLL disabled\n");
516 wm9081->fll_fref = 0;
517 wm9081->fll_fout = 0;
518
519 return 0;
520 }
521
522 ret = fll_factors(&fll_div, Fref, Fout);
523 if (ret != 0)
524 return ret;
525
526 reg5 = snd_soc_read(codec, WM9081_FLL_CONTROL_5);
527 reg5 &= ~WM9081_FLL_CLK_SRC_MASK;
528
529 switch (fll_id) {
530 case WM9081_SYSCLK_FLL_MCLK:
531 reg5 |= 0x1;
532 break;
533
534 default:
535 dev_err(codec->dev, "Unknown FLL ID %d\n", fll_id);
536 return -EINVAL;
537 }
538
539 /* Disable CLK_SYS while we reconfigure */
540 clk_sys_reg = snd_soc_read(codec, WM9081_CLOCK_CONTROL_3);
541 if (clk_sys_reg & WM9081_CLK_SYS_ENA)
542 snd_soc_write(codec, WM9081_CLOCK_CONTROL_3,
543 clk_sys_reg & ~WM9081_CLK_SYS_ENA);
544
545 /* Any FLL configuration change requires that the FLL be
546 * disabled first. */
547 reg1 = snd_soc_read(codec, WM9081_FLL_CONTROL_1);
548 reg1 &= ~WM9081_FLL_ENA;
549 snd_soc_write(codec, WM9081_FLL_CONTROL_1, reg1);
550
551 /* Apply the configuration */
552 if (fll_div.k)
553 reg1 |= WM9081_FLL_FRAC_MASK;
554 else
555 reg1 &= ~WM9081_FLL_FRAC_MASK;
556 snd_soc_write(codec, WM9081_FLL_CONTROL_1, reg1);
557
558 snd_soc_write(codec, WM9081_FLL_CONTROL_2,
559 (fll_div.fll_outdiv << WM9081_FLL_OUTDIV_SHIFT) |
560 (fll_div.fll_fratio << WM9081_FLL_FRATIO_SHIFT));
561 snd_soc_write(codec, WM9081_FLL_CONTROL_3, fll_div.k);
562
563 reg4 = snd_soc_read(codec, WM9081_FLL_CONTROL_4);
564 reg4 &= ~WM9081_FLL_N_MASK;
565 reg4 |= fll_div.n << WM9081_FLL_N_SHIFT;
566 snd_soc_write(codec, WM9081_FLL_CONTROL_4, reg4);
567
568 reg5 &= ~WM9081_FLL_CLK_REF_DIV_MASK;
569 reg5 |= fll_div.fll_clk_ref_div << WM9081_FLL_CLK_REF_DIV_SHIFT;
570 snd_soc_write(codec, WM9081_FLL_CONTROL_5, reg5);
571
572 /* Set gain to the recommended value */
573 snd_soc_update_bits(codec, WM9081_FLL_CONTROL_4,
574 WM9081_FLL_GAIN_MASK, 0);
575
576 /* Enable the FLL */
577 snd_soc_write(codec, WM9081_FLL_CONTROL_1, reg1 | WM9081_FLL_ENA);
578
579 /* Then bring CLK_SYS up again if it was disabled */
580 if (clk_sys_reg & WM9081_CLK_SYS_ENA)
581 snd_soc_write(codec, WM9081_CLOCK_CONTROL_3, clk_sys_reg);
582
583 dev_dbg(codec->dev, "FLL enabled at %dHz->%dHz\n", Fref, Fout);
584
585 wm9081->fll_fref = Fref;
586 wm9081->fll_fout = Fout;
587
588 return 0;
589 }
590
591 static int configure_clock(struct snd_soc_codec *codec)
592 {
593 struct wm9081_priv *wm9081 = snd_soc_codec_get_drvdata(codec);
594 int new_sysclk, i, target;
595 unsigned int reg;
596 int ret = 0;
597 int mclkdiv = 0;
598 int fll = 0;
599
600 switch (wm9081->sysclk_source) {
601 case WM9081_SYSCLK_MCLK:
602 if (wm9081->mclk_rate > 12225000) {
603 mclkdiv = 1;
604 wm9081->sysclk_rate = wm9081->mclk_rate / 2;
605 } else {
606 wm9081->sysclk_rate = wm9081->mclk_rate;
607 }
608 wm9081_set_fll(codec, WM9081_SYSCLK_FLL_MCLK, 0, 0);
609 break;
610
611 case WM9081_SYSCLK_FLL_MCLK:
612 /* If we have a sample rate calculate a CLK_SYS that
613 * gives us a suitable DAC configuration, plus BCLK.
614 * Ideally we would check to see if we can clock
615 * directly from MCLK and only use the FLL if this is
616 * not the case, though care must be taken with free
617 * running mode.
618 */
619 if (wm9081->master && wm9081->bclk) {
620 /* Make sure we can generate CLK_SYS and BCLK
621 * and that we've got 3MHz for optimal
622 * performance. */
623 for (i = 0; i < ARRAY_SIZE(clk_sys_rates); i++) {
624 target = wm9081->fs * clk_sys_rates[i].ratio;
625 new_sysclk = target;
626 if (target >= wm9081->bclk &&
627 target > 3000000)
628 break;
629 }
630
631 if (i == ARRAY_SIZE(clk_sys_rates))
632 return -EINVAL;
633
634 } else if (wm9081->fs) {
635 for (i = 0; i < ARRAY_SIZE(clk_sys_rates); i++) {
636 new_sysclk = clk_sys_rates[i].ratio
637 * wm9081->fs;
638 if (new_sysclk > 3000000)
639 break;
640 }
641
642 if (i == ARRAY_SIZE(clk_sys_rates))
643 return -EINVAL;
644
645 } else {
646 new_sysclk = 12288000;
647 }
648
649 ret = wm9081_set_fll(codec, WM9081_SYSCLK_FLL_MCLK,
650 wm9081->mclk_rate, new_sysclk);
651 if (ret == 0) {
652 wm9081->sysclk_rate = new_sysclk;
653
654 /* Switch SYSCLK over to FLL */
655 fll = 1;
656 } else {
657 wm9081->sysclk_rate = wm9081->mclk_rate;
658 }
659 break;
660
661 default:
662 return -EINVAL;
663 }
664
665 reg = snd_soc_read(codec, WM9081_CLOCK_CONTROL_1);
666 if (mclkdiv)
667 reg |= WM9081_MCLKDIV2;
668 else
669 reg &= ~WM9081_MCLKDIV2;
670 snd_soc_write(codec, WM9081_CLOCK_CONTROL_1, reg);
671
672 reg = snd_soc_read(codec, WM9081_CLOCK_CONTROL_3);
673 if (fll)
674 reg |= WM9081_CLK_SRC_SEL;
675 else
676 reg &= ~WM9081_CLK_SRC_SEL;
677 snd_soc_write(codec, WM9081_CLOCK_CONTROL_3, reg);
678
679 dev_dbg(codec->dev, "CLK_SYS is %dHz\n", wm9081->sysclk_rate);
680
681 return ret;
682 }
683
684 static int clk_sys_event(struct snd_soc_dapm_widget *w,
685 struct snd_kcontrol *kcontrol, int event)
686 {
687 struct snd_soc_codec *codec = w->codec;
688 struct wm9081_priv *wm9081 = snd_soc_codec_get_drvdata(codec);
689
690 /* This should be done on init() for bypass paths */
691 switch (wm9081->sysclk_source) {
692 case WM9081_SYSCLK_MCLK:
693 dev_dbg(codec->dev, "Using %dHz MCLK\n", wm9081->mclk_rate);
694 break;
695 case WM9081_SYSCLK_FLL_MCLK:
696 dev_dbg(codec->dev, "Using %dHz MCLK with FLL\n",
697 wm9081->mclk_rate);
698 break;
699 default:
700 dev_err(codec->dev, "System clock not configured\n");
701 return -EINVAL;
702 }
703
704 switch (event) {
705 case SND_SOC_DAPM_PRE_PMU:
706 configure_clock(codec);
707 break;
708
709 case SND_SOC_DAPM_POST_PMD:
710 /* Disable the FLL if it's running */
711 wm9081_set_fll(codec, 0, 0, 0);
712 break;
713 }
714
715 return 0;
716 }
717
718 static const struct snd_soc_dapm_widget wm9081_dapm_widgets[] = {
719 SND_SOC_DAPM_INPUT("IN1"),
720 SND_SOC_DAPM_INPUT("IN2"),
721
722 SND_SOC_DAPM_DAC("DAC", "HiFi Playback", WM9081_POWER_MANAGEMENT, 0, 0),
723
724 SND_SOC_DAPM_MIXER_NAMED_CTL("Mixer", SND_SOC_NOPM, 0, 0,
725 mixer, ARRAY_SIZE(mixer)),
726
727 SND_SOC_DAPM_PGA("LINEOUT PGA", WM9081_POWER_MANAGEMENT, 4, 0, NULL, 0),
728
729 SND_SOC_DAPM_PGA("Speaker PGA", WM9081_POWER_MANAGEMENT, 2, 0, NULL, 0),
730 SND_SOC_DAPM_OUT_DRV("Speaker", WM9081_POWER_MANAGEMENT, 1, 0, NULL, 0),
731
732 SND_SOC_DAPM_OUTPUT("LINEOUT"),
733 SND_SOC_DAPM_OUTPUT("SPKN"),
734 SND_SOC_DAPM_OUTPUT("SPKP"),
735
736 SND_SOC_DAPM_SUPPLY("CLK_SYS", WM9081_CLOCK_CONTROL_3, 0, 0, clk_sys_event,
737 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
738 SND_SOC_DAPM_SUPPLY("CLK_DSP", WM9081_CLOCK_CONTROL_3, 1, 0, NULL, 0),
739 SND_SOC_DAPM_SUPPLY("TOCLK", WM9081_CLOCK_CONTROL_3, 2, 0, NULL, 0),
740 };
741
742
743 static const struct snd_soc_dapm_route wm9081_audio_paths[] = {
744 { "DAC", NULL, "CLK_SYS" },
745 { "DAC", NULL, "CLK_DSP" },
746
747 { "Mixer", "IN1 Switch", "IN1" },
748 { "Mixer", "IN2 Switch", "IN2" },
749 { "Mixer", "Playback Switch", "DAC" },
750
751 { "LINEOUT PGA", NULL, "Mixer" },
752 { "LINEOUT PGA", NULL, "TOCLK" },
753 { "LINEOUT PGA", NULL, "CLK_SYS" },
754
755 { "LINEOUT", NULL, "LINEOUT PGA" },
756
757 { "Speaker PGA", NULL, "Mixer" },
758 { "Speaker PGA", NULL, "TOCLK" },
759 { "Speaker PGA", NULL, "CLK_SYS" },
760
761 { "Speaker", NULL, "Speaker PGA" },
762
763 { "SPKN", NULL, "Speaker" },
764 { "SPKP", NULL, "Speaker" },
765 };
766
767 static int wm9081_set_bias_level(struct snd_soc_codec *codec,
768 enum snd_soc_bias_level level)
769 {
770 u16 reg;
771
772 switch (level) {
773 case SND_SOC_BIAS_ON:
774 break;
775
776 case SND_SOC_BIAS_PREPARE:
777 /* VMID=2*40k */
778 reg = snd_soc_read(codec, WM9081_VMID_CONTROL);
779 reg &= ~WM9081_VMID_SEL_MASK;
780 reg |= 0x2;
781 snd_soc_write(codec, WM9081_VMID_CONTROL, reg);
782
783 /* Normal bias current */
784 reg = snd_soc_read(codec, WM9081_BIAS_CONTROL_1);
785 reg &= ~WM9081_STBY_BIAS_ENA;
786 snd_soc_write(codec, WM9081_BIAS_CONTROL_1, reg);
787 break;
788
789 case SND_SOC_BIAS_STANDBY:
790 /* Initial cold start */
791 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
792 /* Disable LINEOUT discharge */
793 reg = snd_soc_read(codec, WM9081_ANTI_POP_CONTROL);
794 reg &= ~WM9081_LINEOUT_DISCH;
795 snd_soc_write(codec, WM9081_ANTI_POP_CONTROL, reg);
796
797 /* Select startup bias source */
798 reg = snd_soc_read(codec, WM9081_BIAS_CONTROL_1);
799 reg |= WM9081_BIAS_SRC | WM9081_BIAS_ENA;
800 snd_soc_write(codec, WM9081_BIAS_CONTROL_1, reg);
801
802 /* VMID 2*4k; Soft VMID ramp enable */
803 reg = snd_soc_read(codec, WM9081_VMID_CONTROL);
804 reg |= WM9081_VMID_RAMP | 0x6;
805 snd_soc_write(codec, WM9081_VMID_CONTROL, reg);
806
807 mdelay(100);
808
809 /* Normal bias enable & soft start off */
810 reg |= WM9081_BIAS_ENA;
811 reg &= ~WM9081_VMID_RAMP;
812 snd_soc_write(codec, WM9081_VMID_CONTROL, reg);
813
814 /* Standard bias source */
815 reg = snd_soc_read(codec, WM9081_BIAS_CONTROL_1);
816 reg &= ~WM9081_BIAS_SRC;
817 snd_soc_write(codec, WM9081_BIAS_CONTROL_1, reg);
818 }
819
820 /* VMID 2*240k */
821 reg = snd_soc_read(codec, WM9081_BIAS_CONTROL_1);
822 reg &= ~WM9081_VMID_SEL_MASK;
823 reg |= 0x04;
824 snd_soc_write(codec, WM9081_VMID_CONTROL, reg);
825
826 /* Standby bias current on */
827 reg = snd_soc_read(codec, WM9081_BIAS_CONTROL_1);
828 reg |= WM9081_STBY_BIAS_ENA;
829 snd_soc_write(codec, WM9081_BIAS_CONTROL_1, reg);
830 break;
831
832 case SND_SOC_BIAS_OFF:
833 /* Startup bias source */
834 reg = snd_soc_read(codec, WM9081_BIAS_CONTROL_1);
835 reg |= WM9081_BIAS_SRC;
836 snd_soc_write(codec, WM9081_BIAS_CONTROL_1, reg);
837
838 /* Disable VMID and biases with soft ramping */
839 reg = snd_soc_read(codec, WM9081_VMID_CONTROL);
840 reg &= ~(WM9081_VMID_SEL_MASK | WM9081_BIAS_ENA);
841 reg |= WM9081_VMID_RAMP;
842 snd_soc_write(codec, WM9081_VMID_CONTROL, reg);
843
844 /* Actively discharge LINEOUT */
845 reg = snd_soc_read(codec, WM9081_ANTI_POP_CONTROL);
846 reg |= WM9081_LINEOUT_DISCH;
847 snd_soc_write(codec, WM9081_ANTI_POP_CONTROL, reg);
848 break;
849 }
850
851 codec->dapm.bias_level = level;
852
853 return 0;
854 }
855
856 static int wm9081_set_dai_fmt(struct snd_soc_dai *dai,
857 unsigned int fmt)
858 {
859 struct snd_soc_codec *codec = dai->codec;
860 struct wm9081_priv *wm9081 = snd_soc_codec_get_drvdata(codec);
861 unsigned int aif2 = snd_soc_read(codec, WM9081_AUDIO_INTERFACE_2);
862
863 aif2 &= ~(WM9081_AIF_BCLK_INV | WM9081_AIF_LRCLK_INV |
864 WM9081_BCLK_DIR | WM9081_LRCLK_DIR | WM9081_AIF_FMT_MASK);
865
866 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
867 case SND_SOC_DAIFMT_CBS_CFS:
868 wm9081->master = 0;
869 break;
870 case SND_SOC_DAIFMT_CBS_CFM:
871 aif2 |= WM9081_LRCLK_DIR;
872 wm9081->master = 1;
873 break;
874 case SND_SOC_DAIFMT_CBM_CFS:
875 aif2 |= WM9081_BCLK_DIR;
876 wm9081->master = 1;
877 break;
878 case SND_SOC_DAIFMT_CBM_CFM:
879 aif2 |= WM9081_LRCLK_DIR | WM9081_BCLK_DIR;
880 wm9081->master = 1;
881 break;
882 default:
883 return -EINVAL;
884 }
885
886 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
887 case SND_SOC_DAIFMT_DSP_B:
888 aif2 |= WM9081_AIF_LRCLK_INV;
889 case SND_SOC_DAIFMT_DSP_A:
890 aif2 |= 0x3;
891 break;
892 case SND_SOC_DAIFMT_I2S:
893 aif2 |= 0x2;
894 break;
895 case SND_SOC_DAIFMT_RIGHT_J:
896 break;
897 case SND_SOC_DAIFMT_LEFT_J:
898 aif2 |= 0x1;
899 break;
900 default:
901 return -EINVAL;
902 }
903
904 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
905 case SND_SOC_DAIFMT_DSP_A:
906 case SND_SOC_DAIFMT_DSP_B:
907 /* frame inversion not valid for DSP modes */
908 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
909 case SND_SOC_DAIFMT_NB_NF:
910 break;
911 case SND_SOC_DAIFMT_IB_NF:
912 aif2 |= WM9081_AIF_BCLK_INV;
913 break;
914 default:
915 return -EINVAL;
916 }
917 break;
918
919 case SND_SOC_DAIFMT_I2S:
920 case SND_SOC_DAIFMT_RIGHT_J:
921 case SND_SOC_DAIFMT_LEFT_J:
922 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
923 case SND_SOC_DAIFMT_NB_NF:
924 break;
925 case SND_SOC_DAIFMT_IB_IF:
926 aif2 |= WM9081_AIF_BCLK_INV | WM9081_AIF_LRCLK_INV;
927 break;
928 case SND_SOC_DAIFMT_IB_NF:
929 aif2 |= WM9081_AIF_BCLK_INV;
930 break;
931 case SND_SOC_DAIFMT_NB_IF:
932 aif2 |= WM9081_AIF_LRCLK_INV;
933 break;
934 default:
935 return -EINVAL;
936 }
937 break;
938 default:
939 return -EINVAL;
940 }
941
942 snd_soc_write(codec, WM9081_AUDIO_INTERFACE_2, aif2);
943
944 return 0;
945 }
946
947 static int wm9081_hw_params(struct snd_pcm_substream *substream,
948 struct snd_pcm_hw_params *params,
949 struct snd_soc_dai *dai)
950 {
951 struct snd_soc_codec *codec = dai->codec;
952 struct wm9081_priv *wm9081 = snd_soc_codec_get_drvdata(codec);
953 int ret, i, best, best_val, cur_val;
954 unsigned int clk_ctrl2, aif1, aif2, aif3, aif4;
955
956 clk_ctrl2 = snd_soc_read(codec, WM9081_CLOCK_CONTROL_2);
957 clk_ctrl2 &= ~(WM9081_CLK_SYS_RATE_MASK | WM9081_SAMPLE_RATE_MASK);
958
959 aif1 = snd_soc_read(codec, WM9081_AUDIO_INTERFACE_1);
960
961 aif2 = snd_soc_read(codec, WM9081_AUDIO_INTERFACE_2);
962 aif2 &= ~WM9081_AIF_WL_MASK;
963
964 aif3 = snd_soc_read(codec, WM9081_AUDIO_INTERFACE_3);
965 aif3 &= ~WM9081_BCLK_DIV_MASK;
966
967 aif4 = snd_soc_read(codec, WM9081_AUDIO_INTERFACE_4);
968 aif4 &= ~WM9081_LRCLK_RATE_MASK;
969
970 wm9081->fs = params_rate(params);
971
972 if (wm9081->tdm_width) {
973 /* If TDM is set up then that fixes our BCLK. */
974 int slots = ((aif1 & WM9081_AIFDAC_TDM_MODE_MASK) >>
975 WM9081_AIFDAC_TDM_MODE_SHIFT) + 1;
976
977 wm9081->bclk = wm9081->fs * wm9081->tdm_width * slots;
978 } else {
979 /* Otherwise work out a BCLK from the sample size */
980 wm9081->bclk = 2 * wm9081->fs;
981
982 switch (params_format(params)) {
983 case SNDRV_PCM_FORMAT_S16_LE:
984 wm9081->bclk *= 16;
985 break;
986 case SNDRV_PCM_FORMAT_S20_3LE:
987 wm9081->bclk *= 20;
988 aif2 |= 0x4;
989 break;
990 case SNDRV_PCM_FORMAT_S24_LE:
991 wm9081->bclk *= 24;
992 aif2 |= 0x8;
993 break;
994 case SNDRV_PCM_FORMAT_S32_LE:
995 wm9081->bclk *= 32;
996 aif2 |= 0xc;
997 break;
998 default:
999 return -EINVAL;
1000 }
1001 }
1002
1003 dev_dbg(codec->dev, "Target BCLK is %dHz\n", wm9081->bclk);
1004
1005 ret = configure_clock(codec);
1006 if (ret != 0)
1007 return ret;
1008
1009 /* Select nearest CLK_SYS_RATE */
1010 best = 0;
1011 best_val = abs((wm9081->sysclk_rate / clk_sys_rates[0].ratio)
1012 - wm9081->fs);
1013 for (i = 1; i < ARRAY_SIZE(clk_sys_rates); i++) {
1014 cur_val = abs((wm9081->sysclk_rate /
1015 clk_sys_rates[i].ratio) - wm9081->fs);
1016 if (cur_val < best_val) {
1017 best = i;
1018 best_val = cur_val;
1019 }
1020 }
1021 dev_dbg(codec->dev, "Selected CLK_SYS_RATIO of %d\n",
1022 clk_sys_rates[best].ratio);
1023 clk_ctrl2 |= (clk_sys_rates[best].clk_sys_rate
1024 << WM9081_CLK_SYS_RATE_SHIFT);
1025
1026 /* SAMPLE_RATE */
1027 best = 0;
1028 best_val = abs(wm9081->fs - sample_rates[0].rate);
1029 for (i = 1; i < ARRAY_SIZE(sample_rates); i++) {
1030 /* Closest match */
1031 cur_val = abs(wm9081->fs - sample_rates[i].rate);
1032 if (cur_val < best_val) {
1033 best = i;
1034 best_val = cur_val;
1035 }
1036 }
1037 dev_dbg(codec->dev, "Selected SAMPLE_RATE of %dHz\n",
1038 sample_rates[best].rate);
1039 clk_ctrl2 |= (sample_rates[best].sample_rate
1040 << WM9081_SAMPLE_RATE_SHIFT);
1041
1042 /* BCLK_DIV */
1043 best = 0;
1044 best_val = INT_MAX;
1045 for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) {
1046 cur_val = ((wm9081->sysclk_rate * 10) / bclk_divs[i].div)
1047 - wm9081->bclk;
1048 if (cur_val < 0) /* Table is sorted */
1049 break;
1050 if (cur_val < best_val) {
1051 best = i;
1052 best_val = cur_val;
1053 }
1054 }
1055 wm9081->bclk = (wm9081->sysclk_rate * 10) / bclk_divs[best].div;
1056 dev_dbg(codec->dev, "Selected BCLK_DIV of %d for %dHz BCLK\n",
1057 bclk_divs[best].div, wm9081->bclk);
1058 aif3 |= bclk_divs[best].bclk_div;
1059
1060 /* LRCLK is a simple fraction of BCLK */
1061 dev_dbg(codec->dev, "LRCLK_RATE is %d\n", wm9081->bclk / wm9081->fs);
1062 aif4 |= wm9081->bclk / wm9081->fs;
1063
1064 /* Apply a ReTune Mobile configuration if it's in use */
1065 if (wm9081->pdata.num_retune_configs) {
1066 struct wm9081_pdata *pdata = &wm9081->pdata;
1067 struct wm9081_retune_mobile_setting *s;
1068 int eq1;
1069
1070 best = 0;
1071 best_val = abs(pdata->retune_configs[0].rate - wm9081->fs);
1072 for (i = 0; i < pdata->num_retune_configs; i++) {
1073 cur_val = abs(pdata->retune_configs[i].rate -
1074 wm9081->fs);
1075 if (cur_val < best_val) {
1076 best_val = cur_val;
1077 best = i;
1078 }
1079 }
1080 s = &pdata->retune_configs[best];
1081
1082 dev_dbg(codec->dev, "ReTune Mobile %s tuned for %dHz\n",
1083 s->name, s->rate);
1084
1085 /* If the EQ is enabled then disable it while we write out */
1086 eq1 = snd_soc_read(codec, WM9081_EQ_1) & WM9081_EQ_ENA;
1087 if (eq1 & WM9081_EQ_ENA)
1088 snd_soc_write(codec, WM9081_EQ_1, 0);
1089
1090 /* Write out the other values */
1091 for (i = 1; i < ARRAY_SIZE(s->config); i++)
1092 snd_soc_write(codec, WM9081_EQ_1 + i, s->config[i]);
1093
1094 eq1 |= (s->config[0] & ~WM9081_EQ_ENA);
1095 snd_soc_write(codec, WM9081_EQ_1, eq1);
1096 }
1097
1098 snd_soc_write(codec, WM9081_CLOCK_CONTROL_2, clk_ctrl2);
1099 snd_soc_write(codec, WM9081_AUDIO_INTERFACE_2, aif2);
1100 snd_soc_write(codec, WM9081_AUDIO_INTERFACE_3, aif3);
1101 snd_soc_write(codec, WM9081_AUDIO_INTERFACE_4, aif4);
1102
1103 return 0;
1104 }
1105
1106 static int wm9081_digital_mute(struct snd_soc_dai *codec_dai, int mute)
1107 {
1108 struct snd_soc_codec *codec = codec_dai->codec;
1109 unsigned int reg;
1110
1111 reg = snd_soc_read(codec, WM9081_DAC_DIGITAL_2);
1112
1113 if (mute)
1114 reg |= WM9081_DAC_MUTE;
1115 else
1116 reg &= ~WM9081_DAC_MUTE;
1117
1118 snd_soc_write(codec, WM9081_DAC_DIGITAL_2, reg);
1119
1120 return 0;
1121 }
1122
1123 static int wm9081_set_sysclk(struct snd_soc_codec *codec, int clk_id,
1124 int source, unsigned int freq, int dir)
1125 {
1126 struct wm9081_priv *wm9081 = snd_soc_codec_get_drvdata(codec);
1127
1128 switch (clk_id) {
1129 case WM9081_SYSCLK_MCLK:
1130 case WM9081_SYSCLK_FLL_MCLK:
1131 wm9081->sysclk_source = clk_id;
1132 wm9081->mclk_rate = freq;
1133 break;
1134
1135 default:
1136 return -EINVAL;
1137 }
1138
1139 return 0;
1140 }
1141
1142 static int wm9081_set_tdm_slot(struct snd_soc_dai *dai,
1143 unsigned int tx_mask, unsigned int rx_mask, int slots, int slot_width)
1144 {
1145 struct snd_soc_codec *codec = dai->codec;
1146 struct wm9081_priv *wm9081 = snd_soc_codec_get_drvdata(codec);
1147 unsigned int aif1 = snd_soc_read(codec, WM9081_AUDIO_INTERFACE_1);
1148
1149 aif1 &= ~(WM9081_AIFDAC_TDM_SLOT_MASK | WM9081_AIFDAC_TDM_MODE_MASK);
1150
1151 if (slots < 0 || slots > 4)
1152 return -EINVAL;
1153
1154 wm9081->tdm_width = slot_width;
1155
1156 if (slots == 0)
1157 slots = 1;
1158
1159 aif1 |= (slots - 1) << WM9081_AIFDAC_TDM_MODE_SHIFT;
1160
1161 switch (rx_mask) {
1162 case 1:
1163 break;
1164 case 2:
1165 aif1 |= 0x10;
1166 break;
1167 case 4:
1168 aif1 |= 0x20;
1169 break;
1170 case 8:
1171 aif1 |= 0x30;
1172 break;
1173 default:
1174 return -EINVAL;
1175 }
1176
1177 snd_soc_write(codec, WM9081_AUDIO_INTERFACE_1, aif1);
1178
1179 return 0;
1180 }
1181
1182 #define WM9081_RATES SNDRV_PCM_RATE_8000_96000
1183
1184 #define WM9081_FORMATS \
1185 (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
1186 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
1187
1188 static struct snd_soc_dai_ops wm9081_dai_ops = {
1189 .hw_params = wm9081_hw_params,
1190 .set_fmt = wm9081_set_dai_fmt,
1191 .digital_mute = wm9081_digital_mute,
1192 .set_tdm_slot = wm9081_set_tdm_slot,
1193 };
1194
1195 /* We report two channels because the CODEC processes a stereo signal, even
1196 * though it is only capable of handling a mono output.
1197 */
1198 static struct snd_soc_dai_driver wm9081_dai = {
1199 .name = "wm9081-hifi",
1200 .playback = {
1201 .stream_name = "HiFi Playback",
1202 .channels_min = 1,
1203 .channels_max = 2,
1204 .rates = WM9081_RATES,
1205 .formats = WM9081_FORMATS,
1206 },
1207 .ops = &wm9081_dai_ops,
1208 };
1209
1210 static int wm9081_probe(struct snd_soc_codec *codec)
1211 {
1212 struct wm9081_priv *wm9081 = snd_soc_codec_get_drvdata(codec);
1213 int ret;
1214 u16 reg;
1215
1216 ret = snd_soc_codec_set_cache_io(codec, 8, 16, wm9081->control_type);
1217 if (ret != 0) {
1218 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
1219 return ret;
1220 }
1221
1222 reg = snd_soc_read(codec, WM9081_SOFTWARE_RESET);
1223 if (reg != 0x9081) {
1224 dev_err(codec->dev, "Device is not a WM9081: ID=0x%x\n", reg);
1225 ret = -EINVAL;
1226 return ret;
1227 }
1228
1229 ret = wm9081_reset(codec);
1230 if (ret < 0) {
1231 dev_err(codec->dev, "Failed to issue reset\n");
1232 return ret;
1233 }
1234
1235 reg = 0;
1236 if (wm9081->pdata.irq_high)
1237 reg |= WM9081_IRQ_POL;
1238 if (!wm9081->pdata.irq_cmos)
1239 reg |= WM9081_IRQ_OP_CTRL;
1240 snd_soc_update_bits(codec, WM9081_INTERRUPT_CONTROL,
1241 WM9081_IRQ_POL | WM9081_IRQ_OP_CTRL, reg);
1242
1243 wm9081_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1244
1245 /* Enable zero cross by default */
1246 reg = snd_soc_read(codec, WM9081_ANALOGUE_LINEOUT);
1247 snd_soc_write(codec, WM9081_ANALOGUE_LINEOUT, reg | WM9081_LINEOUTZC);
1248 reg = snd_soc_read(codec, WM9081_ANALOGUE_SPEAKER_PGA);
1249 snd_soc_write(codec, WM9081_ANALOGUE_SPEAKER_PGA,
1250 reg | WM9081_SPKPGAZC);
1251
1252 if (!wm9081->pdata.num_retune_configs) {
1253 dev_dbg(codec->dev,
1254 "No ReTune Mobile data, using normal EQ\n");
1255 snd_soc_add_controls(codec, wm9081_eq_controls,
1256 ARRAY_SIZE(wm9081_eq_controls));
1257 }
1258
1259 return ret;
1260 }
1261
1262 static int wm9081_remove(struct snd_soc_codec *codec)
1263 {
1264 wm9081_set_bias_level(codec, SND_SOC_BIAS_OFF);
1265 return 0;
1266 }
1267
1268 #ifdef CONFIG_PM
1269 static int wm9081_suspend(struct snd_soc_codec *codec, pm_message_t state)
1270 {
1271 wm9081_set_bias_level(codec, SND_SOC_BIAS_OFF);
1272
1273 return 0;
1274 }
1275
1276 static int wm9081_resume(struct snd_soc_codec *codec)
1277 {
1278 u16 *reg_cache = codec->reg_cache;
1279 int i;
1280
1281 for (i = 0; i < codec->driver->reg_cache_size; i++) {
1282 if (i == WM9081_SOFTWARE_RESET)
1283 continue;
1284
1285 snd_soc_write(codec, i, reg_cache[i]);
1286 }
1287
1288 wm9081_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1289
1290 return 0;
1291 }
1292 #else
1293 #define wm9081_suspend NULL
1294 #define wm9081_resume NULL
1295 #endif
1296
1297 static struct snd_soc_codec_driver soc_codec_dev_wm9081 = {
1298 .probe = wm9081_probe,
1299 .remove = wm9081_remove,
1300 .suspend = wm9081_suspend,
1301 .resume = wm9081_resume,
1302
1303 .set_sysclk = wm9081_set_sysclk,
1304 .set_bias_level = wm9081_set_bias_level,
1305
1306 .reg_cache_size = ARRAY_SIZE(wm9081_reg_defaults),
1307 .reg_word_size = sizeof(u16),
1308 .reg_cache_default = wm9081_reg_defaults,
1309 .volatile_register = wm9081_volatile_register,
1310
1311 .controls = wm9081_snd_controls,
1312 .num_controls = ARRAY_SIZE(wm9081_snd_controls),
1313 .dapm_widgets = wm9081_dapm_widgets,
1314 .num_dapm_widgets = ARRAY_SIZE(wm9081_dapm_widgets),
1315 .dapm_routes = wm9081_audio_paths,
1316 .num_dapm_routes = ARRAY_SIZE(wm9081_audio_paths),
1317 };
1318
1319 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1320 static __devinit int wm9081_i2c_probe(struct i2c_client *i2c,
1321 const struct i2c_device_id *id)
1322 {
1323 struct wm9081_priv *wm9081;
1324 int ret;
1325
1326 wm9081 = kzalloc(sizeof(struct wm9081_priv), GFP_KERNEL);
1327 if (wm9081 == NULL)
1328 return -ENOMEM;
1329
1330 i2c_set_clientdata(i2c, wm9081);
1331 wm9081->control_type = SND_SOC_I2C;
1332
1333 if (dev_get_platdata(&i2c->dev))
1334 memcpy(&wm9081->pdata, dev_get_platdata(&i2c->dev),
1335 sizeof(wm9081->pdata));
1336
1337 ret = snd_soc_register_codec(&i2c->dev,
1338 &soc_codec_dev_wm9081, &wm9081_dai, 1);
1339 if (ret < 0)
1340 kfree(wm9081);
1341 return ret;
1342 }
1343
1344 static __devexit int wm9081_i2c_remove(struct i2c_client *client)
1345 {
1346 snd_soc_unregister_codec(&client->dev);
1347 kfree(i2c_get_clientdata(client));
1348 return 0;
1349 }
1350
1351 static const struct i2c_device_id wm9081_i2c_id[] = {
1352 { "wm9081", 0 },
1353 { }
1354 };
1355 MODULE_DEVICE_TABLE(i2c, wm9081_i2c_id);
1356
1357 static struct i2c_driver wm9081_i2c_driver = {
1358 .driver = {
1359 .name = "wm9081",
1360 .owner = THIS_MODULE,
1361 },
1362 .probe = wm9081_i2c_probe,
1363 .remove = __devexit_p(wm9081_i2c_remove),
1364 .id_table = wm9081_i2c_id,
1365 };
1366 #endif
1367
1368 static int __init wm9081_modinit(void)
1369 {
1370 int ret = 0;
1371 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1372 ret = i2c_add_driver(&wm9081_i2c_driver);
1373 if (ret != 0) {
1374 printk(KERN_ERR "Failed to register WM9081 I2C driver: %d\n",
1375 ret);
1376 }
1377 #endif
1378 return ret;
1379 }
1380 module_init(wm9081_modinit);
1381
1382 static void __exit wm9081_exit(void)
1383 {
1384 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1385 i2c_del_driver(&wm9081_i2c_driver);
1386 #endif
1387 }
1388 module_exit(wm9081_exit);
1389
1390
1391 MODULE_DESCRIPTION("ASoC WM9081 driver");
1392 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
1393 MODULE_LICENSE("GPL");
Linux with added FPC-III support