sound/soc/samsung/regs-i2s-v2.h

   1 /* linux/include/asm-arm/plat-s3c24xx/regs-s3c2412-iis.h
   2  *
   3  * Copyright 2007 Simtec Electronics <linux@simtec.co.uk>
   4  *      http://armlinux.simtec.co.uk/
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  *
  10  * S3C2412 IIS register definition
  11 */
  12
  13 #ifndef __ASM_ARCH_REGS_S3C2412_IIS_H
  14 #define __ASM_ARCH_REGS_S3C2412_IIS_H
  15
  16 #define S3C2412_IISCON                  (0x00)
  17 #define S3C2412_IISMOD                  (0x04)
  18 #define S3C2412_IISFIC                  (0x08)
  19 #define S3C2412_IISPSR                  (0x0C)
  20 #define S3C2412_IISTXD                  (0x10)
  21 #define S3C2412_IISRXD                  (0x14)
  22
  23 #define S5PC1XX_IISFICS         0x18
  24 #define S5PC1XX_IISTXDS         0x1C
  25
  26 #define S5PC1XX_IISCON_SW_RST           (1 << 31)
  27 #define S5PC1XX_IISCON_FRXOFSTATUS      (1 << 26)
  28 #define S5PC1XX_IISCON_FRXORINTEN       (1 << 25)
  29 #define S5PC1XX_IISCON_FTXSURSTAT       (1 << 24)
  30 #define S5PC1XX_IISCON_FTXSURINTEN      (1 << 23)
  31 #define S5PC1XX_IISCON_TXSDMAPAUSE      (1 << 20)
  32 #define S5PC1XX_IISCON_TXSDMACTIVE      (1 << 18)
  33
  34 #define S3C64XX_IISCON_FTXURSTATUS      (1 << 17)
  35 #define S3C64XX_IISCON_FTXURINTEN       (1 << 16)
  36 #define S3C64XX_IISCON_TXFIFO2_EMPTY    (1 << 15)
  37 #define S3C64XX_IISCON_TXFIFO1_EMPTY    (1 << 14)
  38 #define S3C64XX_IISCON_TXFIFO2_FULL     (1 << 13)
  39 #define S3C64XX_IISCON_TXFIFO1_FULL     (1 << 12)
  40
  41 #define S3C2412_IISCON_LRINDEX          (1 << 11)
  42 #define S3C2412_IISCON_TXFIFO_EMPTY     (1 << 10)
  43 #define S3C2412_IISCON_RXFIFO_EMPTY     (1 << 9)
  44 #define S3C2412_IISCON_TXFIFO_FULL      (1 << 8)
  45 #define S3C2412_IISCON_RXFIFO_FULL      (1 << 7)
  46 #define S3C2412_IISCON_TXDMA_PAUSE      (1 << 6)
  47 #define S3C2412_IISCON_RXDMA_PAUSE      (1 << 5)
  48 #define S3C2412_IISCON_TXCH_PAUSE       (1 << 4)
  49 #define S3C2412_IISCON_RXCH_PAUSE       (1 << 3)
  50 #define S3C2412_IISCON_TXDMA_ACTIVE     (1 << 2)
  51 #define S3C2412_IISCON_RXDMA_ACTIVE     (1 << 1)
  52 #define S3C2412_IISCON_IIS_ACTIVE       (1 << 0)
  53
  54 #define S5PC1XX_IISMOD_OPCLK_CDCLK_OUT  (0 << 30)
  55 #define S5PC1XX_IISMOD_OPCLK_CDCLK_IN   (1 << 30)
  56 #define S5PC1XX_IISMOD_OPCLK_BCLK_OUT   (2 << 30)
  57 #define S5PC1XX_IISMOD_OPCLK_PCLK       (3 << 30)
  58 #define S5PC1XX_IISMOD_OPCLK_MASK       (3 << 30)
  59 #define S5PC1XX_IISMOD_TXS_IDMA         (1 << 28) /* Sec_TXFIFO use I-DMA */
  60 #define S5PC1XX_IISMOD_BLCS_MASK        0x3
  61 #define S5PC1XX_IISMOD_BLCS_SHIFT       26
  62 #define S5PC1XX_IISMOD_BLCP_MASK        0x3
  63 #define S5PC1XX_IISMOD_BLCP_SHIFT       24
  64
  65 #define S3C64XX_IISMOD_C2DD_HHALF       (1 << 21) /* Discard Higher-half */
  66 #define S3C64XX_IISMOD_C2DD_LHALF       (1 << 20) /* Discard Lower-half */
  67 #define S3C64XX_IISMOD_C1DD_HHALF       (1 << 19)
  68 #define S3C64XX_IISMOD_C1DD_LHALF       (1 << 18)
  69 #define S3C64XX_IISMOD_DC2_EN           (1 << 17)
  70 #define S3C64XX_IISMOD_DC1_EN           (1 << 16)
  71 #define S3C64XX_IISMOD_BLC_16BIT        (0 << 13)
  72 #define S3C64XX_IISMOD_BLC_8BIT         (1 << 13)
  73 #define S3C64XX_IISMOD_BLC_24BIT        (2 << 13)
  74 #define S3C64XX_IISMOD_BLC_MASK         (3 << 13)
  75
  76 #define S3C2412_IISMOD_IMS_SYSMUX       (1 << 10)
  77 #define S3C2412_IISMOD_SLAVE            (1 << 11)
  78 #define S3C2412_IISMOD_MODE_TXONLY      (0 << 8)
  79 #define S3C2412_IISMOD_MODE_RXONLY      (1 << 8)
  80 #define S3C2412_IISMOD_MODE_TXRX        (2 << 8)
  81 #define S3C2412_IISMOD_MODE_MASK        (3 << 8)
  82 #define S3C2412_IISMOD_LR_LLOW          (0 << 7)
  83 #define S3C2412_IISMOD_LR_RLOW          (1 << 7)
  84 #define S3C2412_IISMOD_SDF_IIS          (0 << 5)
  85 #define S3C2412_IISMOD_SDF_MSB          (1 << 5)
  86 #define S3C2412_IISMOD_SDF_LSB          (2 << 5)
  87 #define S3C2412_IISMOD_SDF_MASK         (3 << 5)
  88 #define S3C2412_IISMOD_RCLK_256FS       (0 << 3)
  89 #define S3C2412_IISMOD_RCLK_512FS       (1 << 3)
  90 #define S3C2412_IISMOD_RCLK_384FS       (2 << 3)
  91 #define S3C2412_IISMOD_RCLK_768FS       (3 << 3)
  92 #define S3C2412_IISMOD_RCLK_MASK        (3 << 3)
  93 #define S3C2412_IISMOD_BCLK_32FS        (0 << 1)
  94 #define S3C2412_IISMOD_BCLK_48FS        (1 << 1)
  95 #define S3C2412_IISMOD_BCLK_16FS        (2 << 1)
  96 #define S3C2412_IISMOD_BCLK_24FS        (3 << 1)
  97 #define S3C2412_IISMOD_BCLK_MASK        (3 << 1)
  98 #define S3C2412_IISMOD_8BIT             (1 << 0)
  99
 100 #define S3C64XX_IISMOD_CDCLKCON         (1 << 12)
 101
 102 #define S3C2412_IISPSR_PSREN            (1 << 15)
 103
 104 #define S3C64XX_IISFIC_TX2COUNT(x)      (((x) >>  24) & 0xf)
 105 #define S3C64XX_IISFIC_TX1COUNT(x)      (((x) >>  16) & 0xf)
 106
 107 #define S3C2412_IISFIC_TXFLUSH          (1 << 15)
 108 #define S3C2412_IISFIC_RXFLUSH          (1 << 7)
 109 #define S3C2412_IISFIC_TXCOUNT(x)       (((x) >>  8) & 0xf)
 110 #define S3C2412_IISFIC_RXCOUNT(x)       (((x) >>  0) & 0xf)
 111
 112 #define S5PC1XX_IISFICS_TXFLUSH         (1 << 15)
 113 #define S5PC1XX_IISFICS_TXCOUNT(x)      (((x) >>  8) & 0x7f)
 114
 115 #endif /* __ASM_ARCH_REGS_S3C2412_IIS_H */