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workqueue: Make worker_attach/detach_pool() update worker->pool
[linux/fpc-iii.git] / drivers / edac / skx_edac.c
blobfae095162c0175d860bfb9669b6036e4773282fd
1 /*
2 * EDAC driver for Intel(R) Xeon(R) Skylake processors
3 * Copyright (c) 2016, Intel Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 */
14
15 #include <linux/module.h>
16 #include <linux/init.h>
17 #include <linux/acpi.h>
18 #include <linux/dmi.h>
19 #include <linux/pci.h>
20 #include <linux/pci_ids.h>
21 #include <linux/slab.h>
22 #include <linux/delay.h>
23 #include <linux/edac.h>
24 #include <linux/mmzone.h>
25 #include <linux/smp.h>
26 #include <linux/bitmap.h>
27 #include <linux/math64.h>
28 #include <linux/mod_devicetable.h>
29 #include <acpi/nfit.h>
30 #include <asm/cpu_device_id.h>
31 #include <asm/intel-family.h>
32 #include <asm/processor.h>
33 #include <asm/mce.h>
34
35 #include "edac_module.h"
36
37 #define EDAC_MOD_STR "skx_edac"
38
39 /*
40 * Debug macros
41 */
42 #define skx_printk(level, fmt, arg...) \
43 edac_printk(level, "skx", fmt, ##arg)
44
45 #define skx_mc_printk(mci, level, fmt, arg...) \
46 edac_mc_chipset_printk(mci, level, "skx", fmt, ##arg)
47
48 /*
49 * Get a bit field at register value <v>, from bit <lo> to bit <hi>
50 */
51 #define GET_BITFIELD(v, lo, hi) \
52 (((v) & GENMASK_ULL((hi), (lo))) >> (lo))
53
54 static LIST_HEAD(skx_edac_list);
55
56 static u64 skx_tolm, skx_tohm;
57
58 #define NUM_IMC 2 /* memory controllers per socket */
59 #define NUM_CHANNELS 3 /* channels per memory controller */
60 #define NUM_DIMMS 2 /* Max DIMMS per channel */
61
62 #define MASK26 0x3FFFFFF /* Mask for 2^26 */
63 #define MASK29 0x1FFFFFFF /* Mask for 2^29 */
64
65 /*
66 * Each cpu socket contains some pci devices that provide global
67 * information, and also some that are local to each of the two
68 * memory controllers on the die.
69 */
70 struct skx_dev {
71 struct list_head list;
72 u8 bus[4];
73 int seg;
74 struct pci_dev *sad_all;
75 struct pci_dev *util_all;
76 u32 mcroute;
77 struct skx_imc {
78 struct mem_ctl_info *mci;
79 u8 mc; /* system wide mc# */
80 u8 lmc; /* socket relative mc# */
81 u8 src_id, node_id;
82 struct skx_channel {
83 struct pci_dev *cdev;
84 struct skx_dimm {
85 u8 close_pg;
86 u8 bank_xor_enable;
87 u8 fine_grain_bank;
88 u8 rowbits;
89 u8 colbits;
90 } dimms[NUM_DIMMS];
91 } chan[NUM_CHANNELS];
92 } imc[NUM_IMC];
93 };
94 static int skx_num_sockets;
95
96 struct skx_pvt {
97 struct skx_imc *imc;
98 };
99
100 struct decoded_addr {
101 struct skx_dev *dev;
102 u64 addr;
103 int socket;
104 int imc;
105 int channel;
106 u64 chan_addr;
107 int sktways;
108 int chanways;
109 int dimm;
110 int rank;
111 int channel_rank;
112 u64 rank_address;
113 int row;
114 int column;
115 int bank_address;
116 int bank_group;
117 };
118
119 static struct skx_dev *get_skx_dev(struct pci_bus *bus, u8 idx)
120 {
121 struct skx_dev *d;
122
123 list_for_each_entry(d, &skx_edac_list, list) {
124 if (d->seg == pci_domain_nr(bus) && d->bus[idx] == bus->number)
125 return d;
126 }
127
128 return NULL;
129 }
130
131 enum munittype {
132 CHAN0, CHAN1, CHAN2, SAD_ALL, UTIL_ALL, SAD
133 };
134
135 struct munit {
136 u16 did;
137 u16 devfn[NUM_IMC];
138 u8 busidx;
139 u8 per_socket;
140 enum munittype mtype;
141 };
142
143 /*
144 * List of PCI device ids that we need together with some device
145 * number and function numbers to tell which memory controller the
146 * device belongs to.
147 */
148 static const struct munit skx_all_munits[] = {
149 { 0x2054, { }, 1, 1, SAD_ALL },
150 { 0x2055, { }, 1, 1, UTIL_ALL },
151 { 0x2040, { PCI_DEVFN(10, 0), PCI_DEVFN(12, 0) }, 2, 2, CHAN0 },
152 { 0x2044, { PCI_DEVFN(10, 4), PCI_DEVFN(12, 4) }, 2, 2, CHAN1 },
153 { 0x2048, { PCI_DEVFN(11, 0), PCI_DEVFN(13, 0) }, 2, 2, CHAN2 },
154 { 0x208e, { }, 1, 0, SAD },
155 { }
156 };
157
158 /*
159 * We use the per-socket device 0x2016 to count how many sockets are present,
160 * and to detemine which PCI buses are associated with each socket. Allocate
161 * and build the full list of all the skx_dev structures that we need here.
162 */
163 static int get_all_bus_mappings(void)
164 {
165 struct pci_dev *pdev, *prev;
166 struct skx_dev *d;
167 u32 reg;
168 int ndev = 0;
169
170 prev = NULL;
171 for (;;) {
172 pdev = pci_get_device(PCI_VENDOR_ID_INTEL, 0x2016, prev);
173 if (!pdev)
174 break;
175 ndev++;
176 d = kzalloc(sizeof(*d), GFP_KERNEL);
177 if (!d) {
178 pci_dev_put(pdev);
179 return -ENOMEM;
180 }
181 d->seg = pci_domain_nr(pdev->bus);
182 pci_read_config_dword(pdev, 0xCC, &reg);
183 d->bus[0] = GET_BITFIELD(reg, 0, 7);
184 d->bus[1] = GET_BITFIELD(reg, 8, 15);
185 d->bus[2] = GET_BITFIELD(reg, 16, 23);
186 d->bus[3] = GET_BITFIELD(reg, 24, 31);
187 edac_dbg(2, "busses: %x, %x, %x, %x\n",
188 d->bus[0], d->bus[1], d->bus[2], d->bus[3]);
189 list_add_tail(&d->list, &skx_edac_list);
190 skx_num_sockets++;
191 prev = pdev;
192 }
193
194 return ndev;
195 }
196
197 static int get_all_munits(const struct munit *m)
198 {
199 struct pci_dev *pdev, *prev;
200 struct skx_dev *d;
201 u32 reg;
202 int i = 0, ndev = 0;
203
204 prev = NULL;
205 for (;;) {
206 pdev = pci_get_device(PCI_VENDOR_ID_INTEL, m->did, prev);
207 if (!pdev)
208 break;
209 ndev++;
210 if (m->per_socket == NUM_IMC) {
211 for (i = 0; i < NUM_IMC; i++)
212 if (m->devfn[i] == pdev->devfn)
213 break;
214 if (i == NUM_IMC)
215 goto fail;
216 }
217 d = get_skx_dev(pdev->bus, m->busidx);
218 if (!d)
219 goto fail;
220
221 /* Be sure that the device is enabled */
222 if (unlikely(pci_enable_device(pdev) < 0)) {
223 skx_printk(KERN_ERR,
224 "Couldn't enable %04x:%04x\n", PCI_VENDOR_ID_INTEL, m->did);
225 goto fail;
226 }
227
228 switch (m->mtype) {
229 case CHAN0: case CHAN1: case CHAN2:
230 pci_dev_get(pdev);
231 d->imc[i].chan[m->mtype].cdev = pdev;
232 break;
233 case SAD_ALL:
234 pci_dev_get(pdev);
235 d->sad_all = pdev;
236 break;
237 case UTIL_ALL:
238 pci_dev_get(pdev);
239 d->util_all = pdev;
240 break;
241 case SAD:
242 /*
243 * one of these devices per core, including cores
244 * that don't exist on this SKU. Ignore any that
245 * read a route table of zero, make sure all the
246 * non-zero values match.
247 */
248 pci_read_config_dword(pdev, 0xB4, &reg);
249 if (reg != 0) {
250 if (d->mcroute == 0)
251 d->mcroute = reg;
252 else if (d->mcroute != reg) {
253 skx_printk(KERN_ERR,
254 "mcroute mismatch\n");
255 goto fail;
256 }
257 }
258 ndev--;
259 break;
260 }
261
262 prev = pdev;
263 }
264
265 return ndev;
266 fail:
267 pci_dev_put(pdev);
268 return -ENODEV;
269 }
270
271 static const struct x86_cpu_id skx_cpuids[] = {
272 { X86_VENDOR_INTEL, 6, INTEL_FAM6_SKYLAKE_X, 0, 0 },
273 { }
274 };
275 MODULE_DEVICE_TABLE(x86cpu, skx_cpuids);
276
277 static u8 get_src_id(struct skx_dev *d)
278 {
279 u32 reg;
280
281 pci_read_config_dword(d->util_all, 0xF0, &reg);
282
283 return GET_BITFIELD(reg, 12, 14);
284 }
285
286 static u8 skx_get_node_id(struct skx_dev *d)
287 {
288 u32 reg;
289
290 pci_read_config_dword(d->util_all, 0xF4, &reg);
291
292 return GET_BITFIELD(reg, 0, 2);
293 }
294
295 static int get_dimm_attr(u32 reg, int lobit, int hibit, int add, int minval,
296 int maxval, char *name)
297 {
298 u32 val = GET_BITFIELD(reg, lobit, hibit);
299
300 if (val < minval || val > maxval) {
301 edac_dbg(2, "bad %s = %d (raw=%x)\n", name, val, reg);
302 return -EINVAL;
303 }
304 return val + add;
305 }
306
307 #define IS_DIMM_PRESENT(mtr) GET_BITFIELD((mtr), 15, 15)
308 #define IS_NVDIMM_PRESENT(mcddrtcfg, i) GET_BITFIELD((mcddrtcfg), (i), (i))
309
310 #define numrank(reg) get_dimm_attr((reg), 12, 13, 0, 0, 2, "ranks")
311 #define numrow(reg) get_dimm_attr((reg), 2, 4, 12, 1, 6, "rows")
312 #define numcol(reg) get_dimm_attr((reg), 0, 1, 10, 0, 2, "cols")
313
314 static int get_width(u32 mtr)
315 {
316 switch (GET_BITFIELD(mtr, 8, 9)) {
317 case 0:
318 return DEV_X4;
319 case 1:
320 return DEV_X8;
321 case 2:
322 return DEV_X16;
323 }
324 return DEV_UNKNOWN;
325 }
326
327 static int skx_get_hi_lo(void)
328 {
329 struct pci_dev *pdev;
330 u32 reg;
331
332 pdev = pci_get_device(PCI_VENDOR_ID_INTEL, 0x2034, NULL);
333 if (!pdev) {
334 edac_dbg(0, "Can't get tolm/tohm\n");
335 return -ENODEV;
336 }
337
338 pci_read_config_dword(pdev, 0xD0, &reg);
339 skx_tolm = reg;
340 pci_read_config_dword(pdev, 0xD4, &reg);
341 skx_tohm = reg;
342 pci_read_config_dword(pdev, 0xD8, &reg);
343 skx_tohm |= (u64)reg << 32;
344
345 pci_dev_put(pdev);
346 edac_dbg(2, "tolm=%llx tohm=%llx\n", skx_tolm, skx_tohm);
347
348 return 0;
349 }
350
351 static int get_dimm_info(u32 mtr, u32 amap, struct dimm_info *dimm,
352 struct skx_imc *imc, int chan, int dimmno)
353 {
354 int banks = 16, ranks, rows, cols, npages;
355 u64 size;
356
357 ranks = numrank(mtr);
358 rows = numrow(mtr);
359 cols = numcol(mtr);
360
361 /*
362 * Compute size in 8-byte (2^3) words, then shift to MiB (2^20)
363 */
364 size = ((1ull << (rows + cols + ranks)) * banks) >> (20 - 3);
365 npages = MiB_TO_PAGES(size);
366
367 edac_dbg(0, "mc#%d: channel %d, dimm %d, %lld Mb (%d pages) bank: %d, rank: %d, row: %#x, col: %#x\n",
368 imc->mc, chan, dimmno, size, npages,
369 banks, 1 << ranks, rows, cols);
370
371 imc->chan[chan].dimms[dimmno].close_pg = GET_BITFIELD(mtr, 0, 0);
372 imc->chan[chan].dimms[dimmno].bank_xor_enable = GET_BITFIELD(mtr, 9, 9);
373 imc->chan[chan].dimms[dimmno].fine_grain_bank = GET_BITFIELD(amap, 0, 0);
374 imc->chan[chan].dimms[dimmno].rowbits = rows;
375 imc->chan[chan].dimms[dimmno].colbits = cols;
376
377 dimm->nr_pages = npages;
378 dimm->grain = 32;
379 dimm->dtype = get_width(mtr);
380 dimm->mtype = MEM_DDR4;
381 dimm->edac_mode = EDAC_SECDED; /* likely better than this */
382 snprintf(dimm->label, sizeof(dimm->label), "CPU_SrcID#%u_MC#%u_Chan#%u_DIMM#%u",
383 imc->src_id, imc->lmc, chan, dimmno);
384
385 return 1;
386 }
387
388 static int get_nvdimm_info(struct dimm_info *dimm, struct skx_imc *imc,
389 int chan, int dimmno)
390 {
391 int smbios_handle;
392 u32 dev_handle;
393 u16 flags;
394 u64 size = 0;
395
396 dev_handle = ACPI_NFIT_BUILD_DEVICE_HANDLE(dimmno, chan, imc->lmc,
397 imc->src_id, 0);
398
399 smbios_handle = nfit_get_smbios_id(dev_handle, &flags);
400 if (smbios_handle == -EOPNOTSUPP) {
401 pr_warn_once(EDAC_MOD_STR ": Can't find size of NVDIMM. Try enabling CONFIG_ACPI_NFIT\n");
402 goto unknown_size;
403 }
404
405 if (smbios_handle < 0) {
406 skx_printk(KERN_ERR, "Can't find handle for NVDIMM ADR=%x\n", dev_handle);
407 goto unknown_size;
408 }
409
410 if (flags & ACPI_NFIT_MEM_MAP_FAILED) {
411 skx_printk(KERN_ERR, "NVDIMM ADR=%x is not mapped\n", dev_handle);
412 goto unknown_size;
413 }
414
415 size = dmi_memdev_size(smbios_handle);
416 if (size == ~0ull)
417 skx_printk(KERN_ERR, "Can't find size for NVDIMM ADR=%x/SMBIOS=%x\n",
418 dev_handle, smbios_handle);
419
420 unknown_size:
421 dimm->nr_pages = size >> PAGE_SHIFT;
422 dimm->grain = 32;
423 dimm->dtype = DEV_UNKNOWN;
424 dimm->mtype = MEM_NVDIMM;
425 dimm->edac_mode = EDAC_SECDED; /* likely better than this */
426
427 edac_dbg(0, "mc#%d: channel %d, dimm %d, %llu Mb (%u pages)\n",
428 imc->mc, chan, dimmno, size >> 20, dimm->nr_pages);
429
430 snprintf(dimm->label, sizeof(dimm->label), "CPU_SrcID#%u_MC#%u_Chan#%u_DIMM#%u",
431 imc->src_id, imc->lmc, chan, dimmno);
432
433 return (size == 0 || size == ~0ull) ? 0 : 1;
434 }
435
436 #define SKX_GET_MTMTR(dev, reg) \
437 pci_read_config_dword((dev), 0x87c, &reg)
438
439 static bool skx_check_ecc(struct pci_dev *pdev)
440 {
441 u32 mtmtr;
442
443 SKX_GET_MTMTR(pdev, mtmtr);
444
445 return !!GET_BITFIELD(mtmtr, 2, 2);
446 }
447
448 static int skx_get_dimm_config(struct mem_ctl_info *mci)
449 {
450 struct skx_pvt *pvt = mci->pvt_info;
451 struct skx_imc *imc = pvt->imc;
452 u32 mtr, amap, mcddrtcfg;
453 struct dimm_info *dimm;
454 int i, j;
455 int ndimms;
456
457 for (i = 0; i < NUM_CHANNELS; i++) {
458 ndimms = 0;
459 pci_read_config_dword(imc->chan[i].cdev, 0x8C, &amap);
460 pci_read_config_dword(imc->chan[i].cdev, 0x400, &mcddrtcfg);
461 for (j = 0; j < NUM_DIMMS; j++) {
462 dimm = EDAC_DIMM_PTR(mci->layers, mci->dimms,
463 mci->n_layers, i, j, 0);
464 pci_read_config_dword(imc->chan[i].cdev,
465 0x80 + 4*j, &mtr);
466 if (IS_DIMM_PRESENT(mtr))
467 ndimms += get_dimm_info(mtr, amap, dimm, imc, i, j);
468 else if (IS_NVDIMM_PRESENT(mcddrtcfg, j))
469 ndimms += get_nvdimm_info(dimm, imc, i, j);
470 }
471 if (ndimms && !skx_check_ecc(imc->chan[0].cdev)) {
472 skx_printk(KERN_ERR, "ECC is disabled on imc %d\n", imc->mc);
473 return -ENODEV;
474 }
475 }
476
477 return 0;
478 }
479
480 static void skx_unregister_mci(struct skx_imc *imc)
481 {
482 struct mem_ctl_info *mci = imc->mci;
483
484 if (!mci)
485 return;
486
487 edac_dbg(0, "MC%d: mci = %p\n", imc->mc, mci);
488
489 /* Remove MC sysfs nodes */
490 edac_mc_del_mc(mci->pdev);
491
492 edac_dbg(1, "%s: free mci struct\n", mci->ctl_name);
493 kfree(mci->ctl_name);
494 edac_mc_free(mci);
495 }
496
497 static int skx_register_mci(struct skx_imc *imc)
498 {
499 struct mem_ctl_info *mci;
500 struct edac_mc_layer layers[2];
501 struct pci_dev *pdev = imc->chan[0].cdev;
502 struct skx_pvt *pvt;
503 int rc;
504
505 /* allocate a new MC control structure */
506 layers[0].type = EDAC_MC_LAYER_CHANNEL;
507 layers[0].size = NUM_CHANNELS;
508 layers[0].is_virt_csrow = false;
509 layers[1].type = EDAC_MC_LAYER_SLOT;
510 layers[1].size = NUM_DIMMS;
511 layers[1].is_virt_csrow = true;
512 mci = edac_mc_alloc(imc->mc, ARRAY_SIZE(layers), layers,
513 sizeof(struct skx_pvt));
514
515 if (unlikely(!mci))
516 return -ENOMEM;
517
518 edac_dbg(0, "MC#%d: mci = %p\n", imc->mc, mci);
519
520 /* Associate skx_dev and mci for future usage */
521 imc->mci = mci;
522 pvt = mci->pvt_info;
523 pvt->imc = imc;
524
525 mci->ctl_name = kasprintf(GFP_KERNEL, "Skylake Socket#%d IMC#%d",
526 imc->node_id, imc->lmc);
527 if (!mci->ctl_name) {
528 rc = -ENOMEM;
529 goto fail0;
530 }
531
532 mci->mtype_cap = MEM_FLAG_DDR4 | MEM_FLAG_NVDIMM;
533 mci->edac_ctl_cap = EDAC_FLAG_NONE;
534 mci->edac_cap = EDAC_FLAG_NONE;
535 mci->mod_name = EDAC_MOD_STR;
536 mci->dev_name = pci_name(imc->chan[0].cdev);
537 mci->ctl_page_to_phys = NULL;
538
539 rc = skx_get_dimm_config(mci);
540 if (rc < 0)
541 goto fail;
542
543 /* record ptr to the generic device */
544 mci->pdev = &pdev->dev;
545
546 /* add this new MC control structure to EDAC's list of MCs */
547 if (unlikely(edac_mc_add_mc(mci))) {
548 edac_dbg(0, "MC: failed edac_mc_add_mc()\n");
549 rc = -EINVAL;
550 goto fail;
551 }
552
553 return 0;
554
555 fail:
556 kfree(mci->ctl_name);
557 fail0:
558 edac_mc_free(mci);
559 imc->mci = NULL;
560 return rc;
561 }
562
563 #define SKX_MAX_SAD 24
564
565 #define SKX_GET_SAD(d, i, reg) \
566 pci_read_config_dword((d)->sad_all, 0x60 + 8 * (i), &reg)
567 #define SKX_GET_ILV(d, i, reg) \
568 pci_read_config_dword((d)->sad_all, 0x64 + 8 * (i), &reg)
569
570 #define SKX_SAD_MOD3MODE(sad) GET_BITFIELD((sad), 30, 31)
571 #define SKX_SAD_MOD3(sad) GET_BITFIELD((sad), 27, 27)
572 #define SKX_SAD_LIMIT(sad) (((u64)GET_BITFIELD((sad), 7, 26) << 26) | MASK26)
573 #define SKX_SAD_MOD3ASMOD2(sad) GET_BITFIELD((sad), 5, 6)
574 #define SKX_SAD_ATTR(sad) GET_BITFIELD((sad), 3, 4)
575 #define SKX_SAD_INTERLEAVE(sad) GET_BITFIELD((sad), 1, 2)
576 #define SKX_SAD_ENABLE(sad) GET_BITFIELD((sad), 0, 0)
577
578 #define SKX_ILV_REMOTE(tgt) (((tgt) & 8) == 0)
579 #define SKX_ILV_TARGET(tgt) ((tgt) & 7)
580
581 static bool skx_sad_decode(struct decoded_addr *res)
582 {
583 struct skx_dev *d = list_first_entry(&skx_edac_list, typeof(*d), list);
584 u64 addr = res->addr;
585 int i, idx, tgt, lchan, shift;
586 u32 sad, ilv;
587 u64 limit, prev_limit;
588 int remote = 0;
589
590 /* Simple sanity check for I/O space or out of range */
591 if (addr >= skx_tohm || (addr >= skx_tolm && addr < BIT_ULL(32))) {
592 edac_dbg(0, "Address %llx out of range\n", addr);
593 return false;
594 }
595
596 restart:
597 prev_limit = 0;
598 for (i = 0; i < SKX_MAX_SAD; i++) {
599 SKX_GET_SAD(d, i, sad);
600 limit = SKX_SAD_LIMIT(sad);
601 if (SKX_SAD_ENABLE(sad)) {
602 if (addr >= prev_limit && addr <= limit)
603 goto sad_found;
604 }
605 prev_limit = limit + 1;
606 }
607 edac_dbg(0, "No SAD entry for %llx\n", addr);
608 return false;
609
610 sad_found:
611 SKX_GET_ILV(d, i, ilv);
612
613 switch (SKX_SAD_INTERLEAVE(sad)) {
614 case 0:
615 idx = GET_BITFIELD(addr, 6, 8);
616 break;
617 case 1:
618 idx = GET_BITFIELD(addr, 8, 10);
619 break;
620 case 2:
621 idx = GET_BITFIELD(addr, 12, 14);
622 break;
623 case 3:
624 idx = GET_BITFIELD(addr, 30, 32);
625 break;
626 }
627
628 tgt = GET_BITFIELD(ilv, 4 * idx, 4 * idx + 3);
629
630 /* If point to another node, find it and start over */
631 if (SKX_ILV_REMOTE(tgt)) {
632 if (remote) {
633 edac_dbg(0, "Double remote!\n");
634 return false;
635 }
636 remote = 1;
637 list_for_each_entry(d, &skx_edac_list, list) {
638 if (d->imc[0].src_id == SKX_ILV_TARGET(tgt))
639 goto restart;
640 }
641 edac_dbg(0, "Can't find node %d\n", SKX_ILV_TARGET(tgt));
642 return false;
643 }
644
645 if (SKX_SAD_MOD3(sad) == 0)
646 lchan = SKX_ILV_TARGET(tgt);
647 else {
648 switch (SKX_SAD_MOD3MODE(sad)) {
649 case 0:
650 shift = 6;
651 break;
652 case 1:
653 shift = 8;
654 break;
655 case 2:
656 shift = 12;
657 break;
658 default:
659 edac_dbg(0, "illegal mod3mode\n");
660 return false;
661 }
662 switch (SKX_SAD_MOD3ASMOD2(sad)) {
663 case 0:
664 lchan = (addr >> shift) % 3;
665 break;
666 case 1:
667 lchan = (addr >> shift) % 2;
668 break;
669 case 2:
670 lchan = (addr >> shift) % 2;
671 lchan = (lchan << 1) | ~lchan;
672 break;
673 case 3:
674 lchan = ((addr >> shift) % 2) << 1;
675 break;
676 }
677 lchan = (lchan << 1) | (SKX_ILV_TARGET(tgt) & 1);
678 }
679
680 res->dev = d;
681 res->socket = d->imc[0].src_id;
682 res->imc = GET_BITFIELD(d->mcroute, lchan * 3, lchan * 3 + 2);
683 res->channel = GET_BITFIELD(d->mcroute, lchan * 2 + 18, lchan * 2 + 19);
684
685 edac_dbg(2, "%llx: socket=%d imc=%d channel=%d\n",
686 res->addr, res->socket, res->imc, res->channel);
687 return true;
688 }
689
690 #define SKX_MAX_TAD 8
691
692 #define SKX_GET_TADBASE(d, mc, i, reg) \
693 pci_read_config_dword((d)->imc[mc].chan[0].cdev, 0x850 + 4 * (i), &reg)
694 #define SKX_GET_TADWAYNESS(d, mc, i, reg) \
695 pci_read_config_dword((d)->imc[mc].chan[0].cdev, 0x880 + 4 * (i), &reg)
696 #define SKX_GET_TADCHNILVOFFSET(d, mc, ch, i, reg) \
697 pci_read_config_dword((d)->imc[mc].chan[ch].cdev, 0x90 + 4 * (i), &reg)
698
699 #define SKX_TAD_BASE(b) ((u64)GET_BITFIELD((b), 12, 31) << 26)
700 #define SKX_TAD_SKT_GRAN(b) GET_BITFIELD((b), 4, 5)
701 #define SKX_TAD_CHN_GRAN(b) GET_BITFIELD((b), 6, 7)
702 #define SKX_TAD_LIMIT(b) (((u64)GET_BITFIELD((b), 12, 31) << 26) | MASK26)
703 #define SKX_TAD_OFFSET(b) ((u64)GET_BITFIELD((b), 4, 23) << 26)
704 #define SKX_TAD_SKTWAYS(b) (1 << GET_BITFIELD((b), 10, 11))
705 #define SKX_TAD_CHNWAYS(b) (GET_BITFIELD((b), 8, 9) + 1)
706
707 /* which bit used for both socket and channel interleave */
708 static int skx_granularity[] = { 6, 8, 12, 30 };
709
710 static u64 skx_do_interleave(u64 addr, int shift, int ways, u64 lowbits)
711 {
712 addr >>= shift;
713 addr /= ways;
714 addr <<= shift;
715
716 return addr | (lowbits & ((1ull << shift) - 1));
717 }
718
719 static bool skx_tad_decode(struct decoded_addr *res)
720 {
721 int i;
722 u32 base, wayness, chnilvoffset;
723 int skt_interleave_bit, chn_interleave_bit;
724 u64 channel_addr;
725
726 for (i = 0; i < SKX_MAX_TAD; i++) {
727 SKX_GET_TADBASE(res->dev, res->imc, i, base);
728 SKX_GET_TADWAYNESS(res->dev, res->imc, i, wayness);
729 if (SKX_TAD_BASE(base) <= res->addr && res->addr <= SKX_TAD_LIMIT(wayness))
730 goto tad_found;
731 }
732 edac_dbg(0, "No TAD entry for %llx\n", res->addr);
733 return false;
734
735 tad_found:
736 res->sktways = SKX_TAD_SKTWAYS(wayness);
737 res->chanways = SKX_TAD_CHNWAYS(wayness);
738 skt_interleave_bit = skx_granularity[SKX_TAD_SKT_GRAN(base)];
739 chn_interleave_bit = skx_granularity[SKX_TAD_CHN_GRAN(base)];
740
741 SKX_GET_TADCHNILVOFFSET(res->dev, res->imc, res->channel, i, chnilvoffset);
742 channel_addr = res->addr - SKX_TAD_OFFSET(chnilvoffset);
743
744 if (res->chanways == 3 && skt_interleave_bit > chn_interleave_bit) {
745 /* Must handle channel first, then socket */
746 channel_addr = skx_do_interleave(channel_addr, chn_interleave_bit,
747 res->chanways, channel_addr);
748 channel_addr = skx_do_interleave(channel_addr, skt_interleave_bit,
749 res->sktways, channel_addr);
750 } else {
751 /* Handle socket then channel. Preserve low bits from original address */
752 channel_addr = skx_do_interleave(channel_addr, skt_interleave_bit,
753 res->sktways, res->addr);
754 channel_addr = skx_do_interleave(channel_addr, chn_interleave_bit,
755 res->chanways, res->addr);
756 }
757
758 res->chan_addr = channel_addr;
759
760 edac_dbg(2, "%llx: chan_addr=%llx sktways=%d chanways=%d\n",
761 res->addr, res->chan_addr, res->sktways, res->chanways);
762 return true;
763 }
764
765 #define SKX_MAX_RIR 4
766
767 #define SKX_GET_RIRWAYNESS(d, mc, ch, i, reg) \
768 pci_read_config_dword((d)->imc[mc].chan[ch].cdev, \
769 0x108 + 4 * (i), &reg)
770 #define SKX_GET_RIRILV(d, mc, ch, idx, i, reg) \
771 pci_read_config_dword((d)->imc[mc].chan[ch].cdev, \
772 0x120 + 16 * idx + 4 * (i), &reg)
773
774 #define SKX_RIR_VALID(b) GET_BITFIELD((b), 31, 31)
775 #define SKX_RIR_LIMIT(b) (((u64)GET_BITFIELD((b), 1, 11) << 29) | MASK29)
776 #define SKX_RIR_WAYS(b) (1 << GET_BITFIELD((b), 28, 29))
777 #define SKX_RIR_CHAN_RANK(b) GET_BITFIELD((b), 16, 19)
778 #define SKX_RIR_OFFSET(b) ((u64)(GET_BITFIELD((b), 2, 15) << 26))
779
780 static bool skx_rir_decode(struct decoded_addr *res)
781 {
782 int i, idx, chan_rank;
783 int shift;
784 u32 rirway, rirlv;
785 u64 rank_addr, prev_limit = 0, limit;
786
787 if (res->dev->imc[res->imc].chan[res->channel].dimms[0].close_pg)
788 shift = 6;
789 else
790 shift = 13;
791
792 for (i = 0; i < SKX_MAX_RIR; i++) {
793 SKX_GET_RIRWAYNESS(res->dev, res->imc, res->channel, i, rirway);
794 limit = SKX_RIR_LIMIT(rirway);
795 if (SKX_RIR_VALID(rirway)) {
796 if (prev_limit <= res->chan_addr &&
797 res->chan_addr <= limit)
798 goto rir_found;
799 }
800 prev_limit = limit;
801 }
802 edac_dbg(0, "No RIR entry for %llx\n", res->addr);
803 return false;
804
805 rir_found:
806 rank_addr = res->chan_addr >> shift;
807 rank_addr /= SKX_RIR_WAYS(rirway);
808 rank_addr <<= shift;
809 rank_addr |= res->chan_addr & GENMASK_ULL(shift - 1, 0);
810
811 res->rank_address = rank_addr;
812 idx = (res->chan_addr >> shift) % SKX_RIR_WAYS(rirway);
813
814 SKX_GET_RIRILV(res->dev, res->imc, res->channel, idx, i, rirlv);
815 res->rank_address = rank_addr - SKX_RIR_OFFSET(rirlv);
816 chan_rank = SKX_RIR_CHAN_RANK(rirlv);
817 res->channel_rank = chan_rank;
818 res->dimm = chan_rank / 4;
819 res->rank = chan_rank % 4;
820
821 edac_dbg(2, "%llx: dimm=%d rank=%d chan_rank=%d rank_addr=%llx\n",
822 res->addr, res->dimm, res->rank,
823 res->channel_rank, res->rank_address);
824 return true;
825 }
826
827 static u8 skx_close_row[] = {
828 15, 16, 17, 18, 20, 21, 22, 28, 10, 11, 12, 13, 29, 30, 31, 32, 33
829 };
830 static u8 skx_close_column[] = {
831 3, 4, 5, 14, 19, 23, 24, 25, 26, 27
832 };
833 static u8 skx_open_row[] = {
834 14, 15, 16, 20, 28, 21, 22, 23, 24, 25, 26, 27, 29, 30, 31, 32, 33
835 };
836 static u8 skx_open_column[] = {
837 3, 4, 5, 6, 7, 8, 9, 10, 11, 12
838 };
839 static u8 skx_open_fine_column[] = {
840 3, 4, 5, 7, 8, 9, 10, 11, 12, 13
841 };
842
843 static int skx_bits(u64 addr, int nbits, u8 *bits)
844 {
845 int i, res = 0;
846
847 for (i = 0; i < nbits; i++)
848 res |= ((addr >> bits[i]) & 1) << i;
849 return res;
850 }
851
852 static int skx_bank_bits(u64 addr, int b0, int b1, int do_xor, int x0, int x1)
853 {
854 int ret = GET_BITFIELD(addr, b0, b0) | (GET_BITFIELD(addr, b1, b1) << 1);
855
856 if (do_xor)
857 ret ^= GET_BITFIELD(addr, x0, x0) | (GET_BITFIELD(addr, x1, x1) << 1);
858
859 return ret;
860 }
861
862 static bool skx_mad_decode(struct decoded_addr *r)
863 {
864 struct skx_dimm *dimm = &r->dev->imc[r->imc].chan[r->channel].dimms[r->dimm];
865 int bg0 = dimm->fine_grain_bank ? 6 : 13;
866
867 if (dimm->close_pg) {
868 r->row = skx_bits(r->rank_address, dimm->rowbits, skx_close_row);
869 r->column = skx_bits(r->rank_address, dimm->colbits, skx_close_column);
870 r->column |= 0x400; /* C10 is autoprecharge, always set */
871 r->bank_address = skx_bank_bits(r->rank_address, 8, 9, dimm->bank_xor_enable, 22, 28);
872 r->bank_group = skx_bank_bits(r->rank_address, 6, 7, dimm->bank_xor_enable, 20, 21);
873 } else {
874 r->row = skx_bits(r->rank_address, dimm->rowbits, skx_open_row);
875 if (dimm->fine_grain_bank)
876 r->column = skx_bits(r->rank_address, dimm->colbits, skx_open_fine_column);
877 else
878 r->column = skx_bits(r->rank_address, dimm->colbits, skx_open_column);
879 r->bank_address = skx_bank_bits(r->rank_address, 18, 19, dimm->bank_xor_enable, 22, 23);
880 r->bank_group = skx_bank_bits(r->rank_address, bg0, 17, dimm->bank_xor_enable, 20, 21);
881 }
882 r->row &= (1u << dimm->rowbits) - 1;
883
884 edac_dbg(2, "%llx: row=%x col=%x bank_addr=%d bank_group=%d\n",
885 r->addr, r->row, r->column, r->bank_address,
886 r->bank_group);
887 return true;
888 }
889
890 static bool skx_decode(struct decoded_addr *res)
891 {
892
893 return skx_sad_decode(res) && skx_tad_decode(res) &&
894 skx_rir_decode(res) && skx_mad_decode(res);
895 }
896
897 #ifdef CONFIG_EDAC_DEBUG
898 /*
899 * Debug feature. Make /sys/kernel/debug/skx_edac_test/addr.
900 * Write an address to this file to exercise the address decode
901 * logic in this driver.
902 */
903 static struct dentry *skx_test;
904 static u64 skx_fake_addr;
905
906 static int debugfs_u64_set(void *data, u64 val)
907 {
908 struct decoded_addr res;
909
910 res.addr = val;
911 skx_decode(&res);
912
913 return 0;
914 }
915
916 DEFINE_SIMPLE_ATTRIBUTE(fops_u64_wo, NULL, debugfs_u64_set, "%llu\n");
917
918 static struct dentry *mydebugfs_create(const char *name, umode_t mode,
919 struct dentry *parent, u64 *value)
920 {
921 return debugfs_create_file(name, mode, parent, value, &fops_u64_wo);
922 }
923
924 static void setup_skx_debug(void)
925 {
926 skx_test = debugfs_create_dir("skx_edac_test", NULL);
927 mydebugfs_create("addr", S_IWUSR, skx_test, &skx_fake_addr);
928 }
929
930 static void teardown_skx_debug(void)
931 {
932 debugfs_remove_recursive(skx_test);
933 }
934 #else
935 static void setup_skx_debug(void)
936 {
937 }
938
939 static void teardown_skx_debug(void)
940 {
941 }
942 #endif /*CONFIG_EDAC_DEBUG*/
943
944 static void skx_mce_output_error(struct mem_ctl_info *mci,
945 const struct mce *m,
946 struct decoded_addr *res)
947 {
948 enum hw_event_mc_err_type tp_event;
949 char *type, *optype, msg[256];
950 bool ripv = GET_BITFIELD(m->mcgstatus, 0, 0);
951 bool overflow = GET_BITFIELD(m->status, 62, 62);
952 bool uncorrected_error = GET_BITFIELD(m->status, 61, 61);
953 bool recoverable;
954 u32 core_err_cnt = GET_BITFIELD(m->status, 38, 52);
955 u32 mscod = GET_BITFIELD(m->status, 16, 31);
956 u32 errcode = GET_BITFIELD(m->status, 0, 15);
957 u32 optypenum = GET_BITFIELD(m->status, 4, 6);
958
959 recoverable = GET_BITFIELD(m->status, 56, 56);
960
961 if (uncorrected_error) {
962 if (ripv) {
963 type = "FATAL";
964 tp_event = HW_EVENT_ERR_FATAL;
965 } else {
966 type = "NON_FATAL";
967 tp_event = HW_EVENT_ERR_UNCORRECTED;
968 }
969 } else {
970 type = "CORRECTED";
971 tp_event = HW_EVENT_ERR_CORRECTED;
972 }
973
974 /*
975 * According with Table 15-9 of the Intel Architecture spec vol 3A,
976 * memory errors should fit in this mask:
977 * 000f 0000 1mmm cccc (binary)
978 * where:
979 * f = Correction Report Filtering Bit. If 1, subsequent errors
980 * won't be shown
981 * mmm = error type
982 * cccc = channel
983 * If the mask doesn't match, report an error to the parsing logic
984 */
985 if (!((errcode & 0xef80) == 0x80)) {
986 optype = "Can't parse: it is not a mem";
987 } else {
988 switch (optypenum) {
989 case 0:
990 optype = "generic undef request error";
991 break;
992 case 1:
993 optype = "memory read error";
994 break;
995 case 2:
996 optype = "memory write error";
997 break;
998 case 3:
999 optype = "addr/cmd error";
1000 break;
1001 case 4:
1002 optype = "memory scrubbing error";
1003 break;
1004 default:
1005 optype = "reserved";
1006 break;
1007 }
1008 }
1009
1010 snprintf(msg, sizeof(msg),
1011 "%s%s err_code:%04x:%04x socket:%d imc:%d rank:%d bg:%d ba:%d row:%x col:%x",
1012 overflow ? " OVERFLOW" : "",
1013 (uncorrected_error && recoverable) ? " recoverable" : "",
1014 mscod, errcode,
1015 res->socket, res->imc, res->rank,
1016 res->bank_group, res->bank_address, res->row, res->column);
1017
1018 edac_dbg(0, "%s\n", msg);
1019
1020 /* Call the helper to output message */
1021 edac_mc_handle_error(tp_event, mci, core_err_cnt,
1022 m->addr >> PAGE_SHIFT, m->addr & ~PAGE_MASK, 0,
1023 res->channel, res->dimm, -1,
1024 optype, msg);
1025 }
1026
1027 static int skx_mce_check_error(struct notifier_block *nb, unsigned long val,
1028 void *data)
1029 {
1030 struct mce *mce = (struct mce *)data;
1031 struct decoded_addr res;
1032 struct mem_ctl_info *mci;
1033 char *type;
1034
1035 if (edac_get_report_status() == EDAC_REPORTING_DISABLED)
1036 return NOTIFY_DONE;
1037
1038 /* ignore unless this is memory related with an address */
1039 if ((mce->status & 0xefff) >> 7 != 1 || !(mce->status & MCI_STATUS_ADDRV))
1040 return NOTIFY_DONE;
1041
1042 res.addr = mce->addr;
1043 if (!skx_decode(&res))
1044 return NOTIFY_DONE;
1045 mci = res.dev->imc[res.imc].mci;
1046
1047 if (mce->mcgstatus & MCG_STATUS_MCIP)
1048 type = "Exception";
1049 else
1050 type = "Event";
1051
1052 skx_mc_printk(mci, KERN_DEBUG, "HANDLING MCE MEMORY ERROR\n");
1053
1054 skx_mc_printk(mci, KERN_DEBUG, "CPU %d: Machine Check %s: %Lx "
1055 "Bank %d: %016Lx\n", mce->extcpu, type,
1056 mce->mcgstatus, mce->bank, mce->status);
1057 skx_mc_printk(mci, KERN_DEBUG, "TSC %llx ", mce->tsc);
1058 skx_mc_printk(mci, KERN_DEBUG, "ADDR %llx ", mce->addr);
1059 skx_mc_printk(mci, KERN_DEBUG, "MISC %llx ", mce->misc);
1060
1061 skx_mc_printk(mci, KERN_DEBUG, "PROCESSOR %u:%x TIME %llu SOCKET "
1062 "%u APIC %x\n", mce->cpuvendor, mce->cpuid,
1063 mce->time, mce->socketid, mce->apicid);
1064
1065 skx_mce_output_error(mci, mce, &res);
1066
1067 return NOTIFY_DONE;
1068 }
1069
1070 static struct notifier_block skx_mce_dec = {
1071 .notifier_call = skx_mce_check_error,
1072 .priority = MCE_PRIO_EDAC,
1073 };
1074
1075 static void skx_remove(void)
1076 {
1077 int i, j;
1078 struct skx_dev *d, *tmp;
1079
1080 edac_dbg(0, "\n");
1081
1082 list_for_each_entry_safe(d, tmp, &skx_edac_list, list) {
1083 list_del(&d->list);
1084 for (i = 0; i < NUM_IMC; i++) {
1085 skx_unregister_mci(&d->imc[i]);
1086 for (j = 0; j < NUM_CHANNELS; j++)
1087 pci_dev_put(d->imc[i].chan[j].cdev);
1088 }
1089 pci_dev_put(d->util_all);
1090 pci_dev_put(d->sad_all);
1091
1092 kfree(d);
1093 }
1094 }
1095
1096 /*
1097 * skx_init:
1098 * make sure we are running on the correct cpu model
1099 * search for all the devices we need
1100 * check which DIMMs are present.
1101 */
1102 static int __init skx_init(void)
1103 {
1104 const struct x86_cpu_id *id;
1105 const struct munit *m;
1106 const char *owner;
1107 int rc = 0, i;
1108 u8 mc = 0, src_id, node_id;
1109 struct skx_dev *d;
1110
1111 edac_dbg(2, "\n");
1112
1113 owner = edac_get_owner();
1114 if (owner && strncmp(owner, EDAC_MOD_STR, sizeof(EDAC_MOD_STR)))
1115 return -EBUSY;
1116
1117 id = x86_match_cpu(skx_cpuids);
1118 if (!id)
1119 return -ENODEV;
1120
1121 rc = skx_get_hi_lo();
1122 if (rc)
1123 return rc;
1124
1125 rc = get_all_bus_mappings();
1126 if (rc < 0)
1127 goto fail;
1128 if (rc == 0) {
1129 edac_dbg(2, "No memory controllers found\n");
1130 return -ENODEV;
1131 }
1132
1133 for (m = skx_all_munits; m->did; m++) {
1134 rc = get_all_munits(m);
1135 if (rc < 0)
1136 goto fail;
1137 if (rc != m->per_socket * skx_num_sockets) {
1138 edac_dbg(2, "Expected %d, got %d of %x\n",
1139 m->per_socket * skx_num_sockets, rc, m->did);
1140 rc = -ENODEV;
1141 goto fail;
1142 }
1143 }
1144
1145 list_for_each_entry(d, &skx_edac_list, list) {
1146 src_id = get_src_id(d);
1147 node_id = skx_get_node_id(d);
1148 edac_dbg(2, "src_id=%d node_id=%d\n", src_id, node_id);
1149 for (i = 0; i < NUM_IMC; i++) {
1150 d->imc[i].mc = mc++;
1151 d->imc[i].lmc = i;
1152 d->imc[i].src_id = src_id;
1153 d->imc[i].node_id = node_id;
1154 rc = skx_register_mci(&d->imc[i]);
1155 if (rc < 0)
1156 goto fail;
1157 }
1158 }
1159
1160 /* Ensure that the OPSTATE is set correctly for POLL or NMI */
1161 opstate_init();
1162
1163 setup_skx_debug();
1164
1165 mce_register_decode_chain(&skx_mce_dec);
1166
1167 return 0;
1168 fail:
1169 skx_remove();
1170 return rc;
1171 }
1172
1173 static void __exit skx_exit(void)
1174 {
1175 edac_dbg(2, "\n");
1176 mce_unregister_decode_chain(&skx_mce_dec);
1177 skx_remove();
1178 teardown_skx_debug();
1179 }
1180
1181 module_init(skx_init);
1182 module_exit(skx_exit);
1183
1184 module_param(edac_op_state, int, 0444);
1185 MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI");
1186
1187 MODULE_LICENSE("GPL v2");
1188 MODULE_AUTHOR("Tony Luck");
1189 MODULE_DESCRIPTION("MC Driver for Intel Skylake server processors");
Linux with added FPC-III support