drivers/platform/x86/intel_pmc_core.c

   1 /*
   2  * Intel Core SoC Power Management Controller Driver
   3  *
   4  * Copyright (c) 2016, Intel Corporation.
   5  * All Rights Reserved.
   6  *
   7  * Authors: Rajneesh Bhardwaj <rajneesh.bhardwaj@intel.com>
   8  *          Vishwanath Somayaji <vishwanath.somayaji@intel.com>
   9  *
  10  * This program is free software; you can redistribute it and/or modify it
  11  * under the terms and conditions of the GNU General Public License,
  12  * version 2, as published by the Free Software Foundation.
  13  *
  14  * This program is distributed in the hope it will be useful, but WITHOUT
  15  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  16  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  17  * more details.
  18  *
  19  */
  20
  21 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  22
  23 #include <linux/acpi.h>
  24 #include <linux/debugfs.h>
  25 #include <linux/delay.h>
  26 #include <linux/io.h>
  27 #include <linux/module.h>
  28 #include <linux/pci.h>
  29 #include <linux/uaccess.h>
  30
  31 #include <asm/cpu_device_id.h>
  32 #include <asm/intel-family.h>
  33
  34 #include "intel_pmc_core.h"
  35
  36 #define ICPU(model, data) \
  37         { X86_VENDOR_INTEL, 6, model, X86_FEATURE_MWAIT, (kernel_ulong_t)data }
  38
  39 static struct pmc_dev pmc;
  40
  41 static const struct pmc_bit_map spt_pll_map[] = {
  42         {"MIPI PLL",                    SPT_PMC_BIT_MPHY_CMN_LANE0},
  43         {"GEN2 USB2PCIE2 PLL",          SPT_PMC_BIT_MPHY_CMN_LANE1},
  44         {"DMIPCIE3 PLL",                SPT_PMC_BIT_MPHY_CMN_LANE2},
  45         {"SATA PLL",                    SPT_PMC_BIT_MPHY_CMN_LANE3},
  46         {},
  47 };
  48
  49 static const struct pmc_bit_map spt_mphy_map[] = {
  50         {"MPHY CORE LANE 0",           SPT_PMC_BIT_MPHY_LANE0},
  51         {"MPHY CORE LANE 1",           SPT_PMC_BIT_MPHY_LANE1},
  52         {"MPHY CORE LANE 2",           SPT_PMC_BIT_MPHY_LANE2},
  53         {"MPHY CORE LANE 3",           SPT_PMC_BIT_MPHY_LANE3},
  54         {"MPHY CORE LANE 4",           SPT_PMC_BIT_MPHY_LANE4},
  55         {"MPHY CORE LANE 5",           SPT_PMC_BIT_MPHY_LANE5},
  56         {"MPHY CORE LANE 6",           SPT_PMC_BIT_MPHY_LANE6},
  57         {"MPHY CORE LANE 7",           SPT_PMC_BIT_MPHY_LANE7},
  58         {"MPHY CORE LANE 8",           SPT_PMC_BIT_MPHY_LANE8},
  59         {"MPHY CORE LANE 9",           SPT_PMC_BIT_MPHY_LANE9},
  60         {"MPHY CORE LANE 10",          SPT_PMC_BIT_MPHY_LANE10},
  61         {"MPHY CORE LANE 11",          SPT_PMC_BIT_MPHY_LANE11},
  62         {"MPHY CORE LANE 12",          SPT_PMC_BIT_MPHY_LANE12},
  63         {"MPHY CORE LANE 13",          SPT_PMC_BIT_MPHY_LANE13},
  64         {"MPHY CORE LANE 14",          SPT_PMC_BIT_MPHY_LANE14},
  65         {"MPHY CORE LANE 15",          SPT_PMC_BIT_MPHY_LANE15},
  66         {},
  67 };
  68
  69 static const struct pmc_bit_map spt_pfear_map[] = {
  70         {"PMC",                         SPT_PMC_BIT_PMC},
  71         {"OPI-DMI",                     SPT_PMC_BIT_OPI},
  72         {"SPI / eSPI",                  SPT_PMC_BIT_SPI},
  73         {"XHCI",                        SPT_PMC_BIT_XHCI},
  74         {"SPA",                         SPT_PMC_BIT_SPA},
  75         {"SPB",                         SPT_PMC_BIT_SPB},
  76         {"SPC",                         SPT_PMC_BIT_SPC},
  77         {"GBE",                         SPT_PMC_BIT_GBE},
  78         {"SATA",                        SPT_PMC_BIT_SATA},
  79         {"HDA-PGD0",                    SPT_PMC_BIT_HDA_PGD0},
  80         {"HDA-PGD1",                    SPT_PMC_BIT_HDA_PGD1},
  81         {"HDA-PGD2",                    SPT_PMC_BIT_HDA_PGD2},
  82         {"HDA-PGD3",                    SPT_PMC_BIT_HDA_PGD3},
  83         {"RSVD",                        SPT_PMC_BIT_RSVD_0B},
  84         {"LPSS",                        SPT_PMC_BIT_LPSS},
  85         {"LPC",                         SPT_PMC_BIT_LPC},
  86         {"SMB",                         SPT_PMC_BIT_SMB},
  87         {"ISH",                         SPT_PMC_BIT_ISH},
  88         {"P2SB",                        SPT_PMC_BIT_P2SB},
  89         {"DFX",                         SPT_PMC_BIT_DFX},
  90         {"SCC",                         SPT_PMC_BIT_SCC},
  91         {"RSVD",                        SPT_PMC_BIT_RSVD_0C},
  92         {"FUSE",                        SPT_PMC_BIT_FUSE},
  93         {"CAMERA",                      SPT_PMC_BIT_CAMREA},
  94         {"RSVD",                        SPT_PMC_BIT_RSVD_0D},
  95         {"USB3-OTG",                    SPT_PMC_BIT_USB3_OTG},
  96         {"EXI",                         SPT_PMC_BIT_EXI},
  97         {"CSE",                         SPT_PMC_BIT_CSE},
  98         {"CSME_KVM",                    SPT_PMC_BIT_CSME_KVM},
  99         {"CSME_PMT",                    SPT_PMC_BIT_CSME_PMT},
 100         {"CSME_CLINK",                  SPT_PMC_BIT_CSME_CLINK},
 101         {"CSME_PTIO",                   SPT_PMC_BIT_CSME_PTIO},
 102         {"CSME_USBR",                   SPT_PMC_BIT_CSME_USBR},
 103         {"CSME_SUSRAM",                 SPT_PMC_BIT_CSME_SUSRAM},
 104         {"CSME_SMT",                    SPT_PMC_BIT_CSME_SMT},
 105         {"RSVD",                        SPT_PMC_BIT_RSVD_1A},
 106         {"CSME_SMS2",                   SPT_PMC_BIT_CSME_SMS2},
 107         {"CSME_SMS1",                   SPT_PMC_BIT_CSME_SMS1},
 108         {"CSME_RTC",                    SPT_PMC_BIT_CSME_RTC},
 109         {"CSME_PSF",                    SPT_PMC_BIT_CSME_PSF},
 110         {},
 111 };
 112
 113 static const struct pmc_reg_map spt_reg_map = {
 114         .pfear_sts = spt_pfear_map,
 115         .mphy_sts = spt_mphy_map,
 116         .pll_sts = spt_pll_map,
 117         .slp_s0_offset = SPT_PMC_SLP_S0_RES_COUNTER_OFFSET,
 118         .ltr_ignore_offset = SPT_PMC_LTR_IGNORE_OFFSET,
 119         .regmap_length = SPT_PMC_MMIO_REG_LEN,
 120         .ppfear0_offset = SPT_PMC_XRAM_PPFEAR0A,
 121         .ppfear_buckets = SPT_PPFEAR_NUM_ENTRIES,
 122         .pm_cfg_offset = SPT_PMC_PM_CFG_OFFSET,
 123         .pm_read_disable_bit = SPT_PMC_READ_DISABLE_BIT,
 124 };
 125
 126 /* Cannonlake: PGD PFET Enable Ack Status Register(s) bitmap */
 127 static const struct pmc_bit_map cnp_pfear_map[] = {
 128         {"PMC",                 BIT(0)},
 129         {"OPI-DMI",             BIT(1)},
 130         {"SPI/eSPI",            BIT(2)},
 131         {"XHCI",                BIT(3)},
 132         {"SPA",                 BIT(4)},
 133         {"SPB",                 BIT(5)},
 134         {"SPC",                 BIT(6)},
 135         {"GBE",                 BIT(7)},
 136
 137         {"SATA",                BIT(0)},
 138         {"HDA_PGD0",            BIT(1)},
 139         {"HDA_PGD1",            BIT(2)},
 140         {"HDA_PGD2",            BIT(3)},
 141         {"HDA_PGD3",            BIT(4)},
 142         {"SPD",                 BIT(5)},
 143         {"LPSS",                BIT(6)},
 144         {"LPC",                 BIT(7)},
 145
 146         {"SMB",                 BIT(0)},
 147         {"ISH",                 BIT(1)},
 148         {"P2SB",                BIT(2)},
 149         {"NPK_VNN",             BIT(3)},
 150         {"SDX",                 BIT(4)},
 151         {"SPE",                 BIT(5)},
 152         {"Fuse",                BIT(6)},
 153         {"Res_23",              BIT(7)},
 154
 155         {"CSME_FSC",            BIT(0)},
 156         {"USB3_OTG",            BIT(1)},
 157         {"EXI",                 BIT(2)},
 158         {"CSE",                 BIT(3)},
 159         {"csme_kvm",            BIT(4)},
 160         {"csme_pmt",            BIT(5)},
 161         {"csme_clink",          BIT(6)},
 162         {"csme_ptio",           BIT(7)},
 163
 164         {"csme_usbr",           BIT(0)},
 165         {"csme_susram",         BIT(1)},
 166         {"csme_smt1",           BIT(2)},
 167         {"CSME_SMT4",           BIT(3)},
 168         {"csme_sms2",           BIT(4)},
 169         {"csme_sms1",           BIT(5)},
 170         {"csme_rtc",            BIT(6)},
 171         {"csme_psf",            BIT(7)},
 172
 173         {"SBR0",                BIT(0)},
 174         {"SBR1",                BIT(1)},
 175         {"SBR2",                BIT(2)},
 176         {"SBR3",                BIT(3)},
 177         {"SBR4",                BIT(4)},
 178         {"SBR5",                BIT(5)},
 179         {"CSME_PECI",           BIT(6)},
 180         {"PSF1",                BIT(7)},
 181
 182         {"PSF2",                BIT(0)},
 183         {"PSF3",                BIT(1)},
 184         {"PSF4",                BIT(2)},
 185         {"CNVI",                BIT(3)},
 186         {"UFS0",                BIT(4)},
 187         {"EMMC",                BIT(5)},
 188         {"Res_6",               BIT(6)},
 189         {"SBR6",                BIT(7)},
 190
 191         {"SBR7",                BIT(0)},
 192         {"NPK_AON",             BIT(1)},
 193         {"HDA_PGD4",            BIT(2)},
 194         {"HDA_PGD5",            BIT(3)},
 195         {"HDA_PGD6",            BIT(4)},
 196         {}
 197 };
 198
 199 static const struct pmc_reg_map cnp_reg_map = {
 200         .pfear_sts = cnp_pfear_map,
 201         .slp_s0_offset = CNP_PMC_SLP_S0_RES_COUNTER_OFFSET,
 202         .ltr_ignore_offset = CNP_PMC_LTR_IGNORE_OFFSET,
 203         .regmap_length = CNP_PMC_MMIO_REG_LEN,
 204         .ppfear0_offset = CNP_PMC_HOST_PPFEAR0A,
 205         .ppfear_buckets = CNP_PPFEAR_NUM_ENTRIES,
 206         .pm_cfg_offset = CNP_PMC_PM_CFG_OFFSET,
 207         .pm_read_disable_bit = CNP_PMC_READ_DISABLE_BIT,
 208 };
 209
 210 static inline u8 pmc_core_reg_read_byte(struct pmc_dev *pmcdev, int offset)
 211 {
 212         return readb(pmcdev->regbase + offset);
 213 }
 214
 215 static inline u32 pmc_core_reg_read(struct pmc_dev *pmcdev, int reg_offset)
 216 {
 217         return readl(pmcdev->regbase + reg_offset);
 218 }
 219
 220 static inline void pmc_core_reg_write(struct pmc_dev *pmcdev, int
 221                                                         reg_offset, u32 val)
 222 {
 223         writel(val, pmcdev->regbase + reg_offset);
 224 }
 225
 226 static inline u32 pmc_core_adjust_slp_s0_step(u32 value)
 227 {
 228         return value * SPT_PMC_SLP_S0_RES_COUNTER_STEP;
 229 }
 230
 231 static int pmc_core_dev_state_get(void *data, u64 *val)
 232 {
 233         struct pmc_dev *pmcdev = data;
 234         const struct pmc_reg_map *map = pmcdev->map;
 235         u32 value;
 236
 237         value = pmc_core_reg_read(pmcdev, map->slp_s0_offset);
 238         *val = pmc_core_adjust_slp_s0_step(value);
 239
 240         return 0;
 241 }
 242
 243 DEFINE_DEBUGFS_ATTRIBUTE(pmc_core_dev_state, pmc_core_dev_state_get, NULL, "%llu\n");
 244
 245 static int pmc_core_check_read_lock_bit(void)
 246 {
 247         struct pmc_dev *pmcdev = &pmc;
 248         u32 value;
 249
 250         value = pmc_core_reg_read(pmcdev, pmcdev->map->pm_cfg_offset);
 251         return value & BIT(pmcdev->map->pm_read_disable_bit);
 252 }
 253
 254 #if IS_ENABLED(CONFIG_DEBUG_FS)
 255 static void pmc_core_display_map(struct seq_file *s, int index,
 256                                  u8 pf_reg, const struct pmc_bit_map *pf_map)
 257 {
 258         seq_printf(s, "PCH IP: %-2d - %-32s\tState: %s\n",
 259                    index, pf_map[index].name,
 260                    pf_map[index].bit_mask & pf_reg ? "Off" : "On");
 261 }
 262
 263 static int pmc_core_ppfear_sts_show(struct seq_file *s, void *unused)
 264 {
 265         struct pmc_dev *pmcdev = s->private;
 266         const struct pmc_bit_map *map = pmcdev->map->pfear_sts;
 267         u8 pf_regs[PPFEAR_MAX_NUM_ENTRIES];
 268         int index, iter;
 269
 270         iter = pmcdev->map->ppfear0_offset;
 271
 272         for (index = 0; index < pmcdev->map->ppfear_buckets &&
 273              index < PPFEAR_MAX_NUM_ENTRIES; index++, iter++)
 274                 pf_regs[index] = pmc_core_reg_read_byte(pmcdev, iter);
 275
 276         for (index = 0; map[index].name; index++)
 277                 pmc_core_display_map(s, index, pf_regs[index / 8], map);
 278
 279         return 0;
 280 }
 281
 282 static int pmc_core_ppfear_sts_open(struct inode *inode, struct file *file)
 283 {
 284         return single_open(file, pmc_core_ppfear_sts_show, inode->i_private);
 285 }
 286
 287 static const struct file_operations pmc_core_ppfear_ops = {
 288         .open           = pmc_core_ppfear_sts_open,
 289         .read           = seq_read,
 290         .llseek         = seq_lseek,
 291         .release        = single_release,
 292 };
 293
 294 /* This function should return link status, 0 means ready */
 295 static int pmc_core_mtpmc_link_status(void)
 296 {
 297         struct pmc_dev *pmcdev = &pmc;
 298         u32 value;
 299
 300         value = pmc_core_reg_read(pmcdev, SPT_PMC_PM_STS_OFFSET);
 301         return value & BIT(SPT_PMC_MSG_FULL_STS_BIT);
 302 }
 303
 304 static int pmc_core_send_msg(u32 *addr_xram)
 305 {
 306         struct pmc_dev *pmcdev = &pmc;
 307         u32 dest;
 308         int timeout;
 309
 310         for (timeout = NUM_RETRIES; timeout > 0; timeout--) {
 311                 if (pmc_core_mtpmc_link_status() == 0)
 312                         break;
 313                 msleep(5);
 314         }
 315
 316         if (timeout <= 0 && pmc_core_mtpmc_link_status())
 317                 return -EBUSY;
 318
 319         dest = (*addr_xram & MTPMC_MASK) | (1U << 1);
 320         pmc_core_reg_write(pmcdev, SPT_PMC_MTPMC_OFFSET, dest);
 321         return 0;
 322 }
 323
 324 static int pmc_core_mphy_pg_sts_show(struct seq_file *s, void *unused)
 325 {
 326         struct pmc_dev *pmcdev = s->private;
 327         const struct pmc_bit_map *map = pmcdev->map->mphy_sts;
 328         u32 mphy_core_reg_low, mphy_core_reg_high;
 329         u32 val_low, val_high;
 330         int index, err = 0;
 331
 332         if (pmcdev->pmc_xram_read_bit) {
 333                 seq_puts(s, "Access denied: please disable PMC_READ_DISABLE setting in BIOS.");
 334                 return 0;
 335         }
 336
 337         mphy_core_reg_low  = (SPT_PMC_MPHY_CORE_STS_0 << 16);
 338         mphy_core_reg_high = (SPT_PMC_MPHY_CORE_STS_1 << 16);
 339
 340         mutex_lock(&pmcdev->lock);
 341
 342         if (pmc_core_send_msg(&mphy_core_reg_low) != 0) {
 343                 err = -EBUSY;
 344                 goto out_unlock;
 345         }
 346
 347         msleep(10);
 348         val_low = pmc_core_reg_read(pmcdev, SPT_PMC_MFPMC_OFFSET);
 349
 350         if (pmc_core_send_msg(&mphy_core_reg_high) != 0) {
 351                 err = -EBUSY;
 352                 goto out_unlock;
 353         }
 354
 355         msleep(10);
 356         val_high = pmc_core_reg_read(pmcdev, SPT_PMC_MFPMC_OFFSET);
 357
 358         for (index = 0; map[index].name && index < 8; index++) {
 359                 seq_printf(s, "%-32s\tState: %s\n",
 360                            map[index].name,
 361                            map[index].bit_mask & val_low ? "Not power gated" :
 362                            "Power gated");
 363         }
 364
 365         for (index = 8; map[index].name; index++) {
 366                 seq_printf(s, "%-32s\tState: %s\n",
 367                            map[index].name,
 368                            map[index].bit_mask & val_high ? "Not power gated" :
 369                            "Power gated");
 370         }
 371
 372 out_unlock:
 373         mutex_unlock(&pmcdev->lock);
 374         return err;
 375 }
 376
 377 static int pmc_core_mphy_pg_sts_open(struct inode *inode, struct file *file)
 378 {
 379         return single_open(file, pmc_core_mphy_pg_sts_show, inode->i_private);
 380 }
 381
 382 static const struct file_operations pmc_core_mphy_pg_ops = {
 383         .open           = pmc_core_mphy_pg_sts_open,
 384         .read           = seq_read,
 385         .llseek         = seq_lseek,
 386         .release        = single_release,
 387 };
 388
 389 static int pmc_core_pll_show(struct seq_file *s, void *unused)
 390 {
 391         struct pmc_dev *pmcdev = s->private;
 392         const struct pmc_bit_map *map = pmcdev->map->pll_sts;
 393         u32 mphy_common_reg, val;
 394         int index, err = 0;
 395
 396         if (pmcdev->pmc_xram_read_bit) {
 397                 seq_puts(s, "Access denied: please disable PMC_READ_DISABLE setting in BIOS.");
 398                 return 0;
 399         }
 400
 401         mphy_common_reg  = (SPT_PMC_MPHY_COM_STS_0 << 16);
 402         mutex_lock(&pmcdev->lock);
 403
 404         if (pmc_core_send_msg(&mphy_common_reg) != 0) {
 405                 err = -EBUSY;
 406                 goto out_unlock;
 407         }
 408
 409         /* Observed PMC HW response latency for MTPMC-MFPMC is ~10 ms */
 410         msleep(10);
 411         val = pmc_core_reg_read(pmcdev, SPT_PMC_MFPMC_OFFSET);
 412
 413         for (index = 0; map[index].name ; index++) {
 414                 seq_printf(s, "%-32s\tState: %s\n",
 415                            map[index].name,
 416                            map[index].bit_mask & val ? "Active" : "Idle");
 417         }
 418
 419 out_unlock:
 420         mutex_unlock(&pmcdev->lock);
 421         return err;
 422 }
 423
 424 static int pmc_core_pll_open(struct inode *inode, struct file *file)
 425 {
 426         return single_open(file, pmc_core_pll_show, inode->i_private);
 427 }
 428
 429 static const struct file_operations pmc_core_pll_ops = {
 430         .open           = pmc_core_pll_open,
 431         .read           = seq_read,
 432         .llseek         = seq_lseek,
 433         .release        = single_release,
 434 };
 435
 436 static ssize_t pmc_core_ltr_ignore_write(struct file *file, const char __user
 437 *userbuf, size_t count, loff_t *ppos)
 438 {
 439         struct pmc_dev *pmcdev = &pmc;
 440         const struct pmc_reg_map *map = pmcdev->map;
 441         u32 val, buf_size, fd;
 442         int err = 0;
 443
 444         buf_size = count < 64 ? count : 64;
 445         mutex_lock(&pmcdev->lock);
 446
 447         if (kstrtou32_from_user(userbuf, buf_size, 10, &val)) {
 448                 err = -EFAULT;
 449                 goto out_unlock;
 450         }
 451
 452         if (val > NUM_IP_IGN_ALLOWED) {
 453                 err = -EINVAL;
 454                 goto out_unlock;
 455         }
 456
 457         fd = pmc_core_reg_read(pmcdev, map->ltr_ignore_offset);
 458         fd |= (1U << val);
 459         pmc_core_reg_write(pmcdev, map->ltr_ignore_offset, fd);
 460
 461 out_unlock:
 462         mutex_unlock(&pmcdev->lock);
 463         return err == 0 ? count : err;
 464 }
 465
 466 static int pmc_core_ltr_ignore_show(struct seq_file *s, void *unused)
 467 {
 468         return 0;
 469 }
 470
 471 static int pmc_core_ltr_ignore_open(struct inode *inode, struct file *file)
 472 {
 473         return single_open(file, pmc_core_ltr_ignore_show, inode->i_private);
 474 }
 475
 476 static const struct file_operations pmc_core_ltr_ignore_ops = {
 477         .open           = pmc_core_ltr_ignore_open,
 478         .read           = seq_read,
 479         .write          = pmc_core_ltr_ignore_write,
 480         .llseek         = seq_lseek,
 481         .release        = single_release,
 482 };
 483
 484 static void pmc_core_dbgfs_unregister(struct pmc_dev *pmcdev)
 485 {
 486         debugfs_remove_recursive(pmcdev->dbgfs_dir);
 487 }
 488
 489 static int pmc_core_dbgfs_register(struct pmc_dev *pmcdev)
 490 {
 491         struct dentry *dir;
 492
 493         dir = debugfs_create_dir("pmc_core", NULL);
 494         if (!dir)
 495                 return -ENOMEM;
 496
 497         pmcdev->dbgfs_dir = dir;
 498
 499         debugfs_create_file("slp_s0_residency_usec", 0444, dir, pmcdev,
 500                             &pmc_core_dev_state);
 501
 502         debugfs_create_file("pch_ip_power_gating_status", 0444, dir, pmcdev,
 503                             &pmc_core_ppfear_ops);
 504
 505         debugfs_create_file("ltr_ignore", 0644, dir, pmcdev,
 506                             &pmc_core_ltr_ignore_ops);
 507
 508         if (pmcdev->map->pll_sts)
 509                 debugfs_create_file("pll_status", 0444, dir, pmcdev,
 510                                     &pmc_core_pll_ops);
 511
 512         if (pmcdev->map->mphy_sts)
 513                 debugfs_create_file("mphy_core_lanes_power_gating_status",
 514                                     0444, dir, pmcdev,
 515                                     &pmc_core_mphy_pg_ops);
 516
 517         return 0;
 518 }
 519 #else
 520 static inline int pmc_core_dbgfs_register(struct pmc_dev *pmcdev)
 521 {
 522         return 0;
 523 }
 524
 525 static inline void pmc_core_dbgfs_unregister(struct pmc_dev *pmcdev)
 526 {
 527 }
 528 #endif /* CONFIG_DEBUG_FS */
 529
 530 static const struct x86_cpu_id intel_pmc_core_ids[] = {
 531         ICPU(INTEL_FAM6_SKYLAKE_MOBILE, &spt_reg_map),
 532         ICPU(INTEL_FAM6_SKYLAKE_DESKTOP, &spt_reg_map),
 533         ICPU(INTEL_FAM6_KABYLAKE_MOBILE, &spt_reg_map),
 534         ICPU(INTEL_FAM6_KABYLAKE_DESKTOP, &spt_reg_map),
 535         ICPU(INTEL_FAM6_CANNONLAKE_MOBILE, &cnp_reg_map),
 536         {}
 537 };
 538
 539 MODULE_DEVICE_TABLE(x86cpu, intel_pmc_core_ids);
 540
 541 static const struct pci_device_id pmc_pci_ids[] = {
 542         { PCI_VDEVICE(INTEL, SPT_PMC_PCI_DEVICE_ID), 0},
 543         { 0, },
 544 };
 545
 546 static int __init pmc_core_probe(void)
 547 {
 548         struct pmc_dev *pmcdev = &pmc;
 549         const struct x86_cpu_id *cpu_id;
 550         u64 slp_s0_addr;
 551         int err;
 552
 553         cpu_id = x86_match_cpu(intel_pmc_core_ids);
 554         if (!cpu_id)
 555                 return -ENODEV;
 556
 557         pmcdev->map = (struct pmc_reg_map *)cpu_id->driver_data;
 558
 559         /*
 560          * Coffeelake has CPU ID of Kabylake and Cannonlake PCH. So here
 561          * Sunrisepoint PCH regmap can't be used. Use Cannonlake PCH regmap
 562          * in this case.
 563          */
 564         if (!pci_dev_present(pmc_pci_ids))
 565                 pmcdev->map = &cnp_reg_map;
 566
 567         if (lpit_read_residency_count_address(&slp_s0_addr))
 568                 pmcdev->base_addr = PMC_BASE_ADDR_DEFAULT;
 569         else
 570                 pmcdev->base_addr = slp_s0_addr - pmcdev->map->slp_s0_offset;
 571
 572         pmcdev->regbase = ioremap(pmcdev->base_addr,
 573                                   pmcdev->map->regmap_length);
 574         if (!pmcdev->regbase)
 575                 return -ENOMEM;
 576
 577         mutex_init(&pmcdev->lock);
 578         pmcdev->pmc_xram_read_bit = pmc_core_check_read_lock_bit();
 579
 580         err = pmc_core_dbgfs_register(pmcdev);
 581         if (err < 0) {
 582                 pr_warn(" debugfs register failed.\n");
 583                 iounmap(pmcdev->regbase);
 584                 return err;
 585         }
 586
 587         pr_info(" initialized\n");
 588         return 0;
 589 }
 590 module_init(pmc_core_probe)
 591
 592 static void __exit pmc_core_remove(void)
 593 {
 594         struct pmc_dev *pmcdev = &pmc;
 595
 596         pmc_core_dbgfs_unregister(pmcdev);
 597         mutex_destroy(&pmcdev->lock);
 598         iounmap(pmcdev->regbase);
 599 }
 600 module_exit(pmc_core_remove)
 601
 602 MODULE_LICENSE("GPL v2");
 603 MODULE_DESCRIPTION("Intel PMC Core Driver");