drivers/iio/imu/inv_mpu6050/inv_mpu_iio.h

   1 /*
   2 * Copyright (C) 2012 Invensense, Inc.
   3 *
   4 * This software is licensed under the terms of the GNU General Public
   5 * License version 2, as published by the Free Software Foundation, and
   6 * may be copied, distributed, and modified under those terms.
   7 *
   8 * This program is distributed in the hope that it will be useful,
   9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11 * GNU General Public License for more details.
  12 */
  13 #include <linux/i2c.h>
  14 #include <linux/i2c-mux.h>
  15 #include <linux/mutex.h>
  16 #include <linux/iio/iio.h>
  17 #include <linux/iio/buffer.h>
  18 #include <linux/regmap.h>
  19 #include <linux/iio/sysfs.h>
  20 #include <linux/iio/kfifo_buf.h>
  21 #include <linux/iio/trigger.h>
  22 #include <linux/iio/triggered_buffer.h>
  23 #include <linux/iio/trigger_consumer.h>
  24 #include <linux/platform_data/invensense_mpu6050.h>
  25
  26 /**
  27  *  struct inv_mpu6050_reg_map - Notable registers.
  28  *  @sample_rate_div:   Divider applied to gyro output rate.
  29  *  @lpf:               Configures internal low pass filter.
  30  *  @accel_lpf:         Configures accelerometer low pass filter.
  31  *  @user_ctrl:         Enables/resets the FIFO.
  32  *  @fifo_en:           Determines which data will appear in FIFO.
  33  *  @gyro_config:       gyro config register.
  34  *  @accl_config:       accel config register
  35  *  @fifo_count_h:      Upper byte of FIFO count.
  36  *  @fifo_r_w:          FIFO register.
  37  *  @raw_gyro:          Address of first gyro register.
  38  *  @raw_accl:          Address of first accel register.
  39  *  @temperature:       temperature register
  40  *  @int_enable:        Interrupt enable register.
  41  *  @int_status:        Interrupt status register.
  42  *  @pwr_mgmt_1:        Controls chip's power state and clock source.
  43  *  @pwr_mgmt_2:        Controls power state of individual sensors.
  44  *  @int_pin_cfg;       Controls interrupt pin configuration.
  45  *  @accl_offset:       Controls the accelerometer calibration offset.
  46  *  @gyro_offset:       Controls the gyroscope calibration offset.
  47  */
  48 struct inv_mpu6050_reg_map {
  49         u8 sample_rate_div;
  50         u8 lpf;
  51         u8 accel_lpf;
  52         u8 user_ctrl;
  53         u8 fifo_en;
  54         u8 gyro_config;
  55         u8 accl_config;
  56         u8 fifo_count_h;
  57         u8 fifo_r_w;
  58         u8 raw_gyro;
  59         u8 raw_accl;
  60         u8 temperature;
  61         u8 int_enable;
  62         u8 int_status;
  63         u8 pwr_mgmt_1;
  64         u8 pwr_mgmt_2;
  65         u8 int_pin_cfg;
  66         u8 accl_offset;
  67         u8 gyro_offset;
  68 };
  69
  70 /*device enum */
  71 enum inv_devices {
  72         INV_MPU6050,
  73         INV_MPU6500,
  74         INV_MPU6515,
  75         INV_MPU6000,
  76         INV_MPU9150,
  77         INV_MPU9250,
  78         INV_MPU9255,
  79         INV_ICM20608,
  80         INV_NUM_PARTS
  81 };
  82
  83 /**
  84  *  struct inv_mpu6050_chip_config - Cached chip configuration data.
  85  *  @fsr:               Full scale range.
  86  *  @lpf:               Digital low pass filter frequency.
  87  *  @accl_fs:           accel full scale range.
  88  *  @accl_fifo_enable:  enable accel data output
  89  *  @gyro_fifo_enable:  enable gyro data output
  90  *  @divider:           chip sample rate divider (sample rate divider - 1)
  91  */
  92 struct inv_mpu6050_chip_config {
  93         unsigned int fsr:2;
  94         unsigned int lpf:3;
  95         unsigned int accl_fs:2;
  96         unsigned int accl_fifo_enable:1;
  97         unsigned int gyro_fifo_enable:1;
  98         u8 divider;
  99         u8 user_ctrl;
 100 };
 101
 102 /**
 103  *  struct inv_mpu6050_hw - Other important hardware information.
 104  *  @whoami:    Self identification byte from WHO_AM_I register
 105  *  @name:      name of the chip.
 106  *  @reg:   register map of the chip.
 107  *  @config:    configuration of the chip.
 108  */
 109 struct inv_mpu6050_hw {
 110         u8 whoami;
 111         u8 *name;
 112         const struct inv_mpu6050_reg_map *reg;
 113         const struct inv_mpu6050_chip_config *config;
 114 };
 115
 116 /*
 117  *  struct inv_mpu6050_state - Driver state variables.
 118  *  @lock:              Chip access lock.
 119  *  @trig:              IIO trigger.
 120  *  @chip_config:       Cached attribute information.
 121  *  @reg:               Map of important registers.
 122  *  @hw:                Other hardware-specific information.
 123  *  @chip_type:         chip type.
 124  *  @plat_data:         platform data (deprecated in favor of @orientation).
 125  *  @orientation:       sensor chip orientation relative to main hardware.
 126  *  @map                regmap pointer.
 127  *  @irq                interrupt number.
 128  *  @irq_mask           the int_pin_cfg mask to configure interrupt type.
 129  *  @chip_period:       chip internal period estimation (~1kHz).
 130  *  @it_timestamp:      timestamp from previous interrupt.
 131  *  @data_timestamp:    timestamp for next data sample.
 132  *  @vddio_supply       voltage regulator for the chip.
 133  */
 134 struct inv_mpu6050_state {
 135         struct mutex lock;
 136         struct iio_trigger  *trig;
 137         struct inv_mpu6050_chip_config chip_config;
 138         const struct inv_mpu6050_reg_map *reg;
 139         const struct inv_mpu6050_hw *hw;
 140         enum   inv_devices chip_type;
 141         struct i2c_mux_core *muxc;
 142         struct i2c_client *mux_client;
 143         unsigned int powerup_count;
 144         struct inv_mpu6050_platform_data plat_data;
 145         struct iio_mount_matrix orientation;
 146         struct regmap *map;
 147         int irq;
 148         u8 irq_mask;
 149         unsigned skip_samples;
 150         s64 chip_period;
 151         s64 it_timestamp;
 152         s64 data_timestamp;
 153         struct regulator *vddio_supply;
 154 };
 155
 156 /*register and associated bit definition*/
 157 #define INV_MPU6050_REG_ACCEL_OFFSET        0x06
 158 #define INV_MPU6050_REG_GYRO_OFFSET         0x13
 159
 160 #define INV_MPU6050_REG_SAMPLE_RATE_DIV     0x19
 161 #define INV_MPU6050_REG_CONFIG              0x1A
 162 #define INV_MPU6050_REG_GYRO_CONFIG         0x1B
 163 #define INV_MPU6050_REG_ACCEL_CONFIG        0x1C
 164
 165 #define INV_MPU6050_REG_FIFO_EN             0x23
 166 #define INV_MPU6050_BIT_ACCEL_OUT           0x08
 167 #define INV_MPU6050_BITS_GYRO_OUT           0x70
 168
 169 #define INV_MPU6050_REG_INT_ENABLE          0x38
 170 #define INV_MPU6050_BIT_DATA_RDY_EN         0x01
 171 #define INV_MPU6050_BIT_DMP_INT_EN          0x02
 172
 173 #define INV_MPU6050_REG_RAW_ACCEL           0x3B
 174 #define INV_MPU6050_REG_TEMPERATURE         0x41
 175 #define INV_MPU6050_REG_RAW_GYRO            0x43
 176
 177 #define INV_MPU6050_REG_INT_STATUS          0x3A
 178 #define INV_MPU6050_BIT_FIFO_OVERFLOW_INT   0x10
 179 #define INV_MPU6050_BIT_RAW_DATA_RDY_INT    0x01
 180
 181 #define INV_MPU6050_REG_USER_CTRL           0x6A
 182 #define INV_MPU6050_BIT_FIFO_RST            0x04
 183 #define INV_MPU6050_BIT_DMP_RST             0x08
 184 #define INV_MPU6050_BIT_I2C_MST_EN          0x20
 185 #define INV_MPU6050_BIT_FIFO_EN             0x40
 186 #define INV_MPU6050_BIT_DMP_EN              0x80
 187 #define INV_MPU6050_BIT_I2C_IF_DIS          0x10
 188
 189 #define INV_MPU6050_REG_PWR_MGMT_1          0x6B
 190 #define INV_MPU6050_BIT_H_RESET             0x80
 191 #define INV_MPU6050_BIT_SLEEP               0x40
 192 #define INV_MPU6050_BIT_CLK_MASK            0x7
 193
 194 #define INV_MPU6050_REG_PWR_MGMT_2          0x6C
 195 #define INV_MPU6050_BIT_PWR_ACCL_STBY       0x38
 196 #define INV_MPU6050_BIT_PWR_GYRO_STBY       0x07
 197
 198 #define INV_MPU6050_REG_FIFO_COUNT_H        0x72
 199 #define INV_MPU6050_REG_FIFO_R_W            0x74
 200
 201 #define INV_MPU6050_BYTES_PER_3AXIS_SENSOR   6
 202 #define INV_MPU6050_FIFO_COUNT_BYTE          2
 203
 204 /* mpu6500 registers */
 205 #define INV_MPU6500_REG_ACCEL_CONFIG_2      0x1D
 206 #define INV_MPU6500_REG_ACCEL_OFFSET        0x77
 207
 208 /* delay time in milliseconds */
 209 #define INV_MPU6050_POWER_UP_TIME            100
 210 #define INV_MPU6050_TEMP_UP_TIME             100
 211 #define INV_MPU6050_SENSOR_UP_TIME           30
 212
 213 /* delay time in microseconds */
 214 #define INV_MPU6050_REG_UP_TIME_MIN          5000
 215 #define INV_MPU6050_REG_UP_TIME_MAX          10000
 216
 217 #define INV_MPU6050_TEMP_OFFSET              12421
 218 #define INV_MPU6050_TEMP_SCALE               2941
 219 #define INV_MPU6050_MAX_GYRO_FS_PARAM        3
 220 #define INV_MPU6050_MAX_ACCL_FS_PARAM        3
 221 #define INV_MPU6050_THREE_AXIS               3
 222 #define INV_MPU6050_GYRO_CONFIG_FSR_SHIFT    3
 223 #define INV_MPU6050_ACCL_CONFIG_FSR_SHIFT    3
 224
 225 /* 6 + 6 round up and plus 8 */
 226 #define INV_MPU6050_OUTPUT_DATA_SIZE         24
 227
 228 #define INV_MPU6050_REG_INT_PIN_CFG     0x37
 229 #define INV_MPU6050_ACTIVE_HIGH         0x00
 230 #define INV_MPU6050_ACTIVE_LOW          0x80
 231 /* enable level triggering */
 232 #define INV_MPU6050_LATCH_INT_EN        0x20
 233 #define INV_MPU6050_BIT_BYPASS_EN       0x2
 234
 235 /* Allowed timestamp period jitter in percent */
 236 #define INV_MPU6050_TS_PERIOD_JITTER    4
 237
 238 /* init parameters */
 239 #define INV_MPU6050_INIT_FIFO_RATE           50
 240 #define INV_MPU6050_MAX_FIFO_RATE            1000
 241 #define INV_MPU6050_MIN_FIFO_RATE            4
 242
 243 /* chip internal frequency: 1KHz */
 244 #define INV_MPU6050_INTERNAL_FREQ_HZ            1000
 245 /* return the frequency divider (chip sample rate divider + 1) */
 246 #define INV_MPU6050_FREQ_DIVIDER(st)                                    \
 247         ((st)->chip_config.divider + 1)
 248 /* chip sample rate divider to fifo rate */
 249 #define INV_MPU6050_FIFO_RATE_TO_DIVIDER(fifo_rate)                     \
 250         ((INV_MPU6050_INTERNAL_FREQ_HZ / (fifo_rate)) - 1)
 251 #define INV_MPU6050_DIVIDER_TO_FIFO_RATE(divider)                       \
 252         (INV_MPU6050_INTERNAL_FREQ_HZ / ((divider) + 1))
 253
 254 #define INV_MPU6050_REG_WHOAMI                  117
 255
 256 #define INV_MPU6000_WHOAMI_VALUE                0x68
 257 #define INV_MPU6050_WHOAMI_VALUE                0x68
 258 #define INV_MPU6500_WHOAMI_VALUE                0x70
 259 #define INV_MPU9150_WHOAMI_VALUE                0x68
 260 #define INV_MPU9250_WHOAMI_VALUE                0x71
 261 #define INV_MPU9255_WHOAMI_VALUE                0x73
 262 #define INV_MPU6515_WHOAMI_VALUE                0x74
 263 #define INV_ICM20608_WHOAMI_VALUE               0xAF
 264
 265 /* scan element definition */
 266 enum inv_mpu6050_scan {
 267         INV_MPU6050_SCAN_ACCL_X,
 268         INV_MPU6050_SCAN_ACCL_Y,
 269         INV_MPU6050_SCAN_ACCL_Z,
 270         INV_MPU6050_SCAN_GYRO_X,
 271         INV_MPU6050_SCAN_GYRO_Y,
 272         INV_MPU6050_SCAN_GYRO_Z,
 273         INV_MPU6050_SCAN_TIMESTAMP,
 274 };
 275
 276 enum inv_mpu6050_filter_e {
 277         INV_MPU6050_FILTER_256HZ_NOLPF2 = 0,
 278         INV_MPU6050_FILTER_188HZ,
 279         INV_MPU6050_FILTER_98HZ,
 280         INV_MPU6050_FILTER_42HZ,
 281         INV_MPU6050_FILTER_20HZ,
 282         INV_MPU6050_FILTER_10HZ,
 283         INV_MPU6050_FILTER_5HZ,
 284         INV_MPU6050_FILTER_2100HZ_NOLPF,
 285         NUM_MPU6050_FILTER
 286 };
 287
 288 /* IIO attribute address */
 289 enum INV_MPU6050_IIO_ATTR_ADDR {
 290         ATTR_GYRO_MATRIX,
 291         ATTR_ACCL_MATRIX,
 292 };
 293
 294 enum inv_mpu6050_accl_fs_e {
 295         INV_MPU6050_FS_02G = 0,
 296         INV_MPU6050_FS_04G,
 297         INV_MPU6050_FS_08G,
 298         INV_MPU6050_FS_16G,
 299         NUM_ACCL_FSR
 300 };
 301
 302 enum inv_mpu6050_fsr_e {
 303         INV_MPU6050_FSR_250DPS = 0,
 304         INV_MPU6050_FSR_500DPS,
 305         INV_MPU6050_FSR_1000DPS,
 306         INV_MPU6050_FSR_2000DPS,
 307         NUM_MPU6050_FSR
 308 };
 309
 310 enum inv_mpu6050_clock_sel_e {
 311         INV_CLK_INTERNAL = 0,
 312         INV_CLK_PLL,
 313         NUM_CLK
 314 };
 315
 316 irqreturn_t inv_mpu6050_read_fifo(int irq, void *p);
 317 int inv_mpu6050_probe_trigger(struct iio_dev *indio_dev, int irq_type);
 318 int inv_reset_fifo(struct iio_dev *indio_dev);
 319 int inv_mpu6050_switch_engine(struct inv_mpu6050_state *st, bool en, u32 mask);
 320 int inv_mpu6050_write_reg(struct inv_mpu6050_state *st, int reg, u8 val);
 321 int inv_mpu6050_set_power_itg(struct inv_mpu6050_state *st, bool power_on);
 322 int inv_mpu_acpi_create_mux_client(struct i2c_client *client);
 323 void inv_mpu_acpi_delete_mux_client(struct i2c_client *client);
 324 int inv_mpu_core_probe(struct regmap *regmap, int irq, const char *name,
 325                 int (*inv_mpu_bus_setup)(struct iio_dev *), int chip_type);
 326 extern const struct dev_pm_ops inv_mpu_pmops;