drivers/usb/c67x00/c67x00.h

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * c67x00.h: Cypress C67X00 USB register and field definitions
   4  *
   5  * Copyright (C) 2006-2008 Barco N.V.
   6  *    Derived from the Cypress cy7c67200/300 ezusb linux driver and
   7  *    based on multiple host controller drivers inside the linux kernel.
   8  */
   9
  10 #ifndef _USB_C67X00_H
  11 #define _USB_C67X00_H
  12
  13 #include <linux/spinlock.h>
  14 #include <linux/platform_device.h>
  15 #include <linux/completion.h>
  16 #include <linux/mutex.h>
  17
  18 /* ---------------------------------------------------------------------
  19  * Cypress C67x00 register definitions
  20  */
  21
  22 /* Hardware Revision Register */
  23 #define HW_REV_REG              0xC004
  24
  25 /* General USB registers */
  26 /* ===================== */
  27
  28 /* USB Control Register */
  29 #define USB_CTL_REG(x)          ((x) ? 0xC0AA : 0xC08A)
  30
  31 #define LOW_SPEED_PORT(x)       ((x) ? 0x0800 : 0x0400)
  32 #define HOST_MODE               0x0200
  33 #define PORT_RES_EN(x)          ((x) ? 0x0100 : 0x0080)
  34 #define SOF_EOP_EN(x)           ((x) ? 0x0002 : 0x0001)
  35
  36 /* USB status register - Notice it has different content in hcd/udc mode */
  37 #define USB_STAT_REG(x)         ((x) ? 0xC0B0 : 0xC090)
  38
  39 #define EP0_IRQ_FLG             0x0001
  40 #define EP1_IRQ_FLG             0x0002
  41 #define EP2_IRQ_FLG             0x0004
  42 #define EP3_IRQ_FLG             0x0008
  43 #define EP4_IRQ_FLG             0x0010
  44 #define EP5_IRQ_FLG             0x0020
  45 #define EP6_IRQ_FLG             0x0040
  46 #define EP7_IRQ_FLG             0x0080
  47 #define RESET_IRQ_FLG           0x0100
  48 #define SOF_EOP_IRQ_FLG         0x0200
  49 #define ID_IRQ_FLG              0x4000
  50 #define VBUS_IRQ_FLG            0x8000
  51
  52 /* USB Host only registers */
  53 /* ======================= */
  54
  55 /* Host n Control Register */
  56 #define HOST_CTL_REG(x)         ((x) ? 0xC0A0 : 0xC080)
  57
  58 #define PREAMBLE_EN             0x0080  /* Preamble enable */
  59 #define SEQ_SEL                 0x0040  /* Data Toggle Sequence Bit Select */
  60 #define ISO_EN                  0x0010  /* Isochronous enable  */
  61 #define ARM_EN                  0x0001  /* Arm operation */
  62
  63 /* Host n Interrupt Enable Register */
  64 #define HOST_IRQ_EN_REG(x)      ((x) ? 0xC0AC : 0xC08C)
  65
  66 #define SOF_EOP_IRQ_EN          0x0200  /* SOF/EOP Interrupt Enable  */
  67 #define SOF_EOP_TMOUT_IRQ_EN    0x0800  /* SOF/EOP Timeout Interrupt Enable  */
  68 #define ID_IRQ_EN               0x4000  /* ID interrupt enable */
  69 #define VBUS_IRQ_EN             0x8000  /* VBUS interrupt enable */
  70 #define DONE_IRQ_EN             0x0001  /* Done Interrupt Enable  */
  71
  72 /* USB status register */
  73 #define HOST_STAT_MASK          0x02FD
  74 #define PORT_CONNECT_CHANGE(x)  ((x) ? 0x0020 : 0x0010)
  75 #define PORT_SE0_STATUS(x)      ((x) ? 0x0008 : 0x0004)
  76
  77 /* Host Frame Register */
  78 #define HOST_FRAME_REG(x)       ((x) ? 0xC0B6 : 0xC096)
  79
  80 #define HOST_FRAME_MASK         0x07FF
  81
  82 /* USB Peripheral only registers */
  83 /* ============================= */
  84
  85 /* Device n Port Sel reg */
  86 #define DEVICE_N_PORT_SEL(x)    ((x) ? 0xC0A4 : 0xC084)
  87
  88 /* Device n Interrupt Enable Register */
  89 #define DEVICE_N_IRQ_EN_REG(x)  ((x) ? 0xC0AC : 0xC08C)
  90
  91 #define DEVICE_N_ENDPOINT_N_CTL_REG(dev, ep)    ((dev)                  \
  92                                                  ? (0x0280 + (ep << 4)) \
  93                                                  : (0x0200 + (ep << 4)))
  94 #define DEVICE_N_ENDPOINT_N_STAT_REG(dev, ep)   ((dev)                  \
  95                                                  ? (0x0286 + (ep << 4)) \
  96                                                  : (0x0206 + (ep << 4)))
  97
  98 #define DEVICE_N_ADDRESS(dev)   ((dev) ? (0xC0AE) : (0xC08E))
  99
 100 /* HPI registers */
 101 /* ============= */
 102
 103 /* HPI Status register */
 104 #define SOFEOP_FLG(x)           (1 << ((x) ? 12 : 10))
 105 #define SIEMSG_FLG(x)           (1 << (4 + (x)))
 106 #define RESET_FLG(x)            ((x) ? 0x0200 : 0x0002)
 107 #define DONE_FLG(x)             (1 << (2 + (x)))
 108 #define RESUME_FLG(x)           (1 << (6 + (x)))
 109 #define MBX_OUT_FLG             0x0001  /* Message out available */
 110 #define MBX_IN_FLG              0x0100
 111 #define ID_FLG                  0x4000
 112 #define VBUS_FLG                0x8000
 113
 114 /* Interrupt routing register */
 115 #define HPI_IRQ_ROUTING_REG     0x0142
 116
 117 #define HPI_SWAP_ENABLE(x)      ((x) ? 0x0100 : 0x0001)
 118 #define RESET_TO_HPI_ENABLE(x)  ((x) ? 0x0200 : 0x0002)
 119 #define DONE_TO_HPI_ENABLE(x)   ((x) ? 0x0008 : 0x0004)
 120 #define RESUME_TO_HPI_ENABLE(x) ((x) ? 0x0080 : 0x0040)
 121 #define SOFEOP_TO_HPI_EN(x)     ((x) ? 0x2000 : 0x0800)
 122 #define SOFEOP_TO_CPU_EN(x)     ((x) ? 0x1000 : 0x0400)
 123 #define ID_TO_HPI_ENABLE        0x4000
 124 #define VBUS_TO_HPI_ENABLE      0x8000
 125
 126 /* SIE msg registers */
 127 #define SIEMSG_REG(x)           ((x) ? 0x0148 : 0x0144)
 128
 129 #define HUSB_TDListDone         0x1000
 130
 131 #define SUSB_EP0_MSG            0x0001
 132 #define SUSB_EP1_MSG            0x0002
 133 #define SUSB_EP2_MSG            0x0004
 134 #define SUSB_EP3_MSG            0x0008
 135 #define SUSB_EP4_MSG            0x0010
 136 #define SUSB_EP5_MSG            0x0020
 137 #define SUSB_EP6_MSG            0x0040
 138 #define SUSB_EP7_MSG            0x0080
 139 #define SUSB_RST_MSG            0x0100
 140 #define SUSB_SOF_MSG            0x0200
 141 #define SUSB_CFG_MSG            0x0400
 142 #define SUSB_SUS_MSG            0x0800
 143 #define SUSB_ID_MSG             0x4000
 144 #define SUSB_VBUS_MSG           0x8000
 145
 146 /* BIOS interrupt routines */
 147
 148 #define SUSBx_RECEIVE_INT(x)    ((x) ? 97 : 81)
 149 #define SUSBx_SEND_INT(x)       ((x) ? 96 : 80)
 150
 151 #define SUSBx_DEV_DESC_VEC(x)   ((x) ? 0x00D4 : 0x00B4)
 152 #define SUSBx_CONF_DESC_VEC(x)  ((x) ? 0x00D6 : 0x00B6)
 153 #define SUSBx_STRING_DESC_VEC(x) ((x) ? 0x00D8 : 0x00B8)
 154
 155 #define CY_HCD_BUF_ADDR         0x500   /* Base address for host */
 156 #define SIE_TD_SIZE             0x200   /* size of the td list */
 157 #define SIE_TD_BUF_SIZE         0x400   /* size of the data buffer */
 158
 159 #define SIE_TD_OFFSET(host)     ((host) ? (SIE_TD_SIZE+SIE_TD_BUF_SIZE) : 0)
 160 #define SIE_BUF_OFFSET(host)    (SIE_TD_OFFSET(host) + SIE_TD_SIZE)
 161
 162 /* Base address of HCD + 2 x TD_SIZE + 2 x TD_BUF_SIZE */
 163 #define CY_UDC_REQ_HEADER_BASE  0x1100
 164 /* 8- byte request headers for IN/OUT transfers */
 165 #define CY_UDC_REQ_HEADER_SIZE  8
 166
 167 #define CY_UDC_REQ_HEADER_ADDR(ep_num)  (CY_UDC_REQ_HEADER_BASE + \
 168                                          ((ep_num) * CY_UDC_REQ_HEADER_SIZE))
 169 #define CY_UDC_DESC_BASE_ADDRESS        (CY_UDC_REQ_HEADER_ADDR(8))
 170
 171 #define CY_UDC_BIOS_REPLACE_BASE        0x1800
 172 #define CY_UDC_REQ_BUFFER_BASE          0x2000
 173 #define CY_UDC_REQ_BUFFER_SIZE          0x0400
 174 #define CY_UDC_REQ_BUFFER_ADDR(ep_num)  (CY_UDC_REQ_BUFFER_BASE + \
 175                                          ((ep_num) * CY_UDC_REQ_BUFFER_SIZE))
 176
 177 /* ---------------------------------------------------------------------
 178  * Driver data structures
 179  */
 180
 181 struct c67x00_device;
 182
 183 /**
 184  * struct c67x00_sie - Common data associated with a SIE
 185  * @lock: lock to protect this struct and the associated chip registers
 186  * @private_data: subdriver dependent data
 187  * @irq: subdriver dependent irq handler, set NULL when not used
 188  * @dev: link to common driver structure
 189  * @sie_num: SIE number on chip, starting from 0
 190  * @mode: SIE mode (host/peripheral/otg/not used)
 191  */
 192 struct c67x00_sie {
 193         /* Entries to be used by the subdrivers */
 194         spinlock_t lock;        /* protect this structure */
 195         void *private_data;
 196         void (*irq) (struct c67x00_sie *sie, u16 int_status, u16 msg);
 197
 198         /* Read only: */
 199         struct c67x00_device *dev;
 200         int sie_num;
 201         int mode;
 202 };
 203
 204 #define sie_dev(s)      (&(s)->dev->pdev->dev)
 205
 206 /**
 207  * struct c67x00_lcp
 208  */
 209 struct c67x00_lcp {
 210         /* Internal use only */
 211         struct mutex mutex;
 212         struct completion msg_received;
 213         u16 last_msg;
 214 };
 215
 216 /*
 217  * struct c67x00_hpi
 218  */
 219 struct c67x00_hpi {
 220         void __iomem *base;
 221         int regstep;
 222         spinlock_t lock;
 223         struct c67x00_lcp lcp;
 224 };
 225
 226 #define C67X00_SIES     2
 227 #define C67X00_PORTS    2
 228
 229 /**
 230  * struct c67x00_device - Common data associated with a c67x00 instance
 231  * @hpi: hpi addresses
 232  * @sie: array of sie's on this chip
 233  * @pdev: platform device of instance
 234  * @pdata: configuration provided by the platform
 235  */
 236 struct c67x00_device {
 237         struct c67x00_hpi hpi;
 238         struct c67x00_sie sie[C67X00_SIES];
 239         struct platform_device *pdev;
 240         struct c67x00_platform_data *pdata;
 241 };
 242
 243 /* ---------------------------------------------------------------------
 244  * Low level interface functions
 245  */
 246
 247 /* Host Port Interface (HPI) functions */
 248 u16 c67x00_ll_hpi_status(struct c67x00_device *dev);
 249 void c67x00_ll_hpi_reg_init(struct c67x00_device *dev);
 250 void c67x00_ll_hpi_enable_sofeop(struct c67x00_sie *sie);
 251 void c67x00_ll_hpi_disable_sofeop(struct c67x00_sie *sie);
 252
 253 /* General functions */
 254 u16 c67x00_ll_fetch_siemsg(struct c67x00_device *dev, int sie_num);
 255 u16 c67x00_ll_get_usb_ctl(struct c67x00_sie *sie);
 256 void c67x00_ll_usb_clear_status(struct c67x00_sie *sie, u16 bits);
 257 u16 c67x00_ll_usb_get_status(struct c67x00_sie *sie);
 258 void c67x00_ll_write_mem_le16(struct c67x00_device *dev, u16 addr,
 259                               void *data, int len);
 260 void c67x00_ll_read_mem_le16(struct c67x00_device *dev, u16 addr,
 261                              void *data, int len);
 262
 263 /* Host specific functions */
 264 void c67x00_ll_set_husb_eot(struct c67x00_device *dev, u16 value);
 265 void c67x00_ll_husb_reset(struct c67x00_sie *sie, int port);
 266 void c67x00_ll_husb_set_current_td(struct c67x00_sie *sie, u16 addr);
 267 u16 c67x00_ll_husb_get_current_td(struct c67x00_sie *sie);
 268 u16 c67x00_ll_husb_get_frame(struct c67x00_sie *sie);
 269 void c67x00_ll_husb_init_host_port(struct c67x00_sie *sie);
 270 void c67x00_ll_husb_reset_port(struct c67x00_sie *sie, int port);
 271
 272 /* Called by c67x00_irq to handle lcp interrupts */
 273 void c67x00_ll_irq(struct c67x00_device *dev, u16 int_status);
 274
 275 /* Setup and teardown */
 276 void c67x00_ll_init(struct c67x00_device *dev);
 277 void c67x00_ll_release(struct c67x00_device *dev);
 278 int c67x00_ll_reset(struct c67x00_device *dev);
 279
 280 #endif                          /* _USB_C67X00_H */