drivers/usb/chipidea/ci.h

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * ci.h - common structures, functions, and macros of the ChipIdea driver
   4  *
   5  * Copyright (C) 2008 Chipidea - MIPS Technologies, Inc. All rights reserved.
   6  *
   7  * Author: David Lopo
   8  */
   9
  10 #ifndef __DRIVERS_USB_CHIPIDEA_CI_H
  11 #define __DRIVERS_USB_CHIPIDEA_CI_H
  12
  13 #include <linux/list.h>
  14 #include <linux/irqreturn.h>
  15 #include <linux/usb.h>
  16 #include <linux/usb/gadget.h>
  17 #include <linux/usb/otg-fsm.h>
  18 #include <linux/usb/otg.h>
  19 #include <linux/ulpi/interface.h>
  20
  21 /******************************************************************************
  22  * DEFINE
  23  *****************************************************************************/
  24 #define TD_PAGE_COUNT      5
  25 #define CI_HDRC_PAGE_SIZE  4096ul /* page size for TD's */
  26 #define ENDPT_MAX          32
  27
  28 /******************************************************************************
  29  * REGISTERS
  30  *****************************************************************************/
  31 /* Identification Registers */
  32 #define ID_ID                           0x0
  33 #define ID_HWGENERAL                    0x4
  34 #define ID_HWHOST                       0x8
  35 #define ID_HWDEVICE                     0xc
  36 #define ID_HWTXBUF                      0x10
  37 #define ID_HWRXBUF                      0x14
  38 #define ID_SBUSCFG                      0x90
  39
  40 /* register indices */
  41 enum ci_hw_regs {
  42         CAP_CAPLENGTH,
  43         CAP_HCCPARAMS,
  44         CAP_DCCPARAMS,
  45         CAP_TESTMODE,
  46         CAP_LAST = CAP_TESTMODE,
  47         OP_USBCMD,
  48         OP_USBSTS,
  49         OP_USBINTR,
  50         OP_DEVICEADDR,
  51         OP_ENDPTLISTADDR,
  52         OP_TTCTRL,
  53         OP_BURSTSIZE,
  54         OP_ULPI_VIEWPORT,
  55         OP_PORTSC,
  56         OP_DEVLC,
  57         OP_OTGSC,
  58         OP_USBMODE,
  59         OP_ENDPTSETUPSTAT,
  60         OP_ENDPTPRIME,
  61         OP_ENDPTFLUSH,
  62         OP_ENDPTSTAT,
  63         OP_ENDPTCOMPLETE,
  64         OP_ENDPTCTRL,
  65         /* endptctrl1..15 follow */
  66         OP_LAST = OP_ENDPTCTRL + ENDPT_MAX / 2,
  67 };
  68
  69 /******************************************************************************
  70  * STRUCTURES
  71  *****************************************************************************/
  72 /**
  73  * struct ci_hw_ep - endpoint representation
  74  * @ep: endpoint structure for gadget drivers
  75  * @dir: endpoint direction (TX/RX)
  76  * @num: endpoint number
  77  * @type: endpoint type
  78  * @name: string description of the endpoint
  79  * @qh: queue head for this endpoint
  80  * @wedge: is the endpoint wedged
  81  * @ci: pointer to the controller
  82  * @lock: pointer to controller's spinlock
  83  * @td_pool: pointer to controller's TD pool
  84  */
  85 struct ci_hw_ep {
  86         struct usb_ep                           ep;
  87         u8                                      dir;
  88         u8                                      num;
  89         u8                                      type;
  90         char                                    name[16];
  91         struct {
  92                 struct list_head        queue;
  93                 struct ci_hw_qh         *ptr;
  94                 dma_addr_t              dma;
  95         }                                       qh;
  96         int                                     wedge;
  97
  98         /* global resources */
  99         struct ci_hdrc                          *ci;
 100         spinlock_t                              *lock;
 101         struct dma_pool                         *td_pool;
 102         struct td_node                          *pending_td;
 103 };
 104
 105 enum ci_role {
 106         CI_ROLE_HOST = 0,
 107         CI_ROLE_GADGET,
 108         CI_ROLE_END,
 109 };
 110
 111 enum ci_revision {
 112         CI_REVISION_1X = 10,    /* Revision 1.x */
 113         CI_REVISION_20 = 20, /* Revision 2.0 */
 114         CI_REVISION_21, /* Revision 2.1 */
 115         CI_REVISION_22, /* Revision 2.2 */
 116         CI_REVISION_23, /* Revision 2.3 */
 117         CI_REVISION_24, /* Revision 2.4 */
 118         CI_REVISION_25, /* Revision 2.5 */
 119         CI_REVISION_25_PLUS, /* Revision above than 2.5 */
 120         CI_REVISION_UNKNOWN = 99, /* Unknown Revision */
 121 };
 122
 123 /**
 124  * struct ci_role_driver - host/gadget role driver
 125  * @start: start this role
 126  * @stop: stop this role
 127  * @irq: irq handler for this role
 128  * @name: role name string (host/gadget)
 129  */
 130 struct ci_role_driver {
 131         int             (*start)(struct ci_hdrc *);
 132         void            (*stop)(struct ci_hdrc *);
 133         irqreturn_t     (*irq)(struct ci_hdrc *);
 134         const char      *name;
 135 };
 136
 137 /**
 138  * struct hw_bank - hardware register mapping representation
 139  * @lpm: set if the device is LPM capable
 140  * @phys: physical address of the controller's registers
 141  * @abs: absolute address of the beginning of register window
 142  * @cap: capability registers
 143  * @op: operational registers
 144  * @size: size of the register window
 145  * @regmap: register lookup table
 146  */
 147 struct hw_bank {
 148         unsigned        lpm;
 149         resource_size_t phys;
 150         void __iomem    *abs;
 151         void __iomem    *cap;
 152         void __iomem    *op;
 153         size_t          size;
 154         void __iomem    *regmap[OP_LAST + 1];
 155 };
 156
 157 /**
 158  * struct ci_hdrc - chipidea device representation
 159  * @dev: pointer to parent device
 160  * @lock: access synchronization
 161  * @hw_bank: hardware register mapping
 162  * @irq: IRQ number
 163  * @roles: array of supported roles for this controller
 164  * @role: current role
 165  * @is_otg: if the device is otg-capable
 166  * @fsm: otg finite state machine
 167  * @otg_fsm_hrtimer: hrtimer for otg fsm timers
 168  * @hr_timeouts: time out list for active otg fsm timers
 169  * @enabled_otg_timer_bits: bits of enabled otg timers
 170  * @next_otg_timer: next nearest enabled timer to be expired
 171  * @work: work for role changing
 172  * @wq: workqueue thread
 173  * @qh_pool: allocation pool for queue heads
 174  * @td_pool: allocation pool for transfer descriptors
 175  * @gadget: device side representation for peripheral controller
 176  * @driver: gadget driver
 177  * @resume_state: save the state of gadget suspend from
 178  * @hw_ep_max: total number of endpoints supported by hardware
 179  * @ci_hw_ep: array of endpoints
 180  * @ep0_dir: ep0 direction
 181  * @ep0out: pointer to ep0 OUT endpoint
 182  * @ep0in: pointer to ep0 IN endpoint
 183  * @status: ep0 status request
 184  * @setaddr: if we should set the address on status completion
 185  * @address: usb address received from the host
 186  * @remote_wakeup: host-enabled remote wakeup
 187  * @suspended: suspended by host
 188  * @test_mode: the selected test mode
 189  * @platdata: platform specific information supplied by parent device
 190  * @vbus_active: is VBUS active
 191  * @ulpi: pointer to ULPI device, if any
 192  * @ulpi_ops: ULPI read/write ops for this device
 193  * @phy: pointer to PHY, if any
 194  * @usb_phy: pointer to USB PHY, if any and if using the USB PHY framework
 195  * @hcd: pointer to usb_hcd for ehci host driver
 196  * @debugfs: root dentry for this controller in debugfs
 197  * @id_event: indicates there is an id event, and handled at ci_otg_work
 198  * @b_sess_valid_event: indicates there is a vbus event, and handled
 199  * at ci_otg_work
 200  * @imx28_write_fix: Freescale imx28 needs swp instruction for writing
 201  * @supports_runtime_pm: if runtime pm is supported
 202  * @in_lpm: if the core in low power mode
 203  * @wakeup_int: if wakeup interrupt occur
 204  * @rev: The revision number for controller
 205  */
 206 struct ci_hdrc {
 207         struct device                   *dev;
 208         spinlock_t                      lock;
 209         struct hw_bank                  hw_bank;
 210         int                             irq;
 211         struct ci_role_driver           *roles[CI_ROLE_END];
 212         enum ci_role                    role;
 213         bool                            is_otg;
 214         struct usb_otg                  otg;
 215         struct otg_fsm                  fsm;
 216         struct hrtimer                  otg_fsm_hrtimer;
 217         ktime_t                         hr_timeouts[NUM_OTG_FSM_TIMERS];
 218         unsigned                        enabled_otg_timer_bits;
 219         enum otg_fsm_timer              next_otg_timer;
 220         struct work_struct              work;
 221         struct workqueue_struct         *wq;
 222
 223         struct dma_pool                 *qh_pool;
 224         struct dma_pool                 *td_pool;
 225
 226         struct usb_gadget               gadget;
 227         struct usb_gadget_driver        *driver;
 228         enum usb_device_state           resume_state;
 229         unsigned                        hw_ep_max;
 230         struct ci_hw_ep                 ci_hw_ep[ENDPT_MAX];
 231         u32                             ep0_dir;
 232         struct ci_hw_ep                 *ep0out, *ep0in;
 233
 234         struct usb_request              *status;
 235         bool                            setaddr;
 236         u8                              address;
 237         u8                              remote_wakeup;
 238         u8                              suspended;
 239         u8                              test_mode;
 240
 241         struct ci_hdrc_platform_data    *platdata;
 242         int                             vbus_active;
 243         struct ulpi                     *ulpi;
 244         struct ulpi_ops                 ulpi_ops;
 245         struct phy                      *phy;
 246         /* old usb_phy interface */
 247         struct usb_phy                  *usb_phy;
 248         struct usb_hcd                  *hcd;
 249         struct dentry                   *debugfs;
 250         bool                            id_event;
 251         bool                            b_sess_valid_event;
 252         bool                            imx28_write_fix;
 253         bool                            supports_runtime_pm;
 254         bool                            in_lpm;
 255         bool                            wakeup_int;
 256         enum ci_revision                rev;
 257 };
 258
 259 static inline struct ci_role_driver *ci_role(struct ci_hdrc *ci)
 260 {
 261         BUG_ON(ci->role >= CI_ROLE_END || !ci->roles[ci->role]);
 262         return ci->roles[ci->role];
 263 }
 264
 265 static inline int ci_role_start(struct ci_hdrc *ci, enum ci_role role)
 266 {
 267         int ret;
 268
 269         if (role >= CI_ROLE_END)
 270                 return -EINVAL;
 271
 272         if (!ci->roles[role])
 273                 return -ENXIO;
 274
 275         ret = ci->roles[role]->start(ci);
 276         if (!ret)
 277                 ci->role = role;
 278         return ret;
 279 }
 280
 281 static inline void ci_role_stop(struct ci_hdrc *ci)
 282 {
 283         enum ci_role role = ci->role;
 284
 285         if (role == CI_ROLE_END)
 286                 return;
 287
 288         ci->role = CI_ROLE_END;
 289
 290         ci->roles[role]->stop(ci);
 291 }
 292
 293 /**
 294  * hw_read_id_reg: reads from a identification register
 295  * @ci: the controller
 296  * @offset: offset from the beginning of identification registers region
 297  * @mask: bitfield mask
 298  *
 299  * This function returns register contents
 300  */
 301 static inline u32 hw_read_id_reg(struct ci_hdrc *ci, u32 offset, u32 mask)
 302 {
 303         return ioread32(ci->hw_bank.abs + offset) & mask;
 304 }
 305
 306 /**
 307  * hw_write_id_reg: writes to a identification register
 308  * @ci: the controller
 309  * @offset: offset from the beginning of identification registers region
 310  * @mask: bitfield mask
 311  * @data: new value
 312  */
 313 static inline void hw_write_id_reg(struct ci_hdrc *ci, u32 offset,
 314                             u32 mask, u32 data)
 315 {
 316         if (~mask)
 317                 data = (ioread32(ci->hw_bank.abs + offset) & ~mask)
 318                         | (data & mask);
 319
 320         iowrite32(data, ci->hw_bank.abs + offset);
 321 }
 322
 323 /**
 324  * hw_read: reads from a hw register
 325  * @ci: the controller
 326  * @reg:  register index
 327  * @mask: bitfield mask
 328  *
 329  * This function returns register contents
 330  */
 331 static inline u32 hw_read(struct ci_hdrc *ci, enum ci_hw_regs reg, u32 mask)
 332 {
 333         return ioread32(ci->hw_bank.regmap[reg]) & mask;
 334 }
 335
 336 #ifdef CONFIG_SOC_IMX28
 337 static inline void imx28_ci_writel(u32 val, volatile void __iomem *addr)
 338 {
 339         __asm__ ("swp %0, %0, [%1]" : : "r"(val), "r"(addr));
 340 }
 341 #else
 342 static inline void imx28_ci_writel(u32 val, volatile void __iomem *addr)
 343 {
 344 }
 345 #endif
 346
 347 static inline void __hw_write(struct ci_hdrc *ci, u32 val,
 348                 void __iomem *addr)
 349 {
 350         if (ci->imx28_write_fix)
 351                 imx28_ci_writel(val, addr);
 352         else
 353                 iowrite32(val, addr);
 354 }
 355
 356 /**
 357  * hw_write: writes to a hw register
 358  * @ci: the controller
 359  * @reg:  register index
 360  * @mask: bitfield mask
 361  * @data: new value
 362  */
 363 static inline void hw_write(struct ci_hdrc *ci, enum ci_hw_regs reg,
 364                             u32 mask, u32 data)
 365 {
 366         if (~mask)
 367                 data = (ioread32(ci->hw_bank.regmap[reg]) & ~mask)
 368                         | (data & mask);
 369
 370         __hw_write(ci, data, ci->hw_bank.regmap[reg]);
 371 }
 372
 373 /**
 374  * hw_test_and_clear: tests & clears a hw register
 375  * @ci: the controller
 376  * @reg:  register index
 377  * @mask: bitfield mask
 378  *
 379  * This function returns register contents
 380  */
 381 static inline u32 hw_test_and_clear(struct ci_hdrc *ci, enum ci_hw_regs reg,
 382                                     u32 mask)
 383 {
 384         u32 val = ioread32(ci->hw_bank.regmap[reg]) & mask;
 385
 386         __hw_write(ci, val, ci->hw_bank.regmap[reg]);
 387         return val;
 388 }
 389
 390 /**
 391  * hw_test_and_write: tests & writes a hw register
 392  * @ci: the controller
 393  * @reg:  register index
 394  * @mask: bitfield mask
 395  * @data: new value
 396  *
 397  * This function returns register contents
 398  */
 399 static inline u32 hw_test_and_write(struct ci_hdrc *ci, enum ci_hw_regs reg,
 400                                     u32 mask, u32 data)
 401 {
 402         u32 val = hw_read(ci, reg, ~0);
 403
 404         hw_write(ci, reg, mask, data);
 405         return (val & mask) >> __ffs(mask);
 406 }
 407
 408 /**
 409  * ci_otg_is_fsm_mode: runtime check if otg controller
 410  * is in otg fsm mode.
 411  *
 412  * @ci: chipidea device
 413  */
 414 static inline bool ci_otg_is_fsm_mode(struct ci_hdrc *ci)
 415 {
 416 #ifdef CONFIG_USB_OTG_FSM
 417         struct usb_otg_caps *otg_caps = &ci->platdata->ci_otg_caps;
 418
 419         return ci->is_otg && ci->roles[CI_ROLE_HOST] &&
 420                 ci->roles[CI_ROLE_GADGET] && (otg_caps->srp_support ||
 421                 otg_caps->hnp_support || otg_caps->adp_support);
 422 #else
 423         return false;
 424 #endif
 425 }
 426
 427 int ci_ulpi_init(struct ci_hdrc *ci);
 428 void ci_ulpi_exit(struct ci_hdrc *ci);
 429 int ci_ulpi_resume(struct ci_hdrc *ci);
 430
 431 u32 hw_read_intr_enable(struct ci_hdrc *ci);
 432
 433 u32 hw_read_intr_status(struct ci_hdrc *ci);
 434
 435 int hw_device_reset(struct ci_hdrc *ci);
 436
 437 int hw_port_test_set(struct ci_hdrc *ci, u8 mode);
 438
 439 u8 hw_port_test_get(struct ci_hdrc *ci);
 440
 441 void hw_phymode_configure(struct ci_hdrc *ci);
 442
 443 void ci_platform_configure(struct ci_hdrc *ci);
 444
 445 void dbg_create_files(struct ci_hdrc *ci);
 446
 447 void dbg_remove_files(struct ci_hdrc *ci);
 448 #endif  /* __DRIVERS_USB_CHIPIDEA_CI_H */