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perf python: Do not force closing original perf descriptor in evlist.get_pollfd()
[linux/fpc-iii.git] / drivers / usb / chipidea / core.c
blob7bfcbb23c2a42b53e1566788b53b46d7d7c9cc9c
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * core.c - ChipIdea USB IP core family device controller
4 *
5 * Copyright (C) 2008 Chipidea - MIPS Technologies, Inc. All rights reserved.
6 *
7 * Author: David Lopo
8 */
9
10 /*
11 * Description: ChipIdea USB IP core family device controller
12 *
13 * This driver is composed of several blocks:
14 * - HW: hardware interface
15 * - DBG: debug facilities (optional)
16 * - UTIL: utilities
17 * - ISR: interrupts handling
18 * - ENDPT: endpoint operations (Gadget API)
19 * - GADGET: gadget operations (Gadget API)
20 * - BUS: bus glue code, bus abstraction layer
21 *
22 * Compile Options
23 * - STALL_IN: non-empty bulk-in pipes cannot be halted
24 * if defined mass storage compliance succeeds but with warnings
25 * => case 4: Hi > Dn
26 * => case 5: Hi > Di
27 * => case 8: Hi <> Do
28 * if undefined usbtest 13 fails
29 * - TRACE: enable function tracing (depends on DEBUG)
30 *
31 * Main Features
32 * - Chapter 9 & Mass Storage Compliance with Gadget File Storage
33 * - Chapter 9 Compliance with Gadget Zero (STALL_IN undefined)
34 * - Normal & LPM support
35 *
36 * USBTEST Report
37 * - OK: 0-12, 13 (STALL_IN defined) & 14
38 * - Not Supported: 15 & 16 (ISO)
39 *
40 * TODO List
41 * - Suspend & Remote Wakeup
42 */
43 #include <linux/delay.h>
44 #include <linux/device.h>
45 #include <linux/dma-mapping.h>
46 #include <linux/extcon.h>
47 #include <linux/phy/phy.h>
48 #include <linux/platform_device.h>
49 #include <linux/module.h>
50 #include <linux/idr.h>
51 #include <linux/interrupt.h>
52 #include <linux/io.h>
53 #include <linux/kernel.h>
54 #include <linux/slab.h>
55 #include <linux/pm_runtime.h>
56 #include <linux/pinctrl/consumer.h>
57 #include <linux/usb/ch9.h>
58 #include <linux/usb/gadget.h>
59 #include <linux/usb/otg.h>
60 #include <linux/usb/chipidea.h>
61 #include <linux/usb/of.h>
62 #include <linux/of.h>
63 #include <linux/regulator/consumer.h>
64 #include <linux/usb/ehci_def.h>
65
66 #include "ci.h"
67 #include "udc.h"
68 #include "bits.h"
69 #include "host.h"
70 #include "otg.h"
71 #include "otg_fsm.h"
72
73 /* Controller register map */
74 static const u8 ci_regs_nolpm[] = {
75 [CAP_CAPLENGTH] = 0x00U,
76 [CAP_HCCPARAMS] = 0x08U,
77 [CAP_DCCPARAMS] = 0x24U,
78 [CAP_TESTMODE] = 0x38U,
79 [OP_USBCMD] = 0x00U,
80 [OP_USBSTS] = 0x04U,
81 [OP_USBINTR] = 0x08U,
82 [OP_DEVICEADDR] = 0x14U,
83 [OP_ENDPTLISTADDR] = 0x18U,
84 [OP_TTCTRL] = 0x1CU,
85 [OP_BURSTSIZE] = 0x20U,
86 [OP_ULPI_VIEWPORT] = 0x30U,
87 [OP_PORTSC] = 0x44U,
88 [OP_DEVLC] = 0x84U,
89 [OP_OTGSC] = 0x64U,
90 [OP_USBMODE] = 0x68U,
91 [OP_ENDPTSETUPSTAT] = 0x6CU,
92 [OP_ENDPTPRIME] = 0x70U,
93 [OP_ENDPTFLUSH] = 0x74U,
94 [OP_ENDPTSTAT] = 0x78U,
95 [OP_ENDPTCOMPLETE] = 0x7CU,
96 [OP_ENDPTCTRL] = 0x80U,
97 };
98
99 static const u8 ci_regs_lpm[] = {
100 [CAP_CAPLENGTH] = 0x00U,
101 [CAP_HCCPARAMS] = 0x08U,
102 [CAP_DCCPARAMS] = 0x24U,
103 [CAP_TESTMODE] = 0xFCU,
104 [OP_USBCMD] = 0x00U,
105 [OP_USBSTS] = 0x04U,
106 [OP_USBINTR] = 0x08U,
107 [OP_DEVICEADDR] = 0x14U,
108 [OP_ENDPTLISTADDR] = 0x18U,
109 [OP_TTCTRL] = 0x1CU,
110 [OP_BURSTSIZE] = 0x20U,
111 [OP_ULPI_VIEWPORT] = 0x30U,
112 [OP_PORTSC] = 0x44U,
113 [OP_DEVLC] = 0x84U,
114 [OP_OTGSC] = 0xC4U,
115 [OP_USBMODE] = 0xC8U,
116 [OP_ENDPTSETUPSTAT] = 0xD8U,
117 [OP_ENDPTPRIME] = 0xDCU,
118 [OP_ENDPTFLUSH] = 0xE0U,
119 [OP_ENDPTSTAT] = 0xE4U,
120 [OP_ENDPTCOMPLETE] = 0xE8U,
121 [OP_ENDPTCTRL] = 0xECU,
122 };
123
124 static void hw_alloc_regmap(struct ci_hdrc *ci, bool is_lpm)
125 {
126 int i;
127
128 for (i = 0; i < OP_ENDPTCTRL; i++)
129 ci->hw_bank.regmap[i] =
130 (i <= CAP_LAST ? ci->hw_bank.cap : ci->hw_bank.op) +
131 (is_lpm ? ci_regs_lpm[i] : ci_regs_nolpm[i]);
132
133 for (; i <= OP_LAST; i++)
134 ci->hw_bank.regmap[i] = ci->hw_bank.op +
135 4 * (i - OP_ENDPTCTRL) +
136 (is_lpm
137 ? ci_regs_lpm[OP_ENDPTCTRL]
138 : ci_regs_nolpm[OP_ENDPTCTRL]);
139
140 }
141
142 static enum ci_revision ci_get_revision(struct ci_hdrc *ci)
143 {
144 int ver = hw_read_id_reg(ci, ID_ID, VERSION) >> __ffs(VERSION);
145 enum ci_revision rev = CI_REVISION_UNKNOWN;
146
147 if (ver == 0x2) {
148 rev = hw_read_id_reg(ci, ID_ID, REVISION)
149 >> __ffs(REVISION);
150 rev += CI_REVISION_20;
151 } else if (ver == 0x0) {
152 rev = CI_REVISION_1X;
153 }
154
155 return rev;
156 }
157
158 /**
159 * hw_read_intr_enable: returns interrupt enable register
160 *
161 * @ci: the controller
162 *
163 * This function returns register data
164 */
165 u32 hw_read_intr_enable(struct ci_hdrc *ci)
166 {
167 return hw_read(ci, OP_USBINTR, ~0);
168 }
169
170 /**
171 * hw_read_intr_status: returns interrupt status register
172 *
173 * @ci: the controller
174 *
175 * This function returns register data
176 */
177 u32 hw_read_intr_status(struct ci_hdrc *ci)
178 {
179 return hw_read(ci, OP_USBSTS, ~0);
180 }
181
182 /**
183 * hw_port_test_set: writes port test mode (execute without interruption)
184 * @mode: new value
185 *
186 * This function returns an error code
187 */
188 int hw_port_test_set(struct ci_hdrc *ci, u8 mode)
189 {
190 const u8 TEST_MODE_MAX = 7;
191
192 if (mode > TEST_MODE_MAX)
193 return -EINVAL;
194
195 hw_write(ci, OP_PORTSC, PORTSC_PTC, mode << __ffs(PORTSC_PTC));
196 return 0;
197 }
198
199 /**
200 * hw_port_test_get: reads port test mode value
201 *
202 * @ci: the controller
203 *
204 * This function returns port test mode value
205 */
206 u8 hw_port_test_get(struct ci_hdrc *ci)
207 {
208 return hw_read(ci, OP_PORTSC, PORTSC_PTC) >> __ffs(PORTSC_PTC);
209 }
210
211 static void hw_wait_phy_stable(void)
212 {
213 /*
214 * The phy needs some delay to output the stable status from low
215 * power mode. And for OTGSC, the status inputs are debounced
216 * using a 1 ms time constant, so, delay 2ms for controller to get
217 * the stable status, like vbus and id when the phy leaves low power.
218 */
219 usleep_range(2000, 2500);
220 }
221
222 /* The PHY enters/leaves low power mode */
223 static void ci_hdrc_enter_lpm(struct ci_hdrc *ci, bool enable)
224 {
225 enum ci_hw_regs reg = ci->hw_bank.lpm ? OP_DEVLC : OP_PORTSC;
226 bool lpm = !!(hw_read(ci, reg, PORTSC_PHCD(ci->hw_bank.lpm)));
227
228 if (enable && !lpm)
229 hw_write(ci, reg, PORTSC_PHCD(ci->hw_bank.lpm),
230 PORTSC_PHCD(ci->hw_bank.lpm));
231 else if (!enable && lpm)
232 hw_write(ci, reg, PORTSC_PHCD(ci->hw_bank.lpm),
233 0);
234 }
235
236 static int hw_device_init(struct ci_hdrc *ci, void __iomem *base)
237 {
238 u32 reg;
239
240 /* bank is a module variable */
241 ci->hw_bank.abs = base;
242
243 ci->hw_bank.cap = ci->hw_bank.abs;
244 ci->hw_bank.cap += ci->platdata->capoffset;
245 ci->hw_bank.op = ci->hw_bank.cap + (ioread32(ci->hw_bank.cap) & 0xff);
246
247 hw_alloc_regmap(ci, false);
248 reg = hw_read(ci, CAP_HCCPARAMS, HCCPARAMS_LEN) >>
249 __ffs(HCCPARAMS_LEN);
250 ci->hw_bank.lpm = reg;
251 if (reg)
252 hw_alloc_regmap(ci, !!reg);
253 ci->hw_bank.size = ci->hw_bank.op - ci->hw_bank.abs;
254 ci->hw_bank.size += OP_LAST;
255 ci->hw_bank.size /= sizeof(u32);
256
257 reg = hw_read(ci, CAP_DCCPARAMS, DCCPARAMS_DEN) >>
258 __ffs(DCCPARAMS_DEN);
259 ci->hw_ep_max = reg * 2; /* cache hw ENDPT_MAX */
260
261 if (ci->hw_ep_max > ENDPT_MAX)
262 return -ENODEV;
263
264 ci_hdrc_enter_lpm(ci, false);
265
266 /* Disable all interrupts bits */
267 hw_write(ci, OP_USBINTR, 0xffffffff, 0);
268
269 /* Clear all interrupts status bits*/
270 hw_write(ci, OP_USBSTS, 0xffffffff, 0xffffffff);
271
272 ci->rev = ci_get_revision(ci);
273
274 dev_dbg(ci->dev,
275 "ChipIdea HDRC found, revision: %d, lpm: %d; cap: %p op: %p\n",
276 ci->rev, ci->hw_bank.lpm, ci->hw_bank.cap, ci->hw_bank.op);
277
278 /* setup lock mode ? */
279
280 /* ENDPTSETUPSTAT is '0' by default */
281
282 /* HCSPARAMS.bf.ppc SHOULD BE zero for device */
283
284 return 0;
285 }
286
287 void hw_phymode_configure(struct ci_hdrc *ci)
288 {
289 u32 portsc, lpm, sts = 0;
290
291 switch (ci->platdata->phy_mode) {
292 case USBPHY_INTERFACE_MODE_UTMI:
293 portsc = PORTSC_PTS(PTS_UTMI);
294 lpm = DEVLC_PTS(PTS_UTMI);
295 break;
296 case USBPHY_INTERFACE_MODE_UTMIW:
297 portsc = PORTSC_PTS(PTS_UTMI) | PORTSC_PTW;
298 lpm = DEVLC_PTS(PTS_UTMI) | DEVLC_PTW;
299 break;
300 case USBPHY_INTERFACE_MODE_ULPI:
301 portsc = PORTSC_PTS(PTS_ULPI);
302 lpm = DEVLC_PTS(PTS_ULPI);
303 break;
304 case USBPHY_INTERFACE_MODE_SERIAL:
305 portsc = PORTSC_PTS(PTS_SERIAL);
306 lpm = DEVLC_PTS(PTS_SERIAL);
307 sts = 1;
308 break;
309 case USBPHY_INTERFACE_MODE_HSIC:
310 portsc = PORTSC_PTS(PTS_HSIC);
311 lpm = DEVLC_PTS(PTS_HSIC);
312 break;
313 default:
314 return;
315 }
316
317 if (ci->hw_bank.lpm) {
318 hw_write(ci, OP_DEVLC, DEVLC_PTS(7) | DEVLC_PTW, lpm);
319 if (sts)
320 hw_write(ci, OP_DEVLC, DEVLC_STS, DEVLC_STS);
321 } else {
322 hw_write(ci, OP_PORTSC, PORTSC_PTS(7) | PORTSC_PTW, portsc);
323 if (sts)
324 hw_write(ci, OP_PORTSC, PORTSC_STS, PORTSC_STS);
325 }
326 }
327 EXPORT_SYMBOL_GPL(hw_phymode_configure);
328
329 /**
330 * _ci_usb_phy_init: initialize phy taking in account both phy and usb_phy
331 * interfaces
332 * @ci: the controller
333 *
334 * This function returns an error code if the phy failed to init
335 */
336 static int _ci_usb_phy_init(struct ci_hdrc *ci)
337 {
338 int ret;
339
340 if (ci->phy) {
341 ret = phy_init(ci->phy);
342 if (ret)
343 return ret;
344
345 ret = phy_power_on(ci->phy);
346 if (ret) {
347 phy_exit(ci->phy);
348 return ret;
349 }
350 } else {
351 ret = usb_phy_init(ci->usb_phy);
352 }
353
354 return ret;
355 }
356
357 /**
358 * _ci_usb_phy_exit: deinitialize phy taking in account both phy and usb_phy
359 * interfaces
360 * @ci: the controller
361 */
362 static void ci_usb_phy_exit(struct ci_hdrc *ci)
363 {
364 if (ci->platdata->flags & CI_HDRC_OVERRIDE_PHY_CONTROL)
365 return;
366
367 if (ci->phy) {
368 phy_power_off(ci->phy);
369 phy_exit(ci->phy);
370 } else {
371 usb_phy_shutdown(ci->usb_phy);
372 }
373 }
374
375 /**
376 * ci_usb_phy_init: initialize phy according to different phy type
377 * @ci: the controller
378 *
379 * This function returns an error code if usb_phy_init has failed
380 */
381 static int ci_usb_phy_init(struct ci_hdrc *ci)
382 {
383 int ret;
384
385 if (ci->platdata->flags & CI_HDRC_OVERRIDE_PHY_CONTROL)
386 return 0;
387
388 switch (ci->platdata->phy_mode) {
389 case USBPHY_INTERFACE_MODE_UTMI:
390 case USBPHY_INTERFACE_MODE_UTMIW:
391 case USBPHY_INTERFACE_MODE_HSIC:
392 ret = _ci_usb_phy_init(ci);
393 if (!ret)
394 hw_wait_phy_stable();
395 else
396 return ret;
397 hw_phymode_configure(ci);
398 break;
399 case USBPHY_INTERFACE_MODE_ULPI:
400 case USBPHY_INTERFACE_MODE_SERIAL:
401 hw_phymode_configure(ci);
402 ret = _ci_usb_phy_init(ci);
403 if (ret)
404 return ret;
405 break;
406 default:
407 ret = _ci_usb_phy_init(ci);
408 if (!ret)
409 hw_wait_phy_stable();
410 }
411
412 return ret;
413 }
414
415
416 /**
417 * ci_platform_configure: do controller configure
418 * @ci: the controller
419 *
420 */
421 void ci_platform_configure(struct ci_hdrc *ci)
422 {
423 bool is_device_mode, is_host_mode;
424
425 is_device_mode = hw_read(ci, OP_USBMODE, USBMODE_CM) == USBMODE_CM_DC;
426 is_host_mode = hw_read(ci, OP_USBMODE, USBMODE_CM) == USBMODE_CM_HC;
427
428 if (is_device_mode) {
429 phy_set_mode(ci->phy, PHY_MODE_USB_DEVICE);
430
431 if (ci->platdata->flags & CI_HDRC_DISABLE_DEVICE_STREAMING)
432 hw_write(ci, OP_USBMODE, USBMODE_CI_SDIS,
433 USBMODE_CI_SDIS);
434 }
435
436 if (is_host_mode) {
437 phy_set_mode(ci->phy, PHY_MODE_USB_HOST);
438
439 if (ci->platdata->flags & CI_HDRC_DISABLE_HOST_STREAMING)
440 hw_write(ci, OP_USBMODE, USBMODE_CI_SDIS,
441 USBMODE_CI_SDIS);
442 }
443
444 if (ci->platdata->flags & CI_HDRC_FORCE_FULLSPEED) {
445 if (ci->hw_bank.lpm)
446 hw_write(ci, OP_DEVLC, DEVLC_PFSC, DEVLC_PFSC);
447 else
448 hw_write(ci, OP_PORTSC, PORTSC_PFSC, PORTSC_PFSC);
449 }
450
451 if (ci->platdata->flags & CI_HDRC_SET_NON_ZERO_TTHA)
452 hw_write(ci, OP_TTCTRL, TTCTRL_TTHA_MASK, TTCTRL_TTHA);
453
454 hw_write(ci, OP_USBCMD, 0xff0000, ci->platdata->itc_setting << 16);
455
456 if (ci->platdata->flags & CI_HDRC_OVERRIDE_AHB_BURST)
457 hw_write_id_reg(ci, ID_SBUSCFG, AHBBRST_MASK,
458 ci->platdata->ahb_burst_config);
459
460 /* override burst size, take effect only when ahb_burst_config is 0 */
461 if (!hw_read_id_reg(ci, ID_SBUSCFG, AHBBRST_MASK)) {
462 if (ci->platdata->flags & CI_HDRC_OVERRIDE_TX_BURST)
463 hw_write(ci, OP_BURSTSIZE, TX_BURST_MASK,
464 ci->platdata->tx_burst_size << __ffs(TX_BURST_MASK));
465
466 if (ci->platdata->flags & CI_HDRC_OVERRIDE_RX_BURST)
467 hw_write(ci, OP_BURSTSIZE, RX_BURST_MASK,
468 ci->platdata->rx_burst_size);
469 }
470 }
471
472 /**
473 * hw_controller_reset: do controller reset
474 * @ci: the controller
475 *
476 * This function returns an error code
477 */
478 static int hw_controller_reset(struct ci_hdrc *ci)
479 {
480 int count = 0;
481
482 hw_write(ci, OP_USBCMD, USBCMD_RST, USBCMD_RST);
483 while (hw_read(ci, OP_USBCMD, USBCMD_RST)) {
484 udelay(10);
485 if (count++ > 1000)
486 return -ETIMEDOUT;
487 }
488
489 return 0;
490 }
491
492 /**
493 * hw_device_reset: resets chip (execute without interruption)
494 * @ci: the controller
495 *
496 * This function returns an error code
497 */
498 int hw_device_reset(struct ci_hdrc *ci)
499 {
500 int ret;
501
502 /* should flush & stop before reset */
503 hw_write(ci, OP_ENDPTFLUSH, ~0, ~0);
504 hw_write(ci, OP_USBCMD, USBCMD_RS, 0);
505
506 ret = hw_controller_reset(ci);
507 if (ret) {
508 dev_err(ci->dev, "error resetting controller, ret=%d\n", ret);
509 return ret;
510 }
511
512 if (ci->platdata->notify_event) {
513 ret = ci->platdata->notify_event(ci,
514 CI_HDRC_CONTROLLER_RESET_EVENT);
515 if (ret)
516 return ret;
517 }
518
519 /* USBMODE should be configured step by step */
520 hw_write(ci, OP_USBMODE, USBMODE_CM, USBMODE_CM_IDLE);
521 hw_write(ci, OP_USBMODE, USBMODE_CM, USBMODE_CM_DC);
522 /* HW >= 2.3 */
523 hw_write(ci, OP_USBMODE, USBMODE_SLOM, USBMODE_SLOM);
524
525 if (hw_read(ci, OP_USBMODE, USBMODE_CM) != USBMODE_CM_DC) {
526 pr_err("cannot enter in %s device mode", ci_role(ci)->name);
527 pr_err("lpm = %i", ci->hw_bank.lpm);
528 return -ENODEV;
529 }
530
531 ci_platform_configure(ci);
532
533 return 0;
534 }
535
536 static irqreturn_t ci_irq(int irq, void *data)
537 {
538 struct ci_hdrc *ci = data;
539 irqreturn_t ret = IRQ_NONE;
540 u32 otgsc = 0;
541
542 if (ci->in_lpm) {
543 disable_irq_nosync(irq);
544 ci->wakeup_int = true;
545 pm_runtime_get(ci->dev);
546 return IRQ_HANDLED;
547 }
548
549 if (ci->is_otg) {
550 otgsc = hw_read_otgsc(ci, ~0);
551 if (ci_otg_is_fsm_mode(ci)) {
552 ret = ci_otg_fsm_irq(ci);
553 if (ret == IRQ_HANDLED)
554 return ret;
555 }
556 }
557
558 /*
559 * Handle id change interrupt, it indicates device/host function
560 * switch.
561 */
562 if (ci->is_otg && (otgsc & OTGSC_IDIE) && (otgsc & OTGSC_IDIS)) {
563 ci->id_event = true;
564 /* Clear ID change irq status */
565 hw_write_otgsc(ci, OTGSC_IDIS, OTGSC_IDIS);
566 ci_otg_queue_work(ci);
567 return IRQ_HANDLED;
568 }
569
570 /*
571 * Handle vbus change interrupt, it indicates device connection
572 * and disconnection events.
573 */
574 if (ci->is_otg && (otgsc & OTGSC_BSVIE) && (otgsc & OTGSC_BSVIS)) {
575 ci->b_sess_valid_event = true;
576 /* Clear BSV irq */
577 hw_write_otgsc(ci, OTGSC_BSVIS, OTGSC_BSVIS);
578 ci_otg_queue_work(ci);
579 return IRQ_HANDLED;
580 }
581
582 /* Handle device/host interrupt */
583 if (ci->role != CI_ROLE_END)
584 ret = ci_role(ci)->irq(ci);
585
586 return ret;
587 }
588
589 static int ci_cable_notifier(struct notifier_block *nb, unsigned long event,
590 void *ptr)
591 {
592 struct ci_hdrc_cable *cbl = container_of(nb, struct ci_hdrc_cable, nb);
593 struct ci_hdrc *ci = cbl->ci;
594
595 cbl->connected = event;
596 cbl->changed = true;
597
598 ci_irq(ci->irq, ci);
599 return NOTIFY_DONE;
600 }
601
602 static int ci_get_platdata(struct device *dev,
603 struct ci_hdrc_platform_data *platdata)
604 {
605 struct extcon_dev *ext_vbus, *ext_id;
606 struct ci_hdrc_cable *cable;
607 int ret;
608
609 if (!platdata->phy_mode)
610 platdata->phy_mode = of_usb_get_phy_mode(dev->of_node);
611
612 if (!platdata->dr_mode)
613 platdata->dr_mode = usb_get_dr_mode(dev);
614
615 if (platdata->dr_mode == USB_DR_MODE_UNKNOWN)
616 platdata->dr_mode = USB_DR_MODE_OTG;
617
618 if (platdata->dr_mode != USB_DR_MODE_PERIPHERAL) {
619 /* Get the vbus regulator */
620 platdata->reg_vbus = devm_regulator_get(dev, "vbus");
621 if (PTR_ERR(platdata->reg_vbus) == -EPROBE_DEFER) {
622 return -EPROBE_DEFER;
623 } else if (PTR_ERR(platdata->reg_vbus) == -ENODEV) {
624 /* no vbus regulator is needed */
625 platdata->reg_vbus = NULL;
626 } else if (IS_ERR(platdata->reg_vbus)) {
627 dev_err(dev, "Getting regulator error: %ld\n",
628 PTR_ERR(platdata->reg_vbus));
629 return PTR_ERR(platdata->reg_vbus);
630 }
631 /* Get TPL support */
632 if (!platdata->tpl_support)
633 platdata->tpl_support =
634 of_usb_host_tpl_support(dev->of_node);
635 }
636
637 if (platdata->dr_mode == USB_DR_MODE_OTG) {
638 /* We can support HNP and SRP of OTG 2.0 */
639 platdata->ci_otg_caps.otg_rev = 0x0200;
640 platdata->ci_otg_caps.hnp_support = true;
641 platdata->ci_otg_caps.srp_support = true;
642
643 /* Update otg capabilities by DT properties */
644 ret = of_usb_update_otg_caps(dev->of_node,
645 &platdata->ci_otg_caps);
646 if (ret)
647 return ret;
648 }
649
650 if (usb_get_maximum_speed(dev) == USB_SPEED_FULL)
651 platdata->flags |= CI_HDRC_FORCE_FULLSPEED;
652
653 of_property_read_u32(dev->of_node, "phy-clkgate-delay-us",
654 &platdata->phy_clkgate_delay_us);
655
656 platdata->itc_setting = 1;
657
658 of_property_read_u32(dev->of_node, "itc-setting",
659 &platdata->itc_setting);
660
661 ret = of_property_read_u32(dev->of_node, "ahb-burst-config",
662 &platdata->ahb_burst_config);
663 if (!ret) {
664 platdata->flags |= CI_HDRC_OVERRIDE_AHB_BURST;
665 } else if (ret != -EINVAL) {
666 dev_err(dev, "failed to get ahb-burst-config\n");
667 return ret;
668 }
669
670 ret = of_property_read_u32(dev->of_node, "tx-burst-size-dword",
671 &platdata->tx_burst_size);
672 if (!ret) {
673 platdata->flags |= CI_HDRC_OVERRIDE_TX_BURST;
674 } else if (ret != -EINVAL) {
675 dev_err(dev, "failed to get tx-burst-size-dword\n");
676 return ret;
677 }
678
679 ret = of_property_read_u32(dev->of_node, "rx-burst-size-dword",
680 &platdata->rx_burst_size);
681 if (!ret) {
682 platdata->flags |= CI_HDRC_OVERRIDE_RX_BURST;
683 } else if (ret != -EINVAL) {
684 dev_err(dev, "failed to get rx-burst-size-dword\n");
685 return ret;
686 }
687
688 if (of_find_property(dev->of_node, "non-zero-ttctrl-ttha", NULL))
689 platdata->flags |= CI_HDRC_SET_NON_ZERO_TTHA;
690
691 ext_id = ERR_PTR(-ENODEV);
692 ext_vbus = ERR_PTR(-ENODEV);
693 if (of_property_read_bool(dev->of_node, "extcon")) {
694 /* Each one of them is not mandatory */
695 ext_vbus = extcon_get_edev_by_phandle(dev, 0);
696 if (IS_ERR(ext_vbus) && PTR_ERR(ext_vbus) != -ENODEV)
697 return PTR_ERR(ext_vbus);
698
699 ext_id = extcon_get_edev_by_phandle(dev, 1);
700 if (IS_ERR(ext_id) && PTR_ERR(ext_id) != -ENODEV)
701 return PTR_ERR(ext_id);
702 }
703
704 cable = &platdata->vbus_extcon;
705 cable->nb.notifier_call = ci_cable_notifier;
706 cable->edev = ext_vbus;
707
708 if (!IS_ERR(ext_vbus)) {
709 ret = extcon_get_state(cable->edev, EXTCON_USB);
710 if (ret)
711 cable->connected = true;
712 else
713 cable->connected = false;
714 }
715
716 cable = &platdata->id_extcon;
717 cable->nb.notifier_call = ci_cable_notifier;
718 cable->edev = ext_id;
719
720 if (!IS_ERR(ext_id)) {
721 ret = extcon_get_state(cable->edev, EXTCON_USB_HOST);
722 if (ret)
723 cable->connected = true;
724 else
725 cable->connected = false;
726 }
727
728 platdata->pctl = devm_pinctrl_get(dev);
729 if (!IS_ERR(platdata->pctl)) {
730 struct pinctrl_state *p;
731
732 p = pinctrl_lookup_state(platdata->pctl, "default");
733 if (!IS_ERR(p))
734 platdata->pins_default = p;
735
736 p = pinctrl_lookup_state(platdata->pctl, "host");
737 if (!IS_ERR(p))
738 platdata->pins_host = p;
739
740 p = pinctrl_lookup_state(platdata->pctl, "device");
741 if (!IS_ERR(p))
742 platdata->pins_device = p;
743 }
744
745 return 0;
746 }
747
748 static int ci_extcon_register(struct ci_hdrc *ci)
749 {
750 struct ci_hdrc_cable *id, *vbus;
751 int ret;
752
753 id = &ci->platdata->id_extcon;
754 id->ci = ci;
755 if (!IS_ERR_OR_NULL(id->edev)) {
756 ret = devm_extcon_register_notifier(ci->dev, id->edev,
757 EXTCON_USB_HOST, &id->nb);
758 if (ret < 0) {
759 dev_err(ci->dev, "register ID failed\n");
760 return ret;
761 }
762 }
763
764 vbus = &ci->platdata->vbus_extcon;
765 vbus->ci = ci;
766 if (!IS_ERR_OR_NULL(vbus->edev)) {
767 ret = devm_extcon_register_notifier(ci->dev, vbus->edev,
768 EXTCON_USB, &vbus->nb);
769 if (ret < 0) {
770 dev_err(ci->dev, "register VBUS failed\n");
771 return ret;
772 }
773 }
774
775 return 0;
776 }
777
778 static DEFINE_IDA(ci_ida);
779
780 struct platform_device *ci_hdrc_add_device(struct device *dev,
781 struct resource *res, int nres,
782 struct ci_hdrc_platform_data *platdata)
783 {
784 struct platform_device *pdev;
785 int id, ret;
786
787 ret = ci_get_platdata(dev, platdata);
788 if (ret)
789 return ERR_PTR(ret);
790
791 id = ida_simple_get(&ci_ida, 0, 0, GFP_KERNEL);
792 if (id < 0)
793 return ERR_PTR(id);
794
795 pdev = platform_device_alloc("ci_hdrc", id);
796 if (!pdev) {
797 ret = -ENOMEM;
798 goto put_id;
799 }
800
801 pdev->dev.parent = dev;
802
803 ret = platform_device_add_resources(pdev, res, nres);
804 if (ret)
805 goto err;
806
807 ret = platform_device_add_data(pdev, platdata, sizeof(*platdata));
808 if (ret)
809 goto err;
810
811 ret = platform_device_add(pdev);
812 if (ret)
813 goto err;
814
815 return pdev;
816
817 err:
818 platform_device_put(pdev);
819 put_id:
820 ida_simple_remove(&ci_ida, id);
821 return ERR_PTR(ret);
822 }
823 EXPORT_SYMBOL_GPL(ci_hdrc_add_device);
824
825 void ci_hdrc_remove_device(struct platform_device *pdev)
826 {
827 int id = pdev->id;
828 platform_device_unregister(pdev);
829 ida_simple_remove(&ci_ida, id);
830 }
831 EXPORT_SYMBOL_GPL(ci_hdrc_remove_device);
832
833 static inline void ci_role_destroy(struct ci_hdrc *ci)
834 {
835 ci_hdrc_gadget_destroy(ci);
836 ci_hdrc_host_destroy(ci);
837 if (ci->is_otg && ci->roles[CI_ROLE_GADGET])
838 ci_hdrc_otg_destroy(ci);
839 }
840
841 static void ci_get_otg_capable(struct ci_hdrc *ci)
842 {
843 if (ci->platdata->flags & CI_HDRC_DUAL_ROLE_NOT_OTG)
844 ci->is_otg = false;
845 else
846 ci->is_otg = (hw_read(ci, CAP_DCCPARAMS,
847 DCCPARAMS_DC | DCCPARAMS_HC)
848 == (DCCPARAMS_DC | DCCPARAMS_HC));
849 if (ci->is_otg) {
850 dev_dbg(ci->dev, "It is OTG capable controller\n");
851 /* Disable and clear all OTG irq */
852 hw_write_otgsc(ci, OTGSC_INT_EN_BITS | OTGSC_INT_STATUS_BITS,
853 OTGSC_INT_STATUS_BITS);
854 }
855 }
856
857 static ssize_t role_show(struct device *dev, struct device_attribute *attr,
858 char *buf)
859 {
860 struct ci_hdrc *ci = dev_get_drvdata(dev);
861
862 if (ci->role != CI_ROLE_END)
863 return sprintf(buf, "%s\n", ci_role(ci)->name);
864
865 return 0;
866 }
867
868 static ssize_t role_store(struct device *dev,
869 struct device_attribute *attr, const char *buf, size_t n)
870 {
871 struct ci_hdrc *ci = dev_get_drvdata(dev);
872 enum ci_role role;
873 int ret;
874
875 if (!(ci->roles[CI_ROLE_HOST] && ci->roles[CI_ROLE_GADGET])) {
876 dev_warn(dev, "Current configuration is not dual-role, quit\n");
877 return -EPERM;
878 }
879
880 for (role = CI_ROLE_HOST; role < CI_ROLE_END; role++)
881 if (!strncmp(buf, ci->roles[role]->name,
882 strlen(ci->roles[role]->name)))
883 break;
884
885 if (role == CI_ROLE_END || role == ci->role)
886 return -EINVAL;
887
888 pm_runtime_get_sync(dev);
889 disable_irq(ci->irq);
890 ci_role_stop(ci);
891 ret = ci_role_start(ci, role);
892 if (!ret && ci->role == CI_ROLE_GADGET)
893 ci_handle_vbus_change(ci);
894 enable_irq(ci->irq);
895 pm_runtime_put_sync(dev);
896
897 return (ret == 0) ? n : ret;
898 }
899 static DEVICE_ATTR_RW(role);
900
901 static struct attribute *ci_attrs[] = {
902 &dev_attr_role.attr,
903 NULL,
904 };
905
906 static const struct attribute_group ci_attr_group = {
907 .attrs = ci_attrs,
908 };
909
910 static int ci_hdrc_probe(struct platform_device *pdev)
911 {
912 struct device *dev = &pdev->dev;
913 struct ci_hdrc *ci;
914 struct resource *res;
915 void __iomem *base;
916 int ret;
917 enum usb_dr_mode dr_mode;
918
919 if (!dev_get_platdata(dev)) {
920 dev_err(dev, "platform data missing\n");
921 return -ENODEV;
922 }
923
924 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
925 base = devm_ioremap_resource(dev, res);
926 if (IS_ERR(base))
927 return PTR_ERR(base);
928
929 ci = devm_kzalloc(dev, sizeof(*ci), GFP_KERNEL);
930 if (!ci)
931 return -ENOMEM;
932
933 spin_lock_init(&ci->lock);
934 ci->dev = dev;
935 ci->platdata = dev_get_platdata(dev);
936 ci->imx28_write_fix = !!(ci->platdata->flags &
937 CI_HDRC_IMX28_WRITE_FIX);
938 ci->supports_runtime_pm = !!(ci->platdata->flags &
939 CI_HDRC_SUPPORTS_RUNTIME_PM);
940 platform_set_drvdata(pdev, ci);
941
942 ret = hw_device_init(ci, base);
943 if (ret < 0) {
944 dev_err(dev, "can't initialize hardware\n");
945 return -ENODEV;
946 }
947
948 ret = ci_ulpi_init(ci);
949 if (ret)
950 return ret;
951
952 if (ci->platdata->phy) {
953 ci->phy = ci->platdata->phy;
954 } else if (ci->platdata->usb_phy) {
955 ci->usb_phy = ci->platdata->usb_phy;
956 } else {
957 ci->phy = devm_phy_get(dev->parent, "usb-phy");
958 ci->usb_phy = devm_usb_get_phy(dev->parent, USB_PHY_TYPE_USB2);
959
960 /* if both generic PHY and USB PHY layers aren't enabled */
961 if (PTR_ERR(ci->phy) == -ENOSYS &&
962 PTR_ERR(ci->usb_phy) == -ENXIO) {
963 ret = -ENXIO;
964 goto ulpi_exit;
965 }
966
967 if (IS_ERR(ci->phy) && IS_ERR(ci->usb_phy)) {
968 ret = -EPROBE_DEFER;
969 goto ulpi_exit;
970 }
971
972 if (IS_ERR(ci->phy))
973 ci->phy = NULL;
974 else if (IS_ERR(ci->usb_phy))
975 ci->usb_phy = NULL;
976 }
977
978 ret = ci_usb_phy_init(ci);
979 if (ret) {
980 dev_err(dev, "unable to init phy: %d\n", ret);
981 return ret;
982 }
983
984 ci->hw_bank.phys = res->start;
985
986 ci->irq = platform_get_irq(pdev, 0);
987 if (ci->irq < 0) {
988 dev_err(dev, "missing IRQ\n");
989 ret = ci->irq;
990 goto deinit_phy;
991 }
992
993 ci_get_otg_capable(ci);
994
995 dr_mode = ci->platdata->dr_mode;
996 /* initialize role(s) before the interrupt is requested */
997 if (dr_mode == USB_DR_MODE_OTG || dr_mode == USB_DR_MODE_HOST) {
998 ret = ci_hdrc_host_init(ci);
999 if (ret) {
1000 if (ret == -ENXIO)
1001 dev_info(dev, "doesn't support host\n");
1002 else
1003 goto deinit_phy;
1004 }
1005 }
1006
1007 if (dr_mode == USB_DR_MODE_OTG || dr_mode == USB_DR_MODE_PERIPHERAL) {
1008 ret = ci_hdrc_gadget_init(ci);
1009 if (ret) {
1010 if (ret == -ENXIO)
1011 dev_info(dev, "doesn't support gadget\n");
1012 else
1013 goto deinit_host;
1014 }
1015 }
1016
1017 if (!ci->roles[CI_ROLE_HOST] && !ci->roles[CI_ROLE_GADGET]) {
1018 dev_err(dev, "no supported roles\n");
1019 ret = -ENODEV;
1020 goto deinit_gadget;
1021 }
1022
1023 if (ci->is_otg && ci->roles[CI_ROLE_GADGET]) {
1024 ret = ci_hdrc_otg_init(ci);
1025 if (ret) {
1026 dev_err(dev, "init otg fails, ret = %d\n", ret);
1027 goto deinit_gadget;
1028 }
1029 }
1030
1031 if (ci->roles[CI_ROLE_HOST] && ci->roles[CI_ROLE_GADGET]) {
1032 if (ci->is_otg) {
1033 ci->role = ci_otg_role(ci);
1034 /* Enable ID change irq */
1035 hw_write_otgsc(ci, OTGSC_IDIE, OTGSC_IDIE);
1036 } else {
1037 /*
1038 * If the controller is not OTG capable, but support
1039 * role switch, the defalt role is gadget, and the
1040 * user can switch it through debugfs.
1041 */
1042 ci->role = CI_ROLE_GADGET;
1043 }
1044 } else {
1045 ci->role = ci->roles[CI_ROLE_HOST]
1046 ? CI_ROLE_HOST
1047 : CI_ROLE_GADGET;
1048 }
1049
1050 if (!ci_otg_is_fsm_mode(ci)) {
1051 /* only update vbus status for peripheral */
1052 if (ci->role == CI_ROLE_GADGET)
1053 ci_handle_vbus_change(ci);
1054
1055 ret = ci_role_start(ci, ci->role);
1056 if (ret) {
1057 dev_err(dev, "can't start %s role\n",
1058 ci_role(ci)->name);
1059 goto stop;
1060 }
1061 }
1062
1063 ret = devm_request_irq(dev, ci->irq, ci_irq, IRQF_SHARED,
1064 ci->platdata->name, ci);
1065 if (ret)
1066 goto stop;
1067
1068 ret = ci_extcon_register(ci);
1069 if (ret)
1070 goto stop;
1071
1072 if (ci->supports_runtime_pm) {
1073 pm_runtime_set_active(&pdev->dev);
1074 pm_runtime_enable(&pdev->dev);
1075 pm_runtime_set_autosuspend_delay(&pdev->dev, 2000);
1076 pm_runtime_mark_last_busy(ci->dev);
1077 pm_runtime_use_autosuspend(&pdev->dev);
1078 }
1079
1080 if (ci_otg_is_fsm_mode(ci))
1081 ci_hdrc_otg_fsm_start(ci);
1082
1083 device_set_wakeup_capable(&pdev->dev, true);
1084 dbg_create_files(ci);
1085
1086 ret = sysfs_create_group(&dev->kobj, &ci_attr_group);
1087 if (ret)
1088 goto remove_debug;
1089
1090 return 0;
1091
1092 remove_debug:
1093 dbg_remove_files(ci);
1094 stop:
1095 if (ci->is_otg && ci->roles[CI_ROLE_GADGET])
1096 ci_hdrc_otg_destroy(ci);
1097 deinit_gadget:
1098 ci_hdrc_gadget_destroy(ci);
1099 deinit_host:
1100 ci_hdrc_host_destroy(ci);
1101 deinit_phy:
1102 ci_usb_phy_exit(ci);
1103 ulpi_exit:
1104 ci_ulpi_exit(ci);
1105
1106 return ret;
1107 }
1108
1109 static int ci_hdrc_remove(struct platform_device *pdev)
1110 {
1111 struct ci_hdrc *ci = platform_get_drvdata(pdev);
1112
1113 if (ci->supports_runtime_pm) {
1114 pm_runtime_get_sync(&pdev->dev);
1115 pm_runtime_disable(&pdev->dev);
1116 pm_runtime_put_noidle(&pdev->dev);
1117 }
1118
1119 dbg_remove_files(ci);
1120 sysfs_remove_group(&ci->dev->kobj, &ci_attr_group);
1121 ci_role_destroy(ci);
1122 ci_hdrc_enter_lpm(ci, true);
1123 ci_usb_phy_exit(ci);
1124 ci_ulpi_exit(ci);
1125
1126 return 0;
1127 }
1128
1129 #ifdef CONFIG_PM
1130 /* Prepare wakeup by SRP before suspend */
1131 static void ci_otg_fsm_suspend_for_srp(struct ci_hdrc *ci)
1132 {
1133 if ((ci->fsm.otg->state == OTG_STATE_A_IDLE) &&
1134 !hw_read_otgsc(ci, OTGSC_ID)) {
1135 hw_write(ci, OP_PORTSC, PORTSC_W1C_BITS | PORTSC_PP,
1136 PORTSC_PP);
1137 hw_write(ci, OP_PORTSC, PORTSC_W1C_BITS | PORTSC_WKCN,
1138 PORTSC_WKCN);
1139 }
1140 }
1141
1142 /* Handle SRP when wakeup by data pulse */
1143 static void ci_otg_fsm_wakeup_by_srp(struct ci_hdrc *ci)
1144 {
1145 if ((ci->fsm.otg->state == OTG_STATE_A_IDLE) &&
1146 (ci->fsm.a_bus_drop == 1) && (ci->fsm.a_bus_req == 0)) {
1147 if (!hw_read_otgsc(ci, OTGSC_ID)) {
1148 ci->fsm.a_srp_det = 1;
1149 ci->fsm.a_bus_drop = 0;
1150 } else {
1151 ci->fsm.id = 1;
1152 }
1153 ci_otg_queue_work(ci);
1154 }
1155 }
1156
1157 static void ci_controller_suspend(struct ci_hdrc *ci)
1158 {
1159 disable_irq(ci->irq);
1160 ci_hdrc_enter_lpm(ci, true);
1161 if (ci->platdata->phy_clkgate_delay_us)
1162 usleep_range(ci->platdata->phy_clkgate_delay_us,
1163 ci->platdata->phy_clkgate_delay_us + 50);
1164 usb_phy_set_suspend(ci->usb_phy, 1);
1165 ci->in_lpm = true;
1166 enable_irq(ci->irq);
1167 }
1168
1169 static int ci_controller_resume(struct device *dev)
1170 {
1171 struct ci_hdrc *ci = dev_get_drvdata(dev);
1172 int ret;
1173
1174 dev_dbg(dev, "at %s\n", __func__);
1175
1176 if (!ci->in_lpm) {
1177 WARN_ON(1);
1178 return 0;
1179 }
1180
1181 ci_hdrc_enter_lpm(ci, false);
1182
1183 ret = ci_ulpi_resume(ci);
1184 if (ret)
1185 return ret;
1186
1187 if (ci->usb_phy) {
1188 usb_phy_set_suspend(ci->usb_phy, 0);
1189 usb_phy_set_wakeup(ci->usb_phy, false);
1190 hw_wait_phy_stable();
1191 }
1192
1193 ci->in_lpm = false;
1194 if (ci->wakeup_int) {
1195 ci->wakeup_int = false;
1196 pm_runtime_mark_last_busy(ci->dev);
1197 pm_runtime_put_autosuspend(ci->dev);
1198 enable_irq(ci->irq);
1199 if (ci_otg_is_fsm_mode(ci))
1200 ci_otg_fsm_wakeup_by_srp(ci);
1201 }
1202
1203 return 0;
1204 }
1205
1206 #ifdef CONFIG_PM_SLEEP
1207 static int ci_suspend(struct device *dev)
1208 {
1209 struct ci_hdrc *ci = dev_get_drvdata(dev);
1210
1211 if (ci->wq)
1212 flush_workqueue(ci->wq);
1213 /*
1214 * Controller needs to be active during suspend, otherwise the core
1215 * may run resume when the parent is at suspend if other driver's
1216 * suspend fails, it occurs before parent's suspend has not started,
1217 * but the core suspend has finished.
1218 */
1219 if (ci->in_lpm)
1220 pm_runtime_resume(dev);
1221
1222 if (ci->in_lpm) {
1223 WARN_ON(1);
1224 return 0;
1225 }
1226
1227 if (device_may_wakeup(dev)) {
1228 if (ci_otg_is_fsm_mode(ci))
1229 ci_otg_fsm_suspend_for_srp(ci);
1230
1231 usb_phy_set_wakeup(ci->usb_phy, true);
1232 enable_irq_wake(ci->irq);
1233 }
1234
1235 ci_controller_suspend(ci);
1236
1237 return 0;
1238 }
1239
1240 static int ci_resume(struct device *dev)
1241 {
1242 struct ci_hdrc *ci = dev_get_drvdata(dev);
1243 int ret;
1244
1245 if (device_may_wakeup(dev))
1246 disable_irq_wake(ci->irq);
1247
1248 ret = ci_controller_resume(dev);
1249 if (ret)
1250 return ret;
1251
1252 if (ci->supports_runtime_pm) {
1253 pm_runtime_disable(dev);
1254 pm_runtime_set_active(dev);
1255 pm_runtime_enable(dev);
1256 }
1257
1258 return ret;
1259 }
1260 #endif /* CONFIG_PM_SLEEP */
1261
1262 static int ci_runtime_suspend(struct device *dev)
1263 {
1264 struct ci_hdrc *ci = dev_get_drvdata(dev);
1265
1266 dev_dbg(dev, "at %s\n", __func__);
1267
1268 if (ci->in_lpm) {
1269 WARN_ON(1);
1270 return 0;
1271 }
1272
1273 if (ci_otg_is_fsm_mode(ci))
1274 ci_otg_fsm_suspend_for_srp(ci);
1275
1276 usb_phy_set_wakeup(ci->usb_phy, true);
1277 ci_controller_suspend(ci);
1278
1279 return 0;
1280 }
1281
1282 static int ci_runtime_resume(struct device *dev)
1283 {
1284 return ci_controller_resume(dev);
1285 }
1286
1287 #endif /* CONFIG_PM */
1288 static const struct dev_pm_ops ci_pm_ops = {
1289 SET_SYSTEM_SLEEP_PM_OPS(ci_suspend, ci_resume)
1290 SET_RUNTIME_PM_OPS(ci_runtime_suspend, ci_runtime_resume, NULL)
1291 };
1292
1293 static struct platform_driver ci_hdrc_driver = {
1294 .probe = ci_hdrc_probe,
1295 .remove = ci_hdrc_remove,
1296 .driver = {
1297 .name = "ci_hdrc",
1298 .pm = &ci_pm_ops,
1299 },
1300 };
1301
1302 static int __init ci_hdrc_platform_register(void)
1303 {
1304 ci_hdrc_host_driver_init();
1305 return platform_driver_register(&ci_hdrc_driver);
1306 }
1307 module_init(ci_hdrc_platform_register);
1308
1309 static void __exit ci_hdrc_platform_unregister(void)
1310 {
1311 platform_driver_unregister(&ci_hdrc_driver);
1312 }
1313 module_exit(ci_hdrc_platform_unregister);
1314
1315 MODULE_ALIAS("platform:ci_hdrc");
1316 MODULE_LICENSE("GPL v2");
1317 MODULE_AUTHOR("David Lopo <dlopo@chipidea.mips.com>");
1318 MODULE_DESCRIPTION("ChipIdea HDRC Driver");
Linux with added FPC-III support