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perf python: Do not force closing original perf descriptor in evlist.get_pollfd()
[linux/fpc-iii.git] / drivers / usb / dwc3 / core.c
blob2f2048aa5fde13dde439e52236620f9bab603118
1 // SPDX-License-Identifier: GPL-2.0
2 /**
3 * core.c - DesignWare USB3 DRD Controller Core file
4 *
5 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
6 *
7 * Authors: Felipe Balbi <balbi@ti.com>,
8 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
9 */
10
11 #include <linux/clk.h>
12 #include <linux/version.h>
13 #include <linux/module.h>
14 #include <linux/kernel.h>
15 #include <linux/slab.h>
16 #include <linux/spinlock.h>
17 #include <linux/platform_device.h>
18 #include <linux/pm_runtime.h>
19 #include <linux/interrupt.h>
20 #include <linux/ioport.h>
21 #include <linux/io.h>
22 #include <linux/list.h>
23 #include <linux/delay.h>
24 #include <linux/dma-mapping.h>
25 #include <linux/of.h>
26 #include <linux/acpi.h>
27 #include <linux/pinctrl/consumer.h>
28 #include <linux/reset.h>
29
30 #include <linux/usb/ch9.h>
31 #include <linux/usb/gadget.h>
32 #include <linux/usb/of.h>
33 #include <linux/usb/otg.h>
34
35 #include "core.h"
36 #include "gadget.h"
37 #include "io.h"
38
39 #include "debug.h"
40
41 #define DWC3_DEFAULT_AUTOSUSPEND_DELAY 5000 /* ms */
42
43 /**
44 * dwc3_get_dr_mode - Validates and sets dr_mode
45 * @dwc: pointer to our context structure
46 */
47 static int dwc3_get_dr_mode(struct dwc3 *dwc)
48 {
49 enum usb_dr_mode mode;
50 struct device *dev = dwc->dev;
51 unsigned int hw_mode;
52
53 if (dwc->dr_mode == USB_DR_MODE_UNKNOWN)
54 dwc->dr_mode = USB_DR_MODE_OTG;
55
56 mode = dwc->dr_mode;
57 hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0);
58
59 switch (hw_mode) {
60 case DWC3_GHWPARAMS0_MODE_GADGET:
61 if (IS_ENABLED(CONFIG_USB_DWC3_HOST)) {
62 dev_err(dev,
63 "Controller does not support host mode.\n");
64 return -EINVAL;
65 }
66 mode = USB_DR_MODE_PERIPHERAL;
67 break;
68 case DWC3_GHWPARAMS0_MODE_HOST:
69 if (IS_ENABLED(CONFIG_USB_DWC3_GADGET)) {
70 dev_err(dev,
71 "Controller does not support device mode.\n");
72 return -EINVAL;
73 }
74 mode = USB_DR_MODE_HOST;
75 break;
76 default:
77 if (IS_ENABLED(CONFIG_USB_DWC3_HOST))
78 mode = USB_DR_MODE_HOST;
79 else if (IS_ENABLED(CONFIG_USB_DWC3_GADGET))
80 mode = USB_DR_MODE_PERIPHERAL;
81
82 /*
83 * dwc_usb31 does not support OTG mode. If the controller
84 * supports DRD but the dr_mode is not specified or set to OTG,
85 * then set the mode to peripheral.
86 */
87 if (mode == USB_DR_MODE_OTG && dwc3_is_usb31(dwc))
88 mode = USB_DR_MODE_PERIPHERAL;
89 }
90
91 if (mode != dwc->dr_mode) {
92 dev_warn(dev,
93 "Configuration mismatch. dr_mode forced to %s\n",
94 mode == USB_DR_MODE_HOST ? "host" : "gadget");
95
96 dwc->dr_mode = mode;
97 }
98
99 return 0;
100 }
101
102 void dwc3_set_prtcap(struct dwc3 *dwc, u32 mode)
103 {
104 u32 reg;
105
106 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
107 reg &= ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG));
108 reg |= DWC3_GCTL_PRTCAPDIR(mode);
109 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
110
111 dwc->current_dr_role = mode;
112 }
113
114 static void __dwc3_set_mode(struct work_struct *work)
115 {
116 struct dwc3 *dwc = work_to_dwc(work);
117 unsigned long flags;
118 int ret;
119
120 if (dwc->dr_mode != USB_DR_MODE_OTG)
121 return;
122
123 if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_OTG)
124 dwc3_otg_update(dwc, 0);
125
126 if (!dwc->desired_dr_role)
127 return;
128
129 if (dwc->desired_dr_role == dwc->current_dr_role)
130 return;
131
132 if (dwc->desired_dr_role == DWC3_GCTL_PRTCAP_OTG && dwc->edev)
133 return;
134
135 switch (dwc->current_dr_role) {
136 case DWC3_GCTL_PRTCAP_HOST:
137 dwc3_host_exit(dwc);
138 break;
139 case DWC3_GCTL_PRTCAP_DEVICE:
140 dwc3_gadget_exit(dwc);
141 dwc3_event_buffers_cleanup(dwc);
142 break;
143 case DWC3_GCTL_PRTCAP_OTG:
144 dwc3_otg_exit(dwc);
145 spin_lock_irqsave(&dwc->lock, flags);
146 dwc->desired_otg_role = DWC3_OTG_ROLE_IDLE;
147 spin_unlock_irqrestore(&dwc->lock, flags);
148 dwc3_otg_update(dwc, 1);
149 break;
150 default:
151 break;
152 }
153
154 spin_lock_irqsave(&dwc->lock, flags);
155
156 dwc3_set_prtcap(dwc, dwc->desired_dr_role);
157
158 spin_unlock_irqrestore(&dwc->lock, flags);
159
160 switch (dwc->desired_dr_role) {
161 case DWC3_GCTL_PRTCAP_HOST:
162 ret = dwc3_host_init(dwc);
163 if (ret) {
164 dev_err(dwc->dev, "failed to initialize host\n");
165 } else {
166 if (dwc->usb2_phy)
167 otg_set_vbus(dwc->usb2_phy->otg, true);
168 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_HOST);
169 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_HOST);
170 phy_calibrate(dwc->usb2_generic_phy);
171 }
172 break;
173 case DWC3_GCTL_PRTCAP_DEVICE:
174 dwc3_event_buffers_setup(dwc);
175
176 if (dwc->usb2_phy)
177 otg_set_vbus(dwc->usb2_phy->otg, false);
178 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_DEVICE);
179 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_DEVICE);
180
181 ret = dwc3_gadget_init(dwc);
182 if (ret)
183 dev_err(dwc->dev, "failed to initialize peripheral\n");
184 break;
185 case DWC3_GCTL_PRTCAP_OTG:
186 dwc3_otg_init(dwc);
187 dwc3_otg_update(dwc, 0);
188 break;
189 default:
190 break;
191 }
192
193 }
194
195 void dwc3_set_mode(struct dwc3 *dwc, u32 mode)
196 {
197 unsigned long flags;
198
199 spin_lock_irqsave(&dwc->lock, flags);
200 dwc->desired_dr_role = mode;
201 spin_unlock_irqrestore(&dwc->lock, flags);
202
203 queue_work(system_freezable_wq, &dwc->drd_work);
204 }
205
206 u32 dwc3_core_fifo_space(struct dwc3_ep *dep, u8 type)
207 {
208 struct dwc3 *dwc = dep->dwc;
209 u32 reg;
210
211 dwc3_writel(dwc->regs, DWC3_GDBGFIFOSPACE,
212 DWC3_GDBGFIFOSPACE_NUM(dep->number) |
213 DWC3_GDBGFIFOSPACE_TYPE(type));
214
215 reg = dwc3_readl(dwc->regs, DWC3_GDBGFIFOSPACE);
216
217 return DWC3_GDBGFIFOSPACE_SPACE_AVAILABLE(reg);
218 }
219
220 /**
221 * dwc3_core_soft_reset - Issues core soft reset and PHY reset
222 * @dwc: pointer to our context structure
223 */
224 static int dwc3_core_soft_reset(struct dwc3 *dwc)
225 {
226 u32 reg;
227 int retries = 1000;
228 int ret;
229
230 usb_phy_init(dwc->usb2_phy);
231 usb_phy_init(dwc->usb3_phy);
232 ret = phy_init(dwc->usb2_generic_phy);
233 if (ret < 0)
234 return ret;
235
236 ret = phy_init(dwc->usb3_generic_phy);
237 if (ret < 0) {
238 phy_exit(dwc->usb2_generic_phy);
239 return ret;
240 }
241
242 /*
243 * We're resetting only the device side because, if we're in host mode,
244 * XHCI driver will reset the host block. If dwc3 was configured for
245 * host-only mode, then we can return early.
246 */
247 if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_HOST)
248 return 0;
249
250 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
251 reg |= DWC3_DCTL_CSFTRST;
252 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
253
254 do {
255 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
256 if (!(reg & DWC3_DCTL_CSFTRST))
257 goto done;
258
259 udelay(1);
260 } while (--retries);
261
262 phy_exit(dwc->usb3_generic_phy);
263 phy_exit(dwc->usb2_generic_phy);
264
265 return -ETIMEDOUT;
266
267 done:
268 /*
269 * For DWC_usb31 controller, once DWC3_DCTL_CSFTRST bit is cleared,
270 * we must wait at least 50ms before accessing the PHY domain
271 * (synchronization delay). DWC_usb31 programming guide section 1.3.2.
272 */
273 if (dwc3_is_usb31(dwc))
274 msleep(50);
275
276 return 0;
277 }
278
279 static const struct clk_bulk_data dwc3_core_clks[] = {
280 { .id = "ref" },
281 { .id = "bus_early" },
282 { .id = "suspend" },
283 };
284
285 /*
286 * dwc3_frame_length_adjustment - Adjusts frame length if required
287 * @dwc3: Pointer to our controller context structure
288 */
289 static void dwc3_frame_length_adjustment(struct dwc3 *dwc)
290 {
291 u32 reg;
292 u32 dft;
293
294 if (dwc->revision < DWC3_REVISION_250A)
295 return;
296
297 if (dwc->fladj == 0)
298 return;
299
300 reg = dwc3_readl(dwc->regs, DWC3_GFLADJ);
301 dft = reg & DWC3_GFLADJ_30MHZ_MASK;
302 if (!dev_WARN_ONCE(dwc->dev, dft == dwc->fladj,
303 "request value same as default, ignoring\n")) {
304 reg &= ~DWC3_GFLADJ_30MHZ_MASK;
305 reg |= DWC3_GFLADJ_30MHZ_SDBND_SEL | dwc->fladj;
306 dwc3_writel(dwc->regs, DWC3_GFLADJ, reg);
307 }
308 }
309
310 /**
311 * dwc3_free_one_event_buffer - Frees one event buffer
312 * @dwc: Pointer to our controller context structure
313 * @evt: Pointer to event buffer to be freed
314 */
315 static void dwc3_free_one_event_buffer(struct dwc3 *dwc,
316 struct dwc3_event_buffer *evt)
317 {
318 dma_free_coherent(dwc->sysdev, evt->length, evt->buf, evt->dma);
319 }
320
321 /**
322 * dwc3_alloc_one_event_buffer - Allocates one event buffer structure
323 * @dwc: Pointer to our controller context structure
324 * @length: size of the event buffer
325 *
326 * Returns a pointer to the allocated event buffer structure on success
327 * otherwise ERR_PTR(errno).
328 */
329 static struct dwc3_event_buffer *dwc3_alloc_one_event_buffer(struct dwc3 *dwc,
330 unsigned length)
331 {
332 struct dwc3_event_buffer *evt;
333
334 evt = devm_kzalloc(dwc->dev, sizeof(*evt), GFP_KERNEL);
335 if (!evt)
336 return ERR_PTR(-ENOMEM);
337
338 evt->dwc = dwc;
339 evt->length = length;
340 evt->cache = devm_kzalloc(dwc->dev, length, GFP_KERNEL);
341 if (!evt->cache)
342 return ERR_PTR(-ENOMEM);
343
344 evt->buf = dma_alloc_coherent(dwc->sysdev, length,
345 &evt->dma, GFP_KERNEL);
346 if (!evt->buf)
347 return ERR_PTR(-ENOMEM);
348
349 return evt;
350 }
351
352 /**
353 * dwc3_free_event_buffers - frees all allocated event buffers
354 * @dwc: Pointer to our controller context structure
355 */
356 static void dwc3_free_event_buffers(struct dwc3 *dwc)
357 {
358 struct dwc3_event_buffer *evt;
359
360 evt = dwc->ev_buf;
361 if (evt)
362 dwc3_free_one_event_buffer(dwc, evt);
363 }
364
365 /**
366 * dwc3_alloc_event_buffers - Allocates @num event buffers of size @length
367 * @dwc: pointer to our controller context structure
368 * @length: size of event buffer
369 *
370 * Returns 0 on success otherwise negative errno. In the error case, dwc
371 * may contain some buffers allocated but not all which were requested.
372 */
373 static int dwc3_alloc_event_buffers(struct dwc3 *dwc, unsigned length)
374 {
375 struct dwc3_event_buffer *evt;
376
377 evt = dwc3_alloc_one_event_buffer(dwc, length);
378 if (IS_ERR(evt)) {
379 dev_err(dwc->dev, "can't allocate event buffer\n");
380 return PTR_ERR(evt);
381 }
382 dwc->ev_buf = evt;
383
384 return 0;
385 }
386
387 /**
388 * dwc3_event_buffers_setup - setup our allocated event buffers
389 * @dwc: pointer to our controller context structure
390 *
391 * Returns 0 on success otherwise negative errno.
392 */
393 int dwc3_event_buffers_setup(struct dwc3 *dwc)
394 {
395 struct dwc3_event_buffer *evt;
396
397 evt = dwc->ev_buf;
398 evt->lpos = 0;
399 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0),
400 lower_32_bits(evt->dma));
401 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0),
402 upper_32_bits(evt->dma));
403 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0),
404 DWC3_GEVNTSIZ_SIZE(evt->length));
405 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 0);
406
407 return 0;
408 }
409
410 void dwc3_event_buffers_cleanup(struct dwc3 *dwc)
411 {
412 struct dwc3_event_buffer *evt;
413
414 evt = dwc->ev_buf;
415
416 evt->lpos = 0;
417
418 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0), 0);
419 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0), 0);
420 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), DWC3_GEVNTSIZ_INTMASK
421 | DWC3_GEVNTSIZ_SIZE(0));
422 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 0);
423 }
424
425 static int dwc3_alloc_scratch_buffers(struct dwc3 *dwc)
426 {
427 if (!dwc->has_hibernation)
428 return 0;
429
430 if (!dwc->nr_scratch)
431 return 0;
432
433 dwc->scratchbuf = kmalloc_array(dwc->nr_scratch,
434 DWC3_SCRATCHBUF_SIZE, GFP_KERNEL);
435 if (!dwc->scratchbuf)
436 return -ENOMEM;
437
438 return 0;
439 }
440
441 static int dwc3_setup_scratch_buffers(struct dwc3 *dwc)
442 {
443 dma_addr_t scratch_addr;
444 u32 param;
445 int ret;
446
447 if (!dwc->has_hibernation)
448 return 0;
449
450 if (!dwc->nr_scratch)
451 return 0;
452
453 /* should never fall here */
454 if (!WARN_ON(dwc->scratchbuf))
455 return 0;
456
457 scratch_addr = dma_map_single(dwc->sysdev, dwc->scratchbuf,
458 dwc->nr_scratch * DWC3_SCRATCHBUF_SIZE,
459 DMA_BIDIRECTIONAL);
460 if (dma_mapping_error(dwc->sysdev, scratch_addr)) {
461 dev_err(dwc->sysdev, "failed to map scratch buffer\n");
462 ret = -EFAULT;
463 goto err0;
464 }
465
466 dwc->scratch_addr = scratch_addr;
467
468 param = lower_32_bits(scratch_addr);
469
470 ret = dwc3_send_gadget_generic_command(dwc,
471 DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO, param);
472 if (ret < 0)
473 goto err1;
474
475 param = upper_32_bits(scratch_addr);
476
477 ret = dwc3_send_gadget_generic_command(dwc,
478 DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI, param);
479 if (ret < 0)
480 goto err1;
481
482 return 0;
483
484 err1:
485 dma_unmap_single(dwc->sysdev, dwc->scratch_addr, dwc->nr_scratch *
486 DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL);
487
488 err0:
489 return ret;
490 }
491
492 static void dwc3_free_scratch_buffers(struct dwc3 *dwc)
493 {
494 if (!dwc->has_hibernation)
495 return;
496
497 if (!dwc->nr_scratch)
498 return;
499
500 /* should never fall here */
501 if (!WARN_ON(dwc->scratchbuf))
502 return;
503
504 dma_unmap_single(dwc->sysdev, dwc->scratch_addr, dwc->nr_scratch *
505 DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL);
506 kfree(dwc->scratchbuf);
507 }
508
509 static void dwc3_core_num_eps(struct dwc3 *dwc)
510 {
511 struct dwc3_hwparams *parms = &dwc->hwparams;
512
513 dwc->num_eps = DWC3_NUM_EPS(parms);
514 }
515
516 static void dwc3_cache_hwparams(struct dwc3 *dwc)
517 {
518 struct dwc3_hwparams *parms = &dwc->hwparams;
519
520 parms->hwparams0 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS0);
521 parms->hwparams1 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS1);
522 parms->hwparams2 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS2);
523 parms->hwparams3 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS3);
524 parms->hwparams4 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS4);
525 parms->hwparams5 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS5);
526 parms->hwparams6 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS6);
527 parms->hwparams7 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS7);
528 parms->hwparams8 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS8);
529 }
530
531 static int dwc3_core_ulpi_init(struct dwc3 *dwc)
532 {
533 int intf;
534 int ret = 0;
535
536 intf = DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3);
537
538 if (intf == DWC3_GHWPARAMS3_HSPHY_IFC_ULPI ||
539 (intf == DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI &&
540 dwc->hsphy_interface &&
541 !strncmp(dwc->hsphy_interface, "ulpi", 4)))
542 ret = dwc3_ulpi_init(dwc);
543
544 return ret;
545 }
546
547 /**
548 * dwc3_phy_setup - Configure USB PHY Interface of DWC3 Core
549 * @dwc: Pointer to our controller context structure
550 *
551 * Returns 0 on success. The USB PHY interfaces are configured but not
552 * initialized. The PHY interfaces and the PHYs get initialized together with
553 * the core in dwc3_core_init.
554 */
555 static int dwc3_phy_setup(struct dwc3 *dwc)
556 {
557 u32 reg;
558
559 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
560
561 /*
562 * Make sure UX_EXIT_PX is cleared as that causes issues with some
563 * PHYs. Also, this bit is not supposed to be used in normal operation.
564 */
565 reg &= ~DWC3_GUSB3PIPECTL_UX_EXIT_PX;
566
567 /*
568 * Above 1.94a, it is recommended to set DWC3_GUSB3PIPECTL_SUSPHY
569 * to '0' during coreConsultant configuration. So default value
570 * will be '0' when the core is reset. Application needs to set it
571 * to '1' after the core initialization is completed.
572 */
573 if (dwc->revision > DWC3_REVISION_194A)
574 reg |= DWC3_GUSB3PIPECTL_SUSPHY;
575
576 if (dwc->u2ss_inp3_quirk)
577 reg |= DWC3_GUSB3PIPECTL_U2SSINP3OK;
578
579 if (dwc->dis_rxdet_inp3_quirk)
580 reg |= DWC3_GUSB3PIPECTL_DISRXDETINP3;
581
582 if (dwc->req_p1p2p3_quirk)
583 reg |= DWC3_GUSB3PIPECTL_REQP1P2P3;
584
585 if (dwc->del_p1p2p3_quirk)
586 reg |= DWC3_GUSB3PIPECTL_DEP1P2P3_EN;
587
588 if (dwc->del_phy_power_chg_quirk)
589 reg |= DWC3_GUSB3PIPECTL_DEPOCHANGE;
590
591 if (dwc->lfps_filter_quirk)
592 reg |= DWC3_GUSB3PIPECTL_LFPSFILT;
593
594 if (dwc->rx_detect_poll_quirk)
595 reg |= DWC3_GUSB3PIPECTL_RX_DETOPOLL;
596
597 if (dwc->tx_de_emphasis_quirk)
598 reg |= DWC3_GUSB3PIPECTL_TX_DEEPH(dwc->tx_de_emphasis);
599
600 if (dwc->dis_u3_susphy_quirk)
601 reg &= ~DWC3_GUSB3PIPECTL_SUSPHY;
602
603 if (dwc->dis_del_phy_power_chg_quirk)
604 reg &= ~DWC3_GUSB3PIPECTL_DEPOCHANGE;
605
606 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
607
608 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
609
610 /* Select the HS PHY interface */
611 switch (DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3)) {
612 case DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI:
613 if (dwc->hsphy_interface &&
614 !strncmp(dwc->hsphy_interface, "utmi", 4)) {
615 reg &= ~DWC3_GUSB2PHYCFG_ULPI_UTMI;
616 break;
617 } else if (dwc->hsphy_interface &&
618 !strncmp(dwc->hsphy_interface, "ulpi", 4)) {
619 reg |= DWC3_GUSB2PHYCFG_ULPI_UTMI;
620 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
621 } else {
622 /* Relying on default value. */
623 if (!(reg & DWC3_GUSB2PHYCFG_ULPI_UTMI))
624 break;
625 }
626 /* FALLTHROUGH */
627 case DWC3_GHWPARAMS3_HSPHY_IFC_ULPI:
628 /* FALLTHROUGH */
629 default:
630 break;
631 }
632
633 switch (dwc->hsphy_mode) {
634 case USBPHY_INTERFACE_MODE_UTMI:
635 reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK |
636 DWC3_GUSB2PHYCFG_USBTRDTIM_MASK);
637 reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_8_BIT) |
638 DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_8_BIT);
639 break;
640 case USBPHY_INTERFACE_MODE_UTMIW:
641 reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK |
642 DWC3_GUSB2PHYCFG_USBTRDTIM_MASK);
643 reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_16_BIT) |
644 DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_16_BIT);
645 break;
646 default:
647 break;
648 }
649
650 /*
651 * Above 1.94a, it is recommended to set DWC3_GUSB2PHYCFG_SUSPHY to
652 * '0' during coreConsultant configuration. So default value will
653 * be '0' when the core is reset. Application needs to set it to
654 * '1' after the core initialization is completed.
655 */
656 if (dwc->revision > DWC3_REVISION_194A)
657 reg |= DWC3_GUSB2PHYCFG_SUSPHY;
658
659 if (dwc->dis_u2_susphy_quirk)
660 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
661
662 if (dwc->dis_enblslpm_quirk)
663 reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
664
665 if (dwc->dis_u2_freeclk_exists_quirk)
666 reg &= ~DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS;
667
668 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
669
670 return 0;
671 }
672
673 static void dwc3_core_exit(struct dwc3 *dwc)
674 {
675 dwc3_event_buffers_cleanup(dwc);
676
677 usb_phy_shutdown(dwc->usb2_phy);
678 usb_phy_shutdown(dwc->usb3_phy);
679 phy_exit(dwc->usb2_generic_phy);
680 phy_exit(dwc->usb3_generic_phy);
681
682 usb_phy_set_suspend(dwc->usb2_phy, 1);
683 usb_phy_set_suspend(dwc->usb3_phy, 1);
684 phy_power_off(dwc->usb2_generic_phy);
685 phy_power_off(dwc->usb3_generic_phy);
686 clk_bulk_disable(dwc->num_clks, dwc->clks);
687 clk_bulk_unprepare(dwc->num_clks, dwc->clks);
688 reset_control_assert(dwc->reset);
689 }
690
691 static bool dwc3_core_is_valid(struct dwc3 *dwc)
692 {
693 u32 reg;
694
695 reg = dwc3_readl(dwc->regs, DWC3_GSNPSID);
696
697 /* This should read as U3 followed by revision number */
698 if ((reg & DWC3_GSNPSID_MASK) == 0x55330000) {
699 /* Detected DWC_usb3 IP */
700 dwc->revision = reg;
701 } else if ((reg & DWC3_GSNPSID_MASK) == 0x33310000) {
702 /* Detected DWC_usb31 IP */
703 dwc->revision = dwc3_readl(dwc->regs, DWC3_VER_NUMBER);
704 dwc->revision |= DWC3_REVISION_IS_DWC31;
705 } else {
706 return false;
707 }
708
709 return true;
710 }
711
712 static void dwc3_core_setup_global_control(struct dwc3 *dwc)
713 {
714 u32 hwparams4 = dwc->hwparams.hwparams4;
715 u32 reg;
716
717 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
718 reg &= ~DWC3_GCTL_SCALEDOWN_MASK;
719
720 switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1)) {
721 case DWC3_GHWPARAMS1_EN_PWROPT_CLK:
722 /**
723 * WORKAROUND: DWC3 revisions between 2.10a and 2.50a have an
724 * issue which would cause xHCI compliance tests to fail.
725 *
726 * Because of that we cannot enable clock gating on such
727 * configurations.
728 *
729 * Refers to:
730 *
731 * STAR#9000588375: Clock Gating, SOF Issues when ref_clk-Based
732 * SOF/ITP Mode Used
733 */
734 if ((dwc->dr_mode == USB_DR_MODE_HOST ||
735 dwc->dr_mode == USB_DR_MODE_OTG) &&
736 (dwc->revision >= DWC3_REVISION_210A &&
737 dwc->revision <= DWC3_REVISION_250A))
738 reg |= DWC3_GCTL_DSBLCLKGTNG | DWC3_GCTL_SOFITPSYNC;
739 else
740 reg &= ~DWC3_GCTL_DSBLCLKGTNG;
741 break;
742 case DWC3_GHWPARAMS1_EN_PWROPT_HIB:
743 /* enable hibernation here */
744 dwc->nr_scratch = DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(hwparams4);
745
746 /*
747 * REVISIT Enabling this bit so that host-mode hibernation
748 * will work. Device-mode hibernation is not yet implemented.
749 */
750 reg |= DWC3_GCTL_GBLHIBERNATIONEN;
751 break;
752 default:
753 /* nothing */
754 break;
755 }
756
757 /* check if current dwc3 is on simulation board */
758 if (dwc->hwparams.hwparams6 & DWC3_GHWPARAMS6_EN_FPGA) {
759 dev_info(dwc->dev, "Running with FPGA optimizations\n");
760 dwc->is_fpga = true;
761 }
762
763 WARN_ONCE(dwc->disable_scramble_quirk && !dwc->is_fpga,
764 "disable_scramble cannot be used on non-FPGA builds\n");
765
766 if (dwc->disable_scramble_quirk && dwc->is_fpga)
767 reg |= DWC3_GCTL_DISSCRAMBLE;
768 else
769 reg &= ~DWC3_GCTL_DISSCRAMBLE;
770
771 if (dwc->u2exit_lfps_quirk)
772 reg |= DWC3_GCTL_U2EXIT_LFPS;
773
774 /*
775 * WORKAROUND: DWC3 revisions <1.90a have a bug
776 * where the device can fail to connect at SuperSpeed
777 * and falls back to high-speed mode which causes
778 * the device to enter a Connect/Disconnect loop
779 */
780 if (dwc->revision < DWC3_REVISION_190A)
781 reg |= DWC3_GCTL_U2RSTECN;
782
783 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
784 }
785
786 static int dwc3_core_get_phy(struct dwc3 *dwc);
787 static int dwc3_core_ulpi_init(struct dwc3 *dwc);
788
789 /* set global incr burst type configuration registers */
790 static void dwc3_set_incr_burst_type(struct dwc3 *dwc)
791 {
792 struct device *dev = dwc->dev;
793 /* incrx_mode : for INCR burst type. */
794 bool incrx_mode;
795 /* incrx_size : for size of INCRX burst. */
796 u32 incrx_size;
797 u32 *vals;
798 u32 cfg;
799 int ntype;
800 int ret;
801 int i;
802
803 cfg = dwc3_readl(dwc->regs, DWC3_GSBUSCFG0);
804
805 /*
806 * Handle property "snps,incr-burst-type-adjustment".
807 * Get the number of value from this property:
808 * result <= 0, means this property is not supported.
809 * result = 1, means INCRx burst mode supported.
810 * result > 1, means undefined length burst mode supported.
811 */
812 ntype = device_property_read_u32_array(dev,
813 "snps,incr-burst-type-adjustment", NULL, 0);
814 if (ntype <= 0)
815 return;
816
817 vals = kcalloc(ntype, sizeof(u32), GFP_KERNEL);
818 if (!vals) {
819 dev_err(dev, "Error to get memory\n");
820 return;
821 }
822
823 /* Get INCR burst type, and parse it */
824 ret = device_property_read_u32_array(dev,
825 "snps,incr-burst-type-adjustment", vals, ntype);
826 if (ret) {
827 dev_err(dev, "Error to get property\n");
828 return;
829 }
830
831 incrx_size = *vals;
832
833 if (ntype > 1) {
834 /* INCRX (undefined length) burst mode */
835 incrx_mode = INCRX_UNDEF_LENGTH_BURST_MODE;
836 for (i = 1; i < ntype; i++) {
837 if (vals[i] > incrx_size)
838 incrx_size = vals[i];
839 }
840 } else {
841 /* INCRX burst mode */
842 incrx_mode = INCRX_BURST_MODE;
843 }
844
845 /* Enable Undefined Length INCR Burst and Enable INCRx Burst */
846 cfg &= ~DWC3_GSBUSCFG0_INCRBRST_MASK;
847 if (incrx_mode)
848 cfg |= DWC3_GSBUSCFG0_INCRBRSTENA;
849 switch (incrx_size) {
850 case 256:
851 cfg |= DWC3_GSBUSCFG0_INCR256BRSTENA;
852 break;
853 case 128:
854 cfg |= DWC3_GSBUSCFG0_INCR128BRSTENA;
855 break;
856 case 64:
857 cfg |= DWC3_GSBUSCFG0_INCR64BRSTENA;
858 break;
859 case 32:
860 cfg |= DWC3_GSBUSCFG0_INCR32BRSTENA;
861 break;
862 case 16:
863 cfg |= DWC3_GSBUSCFG0_INCR16BRSTENA;
864 break;
865 case 8:
866 cfg |= DWC3_GSBUSCFG0_INCR8BRSTENA;
867 break;
868 case 4:
869 cfg |= DWC3_GSBUSCFG0_INCR4BRSTENA;
870 break;
871 case 1:
872 break;
873 default:
874 dev_err(dev, "Invalid property\n");
875 break;
876 }
877
878 dwc3_writel(dwc->regs, DWC3_GSBUSCFG0, cfg);
879 }
880
881 /**
882 * dwc3_core_init - Low-level initialization of DWC3 Core
883 * @dwc: Pointer to our controller context structure
884 *
885 * Returns 0 on success otherwise negative errno.
886 */
887 static int dwc3_core_init(struct dwc3 *dwc)
888 {
889 u32 reg;
890 int ret;
891
892 if (!dwc3_core_is_valid(dwc)) {
893 dev_err(dwc->dev, "this is not a DesignWare USB3 DRD Core\n");
894 ret = -ENODEV;
895 goto err0;
896 }
897
898 /*
899 * Write Linux Version Code to our GUID register so it's easy to figure
900 * out which kernel version a bug was found.
901 */
902 dwc3_writel(dwc->regs, DWC3_GUID, LINUX_VERSION_CODE);
903
904 /* Handle USB2.0-only core configuration */
905 if (DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3) ==
906 DWC3_GHWPARAMS3_SSPHY_IFC_DIS) {
907 if (dwc->maximum_speed == USB_SPEED_SUPER)
908 dwc->maximum_speed = USB_SPEED_HIGH;
909 }
910
911 ret = dwc3_phy_setup(dwc);
912 if (ret)
913 goto err0;
914
915 if (!dwc->ulpi_ready) {
916 ret = dwc3_core_ulpi_init(dwc);
917 if (ret)
918 goto err0;
919 dwc->ulpi_ready = true;
920 }
921
922 if (!dwc->phys_ready) {
923 ret = dwc3_core_get_phy(dwc);
924 if (ret)
925 goto err0a;
926 dwc->phys_ready = true;
927 }
928
929 ret = dwc3_core_soft_reset(dwc);
930 if (ret)
931 goto err0a;
932
933 dwc3_core_setup_global_control(dwc);
934 dwc3_core_num_eps(dwc);
935
936 ret = dwc3_setup_scratch_buffers(dwc);
937 if (ret)
938 goto err1;
939
940 /* Adjust Frame Length */
941 dwc3_frame_length_adjustment(dwc);
942
943 dwc3_set_incr_burst_type(dwc);
944
945 usb_phy_set_suspend(dwc->usb2_phy, 0);
946 usb_phy_set_suspend(dwc->usb3_phy, 0);
947 ret = phy_power_on(dwc->usb2_generic_phy);
948 if (ret < 0)
949 goto err2;
950
951 ret = phy_power_on(dwc->usb3_generic_phy);
952 if (ret < 0)
953 goto err3;
954
955 ret = dwc3_event_buffers_setup(dwc);
956 if (ret) {
957 dev_err(dwc->dev, "failed to setup event buffers\n");
958 goto err4;
959 }
960
961 /*
962 * ENDXFER polling is available on version 3.10a and later of
963 * the DWC_usb3 controller. It is NOT available in the
964 * DWC_usb31 controller.
965 */
966 if (!dwc3_is_usb31(dwc) && dwc->revision >= DWC3_REVISION_310A) {
967 reg = dwc3_readl(dwc->regs, DWC3_GUCTL2);
968 reg |= DWC3_GUCTL2_RST_ACTBITLATER;
969 dwc3_writel(dwc->regs, DWC3_GUCTL2, reg);
970 }
971
972 if (dwc->revision >= DWC3_REVISION_250A) {
973 reg = dwc3_readl(dwc->regs, DWC3_GUCTL1);
974
975 /*
976 * Enable hardware control of sending remote wakeup
977 * in HS when the device is in the L1 state.
978 */
979 if (dwc->revision >= DWC3_REVISION_290A)
980 reg |= DWC3_GUCTL1_DEV_L1_EXIT_BY_HW;
981
982 if (dwc->dis_tx_ipgap_linecheck_quirk)
983 reg |= DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS;
984
985 dwc3_writel(dwc->regs, DWC3_GUCTL1, reg);
986 }
987
988 if (dwc->dr_mode == USB_DR_MODE_HOST ||
989 dwc->dr_mode == USB_DR_MODE_OTG) {
990 reg = dwc3_readl(dwc->regs, DWC3_GUCTL);
991
992 /*
993 * Enable Auto retry Feature to make the controller operating in
994 * Host mode on seeing transaction errors(CRC errors or internal
995 * overrun scenerios) on IN transfers to reply to the device
996 * with a non-terminating retry ACK (i.e, an ACK transcation
997 * packet with Retry=1 & Nump != 0)
998 */
999 reg |= DWC3_GUCTL_HSTINAUTORETRY;
1000
1001 dwc3_writel(dwc->regs, DWC3_GUCTL, reg);
1002 }
1003
1004 /*
1005 * Must config both number of packets and max burst settings to enable
1006 * RX and/or TX threshold.
1007 */
1008 if (dwc3_is_usb31(dwc) && dwc->dr_mode == USB_DR_MODE_HOST) {
1009 u8 rx_thr_num = dwc->rx_thr_num_pkt_prd;
1010 u8 rx_maxburst = dwc->rx_max_burst_prd;
1011 u8 tx_thr_num = dwc->tx_thr_num_pkt_prd;
1012 u8 tx_maxburst = dwc->tx_max_burst_prd;
1013
1014 if (rx_thr_num && rx_maxburst) {
1015 reg = dwc3_readl(dwc->regs, DWC3_GRXTHRCFG);
1016 reg |= DWC31_RXTHRNUMPKTSEL_PRD;
1017
1018 reg &= ~DWC31_RXTHRNUMPKT_PRD(~0);
1019 reg |= DWC31_RXTHRNUMPKT_PRD(rx_thr_num);
1020
1021 reg &= ~DWC31_MAXRXBURSTSIZE_PRD(~0);
1022 reg |= DWC31_MAXRXBURSTSIZE_PRD(rx_maxburst);
1023
1024 dwc3_writel(dwc->regs, DWC3_GRXTHRCFG, reg);
1025 }
1026
1027 if (tx_thr_num && tx_maxburst) {
1028 reg = dwc3_readl(dwc->regs, DWC3_GTXTHRCFG);
1029 reg |= DWC31_TXTHRNUMPKTSEL_PRD;
1030
1031 reg &= ~DWC31_TXTHRNUMPKT_PRD(~0);
1032 reg |= DWC31_TXTHRNUMPKT_PRD(tx_thr_num);
1033
1034 reg &= ~DWC31_MAXTXBURSTSIZE_PRD(~0);
1035 reg |= DWC31_MAXTXBURSTSIZE_PRD(tx_maxburst);
1036
1037 dwc3_writel(dwc->regs, DWC3_GTXTHRCFG, reg);
1038 }
1039 }
1040
1041 return 0;
1042
1043 err4:
1044 phy_power_off(dwc->usb3_generic_phy);
1045
1046 err3:
1047 phy_power_off(dwc->usb2_generic_phy);
1048
1049 err2:
1050 usb_phy_set_suspend(dwc->usb2_phy, 1);
1051 usb_phy_set_suspend(dwc->usb3_phy, 1);
1052
1053 err1:
1054 usb_phy_shutdown(dwc->usb2_phy);
1055 usb_phy_shutdown(dwc->usb3_phy);
1056 phy_exit(dwc->usb2_generic_phy);
1057 phy_exit(dwc->usb3_generic_phy);
1058
1059 err0a:
1060 dwc3_ulpi_exit(dwc);
1061
1062 err0:
1063 return ret;
1064 }
1065
1066 static int dwc3_core_get_phy(struct dwc3 *dwc)
1067 {
1068 struct device *dev = dwc->dev;
1069 struct device_node *node = dev->of_node;
1070 int ret;
1071
1072 if (node) {
1073 dwc->usb2_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 0);
1074 dwc->usb3_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 1);
1075 } else {
1076 dwc->usb2_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB2);
1077 dwc->usb3_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB3);
1078 }
1079
1080 if (IS_ERR(dwc->usb2_phy)) {
1081 ret = PTR_ERR(dwc->usb2_phy);
1082 if (ret == -ENXIO || ret == -ENODEV) {
1083 dwc->usb2_phy = NULL;
1084 } else if (ret == -EPROBE_DEFER) {
1085 return ret;
1086 } else {
1087 dev_err(dev, "no usb2 phy configured\n");
1088 return ret;
1089 }
1090 }
1091
1092 if (IS_ERR(dwc->usb3_phy)) {
1093 ret = PTR_ERR(dwc->usb3_phy);
1094 if (ret == -ENXIO || ret == -ENODEV) {
1095 dwc->usb3_phy = NULL;
1096 } else if (ret == -EPROBE_DEFER) {
1097 return ret;
1098 } else {
1099 dev_err(dev, "no usb3 phy configured\n");
1100 return ret;
1101 }
1102 }
1103
1104 dwc->usb2_generic_phy = devm_phy_get(dev, "usb2-phy");
1105 if (IS_ERR(dwc->usb2_generic_phy)) {
1106 ret = PTR_ERR(dwc->usb2_generic_phy);
1107 if (ret == -ENOSYS || ret == -ENODEV) {
1108 dwc->usb2_generic_phy = NULL;
1109 } else if (ret == -EPROBE_DEFER) {
1110 return ret;
1111 } else {
1112 dev_err(dev, "no usb2 phy configured\n");
1113 return ret;
1114 }
1115 }
1116
1117 dwc->usb3_generic_phy = devm_phy_get(dev, "usb3-phy");
1118 if (IS_ERR(dwc->usb3_generic_phy)) {
1119 ret = PTR_ERR(dwc->usb3_generic_phy);
1120 if (ret == -ENOSYS || ret == -ENODEV) {
1121 dwc->usb3_generic_phy = NULL;
1122 } else if (ret == -EPROBE_DEFER) {
1123 return ret;
1124 } else {
1125 dev_err(dev, "no usb3 phy configured\n");
1126 return ret;
1127 }
1128 }
1129
1130 return 0;
1131 }
1132
1133 static int dwc3_core_init_mode(struct dwc3 *dwc)
1134 {
1135 struct device *dev = dwc->dev;
1136 int ret;
1137
1138 switch (dwc->dr_mode) {
1139 case USB_DR_MODE_PERIPHERAL:
1140 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE);
1141
1142 if (dwc->usb2_phy)
1143 otg_set_vbus(dwc->usb2_phy->otg, false);
1144 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_DEVICE);
1145 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_DEVICE);
1146
1147 ret = dwc3_gadget_init(dwc);
1148 if (ret) {
1149 if (ret != -EPROBE_DEFER)
1150 dev_err(dev, "failed to initialize gadget\n");
1151 return ret;
1152 }
1153 break;
1154 case USB_DR_MODE_HOST:
1155 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_HOST);
1156
1157 if (dwc->usb2_phy)
1158 otg_set_vbus(dwc->usb2_phy->otg, true);
1159 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_HOST);
1160 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_HOST);
1161
1162 ret = dwc3_host_init(dwc);
1163 if (ret) {
1164 if (ret != -EPROBE_DEFER)
1165 dev_err(dev, "failed to initialize host\n");
1166 return ret;
1167 }
1168 phy_calibrate(dwc->usb2_generic_phy);
1169 break;
1170 case USB_DR_MODE_OTG:
1171 INIT_WORK(&dwc->drd_work, __dwc3_set_mode);
1172 ret = dwc3_drd_init(dwc);
1173 if (ret) {
1174 if (ret != -EPROBE_DEFER)
1175 dev_err(dev, "failed to initialize dual-role\n");
1176 return ret;
1177 }
1178 break;
1179 default:
1180 dev_err(dev, "Unsupported mode of operation %d\n", dwc->dr_mode);
1181 return -EINVAL;
1182 }
1183
1184 return 0;
1185 }
1186
1187 static void dwc3_core_exit_mode(struct dwc3 *dwc)
1188 {
1189 switch (dwc->dr_mode) {
1190 case USB_DR_MODE_PERIPHERAL:
1191 dwc3_gadget_exit(dwc);
1192 break;
1193 case USB_DR_MODE_HOST:
1194 dwc3_host_exit(dwc);
1195 break;
1196 case USB_DR_MODE_OTG:
1197 dwc3_drd_exit(dwc);
1198 break;
1199 default:
1200 /* do nothing */
1201 break;
1202 }
1203 }
1204
1205 static void dwc3_get_properties(struct dwc3 *dwc)
1206 {
1207 struct device *dev = dwc->dev;
1208 u8 lpm_nyet_threshold;
1209 u8 tx_de_emphasis;
1210 u8 hird_threshold;
1211 u8 rx_thr_num_pkt_prd;
1212 u8 rx_max_burst_prd;
1213 u8 tx_thr_num_pkt_prd;
1214 u8 tx_max_burst_prd;
1215
1216 /* default to highest possible threshold */
1217 lpm_nyet_threshold = 0xff;
1218
1219 /* default to -3.5dB de-emphasis */
1220 tx_de_emphasis = 1;
1221
1222 /*
1223 * default to assert utmi_sleep_n and use maximum allowed HIRD
1224 * threshold value of 0b1100
1225 */
1226 hird_threshold = 12;
1227
1228 dwc->maximum_speed = usb_get_maximum_speed(dev);
1229 dwc->dr_mode = usb_get_dr_mode(dev);
1230 dwc->hsphy_mode = of_usb_get_phy_mode(dev->of_node);
1231
1232 dwc->sysdev_is_parent = device_property_read_bool(dev,
1233 "linux,sysdev_is_parent");
1234 if (dwc->sysdev_is_parent)
1235 dwc->sysdev = dwc->dev->parent;
1236 else
1237 dwc->sysdev = dwc->dev;
1238
1239 dwc->has_lpm_erratum = device_property_read_bool(dev,
1240 "snps,has-lpm-erratum");
1241 device_property_read_u8(dev, "snps,lpm-nyet-threshold",
1242 &lpm_nyet_threshold);
1243 dwc->is_utmi_l1_suspend = device_property_read_bool(dev,
1244 "snps,is-utmi-l1-suspend");
1245 device_property_read_u8(dev, "snps,hird-threshold",
1246 &hird_threshold);
1247 dwc->usb3_lpm_capable = device_property_read_bool(dev,
1248 "snps,usb3_lpm_capable");
1249 device_property_read_u8(dev, "snps,rx-thr-num-pkt-prd",
1250 &rx_thr_num_pkt_prd);
1251 device_property_read_u8(dev, "snps,rx-max-burst-prd",
1252 &rx_max_burst_prd);
1253 device_property_read_u8(dev, "snps,tx-thr-num-pkt-prd",
1254 &tx_thr_num_pkt_prd);
1255 device_property_read_u8(dev, "snps,tx-max-burst-prd",
1256 &tx_max_burst_prd);
1257
1258 dwc->disable_scramble_quirk = device_property_read_bool(dev,
1259 "snps,disable_scramble_quirk");
1260 dwc->u2exit_lfps_quirk = device_property_read_bool(dev,
1261 "snps,u2exit_lfps_quirk");
1262 dwc->u2ss_inp3_quirk = device_property_read_bool(dev,
1263 "snps,u2ss_inp3_quirk");
1264 dwc->req_p1p2p3_quirk = device_property_read_bool(dev,
1265 "snps,req_p1p2p3_quirk");
1266 dwc->del_p1p2p3_quirk = device_property_read_bool(dev,
1267 "snps,del_p1p2p3_quirk");
1268 dwc->del_phy_power_chg_quirk = device_property_read_bool(dev,
1269 "snps,del_phy_power_chg_quirk");
1270 dwc->lfps_filter_quirk = device_property_read_bool(dev,
1271 "snps,lfps_filter_quirk");
1272 dwc->rx_detect_poll_quirk = device_property_read_bool(dev,
1273 "snps,rx_detect_poll_quirk");
1274 dwc->dis_u3_susphy_quirk = device_property_read_bool(dev,
1275 "snps,dis_u3_susphy_quirk");
1276 dwc->dis_u2_susphy_quirk = device_property_read_bool(dev,
1277 "snps,dis_u2_susphy_quirk");
1278 dwc->dis_enblslpm_quirk = device_property_read_bool(dev,
1279 "snps,dis_enblslpm_quirk");
1280 dwc->dis_rxdet_inp3_quirk = device_property_read_bool(dev,
1281 "snps,dis_rxdet_inp3_quirk");
1282 dwc->dis_u2_freeclk_exists_quirk = device_property_read_bool(dev,
1283 "snps,dis-u2-freeclk-exists-quirk");
1284 dwc->dis_del_phy_power_chg_quirk = device_property_read_bool(dev,
1285 "snps,dis-del-phy-power-chg-quirk");
1286 dwc->dis_tx_ipgap_linecheck_quirk = device_property_read_bool(dev,
1287 "snps,dis-tx-ipgap-linecheck-quirk");
1288
1289 dwc->tx_de_emphasis_quirk = device_property_read_bool(dev,
1290 "snps,tx_de_emphasis_quirk");
1291 device_property_read_u8(dev, "snps,tx_de_emphasis",
1292 &tx_de_emphasis);
1293 device_property_read_string(dev, "snps,hsphy_interface",
1294 &dwc->hsphy_interface);
1295 device_property_read_u32(dev, "snps,quirk-frame-length-adjustment",
1296 &dwc->fladj);
1297
1298 dwc->dis_metastability_quirk = device_property_read_bool(dev,
1299 "snps,dis_metastability_quirk");
1300
1301 dwc->lpm_nyet_threshold = lpm_nyet_threshold;
1302 dwc->tx_de_emphasis = tx_de_emphasis;
1303
1304 dwc->hird_threshold = hird_threshold
1305 | (dwc->is_utmi_l1_suspend << 4);
1306
1307 dwc->rx_thr_num_pkt_prd = rx_thr_num_pkt_prd;
1308 dwc->rx_max_burst_prd = rx_max_burst_prd;
1309
1310 dwc->tx_thr_num_pkt_prd = tx_thr_num_pkt_prd;
1311 dwc->tx_max_burst_prd = tx_max_burst_prd;
1312
1313 dwc->imod_interval = 0;
1314 }
1315
1316 /* check whether the core supports IMOD */
1317 bool dwc3_has_imod(struct dwc3 *dwc)
1318 {
1319 return ((dwc3_is_usb3(dwc) &&
1320 dwc->revision >= DWC3_REVISION_300A) ||
1321 (dwc3_is_usb31(dwc) &&
1322 dwc->revision >= DWC3_USB31_REVISION_120A));
1323 }
1324
1325 static void dwc3_check_params(struct dwc3 *dwc)
1326 {
1327 struct device *dev = dwc->dev;
1328
1329 /* Check for proper value of imod_interval */
1330 if (dwc->imod_interval && !dwc3_has_imod(dwc)) {
1331 dev_warn(dwc->dev, "Interrupt moderation not supported\n");
1332 dwc->imod_interval = 0;
1333 }
1334
1335 /*
1336 * Workaround for STAR 9000961433 which affects only version
1337 * 3.00a of the DWC_usb3 core. This prevents the controller
1338 * interrupt from being masked while handling events. IMOD
1339 * allows us to work around this issue. Enable it for the
1340 * affected version.
1341 */
1342 if (!dwc->imod_interval &&
1343 (dwc->revision == DWC3_REVISION_300A))
1344 dwc->imod_interval = 1;
1345
1346 /* Check the maximum_speed parameter */
1347 switch (dwc->maximum_speed) {
1348 case USB_SPEED_LOW:
1349 case USB_SPEED_FULL:
1350 case USB_SPEED_HIGH:
1351 case USB_SPEED_SUPER:
1352 case USB_SPEED_SUPER_PLUS:
1353 break;
1354 default:
1355 dev_err(dev, "invalid maximum_speed parameter %d\n",
1356 dwc->maximum_speed);
1357 /* fall through */
1358 case USB_SPEED_UNKNOWN:
1359 /* default to superspeed */
1360 dwc->maximum_speed = USB_SPEED_SUPER;
1361
1362 /*
1363 * default to superspeed plus if we are capable.
1364 */
1365 if (dwc3_is_usb31(dwc) &&
1366 (DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3) ==
1367 DWC3_GHWPARAMS3_SSPHY_IFC_GEN2))
1368 dwc->maximum_speed = USB_SPEED_SUPER_PLUS;
1369
1370 break;
1371 }
1372 }
1373
1374 static int dwc3_probe(struct platform_device *pdev)
1375 {
1376 struct device *dev = &pdev->dev;
1377 struct resource *res, dwc_res;
1378 struct dwc3 *dwc;
1379
1380 int ret;
1381
1382 void __iomem *regs;
1383
1384 dwc = devm_kzalloc(dev, sizeof(*dwc), GFP_KERNEL);
1385 if (!dwc)
1386 return -ENOMEM;
1387
1388 dwc->clks = devm_kmemdup(dev, dwc3_core_clks, sizeof(dwc3_core_clks),
1389 GFP_KERNEL);
1390 if (!dwc->clks)
1391 return -ENOMEM;
1392
1393 dwc->dev = dev;
1394
1395 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1396 if (!res) {
1397 dev_err(dev, "missing memory resource\n");
1398 return -ENODEV;
1399 }
1400
1401 dwc->xhci_resources[0].start = res->start;
1402 dwc->xhci_resources[0].end = dwc->xhci_resources[0].start +
1403 DWC3_XHCI_REGS_END;
1404 dwc->xhci_resources[0].flags = res->flags;
1405 dwc->xhci_resources[0].name = res->name;
1406
1407 /*
1408 * Request memory region but exclude xHCI regs,
1409 * since it will be requested by the xhci-plat driver.
1410 */
1411 dwc_res = *res;
1412 dwc_res.start += DWC3_GLOBALS_REGS_START;
1413
1414 regs = devm_ioremap_resource(dev, &dwc_res);
1415 if (IS_ERR(regs))
1416 return PTR_ERR(regs);
1417
1418 dwc->regs = regs;
1419 dwc->regs_size = resource_size(&dwc_res);
1420
1421 dwc3_get_properties(dwc);
1422
1423 dwc->reset = devm_reset_control_get_optional_shared(dev, NULL);
1424 if (IS_ERR(dwc->reset))
1425 return PTR_ERR(dwc->reset);
1426
1427 if (dev->of_node) {
1428 dwc->num_clks = ARRAY_SIZE(dwc3_core_clks);
1429
1430 ret = clk_bulk_get(dev, dwc->num_clks, dwc->clks);
1431 if (ret == -EPROBE_DEFER)
1432 return ret;
1433 /*
1434 * Clocks are optional, but new DT platforms should support all
1435 * clocks as required by the DT-binding.
1436 */
1437 if (ret)
1438 dwc->num_clks = 0;
1439 }
1440
1441 ret = reset_control_deassert(dwc->reset);
1442 if (ret)
1443 goto put_clks;
1444
1445 ret = clk_bulk_prepare(dwc->num_clks, dwc->clks);
1446 if (ret)
1447 goto assert_reset;
1448
1449 ret = clk_bulk_enable(dwc->num_clks, dwc->clks);
1450 if (ret)
1451 goto unprepare_clks;
1452
1453 platform_set_drvdata(pdev, dwc);
1454 dwc3_cache_hwparams(dwc);
1455
1456 spin_lock_init(&dwc->lock);
1457
1458 pm_runtime_set_active(dev);
1459 pm_runtime_use_autosuspend(dev);
1460 pm_runtime_set_autosuspend_delay(dev, DWC3_DEFAULT_AUTOSUSPEND_DELAY);
1461 pm_runtime_enable(dev);
1462 ret = pm_runtime_get_sync(dev);
1463 if (ret < 0)
1464 goto err1;
1465
1466 pm_runtime_forbid(dev);
1467
1468 ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE);
1469 if (ret) {
1470 dev_err(dwc->dev, "failed to allocate event buffers\n");
1471 ret = -ENOMEM;
1472 goto err2;
1473 }
1474
1475 ret = dwc3_get_dr_mode(dwc);
1476 if (ret)
1477 goto err3;
1478
1479 ret = dwc3_alloc_scratch_buffers(dwc);
1480 if (ret)
1481 goto err3;
1482
1483 ret = dwc3_core_init(dwc);
1484 if (ret) {
1485 dev_err(dev, "failed to initialize core\n");
1486 goto err4;
1487 }
1488
1489 dwc3_check_params(dwc);
1490
1491 ret = dwc3_core_init_mode(dwc);
1492 if (ret)
1493 goto err5;
1494
1495 dwc3_debugfs_init(dwc);
1496 pm_runtime_put(dev);
1497
1498 return 0;
1499
1500 err5:
1501 dwc3_event_buffers_cleanup(dwc);
1502 dwc3_ulpi_exit(dwc);
1503
1504 err4:
1505 dwc3_free_scratch_buffers(dwc);
1506
1507 err3:
1508 dwc3_free_event_buffers(dwc);
1509
1510 err2:
1511 pm_runtime_allow(&pdev->dev);
1512
1513 err1:
1514 pm_runtime_put_sync(&pdev->dev);
1515 pm_runtime_disable(&pdev->dev);
1516
1517 clk_bulk_disable(dwc->num_clks, dwc->clks);
1518 unprepare_clks:
1519 clk_bulk_unprepare(dwc->num_clks, dwc->clks);
1520 assert_reset:
1521 reset_control_assert(dwc->reset);
1522 put_clks:
1523 clk_bulk_put(dwc->num_clks, dwc->clks);
1524
1525 return ret;
1526 }
1527
1528 static int dwc3_remove(struct platform_device *pdev)
1529 {
1530 struct dwc3 *dwc = platform_get_drvdata(pdev);
1531
1532 pm_runtime_get_sync(&pdev->dev);
1533
1534 dwc3_debugfs_exit(dwc);
1535 dwc3_core_exit_mode(dwc);
1536
1537 dwc3_core_exit(dwc);
1538 dwc3_ulpi_exit(dwc);
1539
1540 pm_runtime_put_sync(&pdev->dev);
1541 pm_runtime_allow(&pdev->dev);
1542 pm_runtime_disable(&pdev->dev);
1543
1544 dwc3_free_event_buffers(dwc);
1545 dwc3_free_scratch_buffers(dwc);
1546 clk_bulk_put(dwc->num_clks, dwc->clks);
1547
1548 return 0;
1549 }
1550
1551 #ifdef CONFIG_PM
1552 static int dwc3_core_init_for_resume(struct dwc3 *dwc)
1553 {
1554 int ret;
1555
1556 ret = reset_control_deassert(dwc->reset);
1557 if (ret)
1558 return ret;
1559
1560 ret = clk_bulk_prepare(dwc->num_clks, dwc->clks);
1561 if (ret)
1562 goto assert_reset;
1563
1564 ret = clk_bulk_enable(dwc->num_clks, dwc->clks);
1565 if (ret)
1566 goto unprepare_clks;
1567
1568 ret = dwc3_core_init(dwc);
1569 if (ret)
1570 goto disable_clks;
1571
1572 return 0;
1573
1574 disable_clks:
1575 clk_bulk_disable(dwc->num_clks, dwc->clks);
1576 unprepare_clks:
1577 clk_bulk_unprepare(dwc->num_clks, dwc->clks);
1578 assert_reset:
1579 reset_control_assert(dwc->reset);
1580
1581 return ret;
1582 }
1583
1584 static int dwc3_suspend_common(struct dwc3 *dwc, pm_message_t msg)
1585 {
1586 unsigned long flags;
1587 u32 reg;
1588
1589 switch (dwc->current_dr_role) {
1590 case DWC3_GCTL_PRTCAP_DEVICE:
1591 spin_lock_irqsave(&dwc->lock, flags);
1592 dwc3_gadget_suspend(dwc);
1593 spin_unlock_irqrestore(&dwc->lock, flags);
1594 dwc3_core_exit(dwc);
1595 break;
1596 case DWC3_GCTL_PRTCAP_HOST:
1597 if (!PMSG_IS_AUTO(msg)) {
1598 dwc3_core_exit(dwc);
1599 break;
1600 }
1601
1602 /* Let controller to suspend HSPHY before PHY driver suspends */
1603 if (dwc->dis_u2_susphy_quirk ||
1604 dwc->dis_enblslpm_quirk) {
1605 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
1606 reg |= DWC3_GUSB2PHYCFG_ENBLSLPM |
1607 DWC3_GUSB2PHYCFG_SUSPHY;
1608 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
1609
1610 /* Give some time for USB2 PHY to suspend */
1611 usleep_range(5000, 6000);
1612 }
1613
1614 phy_pm_runtime_put_sync(dwc->usb2_generic_phy);
1615 phy_pm_runtime_put_sync(dwc->usb3_generic_phy);
1616 break;
1617 case DWC3_GCTL_PRTCAP_OTG:
1618 /* do nothing during runtime_suspend */
1619 if (PMSG_IS_AUTO(msg))
1620 break;
1621
1622 if (dwc->current_otg_role == DWC3_OTG_ROLE_DEVICE) {
1623 spin_lock_irqsave(&dwc->lock, flags);
1624 dwc3_gadget_suspend(dwc);
1625 spin_unlock_irqrestore(&dwc->lock, flags);
1626 }
1627
1628 dwc3_otg_exit(dwc);
1629 dwc3_core_exit(dwc);
1630 break;
1631 default:
1632 /* do nothing */
1633 break;
1634 }
1635
1636 return 0;
1637 }
1638
1639 static int dwc3_resume_common(struct dwc3 *dwc, pm_message_t msg)
1640 {
1641 unsigned long flags;
1642 int ret;
1643 u32 reg;
1644
1645 switch (dwc->current_dr_role) {
1646 case DWC3_GCTL_PRTCAP_DEVICE:
1647 ret = dwc3_core_init_for_resume(dwc);
1648 if (ret)
1649 return ret;
1650
1651 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE);
1652 spin_lock_irqsave(&dwc->lock, flags);
1653 dwc3_gadget_resume(dwc);
1654 spin_unlock_irqrestore(&dwc->lock, flags);
1655 break;
1656 case DWC3_GCTL_PRTCAP_HOST:
1657 if (!PMSG_IS_AUTO(msg)) {
1658 ret = dwc3_core_init_for_resume(dwc);
1659 if (ret)
1660 return ret;
1661 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_HOST);
1662 break;
1663 }
1664 /* Restore GUSB2PHYCFG bits that were modified in suspend */
1665 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
1666 if (dwc->dis_u2_susphy_quirk)
1667 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
1668
1669 if (dwc->dis_enblslpm_quirk)
1670 reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
1671
1672 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
1673
1674 phy_pm_runtime_get_sync(dwc->usb2_generic_phy);
1675 phy_pm_runtime_get_sync(dwc->usb3_generic_phy);
1676 break;
1677 case DWC3_GCTL_PRTCAP_OTG:
1678 /* nothing to do on runtime_resume */
1679 if (PMSG_IS_AUTO(msg))
1680 break;
1681
1682 ret = dwc3_core_init(dwc);
1683 if (ret)
1684 return ret;
1685
1686 dwc3_set_prtcap(dwc, dwc->current_dr_role);
1687
1688 dwc3_otg_init(dwc);
1689 if (dwc->current_otg_role == DWC3_OTG_ROLE_HOST) {
1690 dwc3_otg_host_init(dwc);
1691 } else if (dwc->current_otg_role == DWC3_OTG_ROLE_DEVICE) {
1692 spin_lock_irqsave(&dwc->lock, flags);
1693 dwc3_gadget_resume(dwc);
1694 spin_unlock_irqrestore(&dwc->lock, flags);
1695 }
1696
1697 break;
1698 default:
1699 /* do nothing */
1700 break;
1701 }
1702
1703 return 0;
1704 }
1705
1706 static int dwc3_runtime_checks(struct dwc3 *dwc)
1707 {
1708 switch (dwc->current_dr_role) {
1709 case DWC3_GCTL_PRTCAP_DEVICE:
1710 if (dwc->connected)
1711 return -EBUSY;
1712 break;
1713 case DWC3_GCTL_PRTCAP_HOST:
1714 default:
1715 /* do nothing */
1716 break;
1717 }
1718
1719 return 0;
1720 }
1721
1722 static int dwc3_runtime_suspend(struct device *dev)
1723 {
1724 struct dwc3 *dwc = dev_get_drvdata(dev);
1725 int ret;
1726
1727 if (dwc3_runtime_checks(dwc))
1728 return -EBUSY;
1729
1730 ret = dwc3_suspend_common(dwc, PMSG_AUTO_SUSPEND);
1731 if (ret)
1732 return ret;
1733
1734 device_init_wakeup(dev, true);
1735
1736 return 0;
1737 }
1738
1739 static int dwc3_runtime_resume(struct device *dev)
1740 {
1741 struct dwc3 *dwc = dev_get_drvdata(dev);
1742 int ret;
1743
1744 device_init_wakeup(dev, false);
1745
1746 ret = dwc3_resume_common(dwc, PMSG_AUTO_RESUME);
1747 if (ret)
1748 return ret;
1749
1750 switch (dwc->current_dr_role) {
1751 case DWC3_GCTL_PRTCAP_DEVICE:
1752 dwc3_gadget_process_pending_events(dwc);
1753 break;
1754 case DWC3_GCTL_PRTCAP_HOST:
1755 default:
1756 /* do nothing */
1757 break;
1758 }
1759
1760 pm_runtime_mark_last_busy(dev);
1761
1762 return 0;
1763 }
1764
1765 static int dwc3_runtime_idle(struct device *dev)
1766 {
1767 struct dwc3 *dwc = dev_get_drvdata(dev);
1768
1769 switch (dwc->current_dr_role) {
1770 case DWC3_GCTL_PRTCAP_DEVICE:
1771 if (dwc3_runtime_checks(dwc))
1772 return -EBUSY;
1773 break;
1774 case DWC3_GCTL_PRTCAP_HOST:
1775 default:
1776 /* do nothing */
1777 break;
1778 }
1779
1780 pm_runtime_mark_last_busy(dev);
1781 pm_runtime_autosuspend(dev);
1782
1783 return 0;
1784 }
1785 #endif /* CONFIG_PM */
1786
1787 #ifdef CONFIG_PM_SLEEP
1788 static int dwc3_suspend(struct device *dev)
1789 {
1790 struct dwc3 *dwc = dev_get_drvdata(dev);
1791 int ret;
1792
1793 ret = dwc3_suspend_common(dwc, PMSG_SUSPEND);
1794 if (ret)
1795 return ret;
1796
1797 pinctrl_pm_select_sleep_state(dev);
1798
1799 return 0;
1800 }
1801
1802 static int dwc3_resume(struct device *dev)
1803 {
1804 struct dwc3 *dwc = dev_get_drvdata(dev);
1805 int ret;
1806
1807 pinctrl_pm_select_default_state(dev);
1808
1809 ret = dwc3_resume_common(dwc, PMSG_RESUME);
1810 if (ret)
1811 return ret;
1812
1813 pm_runtime_disable(dev);
1814 pm_runtime_set_active(dev);
1815 pm_runtime_enable(dev);
1816
1817 return 0;
1818 }
1819 #endif /* CONFIG_PM_SLEEP */
1820
1821 static const struct dev_pm_ops dwc3_dev_pm_ops = {
1822 SET_SYSTEM_SLEEP_PM_OPS(dwc3_suspend, dwc3_resume)
1823 SET_RUNTIME_PM_OPS(dwc3_runtime_suspend, dwc3_runtime_resume,
1824 dwc3_runtime_idle)
1825 };
1826
1827 #ifdef CONFIG_OF
1828 static const struct of_device_id of_dwc3_match[] = {
1829 {
1830 .compatible = "snps,dwc3"
1831 },
1832 {
1833 .compatible = "synopsys,dwc3"
1834 },
1835 { },
1836 };
1837 MODULE_DEVICE_TABLE(of, of_dwc3_match);
1838 #endif
1839
1840 #ifdef CONFIG_ACPI
1841
1842 #define ACPI_ID_INTEL_BSW "808622B7"
1843
1844 static const struct acpi_device_id dwc3_acpi_match[] = {
1845 { ACPI_ID_INTEL_BSW, 0 },
1846 { },
1847 };
1848 MODULE_DEVICE_TABLE(acpi, dwc3_acpi_match);
1849 #endif
1850
1851 static struct platform_driver dwc3_driver = {
1852 .probe = dwc3_probe,
1853 .remove = dwc3_remove,
1854 .driver = {
1855 .name = "dwc3",
1856 .of_match_table = of_match_ptr(of_dwc3_match),
1857 .acpi_match_table = ACPI_PTR(dwc3_acpi_match),
1858 .pm = &dwc3_dev_pm_ops,
1859 },
1860 };
1861
1862 module_platform_driver(dwc3_driver);
1863
1864 MODULE_ALIAS("platform:dwc3");
1865 MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
1866 MODULE_LICENSE("GPL v2");
1867 MODULE_DESCRIPTION("DesignWare USB3 DRD Controller Driver");
Linux with added FPC-III support