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perf python: Do not force closing original perf descriptor in evlist.get_pollfd()
[linux/fpc-iii.git] / drivers / usb / gadget / udc / fsl_udc_core.c
blob20141c3096f68ab4a2f51762dc0617715e473633
1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2004-2007,2011-2012 Freescale Semiconductor, Inc.
4 * All rights reserved.
5 *
6 * Author: Li Yang <leoli@freescale.com>
7 * Jiang Bo <tanya.jiang@freescale.com>
8 *
9 * Description:
10 * Freescale high-speed USB SOC DR module device controller driver.
11 * This can be found on MPC8349E/MPC8313E/MPC5121E cpus.
12 * The driver is previously named as mpc_udc. Based on bare board
13 * code from Dave Liu and Shlomi Gridish.
14 */
15
16 #undef VERBOSE
17
18 #include <linux/module.h>
19 #include <linux/kernel.h>
20 #include <linux/ioport.h>
21 #include <linux/types.h>
22 #include <linux/errno.h>
23 #include <linux/err.h>
24 #include <linux/slab.h>
25 #include <linux/init.h>
26 #include <linux/list.h>
27 #include <linux/interrupt.h>
28 #include <linux/proc_fs.h>
29 #include <linux/mm.h>
30 #include <linux/moduleparam.h>
31 #include <linux/device.h>
32 #include <linux/usb/ch9.h>
33 #include <linux/usb/gadget.h>
34 #include <linux/usb/otg.h>
35 #include <linux/dma-mapping.h>
36 #include <linux/platform_device.h>
37 #include <linux/fsl_devices.h>
38 #include <linux/dmapool.h>
39 #include <linux/delay.h>
40 #include <linux/of_device.h>
41
42 #include <asm/byteorder.h>
43 #include <asm/io.h>
44 #include <asm/unaligned.h>
45 #include <asm/dma.h>
46
47 #include "fsl_usb2_udc.h"
48
49 #define DRIVER_DESC "Freescale High-Speed USB SOC Device Controller driver"
50 #define DRIVER_AUTHOR "Li Yang/Jiang Bo"
51 #define DRIVER_VERSION "Apr 20, 2007"
52
53 #define DMA_ADDR_INVALID (~(dma_addr_t)0)
54
55 static const char driver_name[] = "fsl-usb2-udc";
56 static const char driver_desc[] = DRIVER_DESC;
57
58 static struct usb_dr_device __iomem *dr_regs;
59
60 static struct usb_sys_interface __iomem *usb_sys_regs;
61
62 /* it is initialized in probe() */
63 static struct fsl_udc *udc_controller = NULL;
64
65 static const struct usb_endpoint_descriptor
66 fsl_ep0_desc = {
67 .bLength = USB_DT_ENDPOINT_SIZE,
68 .bDescriptorType = USB_DT_ENDPOINT,
69 .bEndpointAddress = 0,
70 .bmAttributes = USB_ENDPOINT_XFER_CONTROL,
71 .wMaxPacketSize = USB_MAX_CTRL_PAYLOAD,
72 };
73
74 static void fsl_ep_fifo_flush(struct usb_ep *_ep);
75
76 #ifdef CONFIG_PPC32
77 /*
78 * On some SoCs, the USB controller registers can be big or little endian,
79 * depending on the version of the chip. In order to be able to run the
80 * same kernel binary on 2 different versions of an SoC, the BE/LE decision
81 * must be made at run time. _fsl_readl and fsl_writel are pointers to the
82 * BE or LE readl() and writel() functions, and fsl_readl() and fsl_writel()
83 * call through those pointers. Platform code for SoCs that have BE USB
84 * registers should set pdata->big_endian_mmio flag.
85 *
86 * This also applies to controller-to-cpu accessors for the USB descriptors,
87 * since their endianness is also SoC dependant. Platform code for SoCs that
88 * have BE USB descriptors should set pdata->big_endian_desc flag.
89 */
90 static u32 _fsl_readl_be(const unsigned __iomem *p)
91 {
92 return in_be32(p);
93 }
94
95 static u32 _fsl_readl_le(const unsigned __iomem *p)
96 {
97 return in_le32(p);
98 }
99
100 static void _fsl_writel_be(u32 v, unsigned __iomem *p)
101 {
102 out_be32(p, v);
103 }
104
105 static void _fsl_writel_le(u32 v, unsigned __iomem *p)
106 {
107 out_le32(p, v);
108 }
109
110 static u32 (*_fsl_readl)(const unsigned __iomem *p);
111 static void (*_fsl_writel)(u32 v, unsigned __iomem *p);
112
113 #define fsl_readl(p) (*_fsl_readl)((p))
114 #define fsl_writel(v, p) (*_fsl_writel)((v), (p))
115
116 static inline void fsl_set_accessors(struct fsl_usb2_platform_data *pdata)
117 {
118 if (pdata->big_endian_mmio) {
119 _fsl_readl = _fsl_readl_be;
120 _fsl_writel = _fsl_writel_be;
121 } else {
122 _fsl_readl = _fsl_readl_le;
123 _fsl_writel = _fsl_writel_le;
124 }
125 }
126
127 static inline u32 cpu_to_hc32(const u32 x)
128 {
129 return udc_controller->pdata->big_endian_desc
130 ? (__force u32)cpu_to_be32(x)
131 : (__force u32)cpu_to_le32(x);
132 }
133
134 static inline u32 hc32_to_cpu(const u32 x)
135 {
136 return udc_controller->pdata->big_endian_desc
137 ? be32_to_cpu((__force __be32)x)
138 : le32_to_cpu((__force __le32)x);
139 }
140 #else /* !CONFIG_PPC32 */
141 static inline void fsl_set_accessors(struct fsl_usb2_platform_data *pdata) {}
142
143 #define fsl_readl(addr) readl(addr)
144 #define fsl_writel(val32, addr) writel(val32, addr)
145 #define cpu_to_hc32(x) cpu_to_le32(x)
146 #define hc32_to_cpu(x) le32_to_cpu(x)
147 #endif /* CONFIG_PPC32 */
148
149 /********************************************************************
150 * Internal Used Function
151 ********************************************************************/
152 /*-----------------------------------------------------------------
153 * done() - retire a request; caller blocked irqs
154 * @status : request status to be set, only works when
155 * request is still in progress.
156 *--------------------------------------------------------------*/
157 static void done(struct fsl_ep *ep, struct fsl_req *req, int status)
158 __releases(ep->udc->lock)
159 __acquires(ep->udc->lock)
160 {
161 struct fsl_udc *udc = NULL;
162 unsigned char stopped = ep->stopped;
163 struct ep_td_struct *curr_td, *next_td;
164 int j;
165
166 udc = (struct fsl_udc *)ep->udc;
167 /* Removed the req from fsl_ep->queue */
168 list_del_init(&req->queue);
169
170 /* req.status should be set as -EINPROGRESS in ep_queue() */
171 if (req->req.status == -EINPROGRESS)
172 req->req.status = status;
173 else
174 status = req->req.status;
175
176 /* Free dtd for the request */
177 next_td = req->head;
178 for (j = 0; j < req->dtd_count; j++) {
179 curr_td = next_td;
180 if (j != req->dtd_count - 1) {
181 next_td = curr_td->next_td_virt;
182 }
183 dma_pool_free(udc->td_pool, curr_td, curr_td->td_dma);
184 }
185
186 usb_gadget_unmap_request(&ep->udc->gadget, &req->req, ep_is_in(ep));
187
188 if (status && (status != -ESHUTDOWN))
189 VDBG("complete %s req %p stat %d len %u/%u",
190 ep->ep.name, &req->req, status,
191 req->req.actual, req->req.length);
192
193 ep->stopped = 1;
194
195 spin_unlock(&ep->udc->lock);
196
197 usb_gadget_giveback_request(&ep->ep, &req->req);
198
199 spin_lock(&ep->udc->lock);
200 ep->stopped = stopped;
201 }
202
203 /*-----------------------------------------------------------------
204 * nuke(): delete all requests related to this ep
205 * called with spinlock held
206 *--------------------------------------------------------------*/
207 static void nuke(struct fsl_ep *ep, int status)
208 {
209 ep->stopped = 1;
210
211 /* Flush fifo */
212 fsl_ep_fifo_flush(&ep->ep);
213
214 /* Whether this eq has request linked */
215 while (!list_empty(&ep->queue)) {
216 struct fsl_req *req = NULL;
217
218 req = list_entry(ep->queue.next, struct fsl_req, queue);
219 done(ep, req, status);
220 }
221 }
222
223 /*------------------------------------------------------------------
224 Internal Hardware related function
225 ------------------------------------------------------------------*/
226
227 static int dr_controller_setup(struct fsl_udc *udc)
228 {
229 unsigned int tmp, portctrl, ep_num;
230 unsigned int max_no_of_ep;
231 unsigned int ctrl;
232 unsigned long timeout;
233
234 #define FSL_UDC_RESET_TIMEOUT 1000
235
236 /* Config PHY interface */
237 portctrl = fsl_readl(&dr_regs->portsc1);
238 portctrl &= ~(PORTSCX_PHY_TYPE_SEL | PORTSCX_PORT_WIDTH);
239 switch (udc->phy_mode) {
240 case FSL_USB2_PHY_ULPI:
241 if (udc->pdata->have_sysif_regs) {
242 if (udc->pdata->controller_ver) {
243 /* controller version 1.6 or above */
244 ctrl = __raw_readl(&usb_sys_regs->control);
245 ctrl &= ~USB_CTRL_UTMI_PHY_EN;
246 ctrl |= USB_CTRL_USB_EN;
247 __raw_writel(ctrl, &usb_sys_regs->control);
248 }
249 }
250 portctrl |= PORTSCX_PTS_ULPI;
251 break;
252 case FSL_USB2_PHY_UTMI_WIDE:
253 portctrl |= PORTSCX_PTW_16BIT;
254 /* fall through */
255 case FSL_USB2_PHY_UTMI:
256 case FSL_USB2_PHY_UTMI_DUAL:
257 if (udc->pdata->have_sysif_regs) {
258 if (udc->pdata->controller_ver) {
259 /* controller version 1.6 or above */
260 ctrl = __raw_readl(&usb_sys_regs->control);
261 ctrl |= (USB_CTRL_UTMI_PHY_EN |
262 USB_CTRL_USB_EN);
263 __raw_writel(ctrl, &usb_sys_regs->control);
264 mdelay(FSL_UTMI_PHY_DLY); /* Delay for UTMI
265 PHY CLK to become stable - 10ms*/
266 }
267 }
268 portctrl |= PORTSCX_PTS_UTMI;
269 break;
270 case FSL_USB2_PHY_SERIAL:
271 portctrl |= PORTSCX_PTS_FSLS;
272 break;
273 default:
274 return -EINVAL;
275 }
276 fsl_writel(portctrl, &dr_regs->portsc1);
277
278 /* Stop and reset the usb controller */
279 tmp = fsl_readl(&dr_regs->usbcmd);
280 tmp &= ~USB_CMD_RUN_STOP;
281 fsl_writel(tmp, &dr_regs->usbcmd);
282
283 tmp = fsl_readl(&dr_regs->usbcmd);
284 tmp |= USB_CMD_CTRL_RESET;
285 fsl_writel(tmp, &dr_regs->usbcmd);
286
287 /* Wait for reset to complete */
288 timeout = jiffies + FSL_UDC_RESET_TIMEOUT;
289 while (fsl_readl(&dr_regs->usbcmd) & USB_CMD_CTRL_RESET) {
290 if (time_after(jiffies, timeout)) {
291 ERR("udc reset timeout!\n");
292 return -ETIMEDOUT;
293 }
294 cpu_relax();
295 }
296
297 /* Set the controller as device mode */
298 tmp = fsl_readl(&dr_regs->usbmode);
299 tmp &= ~USB_MODE_CTRL_MODE_MASK; /* clear mode bits */
300 tmp |= USB_MODE_CTRL_MODE_DEVICE;
301 /* Disable Setup Lockout */
302 tmp |= USB_MODE_SETUP_LOCK_OFF;
303 if (udc->pdata->es)
304 tmp |= USB_MODE_ES;
305 fsl_writel(tmp, &dr_regs->usbmode);
306
307 /* Clear the setup status */
308 fsl_writel(0, &dr_regs->usbsts);
309
310 tmp = udc->ep_qh_dma;
311 tmp &= USB_EP_LIST_ADDRESS_MASK;
312 fsl_writel(tmp, &dr_regs->endpointlistaddr);
313
314 VDBG("vir[qh_base] is %p phy[qh_base] is 0x%8x reg is 0x%8x",
315 udc->ep_qh, (int)tmp,
316 fsl_readl(&dr_regs->endpointlistaddr));
317
318 max_no_of_ep = (0x0000001F & fsl_readl(&dr_regs->dccparams));
319 for (ep_num = 1; ep_num < max_no_of_ep; ep_num++) {
320 tmp = fsl_readl(&dr_regs->endptctrl[ep_num]);
321 tmp &= ~(EPCTRL_TX_TYPE | EPCTRL_RX_TYPE);
322 tmp |= (EPCTRL_EP_TYPE_BULK << EPCTRL_TX_EP_TYPE_SHIFT)
323 | (EPCTRL_EP_TYPE_BULK << EPCTRL_RX_EP_TYPE_SHIFT);
324 fsl_writel(tmp, &dr_regs->endptctrl[ep_num]);
325 }
326 /* Config control enable i/o output, cpu endian register */
327 #ifndef CONFIG_ARCH_MXC
328 if (udc->pdata->have_sysif_regs) {
329 ctrl = __raw_readl(&usb_sys_regs->control);
330 ctrl |= USB_CTRL_IOENB;
331 __raw_writel(ctrl, &usb_sys_regs->control);
332 }
333 #endif
334
335 #if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
336 /* Turn on cache snooping hardware, since some PowerPC platforms
337 * wholly rely on hardware to deal with cache coherent. */
338
339 if (udc->pdata->have_sysif_regs) {
340 /* Setup Snooping for all the 4GB space */
341 tmp = SNOOP_SIZE_2GB; /* starts from 0x0, size 2G */
342 __raw_writel(tmp, &usb_sys_regs->snoop1);
343 tmp |= 0x80000000; /* starts from 0x8000000, size 2G */
344 __raw_writel(tmp, &usb_sys_regs->snoop2);
345 }
346 #endif
347
348 return 0;
349 }
350
351 /* Enable DR irq and set controller to run state */
352 static void dr_controller_run(struct fsl_udc *udc)
353 {
354 u32 temp;
355
356 /* Enable DR irq reg */
357 temp = USB_INTR_INT_EN | USB_INTR_ERR_INT_EN
358 | USB_INTR_PTC_DETECT_EN | USB_INTR_RESET_EN
359 | USB_INTR_DEVICE_SUSPEND | USB_INTR_SYS_ERR_EN;
360
361 fsl_writel(temp, &dr_regs->usbintr);
362
363 /* Clear stopped bit */
364 udc->stopped = 0;
365
366 /* Set the controller as device mode */
367 temp = fsl_readl(&dr_regs->usbmode);
368 temp |= USB_MODE_CTRL_MODE_DEVICE;
369 fsl_writel(temp, &dr_regs->usbmode);
370
371 /* Set controller to Run */
372 temp = fsl_readl(&dr_regs->usbcmd);
373 temp |= USB_CMD_RUN_STOP;
374 fsl_writel(temp, &dr_regs->usbcmd);
375 }
376
377 static void dr_controller_stop(struct fsl_udc *udc)
378 {
379 unsigned int tmp;
380
381 pr_debug("%s\n", __func__);
382
383 /* if we're in OTG mode, and the Host is currently using the port,
384 * stop now and don't rip the controller out from under the
385 * ehci driver
386 */
387 if (udc->gadget.is_otg) {
388 if (!(fsl_readl(&dr_regs->otgsc) & OTGSC_STS_USB_ID)) {
389 pr_debug("udc: Leaving early\n");
390 return;
391 }
392 }
393
394 /* disable all INTR */
395 fsl_writel(0, &dr_regs->usbintr);
396
397 /* Set stopped bit for isr */
398 udc->stopped = 1;
399
400 /* disable IO output */
401 /* usb_sys_regs->control = 0; */
402
403 /* set controller to Stop */
404 tmp = fsl_readl(&dr_regs->usbcmd);
405 tmp &= ~USB_CMD_RUN_STOP;
406 fsl_writel(tmp, &dr_regs->usbcmd);
407 }
408
409 static void dr_ep_setup(unsigned char ep_num, unsigned char dir,
410 unsigned char ep_type)
411 {
412 unsigned int tmp_epctrl = 0;
413
414 tmp_epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]);
415 if (dir) {
416 if (ep_num)
417 tmp_epctrl |= EPCTRL_TX_DATA_TOGGLE_RST;
418 tmp_epctrl |= EPCTRL_TX_ENABLE;
419 tmp_epctrl &= ~EPCTRL_TX_TYPE;
420 tmp_epctrl |= ((unsigned int)(ep_type)
421 << EPCTRL_TX_EP_TYPE_SHIFT);
422 } else {
423 if (ep_num)
424 tmp_epctrl |= EPCTRL_RX_DATA_TOGGLE_RST;
425 tmp_epctrl |= EPCTRL_RX_ENABLE;
426 tmp_epctrl &= ~EPCTRL_RX_TYPE;
427 tmp_epctrl |= ((unsigned int)(ep_type)
428 << EPCTRL_RX_EP_TYPE_SHIFT);
429 }
430
431 fsl_writel(tmp_epctrl, &dr_regs->endptctrl[ep_num]);
432 }
433
434 static void
435 dr_ep_change_stall(unsigned char ep_num, unsigned char dir, int value)
436 {
437 u32 tmp_epctrl = 0;
438
439 tmp_epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]);
440
441 if (value) {
442 /* set the stall bit */
443 if (dir)
444 tmp_epctrl |= EPCTRL_TX_EP_STALL;
445 else
446 tmp_epctrl |= EPCTRL_RX_EP_STALL;
447 } else {
448 /* clear the stall bit and reset data toggle */
449 if (dir) {
450 tmp_epctrl &= ~EPCTRL_TX_EP_STALL;
451 tmp_epctrl |= EPCTRL_TX_DATA_TOGGLE_RST;
452 } else {
453 tmp_epctrl &= ~EPCTRL_RX_EP_STALL;
454 tmp_epctrl |= EPCTRL_RX_DATA_TOGGLE_RST;
455 }
456 }
457 fsl_writel(tmp_epctrl, &dr_regs->endptctrl[ep_num]);
458 }
459
460 /* Get stall status of a specific ep
461 Return: 0: not stalled; 1:stalled */
462 static int dr_ep_get_stall(unsigned char ep_num, unsigned char dir)
463 {
464 u32 epctrl;
465
466 epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]);
467 if (dir)
468 return (epctrl & EPCTRL_TX_EP_STALL) ? 1 : 0;
469 else
470 return (epctrl & EPCTRL_RX_EP_STALL) ? 1 : 0;
471 }
472
473 /********************************************************************
474 Internal Structure Build up functions
475 ********************************************************************/
476
477 /*------------------------------------------------------------------
478 * struct_ep_qh_setup(): set the Endpoint Capabilites field of QH
479 * @zlt: Zero Length Termination Select (1: disable; 0: enable)
480 * @mult: Mult field
481 ------------------------------------------------------------------*/
482 static void struct_ep_qh_setup(struct fsl_udc *udc, unsigned char ep_num,
483 unsigned char dir, unsigned char ep_type,
484 unsigned int max_pkt_len,
485 unsigned int zlt, unsigned char mult)
486 {
487 struct ep_queue_head *p_QH = &udc->ep_qh[2 * ep_num + dir];
488 unsigned int tmp = 0;
489
490 /* set the Endpoint Capabilites in QH */
491 switch (ep_type) {
492 case USB_ENDPOINT_XFER_CONTROL:
493 /* Interrupt On Setup (IOS). for control ep */
494 tmp = (max_pkt_len << EP_QUEUE_HEAD_MAX_PKT_LEN_POS)
495 | EP_QUEUE_HEAD_IOS;
496 break;
497 case USB_ENDPOINT_XFER_ISOC:
498 tmp = (max_pkt_len << EP_QUEUE_HEAD_MAX_PKT_LEN_POS)
499 | (mult << EP_QUEUE_HEAD_MULT_POS);
500 break;
501 case USB_ENDPOINT_XFER_BULK:
502 case USB_ENDPOINT_XFER_INT:
503 tmp = max_pkt_len << EP_QUEUE_HEAD_MAX_PKT_LEN_POS;
504 break;
505 default:
506 VDBG("error ep type is %d", ep_type);
507 return;
508 }
509 if (zlt)
510 tmp |= EP_QUEUE_HEAD_ZLT_SEL;
511
512 p_QH->max_pkt_length = cpu_to_hc32(tmp);
513 p_QH->next_dtd_ptr = 1;
514 p_QH->size_ioc_int_sts = 0;
515 }
516
517 /* Setup qh structure and ep register for ep0. */
518 static void ep0_setup(struct fsl_udc *udc)
519 {
520 /* the initialization of an ep includes: fields in QH, Regs,
521 * fsl_ep struct */
522 struct_ep_qh_setup(udc, 0, USB_RECV, USB_ENDPOINT_XFER_CONTROL,
523 USB_MAX_CTRL_PAYLOAD, 0, 0);
524 struct_ep_qh_setup(udc, 0, USB_SEND, USB_ENDPOINT_XFER_CONTROL,
525 USB_MAX_CTRL_PAYLOAD, 0, 0);
526 dr_ep_setup(0, USB_RECV, USB_ENDPOINT_XFER_CONTROL);
527 dr_ep_setup(0, USB_SEND, USB_ENDPOINT_XFER_CONTROL);
528
529 return;
530
531 }
532
533 /***********************************************************************
534 Endpoint Management Functions
535 ***********************************************************************/
536
537 /*-------------------------------------------------------------------------
538 * when configurations are set, or when interface settings change
539 * for example the do_set_interface() in gadget layer,
540 * the driver will enable or disable the relevant endpoints
541 * ep0 doesn't use this routine. It is always enabled.
542 -------------------------------------------------------------------------*/
543 static int fsl_ep_enable(struct usb_ep *_ep,
544 const struct usb_endpoint_descriptor *desc)
545 {
546 struct fsl_udc *udc = NULL;
547 struct fsl_ep *ep = NULL;
548 unsigned short max = 0;
549 unsigned char mult = 0, zlt;
550 int retval = -EINVAL;
551 unsigned long flags = 0;
552
553 ep = container_of(_ep, struct fsl_ep, ep);
554
555 /* catch various bogus parameters */
556 if (!_ep || !desc
557 || (desc->bDescriptorType != USB_DT_ENDPOINT))
558 return -EINVAL;
559
560 udc = ep->udc;
561
562 if (!udc->driver || (udc->gadget.speed == USB_SPEED_UNKNOWN))
563 return -ESHUTDOWN;
564
565 max = usb_endpoint_maxp(desc);
566
567 /* Disable automatic zlp generation. Driver is responsible to indicate
568 * explicitly through req->req.zero. This is needed to enable multi-td
569 * request. */
570 zlt = 1;
571
572 /* Assume the max packet size from gadget is always correct */
573 switch (desc->bmAttributes & 0x03) {
574 case USB_ENDPOINT_XFER_CONTROL:
575 case USB_ENDPOINT_XFER_BULK:
576 case USB_ENDPOINT_XFER_INT:
577 /* mult = 0. Execute N Transactions as demonstrated by
578 * the USB variable length packet protocol where N is
579 * computed using the Maximum Packet Length (dQH) and
580 * the Total Bytes field (dTD) */
581 mult = 0;
582 break;
583 case USB_ENDPOINT_XFER_ISOC:
584 /* Calculate transactions needed for high bandwidth iso */
585 mult = usb_endpoint_maxp_mult(desc);
586 /* 3 transactions at most */
587 if (mult > 3)
588 goto en_done;
589 break;
590 default:
591 goto en_done;
592 }
593
594 spin_lock_irqsave(&udc->lock, flags);
595 ep->ep.maxpacket = max;
596 ep->ep.desc = desc;
597 ep->stopped = 0;
598
599 /* Controller related setup */
600 /* Init EPx Queue Head (Ep Capabilites field in QH
601 * according to max, zlt, mult) */
602 struct_ep_qh_setup(udc, (unsigned char) ep_index(ep),
603 (unsigned char) ((desc->bEndpointAddress & USB_DIR_IN)
604 ? USB_SEND : USB_RECV),
605 (unsigned char) (desc->bmAttributes
606 & USB_ENDPOINT_XFERTYPE_MASK),
607 max, zlt, mult);
608
609 /* Init endpoint ctrl register */
610 dr_ep_setup((unsigned char) ep_index(ep),
611 (unsigned char) ((desc->bEndpointAddress & USB_DIR_IN)
612 ? USB_SEND : USB_RECV),
613 (unsigned char) (desc->bmAttributes
614 & USB_ENDPOINT_XFERTYPE_MASK));
615
616 spin_unlock_irqrestore(&udc->lock, flags);
617 retval = 0;
618
619 VDBG("enabled %s (ep%d%s) maxpacket %d",ep->ep.name,
620 ep->ep.desc->bEndpointAddress & 0x0f,
621 (desc->bEndpointAddress & USB_DIR_IN)
622 ? "in" : "out", max);
623 en_done:
624 return retval;
625 }
626
627 /*---------------------------------------------------------------------
628 * @ep : the ep being unconfigured. May not be ep0
629 * Any pending and uncomplete req will complete with status (-ESHUTDOWN)
630 *---------------------------------------------------------------------*/
631 static int fsl_ep_disable(struct usb_ep *_ep)
632 {
633 struct fsl_udc *udc = NULL;
634 struct fsl_ep *ep = NULL;
635 unsigned long flags = 0;
636 u32 epctrl;
637 int ep_num;
638
639 ep = container_of(_ep, struct fsl_ep, ep);
640 if (!_ep || !ep->ep.desc) {
641 VDBG("%s not enabled", _ep ? ep->ep.name : NULL);
642 return -EINVAL;
643 }
644
645 /* disable ep on controller */
646 ep_num = ep_index(ep);
647 epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]);
648 if (ep_is_in(ep)) {
649 epctrl &= ~(EPCTRL_TX_ENABLE | EPCTRL_TX_TYPE);
650 epctrl |= EPCTRL_EP_TYPE_BULK << EPCTRL_TX_EP_TYPE_SHIFT;
651 } else {
652 epctrl &= ~(EPCTRL_RX_ENABLE | EPCTRL_TX_TYPE);
653 epctrl |= EPCTRL_EP_TYPE_BULK << EPCTRL_RX_EP_TYPE_SHIFT;
654 }
655 fsl_writel(epctrl, &dr_regs->endptctrl[ep_num]);
656
657 udc = (struct fsl_udc *)ep->udc;
658 spin_lock_irqsave(&udc->lock, flags);
659
660 /* nuke all pending requests (does flush) */
661 nuke(ep, -ESHUTDOWN);
662
663 ep->ep.desc = NULL;
664 ep->stopped = 1;
665 spin_unlock_irqrestore(&udc->lock, flags);
666
667 VDBG("disabled %s OK", _ep->name);
668 return 0;
669 }
670
671 /*---------------------------------------------------------------------
672 * allocate a request object used by this endpoint
673 * the main operation is to insert the req->queue to the eq->queue
674 * Returns the request, or null if one could not be allocated
675 *---------------------------------------------------------------------*/
676 static struct usb_request *
677 fsl_alloc_request(struct usb_ep *_ep, gfp_t gfp_flags)
678 {
679 struct fsl_req *req = NULL;
680
681 req = kzalloc(sizeof *req, gfp_flags);
682 if (!req)
683 return NULL;
684
685 req->req.dma = DMA_ADDR_INVALID;
686 INIT_LIST_HEAD(&req->queue);
687
688 return &req->req;
689 }
690
691 static void fsl_free_request(struct usb_ep *_ep, struct usb_request *_req)
692 {
693 struct fsl_req *req = NULL;
694
695 req = container_of(_req, struct fsl_req, req);
696
697 if (_req)
698 kfree(req);
699 }
700
701 /* Actually add a dTD chain to an empty dQH and let go */
702 static void fsl_prime_ep(struct fsl_ep *ep, struct ep_td_struct *td)
703 {
704 struct ep_queue_head *qh = get_qh_by_ep(ep);
705
706 /* Write dQH next pointer and terminate bit to 0 */
707 qh->next_dtd_ptr = cpu_to_hc32(td->td_dma
708 & EP_QUEUE_HEAD_NEXT_POINTER_MASK);
709
710 /* Clear active and halt bit */
711 qh->size_ioc_int_sts &= cpu_to_hc32(~(EP_QUEUE_HEAD_STATUS_ACTIVE
712 | EP_QUEUE_HEAD_STATUS_HALT));
713
714 /* Ensure that updates to the QH will occur before priming. */
715 wmb();
716
717 /* Prime endpoint by writing correct bit to ENDPTPRIME */
718 fsl_writel(ep_is_in(ep) ? (1 << (ep_index(ep) + 16))
719 : (1 << (ep_index(ep))), &dr_regs->endpointprime);
720 }
721
722 /* Add dTD chain to the dQH of an EP */
723 static void fsl_queue_td(struct fsl_ep *ep, struct fsl_req *req)
724 {
725 u32 temp, bitmask, tmp_stat;
726
727 /* VDBG("QH addr Register 0x%8x", dr_regs->endpointlistaddr);
728 VDBG("ep_qh[%d] addr is 0x%8x", i, (u32)&(ep->udc->ep_qh[i])); */
729
730 bitmask = ep_is_in(ep)
731 ? (1 << (ep_index(ep) + 16))
732 : (1 << (ep_index(ep)));
733
734 /* check if the pipe is empty */
735 if (!(list_empty(&ep->queue)) && !(ep_index(ep) == 0)) {
736 /* Add td to the end */
737 struct fsl_req *lastreq;
738 lastreq = list_entry(ep->queue.prev, struct fsl_req, queue);
739 lastreq->tail->next_td_ptr =
740 cpu_to_hc32(req->head->td_dma & DTD_ADDR_MASK);
741 /* Ensure dTD's next dtd pointer to be updated */
742 wmb();
743 /* Read prime bit, if 1 goto done */
744 if (fsl_readl(&dr_regs->endpointprime) & bitmask)
745 return;
746
747 do {
748 /* Set ATDTW bit in USBCMD */
749 temp = fsl_readl(&dr_regs->usbcmd);
750 fsl_writel(temp | USB_CMD_ATDTW, &dr_regs->usbcmd);
751
752 /* Read correct status bit */
753 tmp_stat = fsl_readl(&dr_regs->endptstatus) & bitmask;
754
755 } while (!(fsl_readl(&dr_regs->usbcmd) & USB_CMD_ATDTW));
756
757 /* Write ATDTW bit to 0 */
758 temp = fsl_readl(&dr_regs->usbcmd);
759 fsl_writel(temp & ~USB_CMD_ATDTW, &dr_regs->usbcmd);
760
761 if (tmp_stat)
762 return;
763 }
764
765 fsl_prime_ep(ep, req->head);
766 }
767
768 /* Fill in the dTD structure
769 * @req: request that the transfer belongs to
770 * @length: return actually data length of the dTD
771 * @dma: return dma address of the dTD
772 * @is_last: return flag if it is the last dTD of the request
773 * return: pointer to the built dTD */
774 static struct ep_td_struct *fsl_build_dtd(struct fsl_req *req, unsigned *length,
775 dma_addr_t *dma, int *is_last, gfp_t gfp_flags)
776 {
777 u32 swap_temp;
778 struct ep_td_struct *dtd;
779
780 /* how big will this transfer be? */
781 *length = min(req->req.length - req->req.actual,
782 (unsigned)EP_MAX_LENGTH_TRANSFER);
783
784 dtd = dma_pool_alloc(udc_controller->td_pool, gfp_flags, dma);
785 if (dtd == NULL)
786 return dtd;
787
788 dtd->td_dma = *dma;
789 /* Clear reserved field */
790 swap_temp = hc32_to_cpu(dtd->size_ioc_sts);
791 swap_temp &= ~DTD_RESERVED_FIELDS;
792 dtd->size_ioc_sts = cpu_to_hc32(swap_temp);
793
794 /* Init all of buffer page pointers */
795 swap_temp = (u32) (req->req.dma + req->req.actual);
796 dtd->buff_ptr0 = cpu_to_hc32(swap_temp);
797 dtd->buff_ptr1 = cpu_to_hc32(swap_temp + 0x1000);
798 dtd->buff_ptr2 = cpu_to_hc32(swap_temp + 0x2000);
799 dtd->buff_ptr3 = cpu_to_hc32(swap_temp + 0x3000);
800 dtd->buff_ptr4 = cpu_to_hc32(swap_temp + 0x4000);
801
802 req->req.actual += *length;
803
804 /* zlp is needed if req->req.zero is set */
805 if (req->req.zero) {
806 if (*length == 0 || (*length % req->ep->ep.maxpacket) != 0)
807 *is_last = 1;
808 else
809 *is_last = 0;
810 } else if (req->req.length == req->req.actual)
811 *is_last = 1;
812 else
813 *is_last = 0;
814
815 if ((*is_last) == 0)
816 VDBG("multi-dtd request!");
817 /* Fill in the transfer size; set active bit */
818 swap_temp = ((*length << DTD_LENGTH_BIT_POS) | DTD_STATUS_ACTIVE);
819
820 /* Enable interrupt for the last dtd of a request */
821 if (*is_last && !req->req.no_interrupt)
822 swap_temp |= DTD_IOC;
823
824 dtd->size_ioc_sts = cpu_to_hc32(swap_temp);
825
826 mb();
827
828 VDBG("length = %d address= 0x%x", *length, (int)*dma);
829
830 return dtd;
831 }
832
833 /* Generate dtd chain for a request */
834 static int fsl_req_to_dtd(struct fsl_req *req, gfp_t gfp_flags)
835 {
836 unsigned count;
837 int is_last;
838 int is_first =1;
839 struct ep_td_struct *last_dtd = NULL, *dtd;
840 dma_addr_t dma;
841
842 do {
843 dtd = fsl_build_dtd(req, &count, &dma, &is_last, gfp_flags);
844 if (dtd == NULL)
845 return -ENOMEM;
846
847 if (is_first) {
848 is_first = 0;
849 req->head = dtd;
850 } else {
851 last_dtd->next_td_ptr = cpu_to_hc32(dma);
852 last_dtd->next_td_virt = dtd;
853 }
854 last_dtd = dtd;
855
856 req->dtd_count++;
857 } while (!is_last);
858
859 dtd->next_td_ptr = cpu_to_hc32(DTD_NEXT_TERMINATE);
860
861 req->tail = dtd;
862
863 return 0;
864 }
865
866 /* queues (submits) an I/O request to an endpoint */
867 static int
868 fsl_ep_queue(struct usb_ep *_ep, struct usb_request *_req, gfp_t gfp_flags)
869 {
870 struct fsl_ep *ep = container_of(_ep, struct fsl_ep, ep);
871 struct fsl_req *req = container_of(_req, struct fsl_req, req);
872 struct fsl_udc *udc;
873 unsigned long flags;
874 int ret;
875
876 /* catch various bogus parameters */
877 if (!_req || !req->req.complete || !req->req.buf
878 || !list_empty(&req->queue)) {
879 VDBG("%s, bad params", __func__);
880 return -EINVAL;
881 }
882 if (unlikely(!_ep || !ep->ep.desc)) {
883 VDBG("%s, bad ep", __func__);
884 return -EINVAL;
885 }
886 if (usb_endpoint_xfer_isoc(ep->ep.desc)) {
887 if (req->req.length > ep->ep.maxpacket)
888 return -EMSGSIZE;
889 }
890
891 udc = ep->udc;
892 if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN)
893 return -ESHUTDOWN;
894
895 req->ep = ep;
896
897 ret = usb_gadget_map_request(&ep->udc->gadget, &req->req, ep_is_in(ep));
898 if (ret)
899 return ret;
900
901 req->req.status = -EINPROGRESS;
902 req->req.actual = 0;
903 req->dtd_count = 0;
904
905 /* build dtds and push them to device queue */
906 if (!fsl_req_to_dtd(req, gfp_flags)) {
907 spin_lock_irqsave(&udc->lock, flags);
908 fsl_queue_td(ep, req);
909 } else {
910 return -ENOMEM;
911 }
912
913 /* irq handler advances the queue */
914 if (req != NULL)
915 list_add_tail(&req->queue, &ep->queue);
916 spin_unlock_irqrestore(&udc->lock, flags);
917
918 return 0;
919 }
920
921 /* dequeues (cancels, unlinks) an I/O request from an endpoint */
922 static int fsl_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req)
923 {
924 struct fsl_ep *ep = container_of(_ep, struct fsl_ep, ep);
925 struct fsl_req *req;
926 unsigned long flags;
927 int ep_num, stopped, ret = 0;
928 u32 epctrl;
929
930 if (!_ep || !_req)
931 return -EINVAL;
932
933 spin_lock_irqsave(&ep->udc->lock, flags);
934 stopped = ep->stopped;
935
936 /* Stop the ep before we deal with the queue */
937 ep->stopped = 1;
938 ep_num = ep_index(ep);
939 epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]);
940 if (ep_is_in(ep))
941 epctrl &= ~EPCTRL_TX_ENABLE;
942 else
943 epctrl &= ~EPCTRL_RX_ENABLE;
944 fsl_writel(epctrl, &dr_regs->endptctrl[ep_num]);
945
946 /* make sure it's actually queued on this endpoint */
947 list_for_each_entry(req, &ep->queue, queue) {
948 if (&req->req == _req)
949 break;
950 }
951 if (&req->req != _req) {
952 ret = -EINVAL;
953 goto out;
954 }
955
956 /* The request is in progress, or completed but not dequeued */
957 if (ep->queue.next == &req->queue) {
958 _req->status = -ECONNRESET;
959 fsl_ep_fifo_flush(_ep); /* flush current transfer */
960
961 /* The request isn't the last request in this ep queue */
962 if (req->queue.next != &ep->queue) {
963 struct fsl_req *next_req;
964
965 next_req = list_entry(req->queue.next, struct fsl_req,
966 queue);
967
968 /* prime with dTD of next request */
969 fsl_prime_ep(ep, next_req->head);
970 }
971 /* The request hasn't been processed, patch up the TD chain */
972 } else {
973 struct fsl_req *prev_req;
974
975 prev_req = list_entry(req->queue.prev, struct fsl_req, queue);
976 prev_req->tail->next_td_ptr = req->tail->next_td_ptr;
977 }
978
979 done(ep, req, -ECONNRESET);
980
981 /* Enable EP */
982 out: epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]);
983 if (ep_is_in(ep))
984 epctrl |= EPCTRL_TX_ENABLE;
985 else
986 epctrl |= EPCTRL_RX_ENABLE;
987 fsl_writel(epctrl, &dr_regs->endptctrl[ep_num]);
988 ep->stopped = stopped;
989
990 spin_unlock_irqrestore(&ep->udc->lock, flags);
991 return ret;
992 }
993
994 /*-------------------------------------------------------------------------*/
995
996 /*-----------------------------------------------------------------
997 * modify the endpoint halt feature
998 * @ep: the non-isochronous endpoint being stalled
999 * @value: 1--set halt 0--clear halt
1000 * Returns zero, or a negative error code.
1001 *----------------------------------------------------------------*/
1002 static int fsl_ep_set_halt(struct usb_ep *_ep, int value)
1003 {
1004 struct fsl_ep *ep = NULL;
1005 unsigned long flags = 0;
1006 int status = -EOPNOTSUPP; /* operation not supported */
1007 unsigned char ep_dir = 0, ep_num = 0;
1008 struct fsl_udc *udc = NULL;
1009
1010 ep = container_of(_ep, struct fsl_ep, ep);
1011 udc = ep->udc;
1012 if (!_ep || !ep->ep.desc) {
1013 status = -EINVAL;
1014 goto out;
1015 }
1016
1017 if (usb_endpoint_xfer_isoc(ep->ep.desc)) {
1018 status = -EOPNOTSUPP;
1019 goto out;
1020 }
1021
1022 /* Attempt to halt IN ep will fail if any transfer requests
1023 * are still queue */
1024 if (value && ep_is_in(ep) && !list_empty(&ep->queue)) {
1025 status = -EAGAIN;
1026 goto out;
1027 }
1028
1029 status = 0;
1030 ep_dir = ep_is_in(ep) ? USB_SEND : USB_RECV;
1031 ep_num = (unsigned char)(ep_index(ep));
1032 spin_lock_irqsave(&ep->udc->lock, flags);
1033 dr_ep_change_stall(ep_num, ep_dir, value);
1034 spin_unlock_irqrestore(&ep->udc->lock, flags);
1035
1036 if (ep_index(ep) == 0) {
1037 udc->ep0_state = WAIT_FOR_SETUP;
1038 udc->ep0_dir = 0;
1039 }
1040 out:
1041 VDBG(" %s %s halt stat %d", ep->ep.name,
1042 value ? "set" : "clear", status);
1043
1044 return status;
1045 }
1046
1047 static int fsl_ep_fifo_status(struct usb_ep *_ep)
1048 {
1049 struct fsl_ep *ep;
1050 struct fsl_udc *udc;
1051 int size = 0;
1052 u32 bitmask;
1053 struct ep_queue_head *qh;
1054
1055 ep = container_of(_ep, struct fsl_ep, ep);
1056 if (!_ep || (!ep->ep.desc && ep_index(ep) != 0))
1057 return -ENODEV;
1058
1059 udc = (struct fsl_udc *)ep->udc;
1060
1061 if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN)
1062 return -ESHUTDOWN;
1063
1064 qh = get_qh_by_ep(ep);
1065
1066 bitmask = (ep_is_in(ep)) ? (1 << (ep_index(ep) + 16)) :
1067 (1 << (ep_index(ep)));
1068
1069 if (fsl_readl(&dr_regs->endptstatus) & bitmask)
1070 size = (qh->size_ioc_int_sts & DTD_PACKET_SIZE)
1071 >> DTD_LENGTH_BIT_POS;
1072
1073 pr_debug("%s %u\n", __func__, size);
1074 return size;
1075 }
1076
1077 static void fsl_ep_fifo_flush(struct usb_ep *_ep)
1078 {
1079 struct fsl_ep *ep;
1080 int ep_num, ep_dir;
1081 u32 bits;
1082 unsigned long timeout;
1083 #define FSL_UDC_FLUSH_TIMEOUT 1000
1084
1085 if (!_ep) {
1086 return;
1087 } else {
1088 ep = container_of(_ep, struct fsl_ep, ep);
1089 if (!ep->ep.desc)
1090 return;
1091 }
1092 ep_num = ep_index(ep);
1093 ep_dir = ep_is_in(ep) ? USB_SEND : USB_RECV;
1094
1095 if (ep_num == 0)
1096 bits = (1 << 16) | 1;
1097 else if (ep_dir == USB_SEND)
1098 bits = 1 << (16 + ep_num);
1099 else
1100 bits = 1 << ep_num;
1101
1102 timeout = jiffies + FSL_UDC_FLUSH_TIMEOUT;
1103 do {
1104 fsl_writel(bits, &dr_regs->endptflush);
1105
1106 /* Wait until flush complete */
1107 while (fsl_readl(&dr_regs->endptflush)) {
1108 if (time_after(jiffies, timeout)) {
1109 ERR("ep flush timeout\n");
1110 return;
1111 }
1112 cpu_relax();
1113 }
1114 /* See if we need to flush again */
1115 } while (fsl_readl(&dr_regs->endptstatus) & bits);
1116 }
1117
1118 static const struct usb_ep_ops fsl_ep_ops = {
1119 .enable = fsl_ep_enable,
1120 .disable = fsl_ep_disable,
1121
1122 .alloc_request = fsl_alloc_request,
1123 .free_request = fsl_free_request,
1124
1125 .queue = fsl_ep_queue,
1126 .dequeue = fsl_ep_dequeue,
1127
1128 .set_halt = fsl_ep_set_halt,
1129 .fifo_status = fsl_ep_fifo_status,
1130 .fifo_flush = fsl_ep_fifo_flush, /* flush fifo */
1131 };
1132
1133 /*-------------------------------------------------------------------------
1134 Gadget Driver Layer Operations
1135 -------------------------------------------------------------------------*/
1136
1137 /*----------------------------------------------------------------------
1138 * Get the current frame number (from DR frame_index Reg )
1139 *----------------------------------------------------------------------*/
1140 static int fsl_get_frame(struct usb_gadget *gadget)
1141 {
1142 return (int)(fsl_readl(&dr_regs->frindex) & USB_FRINDEX_MASKS);
1143 }
1144
1145 /*-----------------------------------------------------------------------
1146 * Tries to wake up the host connected to this gadget
1147 -----------------------------------------------------------------------*/
1148 static int fsl_wakeup(struct usb_gadget *gadget)
1149 {
1150 struct fsl_udc *udc = container_of(gadget, struct fsl_udc, gadget);
1151 u32 portsc;
1152
1153 /* Remote wakeup feature not enabled by host */
1154 if (!udc->remote_wakeup)
1155 return -ENOTSUPP;
1156
1157 portsc = fsl_readl(&dr_regs->portsc1);
1158 /* not suspended? */
1159 if (!(portsc & PORTSCX_PORT_SUSPEND))
1160 return 0;
1161 /* trigger force resume */
1162 portsc |= PORTSCX_PORT_FORCE_RESUME;
1163 fsl_writel(portsc, &dr_regs->portsc1);
1164 return 0;
1165 }
1166
1167 static int can_pullup(struct fsl_udc *udc)
1168 {
1169 return udc->driver && udc->softconnect && udc->vbus_active;
1170 }
1171
1172 /* Notify controller that VBUS is powered, Called by whatever
1173 detects VBUS sessions */
1174 static int fsl_vbus_session(struct usb_gadget *gadget, int is_active)
1175 {
1176 struct fsl_udc *udc;
1177 unsigned long flags;
1178
1179 udc = container_of(gadget, struct fsl_udc, gadget);
1180 spin_lock_irqsave(&udc->lock, flags);
1181 VDBG("VBUS %s", is_active ? "on" : "off");
1182 udc->vbus_active = (is_active != 0);
1183 if (can_pullup(udc))
1184 fsl_writel((fsl_readl(&dr_regs->usbcmd) | USB_CMD_RUN_STOP),
1185 &dr_regs->usbcmd);
1186 else
1187 fsl_writel((fsl_readl(&dr_regs->usbcmd) & ~USB_CMD_RUN_STOP),
1188 &dr_regs->usbcmd);
1189 spin_unlock_irqrestore(&udc->lock, flags);
1190 return 0;
1191 }
1192
1193 /* constrain controller's VBUS power usage
1194 * This call is used by gadget drivers during SET_CONFIGURATION calls,
1195 * reporting how much power the device may consume. For example, this
1196 * could affect how quickly batteries are recharged.
1197 *
1198 * Returns zero on success, else negative errno.
1199 */
1200 static int fsl_vbus_draw(struct usb_gadget *gadget, unsigned mA)
1201 {
1202 struct fsl_udc *udc;
1203
1204 udc = container_of(gadget, struct fsl_udc, gadget);
1205 if (!IS_ERR_OR_NULL(udc->transceiver))
1206 return usb_phy_set_power(udc->transceiver, mA);
1207 return -ENOTSUPP;
1208 }
1209
1210 /* Change Data+ pullup status
1211 * this func is used by usb_gadget_connect/disconnet
1212 */
1213 static int fsl_pullup(struct usb_gadget *gadget, int is_on)
1214 {
1215 struct fsl_udc *udc;
1216
1217 udc = container_of(gadget, struct fsl_udc, gadget);
1218
1219 if (!udc->vbus_active)
1220 return -EOPNOTSUPP;
1221
1222 udc->softconnect = (is_on != 0);
1223 if (can_pullup(udc))
1224 fsl_writel((fsl_readl(&dr_regs->usbcmd) | USB_CMD_RUN_STOP),
1225 &dr_regs->usbcmd);
1226 else
1227 fsl_writel((fsl_readl(&dr_regs->usbcmd) & ~USB_CMD_RUN_STOP),
1228 &dr_regs->usbcmd);
1229
1230 return 0;
1231 }
1232
1233 static int fsl_udc_start(struct usb_gadget *g,
1234 struct usb_gadget_driver *driver);
1235 static int fsl_udc_stop(struct usb_gadget *g);
1236
1237 static const struct usb_gadget_ops fsl_gadget_ops = {
1238 .get_frame = fsl_get_frame,
1239 .wakeup = fsl_wakeup,
1240 /* .set_selfpowered = fsl_set_selfpowered, */ /* Always selfpowered */
1241 .vbus_session = fsl_vbus_session,
1242 .vbus_draw = fsl_vbus_draw,
1243 .pullup = fsl_pullup,
1244 .udc_start = fsl_udc_start,
1245 .udc_stop = fsl_udc_stop,
1246 };
1247
1248 /*
1249 * Empty complete function used by this driver to fill in the req->complete
1250 * field when creating a request since the complete field is mandatory.
1251 */
1252 static void fsl_noop_complete(struct usb_ep *ep, struct usb_request *req) { }
1253
1254 /* Set protocol stall on ep0, protocol stall will automatically be cleared
1255 on new transaction */
1256 static void ep0stall(struct fsl_udc *udc)
1257 {
1258 u32 tmp;
1259
1260 /* must set tx and rx to stall at the same time */
1261 tmp = fsl_readl(&dr_regs->endptctrl[0]);
1262 tmp |= EPCTRL_TX_EP_STALL | EPCTRL_RX_EP_STALL;
1263 fsl_writel(tmp, &dr_regs->endptctrl[0]);
1264 udc->ep0_state = WAIT_FOR_SETUP;
1265 udc->ep0_dir = 0;
1266 }
1267
1268 /* Prime a status phase for ep0 */
1269 static int ep0_prime_status(struct fsl_udc *udc, int direction)
1270 {
1271 struct fsl_req *req = udc->status_req;
1272 struct fsl_ep *ep;
1273 int ret;
1274
1275 if (direction == EP_DIR_IN)
1276 udc->ep0_dir = USB_DIR_IN;
1277 else
1278 udc->ep0_dir = USB_DIR_OUT;
1279
1280 ep = &udc->eps[0];
1281 if (udc->ep0_state != DATA_STATE_XMIT)
1282 udc->ep0_state = WAIT_FOR_OUT_STATUS;
1283
1284 req->ep = ep;
1285 req->req.length = 0;
1286 req->req.status = -EINPROGRESS;
1287 req->req.actual = 0;
1288 req->req.complete = fsl_noop_complete;
1289 req->dtd_count = 0;
1290
1291 ret = usb_gadget_map_request(&ep->udc->gadget, &req->req, ep_is_in(ep));
1292 if (ret)
1293 return ret;
1294
1295 if (fsl_req_to_dtd(req, GFP_ATOMIC) == 0)
1296 fsl_queue_td(ep, req);
1297 else
1298 return -ENOMEM;
1299
1300 list_add_tail(&req->queue, &ep->queue);
1301
1302 return 0;
1303 }
1304
1305 static void udc_reset_ep_queue(struct fsl_udc *udc, u8 pipe)
1306 {
1307 struct fsl_ep *ep = get_ep_by_pipe(udc, pipe);
1308
1309 if (ep->ep.name)
1310 nuke(ep, -ESHUTDOWN);
1311 }
1312
1313 /*
1314 * ch9 Set address
1315 */
1316 static void ch9setaddress(struct fsl_udc *udc, u16 value, u16 index, u16 length)
1317 {
1318 /* Save the new address to device struct */
1319 udc->device_address = (u8) value;
1320 /* Update usb state */
1321 udc->usb_state = USB_STATE_ADDRESS;
1322 /* Status phase */
1323 if (ep0_prime_status(udc, EP_DIR_IN))
1324 ep0stall(udc);
1325 }
1326
1327 /*
1328 * ch9 Get status
1329 */
1330 static void ch9getstatus(struct fsl_udc *udc, u8 request_type, u16 value,
1331 u16 index, u16 length)
1332 {
1333 u16 tmp = 0; /* Status, cpu endian */
1334 struct fsl_req *req;
1335 struct fsl_ep *ep;
1336 int ret;
1337
1338 ep = &udc->eps[0];
1339
1340 if ((request_type & USB_RECIP_MASK) == USB_RECIP_DEVICE) {
1341 /* Get device status */
1342 tmp = udc->gadget.is_selfpowered;
1343 tmp |= udc->remote_wakeup << USB_DEVICE_REMOTE_WAKEUP;
1344 } else if ((request_type & USB_RECIP_MASK) == USB_RECIP_INTERFACE) {
1345 /* Get interface status */
1346 /* We don't have interface information in udc driver */
1347 tmp = 0;
1348 } else if ((request_type & USB_RECIP_MASK) == USB_RECIP_ENDPOINT) {
1349 /* Get endpoint status */
1350 struct fsl_ep *target_ep;
1351
1352 target_ep = get_ep_by_pipe(udc, get_pipe_by_windex(index));
1353
1354 /* stall if endpoint doesn't exist */
1355 if (!target_ep->ep.desc)
1356 goto stall;
1357 tmp = dr_ep_get_stall(ep_index(target_ep), ep_is_in(target_ep))
1358 << USB_ENDPOINT_HALT;
1359 }
1360
1361 udc->ep0_dir = USB_DIR_IN;
1362 /* Borrow the per device status_req */
1363 req = udc->status_req;
1364 /* Fill in the reqest structure */
1365 *((u16 *) req->req.buf) = cpu_to_le16(tmp);
1366
1367 req->ep = ep;
1368 req->req.length = 2;
1369 req->req.status = -EINPROGRESS;
1370 req->req.actual = 0;
1371 req->req.complete = fsl_noop_complete;
1372 req->dtd_count = 0;
1373
1374 ret = usb_gadget_map_request(&ep->udc->gadget, &req->req, ep_is_in(ep));
1375 if (ret)
1376 goto stall;
1377
1378 /* prime the data phase */
1379 if ((fsl_req_to_dtd(req, GFP_ATOMIC) == 0))
1380 fsl_queue_td(ep, req);
1381 else /* no mem */
1382 goto stall;
1383
1384 list_add_tail(&req->queue, &ep->queue);
1385 udc->ep0_state = DATA_STATE_XMIT;
1386 if (ep0_prime_status(udc, EP_DIR_OUT))
1387 ep0stall(udc);
1388
1389 return;
1390 stall:
1391 ep0stall(udc);
1392 }
1393
1394 static void setup_received_irq(struct fsl_udc *udc,
1395 struct usb_ctrlrequest *setup)
1396 __releases(udc->lock)
1397 __acquires(udc->lock)
1398 {
1399 u16 wValue = le16_to_cpu(setup->wValue);
1400 u16 wIndex = le16_to_cpu(setup->wIndex);
1401 u16 wLength = le16_to_cpu(setup->wLength);
1402
1403 udc_reset_ep_queue(udc, 0);
1404
1405 /* We process some stardard setup requests here */
1406 switch (setup->bRequest) {
1407 case USB_REQ_GET_STATUS:
1408 /* Data+Status phase from udc */
1409 if ((setup->bRequestType & (USB_DIR_IN | USB_TYPE_MASK))
1410 != (USB_DIR_IN | USB_TYPE_STANDARD))
1411 break;
1412 ch9getstatus(udc, setup->bRequestType, wValue, wIndex, wLength);
1413 return;
1414
1415 case USB_REQ_SET_ADDRESS:
1416 /* Status phase from udc */
1417 if (setup->bRequestType != (USB_DIR_OUT | USB_TYPE_STANDARD
1418 | USB_RECIP_DEVICE))
1419 break;
1420 ch9setaddress(udc, wValue, wIndex, wLength);
1421 return;
1422
1423 case USB_REQ_CLEAR_FEATURE:
1424 case USB_REQ_SET_FEATURE:
1425 /* Status phase from udc */
1426 {
1427 int rc = -EOPNOTSUPP;
1428 u16 ptc = 0;
1429
1430 if ((setup->bRequestType & (USB_RECIP_MASK | USB_TYPE_MASK))
1431 == (USB_RECIP_ENDPOINT | USB_TYPE_STANDARD)) {
1432 int pipe = get_pipe_by_windex(wIndex);
1433 struct fsl_ep *ep;
1434
1435 if (wValue != 0 || wLength != 0 || pipe >= udc->max_ep)
1436 break;
1437 ep = get_ep_by_pipe(udc, pipe);
1438
1439 spin_unlock(&udc->lock);
1440 rc = fsl_ep_set_halt(&ep->ep,
1441 (setup->bRequest == USB_REQ_SET_FEATURE)
1442 ? 1 : 0);
1443 spin_lock(&udc->lock);
1444
1445 } else if ((setup->bRequestType & (USB_RECIP_MASK
1446 | USB_TYPE_MASK)) == (USB_RECIP_DEVICE
1447 | USB_TYPE_STANDARD)) {
1448 /* Note: The driver has not include OTG support yet.
1449 * This will be set when OTG support is added */
1450 if (wValue == USB_DEVICE_TEST_MODE)
1451 ptc = wIndex >> 8;
1452 else if (gadget_is_otg(&udc->gadget)) {
1453 if (setup->bRequest ==
1454 USB_DEVICE_B_HNP_ENABLE)
1455 udc->gadget.b_hnp_enable = 1;
1456 else if (setup->bRequest ==
1457 USB_DEVICE_A_HNP_SUPPORT)
1458 udc->gadget.a_hnp_support = 1;
1459 else if (setup->bRequest ==
1460 USB_DEVICE_A_ALT_HNP_SUPPORT)
1461 udc->gadget.a_alt_hnp_support = 1;
1462 }
1463 rc = 0;
1464 } else
1465 break;
1466
1467 if (rc == 0) {
1468 if (ep0_prime_status(udc, EP_DIR_IN))
1469 ep0stall(udc);
1470 }
1471 if (ptc) {
1472 u32 tmp;
1473
1474 mdelay(10);
1475 tmp = fsl_readl(&dr_regs->portsc1) | (ptc << 16);
1476 fsl_writel(tmp, &dr_regs->portsc1);
1477 printk(KERN_INFO "udc: switch to test mode %d.\n", ptc);
1478 }
1479
1480 return;
1481 }
1482
1483 default:
1484 break;
1485 }
1486
1487 /* Requests handled by gadget */
1488 if (wLength) {
1489 /* Data phase from gadget, status phase from udc */
1490 udc->ep0_dir = (setup->bRequestType & USB_DIR_IN)
1491 ? USB_DIR_IN : USB_DIR_OUT;
1492 spin_unlock(&udc->lock);
1493 if (udc->driver->setup(&udc->gadget,
1494 &udc->local_setup_buff) < 0)
1495 ep0stall(udc);
1496 spin_lock(&udc->lock);
1497 udc->ep0_state = (setup->bRequestType & USB_DIR_IN)
1498 ? DATA_STATE_XMIT : DATA_STATE_RECV;
1499 /*
1500 * If the data stage is IN, send status prime immediately.
1501 * See 2.0 Spec chapter 8.5.3.3 for detail.
1502 */
1503 if (udc->ep0_state == DATA_STATE_XMIT)
1504 if (ep0_prime_status(udc, EP_DIR_OUT))
1505 ep0stall(udc);
1506
1507 } else {
1508 /* No data phase, IN status from gadget */
1509 udc->ep0_dir = USB_DIR_IN;
1510 spin_unlock(&udc->lock);
1511 if (udc->driver->setup(&udc->gadget,
1512 &udc->local_setup_buff) < 0)
1513 ep0stall(udc);
1514 spin_lock(&udc->lock);
1515 udc->ep0_state = WAIT_FOR_OUT_STATUS;
1516 }
1517 }
1518
1519 /* Process request for Data or Status phase of ep0
1520 * prime status phase if needed */
1521 static void ep0_req_complete(struct fsl_udc *udc, struct fsl_ep *ep0,
1522 struct fsl_req *req)
1523 {
1524 if (udc->usb_state == USB_STATE_ADDRESS) {
1525 /* Set the new address */
1526 u32 new_address = (u32) udc->device_address;
1527 fsl_writel(new_address << USB_DEVICE_ADDRESS_BIT_POS,
1528 &dr_regs->deviceaddr);
1529 }
1530
1531 done(ep0, req, 0);
1532
1533 switch (udc->ep0_state) {
1534 case DATA_STATE_XMIT:
1535 /* already primed at setup_received_irq */
1536 udc->ep0_state = WAIT_FOR_OUT_STATUS;
1537 break;
1538 case DATA_STATE_RECV:
1539 /* send status phase */
1540 if (ep0_prime_status(udc, EP_DIR_IN))
1541 ep0stall(udc);
1542 break;
1543 case WAIT_FOR_OUT_STATUS:
1544 udc->ep0_state = WAIT_FOR_SETUP;
1545 break;
1546 case WAIT_FOR_SETUP:
1547 ERR("Unexpected ep0 packets\n");
1548 break;
1549 default:
1550 ep0stall(udc);
1551 break;
1552 }
1553 }
1554
1555 /* Tripwire mechanism to ensure a setup packet payload is extracted without
1556 * being corrupted by another incoming setup packet */
1557 static void tripwire_handler(struct fsl_udc *udc, u8 ep_num, u8 *buffer_ptr)
1558 {
1559 u32 temp;
1560 struct ep_queue_head *qh;
1561 struct fsl_usb2_platform_data *pdata = udc->pdata;
1562
1563 qh = &udc->ep_qh[ep_num * 2 + EP_DIR_OUT];
1564
1565 /* Clear bit in ENDPTSETUPSTAT */
1566 temp = fsl_readl(&dr_regs->endptsetupstat);
1567 fsl_writel(temp | (1 << ep_num), &dr_regs->endptsetupstat);
1568
1569 /* while a hazard exists when setup package arrives */
1570 do {
1571 /* Set Setup Tripwire */
1572 temp = fsl_readl(&dr_regs->usbcmd);
1573 fsl_writel(temp | USB_CMD_SUTW, &dr_regs->usbcmd);
1574
1575 /* Copy the setup packet to local buffer */
1576 if (pdata->le_setup_buf) {
1577 u32 *p = (u32 *)buffer_ptr;
1578 u32 *s = (u32 *)qh->setup_buffer;
1579
1580 /* Convert little endian setup buffer to CPU endian */
1581 *p++ = le32_to_cpu(*s++);
1582 *p = le32_to_cpu(*s);
1583 } else {
1584 memcpy(buffer_ptr, (u8 *) qh->setup_buffer, 8);
1585 }
1586 } while (!(fsl_readl(&dr_regs->usbcmd) & USB_CMD_SUTW));
1587
1588 /* Clear Setup Tripwire */
1589 temp = fsl_readl(&dr_regs->usbcmd);
1590 fsl_writel(temp & ~USB_CMD_SUTW, &dr_regs->usbcmd);
1591 }
1592
1593 /* process-ep_req(): free the completed Tds for this req */
1594 static int process_ep_req(struct fsl_udc *udc, int pipe,
1595 struct fsl_req *curr_req)
1596 {
1597 struct ep_td_struct *curr_td;
1598 int td_complete, actual, remaining_length, j, tmp;
1599 int status = 0;
1600 int errors = 0;
1601 struct ep_queue_head *curr_qh = &udc->ep_qh[pipe];
1602 int direction = pipe % 2;
1603
1604 curr_td = curr_req->head;
1605 td_complete = 0;
1606 actual = curr_req->req.length;
1607
1608 for (j = 0; j < curr_req->dtd_count; j++) {
1609 remaining_length = (hc32_to_cpu(curr_td->size_ioc_sts)
1610 & DTD_PACKET_SIZE)
1611 >> DTD_LENGTH_BIT_POS;
1612 actual -= remaining_length;
1613
1614 errors = hc32_to_cpu(curr_td->size_ioc_sts);
1615 if (errors & DTD_ERROR_MASK) {
1616 if (errors & DTD_STATUS_HALTED) {
1617 ERR("dTD error %08x QH=%d\n", errors, pipe);
1618 /* Clear the errors and Halt condition */
1619 tmp = hc32_to_cpu(curr_qh->size_ioc_int_sts);
1620 tmp &= ~errors;
1621 curr_qh->size_ioc_int_sts = cpu_to_hc32(tmp);
1622 status = -EPIPE;
1623 /* FIXME: continue with next queued TD? */
1624
1625 break;
1626 }
1627 if (errors & DTD_STATUS_DATA_BUFF_ERR) {
1628 VDBG("Transfer overflow");
1629 status = -EPROTO;
1630 break;
1631 } else if (errors & DTD_STATUS_TRANSACTION_ERR) {
1632 VDBG("ISO error");
1633 status = -EILSEQ;
1634 break;
1635 } else
1636 ERR("Unknown error has occurred (0x%x)!\n",
1637 errors);
1638
1639 } else if (hc32_to_cpu(curr_td->size_ioc_sts)
1640 & DTD_STATUS_ACTIVE) {
1641 VDBG("Request not complete");
1642 status = REQ_UNCOMPLETE;
1643 return status;
1644 } else if (remaining_length) {
1645 if (direction) {
1646 VDBG("Transmit dTD remaining length not zero");
1647 status = -EPROTO;
1648 break;
1649 } else {
1650 td_complete++;
1651 break;
1652 }
1653 } else {
1654 td_complete++;
1655 VDBG("dTD transmitted successful");
1656 }
1657
1658 if (j != curr_req->dtd_count - 1)
1659 curr_td = (struct ep_td_struct *)curr_td->next_td_virt;
1660 }
1661
1662 if (status)
1663 return status;
1664
1665 curr_req->req.actual = actual;
1666
1667 return 0;
1668 }
1669
1670 /* Process a DTD completion interrupt */
1671 static void dtd_complete_irq(struct fsl_udc *udc)
1672 {
1673 u32 bit_pos;
1674 int i, ep_num, direction, bit_mask, status;
1675 struct fsl_ep *curr_ep;
1676 struct fsl_req *curr_req, *temp_req;
1677
1678 /* Clear the bits in the register */
1679 bit_pos = fsl_readl(&dr_regs->endptcomplete);
1680 fsl_writel(bit_pos, &dr_regs->endptcomplete);
1681
1682 if (!bit_pos)
1683 return;
1684
1685 for (i = 0; i < udc->max_ep; i++) {
1686 ep_num = i >> 1;
1687 direction = i % 2;
1688
1689 bit_mask = 1 << (ep_num + 16 * direction);
1690
1691 if (!(bit_pos & bit_mask))
1692 continue;
1693
1694 curr_ep = get_ep_by_pipe(udc, i);
1695
1696 /* If the ep is configured */
1697 if (!curr_ep->ep.name) {
1698 WARNING("Invalid EP?");
1699 continue;
1700 }
1701
1702 /* process the req queue until an uncomplete request */
1703 list_for_each_entry_safe(curr_req, temp_req, &curr_ep->queue,
1704 queue) {
1705 status = process_ep_req(udc, i, curr_req);
1706
1707 VDBG("status of process_ep_req= %d, ep = %d",
1708 status, ep_num);
1709 if (status == REQ_UNCOMPLETE)
1710 break;
1711 /* write back status to req */
1712 curr_req->req.status = status;
1713
1714 if (ep_num == 0) {
1715 ep0_req_complete(udc, curr_ep, curr_req);
1716 break;
1717 } else
1718 done(curr_ep, curr_req, status);
1719 }
1720 }
1721 }
1722
1723 static inline enum usb_device_speed portscx_device_speed(u32 reg)
1724 {
1725 switch (reg & PORTSCX_PORT_SPEED_MASK) {
1726 case PORTSCX_PORT_SPEED_HIGH:
1727 return USB_SPEED_HIGH;
1728 case PORTSCX_PORT_SPEED_FULL:
1729 return USB_SPEED_FULL;
1730 case PORTSCX_PORT_SPEED_LOW:
1731 return USB_SPEED_LOW;
1732 default:
1733 return USB_SPEED_UNKNOWN;
1734 }
1735 }
1736
1737 /* Process a port change interrupt */
1738 static void port_change_irq(struct fsl_udc *udc)
1739 {
1740 if (udc->bus_reset)
1741 udc->bus_reset = 0;
1742
1743 /* Bus resetting is finished */
1744 if (!(fsl_readl(&dr_regs->portsc1) & PORTSCX_PORT_RESET))
1745 /* Get the speed */
1746 udc->gadget.speed =
1747 portscx_device_speed(fsl_readl(&dr_regs->portsc1));
1748
1749 /* Update USB state */
1750 if (!udc->resume_state)
1751 udc->usb_state = USB_STATE_DEFAULT;
1752 }
1753
1754 /* Process suspend interrupt */
1755 static void suspend_irq(struct fsl_udc *udc)
1756 {
1757 udc->resume_state = udc->usb_state;
1758 udc->usb_state = USB_STATE_SUSPENDED;
1759
1760 /* report suspend to the driver, serial.c does not support this */
1761 if (udc->driver->suspend)
1762 udc->driver->suspend(&udc->gadget);
1763 }
1764
1765 static void bus_resume(struct fsl_udc *udc)
1766 {
1767 udc->usb_state = udc->resume_state;
1768 udc->resume_state = 0;
1769
1770 /* report resume to the driver, serial.c does not support this */
1771 if (udc->driver->resume)
1772 udc->driver->resume(&udc->gadget);
1773 }
1774
1775 /* Clear up all ep queues */
1776 static int reset_queues(struct fsl_udc *udc, bool bus_reset)
1777 {
1778 u8 pipe;
1779
1780 for (pipe = 0; pipe < udc->max_pipes; pipe++)
1781 udc_reset_ep_queue(udc, pipe);
1782
1783 /* report disconnect; the driver is already quiesced */
1784 spin_unlock(&udc->lock);
1785 if (bus_reset)
1786 usb_gadget_udc_reset(&udc->gadget, udc->driver);
1787 else
1788 udc->driver->disconnect(&udc->gadget);
1789 spin_lock(&udc->lock);
1790
1791 return 0;
1792 }
1793
1794 /* Process reset interrupt */
1795 static void reset_irq(struct fsl_udc *udc)
1796 {
1797 u32 temp;
1798 unsigned long timeout;
1799
1800 /* Clear the device address */
1801 temp = fsl_readl(&dr_regs->deviceaddr);
1802 fsl_writel(temp & ~USB_DEVICE_ADDRESS_MASK, &dr_regs->deviceaddr);
1803
1804 udc->device_address = 0;
1805
1806 /* Clear usb state */
1807 udc->resume_state = 0;
1808 udc->ep0_dir = 0;
1809 udc->ep0_state = WAIT_FOR_SETUP;
1810 udc->remote_wakeup = 0; /* default to 0 on reset */
1811 udc->gadget.b_hnp_enable = 0;
1812 udc->gadget.a_hnp_support = 0;
1813 udc->gadget.a_alt_hnp_support = 0;
1814
1815 /* Clear all the setup token semaphores */
1816 temp = fsl_readl(&dr_regs->endptsetupstat);
1817 fsl_writel(temp, &dr_regs->endptsetupstat);
1818
1819 /* Clear all the endpoint complete status bits */
1820 temp = fsl_readl(&dr_regs->endptcomplete);
1821 fsl_writel(temp, &dr_regs->endptcomplete);
1822
1823 timeout = jiffies + 100;
1824 while (fsl_readl(&dr_regs->endpointprime)) {
1825 /* Wait until all endptprime bits cleared */
1826 if (time_after(jiffies, timeout)) {
1827 ERR("Timeout for reset\n");
1828 break;
1829 }
1830 cpu_relax();
1831 }
1832
1833 /* Write 1s to the flush register */
1834 fsl_writel(0xffffffff, &dr_regs->endptflush);
1835
1836 if (fsl_readl(&dr_regs->portsc1) & PORTSCX_PORT_RESET) {
1837 VDBG("Bus reset");
1838 /* Bus is reseting */
1839 udc->bus_reset = 1;
1840 /* Reset all the queues, include XD, dTD, EP queue
1841 * head and TR Queue */
1842 reset_queues(udc, true);
1843 udc->usb_state = USB_STATE_DEFAULT;
1844 } else {
1845 VDBG("Controller reset");
1846 /* initialize usb hw reg except for regs for EP, not
1847 * touch usbintr reg */
1848 dr_controller_setup(udc);
1849
1850 /* Reset all internal used Queues */
1851 reset_queues(udc, false);
1852
1853 ep0_setup(udc);
1854
1855 /* Enable DR IRQ reg, Set Run bit, change udc state */
1856 dr_controller_run(udc);
1857 udc->usb_state = USB_STATE_ATTACHED;
1858 }
1859 }
1860
1861 /*
1862 * USB device controller interrupt handler
1863 */
1864 static irqreturn_t fsl_udc_irq(int irq, void *_udc)
1865 {
1866 struct fsl_udc *udc = _udc;
1867 u32 irq_src;
1868 irqreturn_t status = IRQ_NONE;
1869 unsigned long flags;
1870
1871 /* Disable ISR for OTG host mode */
1872 if (udc->stopped)
1873 return IRQ_NONE;
1874 spin_lock_irqsave(&udc->lock, flags);
1875 irq_src = fsl_readl(&dr_regs->usbsts) & fsl_readl(&dr_regs->usbintr);
1876 /* Clear notification bits */
1877 fsl_writel(irq_src, &dr_regs->usbsts);
1878
1879 /* VDBG("irq_src [0x%8x]", irq_src); */
1880
1881 /* Need to resume? */
1882 if (udc->usb_state == USB_STATE_SUSPENDED)
1883 if ((fsl_readl(&dr_regs->portsc1) & PORTSCX_PORT_SUSPEND) == 0)
1884 bus_resume(udc);
1885
1886 /* USB Interrupt */
1887 if (irq_src & USB_STS_INT) {
1888 VDBG("Packet int");
1889 /* Setup package, we only support ep0 as control ep */
1890 if (fsl_readl(&dr_regs->endptsetupstat) & EP_SETUP_STATUS_EP0) {
1891 tripwire_handler(udc, 0,
1892 (u8 *) (&udc->local_setup_buff));
1893 setup_received_irq(udc, &udc->local_setup_buff);
1894 status = IRQ_HANDLED;
1895 }
1896
1897 /* completion of dtd */
1898 if (fsl_readl(&dr_regs->endptcomplete)) {
1899 dtd_complete_irq(udc);
1900 status = IRQ_HANDLED;
1901 }
1902 }
1903
1904 /* SOF (for ISO transfer) */
1905 if (irq_src & USB_STS_SOF) {
1906 status = IRQ_HANDLED;
1907 }
1908
1909 /* Port Change */
1910 if (irq_src & USB_STS_PORT_CHANGE) {
1911 port_change_irq(udc);
1912 status = IRQ_HANDLED;
1913 }
1914
1915 /* Reset Received */
1916 if (irq_src & USB_STS_RESET) {
1917 VDBG("reset int");
1918 reset_irq(udc);
1919 status = IRQ_HANDLED;
1920 }
1921
1922 /* Sleep Enable (Suspend) */
1923 if (irq_src & USB_STS_SUSPEND) {
1924 suspend_irq(udc);
1925 status = IRQ_HANDLED;
1926 }
1927
1928 if (irq_src & (USB_STS_ERR | USB_STS_SYS_ERR)) {
1929 VDBG("Error IRQ %x", irq_src);
1930 }
1931
1932 spin_unlock_irqrestore(&udc->lock, flags);
1933 return status;
1934 }
1935
1936 /*----------------------------------------------------------------*
1937 * Hook to gadget drivers
1938 * Called by initialization code of gadget drivers
1939 *----------------------------------------------------------------*/
1940 static int fsl_udc_start(struct usb_gadget *g,
1941 struct usb_gadget_driver *driver)
1942 {
1943 int retval = 0;
1944 unsigned long flags = 0;
1945
1946 /* lock is needed but whether should use this lock or another */
1947 spin_lock_irqsave(&udc_controller->lock, flags);
1948
1949 driver->driver.bus = NULL;
1950 /* hook up the driver */
1951 udc_controller->driver = driver;
1952 spin_unlock_irqrestore(&udc_controller->lock, flags);
1953 g->is_selfpowered = 1;
1954
1955 if (!IS_ERR_OR_NULL(udc_controller->transceiver)) {
1956 /* Suspend the controller until OTG enable it */
1957 udc_controller->stopped = 1;
1958 printk(KERN_INFO "Suspend udc for OTG auto detect\n");
1959
1960 /* connect to bus through transceiver */
1961 if (!IS_ERR_OR_NULL(udc_controller->transceiver)) {
1962 retval = otg_set_peripheral(
1963 udc_controller->transceiver->otg,
1964 &udc_controller->gadget);
1965 if (retval < 0) {
1966 ERR("can't bind to transceiver\n");
1967 udc_controller->driver = NULL;
1968 return retval;
1969 }
1970 }
1971 } else {
1972 /* Enable DR IRQ reg and set USBCMD reg Run bit */
1973 dr_controller_run(udc_controller);
1974 udc_controller->usb_state = USB_STATE_ATTACHED;
1975 udc_controller->ep0_state = WAIT_FOR_SETUP;
1976 udc_controller->ep0_dir = 0;
1977 }
1978
1979 return retval;
1980 }
1981
1982 /* Disconnect from gadget driver */
1983 static int fsl_udc_stop(struct usb_gadget *g)
1984 {
1985 struct fsl_ep *loop_ep;
1986 unsigned long flags;
1987
1988 if (!IS_ERR_OR_NULL(udc_controller->transceiver))
1989 otg_set_peripheral(udc_controller->transceiver->otg, NULL);
1990
1991 /* stop DR, disable intr */
1992 dr_controller_stop(udc_controller);
1993
1994 /* in fact, no needed */
1995 udc_controller->usb_state = USB_STATE_ATTACHED;
1996 udc_controller->ep0_state = WAIT_FOR_SETUP;
1997 udc_controller->ep0_dir = 0;
1998
1999 /* stand operation */
2000 spin_lock_irqsave(&udc_controller->lock, flags);
2001 udc_controller->gadget.speed = USB_SPEED_UNKNOWN;
2002 nuke(&udc_controller->eps[0], -ESHUTDOWN);
2003 list_for_each_entry(loop_ep, &udc_controller->gadget.ep_list,
2004 ep.ep_list)
2005 nuke(loop_ep, -ESHUTDOWN);
2006 spin_unlock_irqrestore(&udc_controller->lock, flags);
2007
2008 udc_controller->driver = NULL;
2009
2010 return 0;
2011 }
2012
2013 /*-------------------------------------------------------------------------
2014 PROC File System Support
2015 -------------------------------------------------------------------------*/
2016 #ifdef CONFIG_USB_GADGET_DEBUG_FILES
2017
2018 #include <linux/seq_file.h>
2019
2020 static const char proc_filename[] = "driver/fsl_usb2_udc";
2021
2022 static int fsl_proc_read(struct seq_file *m, void *v)
2023 {
2024 unsigned long flags;
2025 int i;
2026 u32 tmp_reg;
2027 struct fsl_ep *ep = NULL;
2028 struct fsl_req *req;
2029
2030 struct fsl_udc *udc = udc_controller;
2031
2032 spin_lock_irqsave(&udc->lock, flags);
2033
2034 /* ------basic driver information ---- */
2035 seq_printf(m,
2036 DRIVER_DESC "\n"
2037 "%s version: %s\n"
2038 "Gadget driver: %s\n\n",
2039 driver_name, DRIVER_VERSION,
2040 udc->driver ? udc->driver->driver.name : "(none)");
2041
2042 /* ------ DR Registers ----- */
2043 tmp_reg = fsl_readl(&dr_regs->usbcmd);
2044 seq_printf(m,
2045 "USBCMD reg:\n"
2046 "SetupTW: %d\n"
2047 "Run/Stop: %s\n\n",
2048 (tmp_reg & USB_CMD_SUTW) ? 1 : 0,
2049 (tmp_reg & USB_CMD_RUN_STOP) ? "Run" : "Stop");
2050
2051 tmp_reg = fsl_readl(&dr_regs->usbsts);
2052 seq_printf(m,
2053 "USB Status Reg:\n"
2054 "Dr Suspend: %d Reset Received: %d System Error: %s "
2055 "USB Error Interrupt: %s\n\n",
2056 (tmp_reg & USB_STS_SUSPEND) ? 1 : 0,
2057 (tmp_reg & USB_STS_RESET) ? 1 : 0,
2058 (tmp_reg & USB_STS_SYS_ERR) ? "Err" : "Normal",
2059 (tmp_reg & USB_STS_ERR) ? "Err detected" : "No err");
2060
2061 tmp_reg = fsl_readl(&dr_regs->usbintr);
2062 seq_printf(m,
2063 "USB Interrupt Enable Reg:\n"
2064 "Sleep Enable: %d SOF Received Enable: %d "
2065 "Reset Enable: %d\n"
2066 "System Error Enable: %d "
2067 "Port Change Dectected Enable: %d\n"
2068 "USB Error Intr Enable: %d USB Intr Enable: %d\n\n",
2069 (tmp_reg & USB_INTR_DEVICE_SUSPEND) ? 1 : 0,
2070 (tmp_reg & USB_INTR_SOF_EN) ? 1 : 0,
2071 (tmp_reg & USB_INTR_RESET_EN) ? 1 : 0,
2072 (tmp_reg & USB_INTR_SYS_ERR_EN) ? 1 : 0,
2073 (tmp_reg & USB_INTR_PTC_DETECT_EN) ? 1 : 0,
2074 (tmp_reg & USB_INTR_ERR_INT_EN) ? 1 : 0,
2075 (tmp_reg & USB_INTR_INT_EN) ? 1 : 0);
2076
2077 tmp_reg = fsl_readl(&dr_regs->frindex);
2078 seq_printf(m,
2079 "USB Frame Index Reg: Frame Number is 0x%x\n\n",
2080 (tmp_reg & USB_FRINDEX_MASKS));
2081
2082 tmp_reg = fsl_readl(&dr_regs->deviceaddr);
2083 seq_printf(m,
2084 "USB Device Address Reg: Device Addr is 0x%x\n\n",
2085 (tmp_reg & USB_DEVICE_ADDRESS_MASK));
2086
2087 tmp_reg = fsl_readl(&dr_regs->endpointlistaddr);
2088 seq_printf(m,
2089 "USB Endpoint List Address Reg: "
2090 "Device Addr is 0x%x\n\n",
2091 (tmp_reg & USB_EP_LIST_ADDRESS_MASK));
2092
2093 tmp_reg = fsl_readl(&dr_regs->portsc1);
2094 seq_printf(m,
2095 "USB Port Status&Control Reg:\n"
2096 "Port Transceiver Type : %s Port Speed: %s\n"
2097 "PHY Low Power Suspend: %s Port Reset: %s "
2098 "Port Suspend Mode: %s\n"
2099 "Over-current Change: %s "
2100 "Port Enable/Disable Change: %s\n"
2101 "Port Enabled/Disabled: %s "
2102 "Current Connect Status: %s\n\n", ( {
2103 const char *s;
2104 switch (tmp_reg & PORTSCX_PTS_FSLS) {
2105 case PORTSCX_PTS_UTMI:
2106 s = "UTMI"; break;
2107 case PORTSCX_PTS_ULPI:
2108 s = "ULPI "; break;
2109 case PORTSCX_PTS_FSLS:
2110 s = "FS/LS Serial"; break;
2111 default:
2112 s = "None"; break;
2113 }
2114 s;} ),
2115 usb_speed_string(portscx_device_speed(tmp_reg)),
2116 (tmp_reg & PORTSCX_PHY_LOW_POWER_SPD) ?
2117 "Normal PHY mode" : "Low power mode",
2118 (tmp_reg & PORTSCX_PORT_RESET) ? "In Reset" :
2119 "Not in Reset",
2120 (tmp_reg & PORTSCX_PORT_SUSPEND) ? "In " : "Not in",
2121 (tmp_reg & PORTSCX_OVER_CURRENT_CHG) ? "Dected" :
2122 "No",
2123 (tmp_reg & PORTSCX_PORT_EN_DIS_CHANGE) ? "Disable" :
2124 "Not change",
2125 (tmp_reg & PORTSCX_PORT_ENABLE) ? "Enable" :
2126 "Not correct",
2127 (tmp_reg & PORTSCX_CURRENT_CONNECT_STATUS) ?
2128 "Attached" : "Not-Att");
2129
2130 tmp_reg = fsl_readl(&dr_regs->usbmode);
2131 seq_printf(m,
2132 "USB Mode Reg: Controller Mode is: %s\n\n", ( {
2133 const char *s;
2134 switch (tmp_reg & USB_MODE_CTRL_MODE_HOST) {
2135 case USB_MODE_CTRL_MODE_IDLE:
2136 s = "Idle"; break;
2137 case USB_MODE_CTRL_MODE_DEVICE:
2138 s = "Device Controller"; break;
2139 case USB_MODE_CTRL_MODE_HOST:
2140 s = "Host Controller"; break;
2141 default:
2142 s = "None"; break;
2143 }
2144 s;
2145 } ));
2146
2147 tmp_reg = fsl_readl(&dr_regs->endptsetupstat);
2148 seq_printf(m,
2149 "Endpoint Setup Status Reg: SETUP on ep 0x%x\n\n",
2150 (tmp_reg & EP_SETUP_STATUS_MASK));
2151
2152 for (i = 0; i < udc->max_ep / 2; i++) {
2153 tmp_reg = fsl_readl(&dr_regs->endptctrl[i]);
2154 seq_printf(m, "EP Ctrl Reg [0x%x]: = [0x%x]\n", i, tmp_reg);
2155 }
2156 tmp_reg = fsl_readl(&dr_regs->endpointprime);
2157 seq_printf(m, "EP Prime Reg = [0x%x]\n\n", tmp_reg);
2158
2159 #ifndef CONFIG_ARCH_MXC
2160 if (udc->pdata->have_sysif_regs) {
2161 tmp_reg = usb_sys_regs->snoop1;
2162 seq_printf(m, "Snoop1 Reg : = [0x%x]\n\n", tmp_reg);
2163
2164 tmp_reg = usb_sys_regs->control;
2165 seq_printf(m, "General Control Reg : = [0x%x]\n\n", tmp_reg);
2166 }
2167 #endif
2168
2169 /* ------fsl_udc, fsl_ep, fsl_request structure information ----- */
2170 ep = &udc->eps[0];
2171 seq_printf(m, "For %s Maxpkt is 0x%x index is 0x%x\n",
2172 ep->ep.name, ep_maxpacket(ep), ep_index(ep));
2173
2174 if (list_empty(&ep->queue)) {
2175 seq_puts(m, "its req queue is empty\n\n");
2176 } else {
2177 list_for_each_entry(req, &ep->queue, queue) {
2178 seq_printf(m,
2179 "req %p actual 0x%x length 0x%x buf %p\n",
2180 &req->req, req->req.actual,
2181 req->req.length, req->req.buf);
2182 }
2183 }
2184 /* other gadget->eplist ep */
2185 list_for_each_entry(ep, &udc->gadget.ep_list, ep.ep_list) {
2186 if (ep->ep.desc) {
2187 seq_printf(m,
2188 "\nFor %s Maxpkt is 0x%x "
2189 "index is 0x%x\n",
2190 ep->ep.name, ep_maxpacket(ep),
2191 ep_index(ep));
2192
2193 if (list_empty(&ep->queue)) {
2194 seq_puts(m, "its req queue is empty\n\n");
2195 } else {
2196 list_for_each_entry(req, &ep->queue, queue) {
2197 seq_printf(m,
2198 "req %p actual 0x%x length "
2199 "0x%x buf %p\n",
2200 &req->req, req->req.actual,
2201 req->req.length, req->req.buf);
2202 } /* end for each_entry of ep req */
2203 } /* end for else */
2204 } /* end for if(ep->queue) */
2205 } /* end (ep->desc) */
2206
2207 spin_unlock_irqrestore(&udc->lock, flags);
2208 return 0;
2209 }
2210
2211 #define create_proc_file() \
2212 proc_create_single(proc_filename, 0, NULL, fsl_proc_read)
2213 #define remove_proc_file() remove_proc_entry(proc_filename, NULL)
2214
2215 #else /* !CONFIG_USB_GADGET_DEBUG_FILES */
2216
2217 #define create_proc_file() do {} while (0)
2218 #define remove_proc_file() do {} while (0)
2219
2220 #endif /* CONFIG_USB_GADGET_DEBUG_FILES */
2221
2222 /*-------------------------------------------------------------------------*/
2223
2224 /* Release udc structures */
2225 static void fsl_udc_release(struct device *dev)
2226 {
2227 complete(udc_controller->done);
2228 dma_free_coherent(dev->parent, udc_controller->ep_qh_size,
2229 udc_controller->ep_qh, udc_controller->ep_qh_dma);
2230 kfree(udc_controller);
2231 }
2232
2233 /******************************************************************
2234 Internal structure setup functions
2235 *******************************************************************/
2236 /*------------------------------------------------------------------
2237 * init resource for global controller called by fsl_udc_probe()
2238 * On success the udc handle is initialized, on failure it is
2239 * unchanged (reset).
2240 * Return 0 on success and -1 on allocation failure
2241 ------------------------------------------------------------------*/
2242 static int struct_udc_setup(struct fsl_udc *udc,
2243 struct platform_device *pdev)
2244 {
2245 struct fsl_usb2_platform_data *pdata;
2246 size_t size;
2247
2248 pdata = dev_get_platdata(&pdev->dev);
2249 udc->phy_mode = pdata->phy_mode;
2250
2251 udc->eps = kcalloc(udc->max_ep, sizeof(struct fsl_ep), GFP_KERNEL);
2252 if (!udc->eps) {
2253 ERR("kmalloc udc endpoint status failed\n");
2254 goto eps_alloc_failed;
2255 }
2256
2257 /* initialized QHs, take care of alignment */
2258 size = udc->max_ep * sizeof(struct ep_queue_head);
2259 if (size < QH_ALIGNMENT)
2260 size = QH_ALIGNMENT;
2261 else if ((size % QH_ALIGNMENT) != 0) {
2262 size += QH_ALIGNMENT + 1;
2263 size &= ~(QH_ALIGNMENT - 1);
2264 }
2265 udc->ep_qh = dma_alloc_coherent(&pdev->dev, size,
2266 &udc->ep_qh_dma, GFP_KERNEL);
2267 if (!udc->ep_qh) {
2268 ERR("malloc QHs for udc failed\n");
2269 goto ep_queue_alloc_failed;
2270 }
2271
2272 udc->ep_qh_size = size;
2273
2274 /* Initialize ep0 status request structure */
2275 /* FIXME: fsl_alloc_request() ignores ep argument */
2276 udc->status_req = container_of(fsl_alloc_request(NULL, GFP_KERNEL),
2277 struct fsl_req, req);
2278 if (!udc->status_req) {
2279 ERR("kzalloc for udc status request failed\n");
2280 goto udc_status_alloc_failed;
2281 }
2282
2283 /* allocate a small amount of memory to get valid address */
2284 udc->status_req->req.buf = kmalloc(8, GFP_KERNEL);
2285 if (!udc->status_req->req.buf) {
2286 ERR("kzalloc for udc request buffer failed\n");
2287 goto udc_req_buf_alloc_failed;
2288 }
2289
2290 udc->resume_state = USB_STATE_NOTATTACHED;
2291 udc->usb_state = USB_STATE_POWERED;
2292 udc->ep0_dir = 0;
2293 udc->remote_wakeup = 0; /* default to 0 on reset */
2294
2295 return 0;
2296
2297 udc_req_buf_alloc_failed:
2298 kfree(udc->status_req);
2299 udc_status_alloc_failed:
2300 kfree(udc->ep_qh);
2301 udc->ep_qh_size = 0;
2302 ep_queue_alloc_failed:
2303 kfree(udc->eps);
2304 eps_alloc_failed:
2305 udc->phy_mode = 0;
2306 return -1;
2307
2308 }
2309
2310 /*----------------------------------------------------------------
2311 * Setup the fsl_ep struct for eps
2312 * Link fsl_ep->ep to gadget->ep_list
2313 * ep0out is not used so do nothing here
2314 * ep0in should be taken care
2315 *--------------------------------------------------------------*/
2316 static int struct_ep_setup(struct fsl_udc *udc, unsigned char index,
2317 char *name, int link)
2318 {
2319 struct fsl_ep *ep = &udc->eps[index];
2320
2321 ep->udc = udc;
2322 strcpy(ep->name, name);
2323 ep->ep.name = ep->name;
2324
2325 ep->ep.ops = &fsl_ep_ops;
2326 ep->stopped = 0;
2327
2328 if (index == 0) {
2329 ep->ep.caps.type_control = true;
2330 } else {
2331 ep->ep.caps.type_iso = true;
2332 ep->ep.caps.type_bulk = true;
2333 ep->ep.caps.type_int = true;
2334 }
2335
2336 if (index & 1)
2337 ep->ep.caps.dir_in = true;
2338 else
2339 ep->ep.caps.dir_out = true;
2340
2341 /* for ep0: maxP defined in desc
2342 * for other eps, maxP is set by epautoconfig() called by gadget layer
2343 */
2344 usb_ep_set_maxpacket_limit(&ep->ep, (unsigned short) ~0);
2345
2346 /* the queue lists any req for this ep */
2347 INIT_LIST_HEAD(&ep->queue);
2348
2349 /* gagdet.ep_list used for ep_autoconfig so no ep0 */
2350 if (link)
2351 list_add_tail(&ep->ep.ep_list, &udc->gadget.ep_list);
2352 ep->gadget = &udc->gadget;
2353 ep->qh = &udc->ep_qh[index];
2354
2355 return 0;
2356 }
2357
2358 /* Driver probe function
2359 * all initialization operations implemented here except enabling usb_intr reg
2360 * board setup should have been done in the platform code
2361 */
2362 static int fsl_udc_probe(struct platform_device *pdev)
2363 {
2364 struct fsl_usb2_platform_data *pdata;
2365 struct resource *res;
2366 int ret = -ENODEV;
2367 unsigned int i;
2368 u32 dccparams;
2369
2370 udc_controller = kzalloc(sizeof(struct fsl_udc), GFP_KERNEL);
2371 if (udc_controller == NULL)
2372 return -ENOMEM;
2373
2374 pdata = dev_get_platdata(&pdev->dev);
2375 udc_controller->pdata = pdata;
2376 spin_lock_init(&udc_controller->lock);
2377 udc_controller->stopped = 1;
2378
2379 #ifdef CONFIG_USB_OTG
2380 if (pdata->operating_mode == FSL_USB2_DR_OTG) {
2381 udc_controller->transceiver = usb_get_phy(USB_PHY_TYPE_USB2);
2382 if (IS_ERR_OR_NULL(udc_controller->transceiver)) {
2383 ERR("Can't find OTG driver!\n");
2384 ret = -ENODEV;
2385 goto err_kfree;
2386 }
2387 }
2388 #endif
2389
2390 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2391 if (!res) {
2392 ret = -ENXIO;
2393 goto err_kfree;
2394 }
2395
2396 if (pdata->operating_mode == FSL_USB2_DR_DEVICE) {
2397 if (!request_mem_region(res->start, resource_size(res),
2398 driver_name)) {
2399 ERR("request mem region for %s failed\n", pdev->name);
2400 ret = -EBUSY;
2401 goto err_kfree;
2402 }
2403 }
2404
2405 dr_regs = ioremap(res->start, resource_size(res));
2406 if (!dr_regs) {
2407 ret = -ENOMEM;
2408 goto err_release_mem_region;
2409 }
2410
2411 pdata->regs = (void __iomem *)dr_regs;
2412
2413 /*
2414 * do platform specific init: check the clock, grab/config pins, etc.
2415 */
2416 if (pdata->init && pdata->init(pdev)) {
2417 ret = -ENODEV;
2418 goto err_iounmap_noclk;
2419 }
2420
2421 /* Set accessors only after pdata->init() ! */
2422 fsl_set_accessors(pdata);
2423
2424 #ifndef CONFIG_ARCH_MXC
2425 if (pdata->have_sysif_regs)
2426 usb_sys_regs = (void *)dr_regs + USB_DR_SYS_OFFSET;
2427 #endif
2428
2429 /* Initialize USB clocks */
2430 ret = fsl_udc_clk_init(pdev);
2431 if (ret < 0)
2432 goto err_iounmap_noclk;
2433
2434 /* Read Device Controller Capability Parameters register */
2435 dccparams = fsl_readl(&dr_regs->dccparams);
2436 if (!(dccparams & DCCPARAMS_DC)) {
2437 ERR("This SOC doesn't support device role\n");
2438 ret = -ENODEV;
2439 goto err_iounmap;
2440 }
2441 /* Get max device endpoints */
2442 /* DEN is bidirectional ep number, max_ep doubles the number */
2443 udc_controller->max_ep = (dccparams & DCCPARAMS_DEN_MASK) * 2;
2444
2445 udc_controller->irq = platform_get_irq(pdev, 0);
2446 if (!udc_controller->irq) {
2447 ret = -ENODEV;
2448 goto err_iounmap;
2449 }
2450
2451 ret = request_irq(udc_controller->irq, fsl_udc_irq, IRQF_SHARED,
2452 driver_name, udc_controller);
2453 if (ret != 0) {
2454 ERR("cannot request irq %d err %d\n",
2455 udc_controller->irq, ret);
2456 goto err_iounmap;
2457 }
2458
2459 /* Initialize the udc structure including QH member and other member */
2460 if (struct_udc_setup(udc_controller, pdev)) {
2461 ERR("Can't initialize udc data structure\n");
2462 ret = -ENOMEM;
2463 goto err_free_irq;
2464 }
2465
2466 if (IS_ERR_OR_NULL(udc_controller->transceiver)) {
2467 /* initialize usb hw reg except for regs for EP,
2468 * leave usbintr reg untouched */
2469 dr_controller_setup(udc_controller);
2470 }
2471
2472 ret = fsl_udc_clk_finalize(pdev);
2473 if (ret)
2474 goto err_free_irq;
2475
2476 /* Setup gadget structure */
2477 udc_controller->gadget.ops = &fsl_gadget_ops;
2478 udc_controller->gadget.max_speed = USB_SPEED_HIGH;
2479 udc_controller->gadget.ep0 = &udc_controller->eps[0].ep;
2480 INIT_LIST_HEAD(&udc_controller->gadget.ep_list);
2481 udc_controller->gadget.speed = USB_SPEED_UNKNOWN;
2482 udc_controller->gadget.name = driver_name;
2483
2484 /* Setup gadget.dev and register with kernel */
2485 dev_set_name(&udc_controller->gadget.dev, "gadget");
2486 udc_controller->gadget.dev.of_node = pdev->dev.of_node;
2487
2488 if (!IS_ERR_OR_NULL(udc_controller->transceiver))
2489 udc_controller->gadget.is_otg = 1;
2490
2491 /* setup QH and epctrl for ep0 */
2492 ep0_setup(udc_controller);
2493
2494 /* setup udc->eps[] for ep0 */
2495 struct_ep_setup(udc_controller, 0, "ep0", 0);
2496 /* for ep0: the desc defined here;
2497 * for other eps, gadget layer called ep_enable with defined desc
2498 */
2499 udc_controller->eps[0].ep.desc = &fsl_ep0_desc;
2500 usb_ep_set_maxpacket_limit(&udc_controller->eps[0].ep,
2501 USB_MAX_CTRL_PAYLOAD);
2502
2503 /* setup the udc->eps[] for non-control endpoints and link
2504 * to gadget.ep_list */
2505 for (i = 1; i < (int)(udc_controller->max_ep / 2); i++) {
2506 char name[14];
2507
2508 sprintf(name, "ep%dout", i);
2509 struct_ep_setup(udc_controller, i * 2, name, 1);
2510 sprintf(name, "ep%din", i);
2511 struct_ep_setup(udc_controller, i * 2 + 1, name, 1);
2512 }
2513
2514 /* use dma_pool for TD management */
2515 udc_controller->td_pool = dma_pool_create("udc_td", &pdev->dev,
2516 sizeof(struct ep_td_struct),
2517 DTD_ALIGNMENT, UDC_DMA_BOUNDARY);
2518 if (udc_controller->td_pool == NULL) {
2519 ret = -ENOMEM;
2520 goto err_free_irq;
2521 }
2522
2523 ret = usb_add_gadget_udc_release(&pdev->dev, &udc_controller->gadget,
2524 fsl_udc_release);
2525 if (ret)
2526 goto err_del_udc;
2527
2528 create_proc_file();
2529 return 0;
2530
2531 err_del_udc:
2532 dma_pool_destroy(udc_controller->td_pool);
2533 err_free_irq:
2534 free_irq(udc_controller->irq, udc_controller);
2535 err_iounmap:
2536 if (pdata->exit)
2537 pdata->exit(pdev);
2538 fsl_udc_clk_release();
2539 err_iounmap_noclk:
2540 iounmap(dr_regs);
2541 err_release_mem_region:
2542 if (pdata->operating_mode == FSL_USB2_DR_DEVICE)
2543 release_mem_region(res->start, resource_size(res));
2544 err_kfree:
2545 kfree(udc_controller);
2546 udc_controller = NULL;
2547 return ret;
2548 }
2549
2550 /* Driver removal function
2551 * Free resources and finish pending transactions
2552 */
2553 static int fsl_udc_remove(struct platform_device *pdev)
2554 {
2555 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2556 struct fsl_usb2_platform_data *pdata = dev_get_platdata(&pdev->dev);
2557
2558 DECLARE_COMPLETION_ONSTACK(done);
2559
2560 if (!udc_controller)
2561 return -ENODEV;
2562
2563 udc_controller->done = &done;
2564 usb_del_gadget_udc(&udc_controller->gadget);
2565
2566 fsl_udc_clk_release();
2567
2568 /* DR has been stopped in usb_gadget_unregister_driver() */
2569 remove_proc_file();
2570
2571 /* Free allocated memory */
2572 kfree(udc_controller->status_req->req.buf);
2573 kfree(udc_controller->status_req);
2574 kfree(udc_controller->eps);
2575
2576 dma_pool_destroy(udc_controller->td_pool);
2577 free_irq(udc_controller->irq, udc_controller);
2578 iounmap(dr_regs);
2579 if (pdata->operating_mode == FSL_USB2_DR_DEVICE)
2580 release_mem_region(res->start, resource_size(res));
2581
2582 /* free udc --wait for the release() finished */
2583 wait_for_completion(&done);
2584
2585 /*
2586 * do platform specific un-initialization:
2587 * release iomux pins, etc.
2588 */
2589 if (pdata->exit)
2590 pdata->exit(pdev);
2591
2592 return 0;
2593 }
2594
2595 /*-----------------------------------------------------------------
2596 * Modify Power management attributes
2597 * Used by OTG statemachine to disable gadget temporarily
2598 -----------------------------------------------------------------*/
2599 static int fsl_udc_suspend(struct platform_device *pdev, pm_message_t state)
2600 {
2601 dr_controller_stop(udc_controller);
2602 return 0;
2603 }
2604
2605 /*-----------------------------------------------------------------
2606 * Invoked on USB resume. May be called in_interrupt.
2607 * Here we start the DR controller and enable the irq
2608 *-----------------------------------------------------------------*/
2609 static int fsl_udc_resume(struct platform_device *pdev)
2610 {
2611 /* Enable DR irq reg and set controller Run */
2612 if (udc_controller->stopped) {
2613 dr_controller_setup(udc_controller);
2614 dr_controller_run(udc_controller);
2615 }
2616 udc_controller->usb_state = USB_STATE_ATTACHED;
2617 udc_controller->ep0_state = WAIT_FOR_SETUP;
2618 udc_controller->ep0_dir = 0;
2619 return 0;
2620 }
2621
2622 static int fsl_udc_otg_suspend(struct device *dev, pm_message_t state)
2623 {
2624 struct fsl_udc *udc = udc_controller;
2625 u32 mode, usbcmd;
2626
2627 mode = fsl_readl(&dr_regs->usbmode) & USB_MODE_CTRL_MODE_MASK;
2628
2629 pr_debug("%s(): mode 0x%x stopped %d\n", __func__, mode, udc->stopped);
2630
2631 /*
2632 * If the controller is already stopped, then this must be a
2633 * PM suspend. Remember this fact, so that we will leave the
2634 * controller stopped at PM resume time.
2635 */
2636 if (udc->stopped) {
2637 pr_debug("gadget already stopped, leaving early\n");
2638 udc->already_stopped = 1;
2639 return 0;
2640 }
2641
2642 if (mode != USB_MODE_CTRL_MODE_DEVICE) {
2643 pr_debug("gadget not in device mode, leaving early\n");
2644 return 0;
2645 }
2646
2647 /* stop the controller */
2648 usbcmd = fsl_readl(&dr_regs->usbcmd) & ~USB_CMD_RUN_STOP;
2649 fsl_writel(usbcmd, &dr_regs->usbcmd);
2650
2651 udc->stopped = 1;
2652
2653 pr_info("USB Gadget suspended\n");
2654
2655 return 0;
2656 }
2657
2658 static int fsl_udc_otg_resume(struct device *dev)
2659 {
2660 pr_debug("%s(): stopped %d already_stopped %d\n", __func__,
2661 udc_controller->stopped, udc_controller->already_stopped);
2662
2663 /*
2664 * If the controller was stopped at suspend time, then
2665 * don't resume it now.
2666 */
2667 if (udc_controller->already_stopped) {
2668 udc_controller->already_stopped = 0;
2669 pr_debug("gadget was already stopped, leaving early\n");
2670 return 0;
2671 }
2672
2673 pr_info("USB Gadget resume\n");
2674
2675 return fsl_udc_resume(NULL);
2676 }
2677 /*-------------------------------------------------------------------------
2678 Register entry point for the peripheral controller driver
2679 --------------------------------------------------------------------------*/
2680 static const struct platform_device_id fsl_udc_devtype[] = {
2681 {
2682 .name = "imx-udc-mx27",
2683 }, {
2684 .name = "imx-udc-mx51",
2685 }, {
2686 .name = "fsl-usb2-udc",
2687 }, {
2688 /* sentinel */
2689 }
2690 };
2691 MODULE_DEVICE_TABLE(platform, fsl_udc_devtype);
2692 static struct platform_driver udc_driver = {
2693 .remove = fsl_udc_remove,
2694 /* Just for FSL i.mx SoC currently */
2695 .id_table = fsl_udc_devtype,
2696 /* these suspend and resume are not usb suspend and resume */
2697 .suspend = fsl_udc_suspend,
2698 .resume = fsl_udc_resume,
2699 .driver = {
2700 .name = driver_name,
2701 /* udc suspend/resume called from OTG driver */
2702 .suspend = fsl_udc_otg_suspend,
2703 .resume = fsl_udc_otg_resume,
2704 },
2705 };
2706
2707 module_platform_driver_probe(udc_driver, fsl_udc_probe);
2708
2709 MODULE_DESCRIPTION(DRIVER_DESC);
2710 MODULE_AUTHOR(DRIVER_AUTHOR);
2711 MODULE_LICENSE("GPL");
2712 MODULE_ALIAS("platform:fsl-usb2-udc");
Linux with added FPC-III support