drivers/usb/gadget/udc/gr_udc.h

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * USB Peripheral Controller driver for Aeroflex Gaisler GRUSBDC.
   4  *
   5  * 2013 (c) Aeroflex Gaisler AB
   6  *
   7  * This driver supports GRUSBDC USB Device Controller cores available in the
   8  * GRLIB VHDL IP core library.
   9  *
  10  * Full documentation of the GRUSBDC core can be found here:
  11  * http://www.gaisler.com/products/grlib/grip.pdf
  12  *
  13  * Contributors:
  14  * - Andreas Larsson <andreas@gaisler.com>
  15  * - Marko Isomaki
  16  */
  17
  18 /* Control registers on the AMBA bus */
  19
  20 #define GR_MAXEP        16      /* Max # endpoints for *each* direction */
  21
  22 struct gr_epregs {
  23         u32 epctrl;
  24         union {
  25                 struct { /* Slave mode*/
  26                         u32 slvctrl;
  27                         u32 slvdata;
  28                 };
  29                 struct { /* DMA mode*/
  30                         u32 dmactrl;
  31                         u32 dmaaddr;
  32                 };
  33         };
  34         u32 epstat;
  35 };
  36
  37 struct gr_regs {
  38         struct gr_epregs        epo[GR_MAXEP];  /* 0x000 - 0x0fc */
  39         struct gr_epregs        epi[GR_MAXEP];  /* 0x100 - 0x1fc */
  40         u32                     control;        /* 0x200 */
  41         u32                     status;         /* 0x204 */
  42 };
  43
  44 #define GR_EPCTRL_BUFSZ_SCALER  8
  45 #define GR_EPCTRL_BUFSZ_MASK    0xffe00000
  46 #define GR_EPCTRL_BUFSZ_POS     21
  47 #define GR_EPCTRL_PI            BIT(20)
  48 #define GR_EPCTRL_CB            BIT(19)
  49 #define GR_EPCTRL_CS            BIT(18)
  50 #define GR_EPCTRL_MAXPL_MASK    0x0003ff80
  51 #define GR_EPCTRL_MAXPL_POS     7
  52 #define GR_EPCTRL_NT_MASK       0x00000060
  53 #define GR_EPCTRL_NT_POS        5
  54 #define GR_EPCTRL_TT_MASK       0x00000018
  55 #define GR_EPCTRL_TT_POS        3
  56 #define GR_EPCTRL_EH            BIT(2)
  57 #define GR_EPCTRL_ED            BIT(1)
  58 #define GR_EPCTRL_EV            BIT(0)
  59
  60 #define GR_DMACTRL_AE           BIT(10)
  61 #define GR_DMACTRL_AD           BIT(3)
  62 #define GR_DMACTRL_AI           BIT(2)
  63 #define GR_DMACTRL_IE           BIT(1)
  64 #define GR_DMACTRL_DA           BIT(0)
  65
  66 #define GR_EPSTAT_PT            BIT(29)
  67 #define GR_EPSTAT_PR            BIT(29)
  68 #define GR_EPSTAT_B1CNT_MASK    0x1fff0000
  69 #define GR_EPSTAT_B1CNT_POS     16
  70 #define GR_EPSTAT_B0CNT_MASK    0x0000fff8
  71 #define GR_EPSTAT_B0CNT_POS     3
  72 #define GR_EPSTAT_B1            BIT(2)
  73 #define GR_EPSTAT_B0            BIT(1)
  74 #define GR_EPSTAT_BS            BIT(0)
  75
  76 #define GR_CONTROL_SI           BIT(31)
  77 #define GR_CONTROL_UI           BIT(30)
  78 #define GR_CONTROL_VI           BIT(29)
  79 #define GR_CONTROL_SP           BIT(28)
  80 #define GR_CONTROL_FI           BIT(27)
  81 #define GR_CONTROL_EP           BIT(14)
  82 #define GR_CONTROL_DH           BIT(13)
  83 #define GR_CONTROL_RW           BIT(12)
  84 #define GR_CONTROL_TS_MASK      0x00000e00
  85 #define GR_CONTROL_TS_POS       9
  86 #define GR_CONTROL_TM           BIT(8)
  87 #define GR_CONTROL_UA_MASK      0x000000fe
  88 #define GR_CONTROL_UA_POS       1
  89 #define GR_CONTROL_SU           BIT(0)
  90
  91 #define GR_STATUS_NEPI_MASK     0xf0000000
  92 #define GR_STATUS_NEPI_POS      28
  93 #define GR_STATUS_NEPO_MASK     0x0f000000
  94 #define GR_STATUS_NEPO_POS      24
  95 #define GR_STATUS_DM            BIT(23)
  96 #define GR_STATUS_SU            BIT(17)
  97 #define GR_STATUS_UR            BIT(16)
  98 #define GR_STATUS_VB            BIT(15)
  99 #define GR_STATUS_SP            BIT(14)
 100 #define GR_STATUS_AF_MASK       0x00003800
 101 #define GR_STATUS_AF_POS        11
 102 #define GR_STATUS_FN_MASK       0x000007ff
 103 #define GR_STATUS_FN_POS        0
 104
 105
 106 #define MAX_CTRL_PL_SIZE 64 /* As per USB standard for full and high speed */
 107
 108 /*-------------------------------------------------------------------------*/
 109
 110 /* Driver data structures and utilities */
 111
 112 struct gr_dma_desc {
 113         u32 ctrl;
 114         u32 data;
 115         u32 next;
 116
 117         /* These must be last because hw uses the previous three */
 118         u32 paddr;
 119         struct gr_dma_desc *next_desc;
 120 };
 121
 122 #define GR_DESC_OUT_CTRL_SE             BIT(17)
 123 #define GR_DESC_OUT_CTRL_IE             BIT(15)
 124 #define GR_DESC_OUT_CTRL_NX             BIT(14)
 125 #define GR_DESC_OUT_CTRL_EN             BIT(13)
 126 #define GR_DESC_OUT_CTRL_LEN_MASK       0x00001fff
 127
 128 #define GR_DESC_IN_CTRL_MO              BIT(18)
 129 #define GR_DESC_IN_CTRL_PI              BIT(17)
 130 #define GR_DESC_IN_CTRL_ML              BIT(16)
 131 #define GR_DESC_IN_CTRL_IE              BIT(15)
 132 #define GR_DESC_IN_CTRL_NX              BIT(14)
 133 #define GR_DESC_IN_CTRL_EN              BIT(13)
 134 #define GR_DESC_IN_CTRL_LEN_MASK        0x00001fff
 135
 136 #define GR_DESC_DMAADDR_MASK            0xfffffffc
 137
 138 struct gr_ep {
 139         struct usb_ep ep;
 140         struct gr_udc *dev;
 141         u16 bytes_per_buffer;
 142         unsigned int dma_start;
 143         struct gr_epregs __iomem *regs;
 144
 145         unsigned num:8;
 146         unsigned is_in:1;
 147         unsigned stopped:1;
 148         unsigned wedged:1;
 149         unsigned callback:1;
 150
 151         /* analogous to a host-side qh */
 152         struct list_head queue;
 153
 154         struct list_head ep_list;
 155
 156         /* Bounce buffer for end of "odd" sized OUT requests */
 157         void *tailbuf;
 158         dma_addr_t tailbuf_paddr;
 159 };
 160
 161 struct gr_request {
 162         struct usb_request req;
 163         struct list_head queue;
 164
 165         /* Chain of dma descriptors */
 166         struct gr_dma_desc *first_desc; /* First in the chain */
 167         struct gr_dma_desc *curr_desc; /* Current descriptor */
 168         struct gr_dma_desc *last_desc; /* Last in the chain */
 169
 170         u16 evenlen; /* Size of even length head (if oddlen != 0) */
 171         u16 oddlen; /* Size of odd length tail if buffer length is "odd" */
 172
 173         u8 setup; /* Setup packet */
 174 };
 175
 176 enum gr_ep0state {
 177         GR_EP0_DISCONNECT = 0,  /* No host */
 178         GR_EP0_SETUP,           /* Between STATUS ack and SETUP report */
 179         GR_EP0_IDATA,           /* IN data stage */
 180         GR_EP0_ODATA,           /* OUT data stage */
 181         GR_EP0_ISTATUS,         /* Status stage after IN data stage */
 182         GR_EP0_OSTATUS,         /* Status stage after OUT data stage */
 183         GR_EP0_STALL,           /* Data or status stages */
 184         GR_EP0_SUSPEND,         /* USB suspend */
 185 };
 186
 187 struct gr_udc {
 188         struct usb_gadget gadget;
 189         struct gr_ep epi[GR_MAXEP];
 190         struct gr_ep epo[GR_MAXEP];
 191         struct usb_gadget_driver *driver;
 192         struct dma_pool *desc_pool;
 193         struct device *dev;
 194
 195         enum gr_ep0state ep0state;
 196         struct gr_request *ep0reqo;
 197         struct gr_request *ep0reqi;
 198
 199         struct gr_regs __iomem *regs;
 200         int irq;
 201         int irqi;
 202         int irqo;
 203
 204         unsigned added:1;
 205         unsigned irq_enabled:1;
 206         unsigned remote_wakeup:1;
 207
 208         u8 test_mode;
 209
 210         enum usb_device_state suspended_from;
 211
 212         unsigned int nepi;
 213         unsigned int nepo;
 214
 215         struct list_head ep_list;
 216
 217         spinlock_t lock; /* General lock, a.k.a. "dev->lock" in comments */
 218
 219         struct dentry *dfs_root;
 220 };
 221
 222 #define to_gr_udc(gadget)       (container_of((gadget), struct gr_udc, gadget))