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rcutorture: Eliminate unused ts_rem local from rcu_trace_clock_local()
[linux/fpc-iii.git] / drivers / gpu / drm / bridge / synopsys / dw-hdmi.c
blobead11242c4b91e2fd0f2c2da7a68ff0e72025b3c
1 /*
2 * DesignWare High-Definition Multimedia Interface (HDMI) driver
3 *
4 * Copyright (C) 2013-2015 Mentor Graphics Inc.
5 * Copyright (C) 2011-2013 Freescale Semiconductor, Inc.
6 * Copyright (C) 2010, Guennadi Liakhovetski <g.liakhovetski@gmx.de>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 */
14 #include <linux/module.h>
15 #include <linux/irq.h>
16 #include <linux/delay.h>
17 #include <linux/err.h>
18 #include <linux/clk.h>
19 #include <linux/hdmi.h>
20 #include <linux/mutex.h>
21 #include <linux/of_device.h>
22 #include <linux/regmap.h>
23 #include <linux/spinlock.h>
24
25 #include <drm/drm_of.h>
26 #include <drm/drmP.h>
27 #include <drm/drm_atomic_helper.h>
28 #include <drm/drm_crtc_helper.h>
29 #include <drm/drm_edid.h>
30 #include <drm/drm_encoder_slave.h>
31 #include <drm/bridge/dw_hdmi.h>
32
33 #include <uapi/linux/media-bus-format.h>
34 #include <uapi/linux/videodev2.h>
35
36 #include "dw-hdmi.h"
37 #include "dw-hdmi-audio.h"
38
39 #define DDC_SEGMENT_ADDR 0x30
40 #define HDMI_EDID_LEN 512
41
42 enum hdmi_datamap {
43 RGB444_8B = 0x01,
44 RGB444_10B = 0x03,
45 RGB444_12B = 0x05,
46 RGB444_16B = 0x07,
47 YCbCr444_8B = 0x09,
48 YCbCr444_10B = 0x0B,
49 YCbCr444_12B = 0x0D,
50 YCbCr444_16B = 0x0F,
51 YCbCr422_8B = 0x16,
52 YCbCr422_10B = 0x14,
53 YCbCr422_12B = 0x12,
54 };
55
56 static const u16 csc_coeff_default[3][4] = {
57 { 0x2000, 0x0000, 0x0000, 0x0000 },
58 { 0x0000, 0x2000, 0x0000, 0x0000 },
59 { 0x0000, 0x0000, 0x2000, 0x0000 }
60 };
61
62 static const u16 csc_coeff_rgb_out_eitu601[3][4] = {
63 { 0x2000, 0x6926, 0x74fd, 0x010e },
64 { 0x2000, 0x2cdd, 0x0000, 0x7e9a },
65 { 0x2000, 0x0000, 0x38b4, 0x7e3b }
66 };
67
68 static const u16 csc_coeff_rgb_out_eitu709[3][4] = {
69 { 0x2000, 0x7106, 0x7a02, 0x00a7 },
70 { 0x2000, 0x3264, 0x0000, 0x7e6d },
71 { 0x2000, 0x0000, 0x3b61, 0x7e25 }
72 };
73
74 static const u16 csc_coeff_rgb_in_eitu601[3][4] = {
75 { 0x2591, 0x1322, 0x074b, 0x0000 },
76 { 0x6535, 0x2000, 0x7acc, 0x0200 },
77 { 0x6acd, 0x7534, 0x2000, 0x0200 }
78 };
79
80 static const u16 csc_coeff_rgb_in_eitu709[3][4] = {
81 { 0x2dc5, 0x0d9b, 0x049e, 0x0000 },
82 { 0x62f0, 0x2000, 0x7d11, 0x0200 },
83 { 0x6756, 0x78ab, 0x2000, 0x0200 }
84 };
85
86 struct hdmi_vmode {
87 bool mdataenablepolarity;
88
89 unsigned int mpixelclock;
90 unsigned int mpixelrepetitioninput;
91 unsigned int mpixelrepetitionoutput;
92 };
93
94 struct hdmi_data_info {
95 unsigned int enc_in_bus_format;
96 unsigned int enc_out_bus_format;
97 unsigned int enc_in_encoding;
98 unsigned int enc_out_encoding;
99 unsigned int pix_repet_factor;
100 unsigned int hdcp_enable;
101 struct hdmi_vmode video_mode;
102 };
103
104 struct dw_hdmi_i2c {
105 struct i2c_adapter adap;
106
107 struct mutex lock; /* used to serialize data transfers */
108 struct completion cmp;
109 u8 stat;
110
111 u8 slave_reg;
112 bool is_regaddr;
113 bool is_segment;
114 };
115
116 struct dw_hdmi_phy_data {
117 enum dw_hdmi_phy_type type;
118 const char *name;
119 unsigned int gen;
120 bool has_svsret;
121 int (*configure)(struct dw_hdmi *hdmi,
122 const struct dw_hdmi_plat_data *pdata,
123 unsigned long mpixelclock);
124 };
125
126 struct dw_hdmi {
127 struct drm_connector connector;
128 struct drm_bridge bridge;
129
130 unsigned int version;
131
132 struct platform_device *audio;
133 struct device *dev;
134 struct clk *isfr_clk;
135 struct clk *iahb_clk;
136 struct dw_hdmi_i2c *i2c;
137
138 struct hdmi_data_info hdmi_data;
139 const struct dw_hdmi_plat_data *plat_data;
140
141 int vic;
142
143 u8 edid[HDMI_EDID_LEN];
144 bool cable_plugin;
145
146 struct {
147 const struct dw_hdmi_phy_ops *ops;
148 const char *name;
149 void *data;
150 bool enabled;
151 } phy;
152
153 struct drm_display_mode previous_mode;
154
155 struct i2c_adapter *ddc;
156 void __iomem *regs;
157 bool sink_is_hdmi;
158 bool sink_has_audio;
159
160 struct mutex mutex; /* for state below and previous_mode */
161 enum drm_connector_force force; /* mutex-protected force state */
162 bool disabled; /* DRM has disabled our bridge */
163 bool bridge_is_on; /* indicates the bridge is on */
164 bool rxsense; /* rxsense state */
165 u8 phy_mask; /* desired phy int mask settings */
166
167 spinlock_t audio_lock;
168 struct mutex audio_mutex;
169 unsigned int sample_rate;
170 unsigned int audio_cts;
171 unsigned int audio_n;
172 bool audio_enable;
173
174 unsigned int reg_shift;
175 struct regmap *regm;
176 void (*enable_audio)(struct dw_hdmi *hdmi);
177 void (*disable_audio)(struct dw_hdmi *hdmi);
178 };
179
180 #define HDMI_IH_PHY_STAT0_RX_SENSE \
181 (HDMI_IH_PHY_STAT0_RX_SENSE0 | HDMI_IH_PHY_STAT0_RX_SENSE1 | \
182 HDMI_IH_PHY_STAT0_RX_SENSE2 | HDMI_IH_PHY_STAT0_RX_SENSE3)
183
184 #define HDMI_PHY_RX_SENSE \
185 (HDMI_PHY_RX_SENSE0 | HDMI_PHY_RX_SENSE1 | \
186 HDMI_PHY_RX_SENSE2 | HDMI_PHY_RX_SENSE3)
187
188 static inline void hdmi_writeb(struct dw_hdmi *hdmi, u8 val, int offset)
189 {
190 regmap_write(hdmi->regm, offset << hdmi->reg_shift, val);
191 }
192
193 static inline u8 hdmi_readb(struct dw_hdmi *hdmi, int offset)
194 {
195 unsigned int val = 0;
196
197 regmap_read(hdmi->regm, offset << hdmi->reg_shift, &val);
198
199 return val;
200 }
201
202 static void hdmi_modb(struct dw_hdmi *hdmi, u8 data, u8 mask, unsigned reg)
203 {
204 regmap_update_bits(hdmi->regm, reg << hdmi->reg_shift, mask, data);
205 }
206
207 static void hdmi_mask_writeb(struct dw_hdmi *hdmi, u8 data, unsigned int reg,
208 u8 shift, u8 mask)
209 {
210 hdmi_modb(hdmi, data << shift, mask, reg);
211 }
212
213 static void dw_hdmi_i2c_init(struct dw_hdmi *hdmi)
214 {
215 /* Software reset */
216 hdmi_writeb(hdmi, 0x00, HDMI_I2CM_SOFTRSTZ);
217
218 /* Set Standard Mode speed (determined to be 100KHz on iMX6) */
219 hdmi_writeb(hdmi, 0x00, HDMI_I2CM_DIV);
220
221 /* Set done, not acknowledged and arbitration interrupt polarities */
222 hdmi_writeb(hdmi, HDMI_I2CM_INT_DONE_POL, HDMI_I2CM_INT);
223 hdmi_writeb(hdmi, HDMI_I2CM_CTLINT_NAC_POL | HDMI_I2CM_CTLINT_ARB_POL,
224 HDMI_I2CM_CTLINT);
225
226 /* Clear DONE and ERROR interrupts */
227 hdmi_writeb(hdmi, HDMI_IH_I2CM_STAT0_ERROR | HDMI_IH_I2CM_STAT0_DONE,
228 HDMI_IH_I2CM_STAT0);
229
230 /* Mute DONE and ERROR interrupts */
231 hdmi_writeb(hdmi, HDMI_IH_I2CM_STAT0_ERROR | HDMI_IH_I2CM_STAT0_DONE,
232 HDMI_IH_MUTE_I2CM_STAT0);
233 }
234
235 static int dw_hdmi_i2c_read(struct dw_hdmi *hdmi,
236 unsigned char *buf, unsigned int length)
237 {
238 struct dw_hdmi_i2c *i2c = hdmi->i2c;
239 int stat;
240
241 if (!i2c->is_regaddr) {
242 dev_dbg(hdmi->dev, "set read register address to 0\n");
243 i2c->slave_reg = 0x00;
244 i2c->is_regaddr = true;
245 }
246
247 while (length--) {
248 reinit_completion(&i2c->cmp);
249
250 hdmi_writeb(hdmi, i2c->slave_reg++, HDMI_I2CM_ADDRESS);
251 if (i2c->is_segment)
252 hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_READ_EXT,
253 HDMI_I2CM_OPERATION);
254 else
255 hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_READ,
256 HDMI_I2CM_OPERATION);
257
258 stat = wait_for_completion_timeout(&i2c->cmp, HZ / 10);
259 if (!stat)
260 return -EAGAIN;
261
262 /* Check for error condition on the bus */
263 if (i2c->stat & HDMI_IH_I2CM_STAT0_ERROR)
264 return -EIO;
265
266 *buf++ = hdmi_readb(hdmi, HDMI_I2CM_DATAI);
267 }
268 i2c->is_segment = false;
269
270 return 0;
271 }
272
273 static int dw_hdmi_i2c_write(struct dw_hdmi *hdmi,
274 unsigned char *buf, unsigned int length)
275 {
276 struct dw_hdmi_i2c *i2c = hdmi->i2c;
277 int stat;
278
279 if (!i2c->is_regaddr) {
280 /* Use the first write byte as register address */
281 i2c->slave_reg = buf[0];
282 length--;
283 buf++;
284 i2c->is_regaddr = true;
285 }
286
287 while (length--) {
288 reinit_completion(&i2c->cmp);
289
290 hdmi_writeb(hdmi, *buf++, HDMI_I2CM_DATAO);
291 hdmi_writeb(hdmi, i2c->slave_reg++, HDMI_I2CM_ADDRESS);
292 hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_WRITE,
293 HDMI_I2CM_OPERATION);
294
295 stat = wait_for_completion_timeout(&i2c->cmp, HZ / 10);
296 if (!stat)
297 return -EAGAIN;
298
299 /* Check for error condition on the bus */
300 if (i2c->stat & HDMI_IH_I2CM_STAT0_ERROR)
301 return -EIO;
302 }
303
304 return 0;
305 }
306
307 static int dw_hdmi_i2c_xfer(struct i2c_adapter *adap,
308 struct i2c_msg *msgs, int num)
309 {
310 struct dw_hdmi *hdmi = i2c_get_adapdata(adap);
311 struct dw_hdmi_i2c *i2c = hdmi->i2c;
312 u8 addr = msgs[0].addr;
313 int i, ret = 0;
314
315 dev_dbg(hdmi->dev, "xfer: num: %d, addr: %#x\n", num, addr);
316
317 for (i = 0; i < num; i++) {
318 if (msgs[i].len == 0) {
319 dev_dbg(hdmi->dev,
320 "unsupported transfer %d/%d, no data\n",
321 i + 1, num);
322 return -EOPNOTSUPP;
323 }
324 }
325
326 mutex_lock(&i2c->lock);
327
328 /* Unmute DONE and ERROR interrupts */
329 hdmi_writeb(hdmi, 0x00, HDMI_IH_MUTE_I2CM_STAT0);
330
331 /* Set slave device address taken from the first I2C message */
332 hdmi_writeb(hdmi, addr, HDMI_I2CM_SLAVE);
333
334 /* Set slave device register address on transfer */
335 i2c->is_regaddr = false;
336
337 /* Set segment pointer for I2C extended read mode operation */
338 i2c->is_segment = false;
339
340 for (i = 0; i < num; i++) {
341 dev_dbg(hdmi->dev, "xfer: num: %d/%d, len: %d, flags: %#x\n",
342 i + 1, num, msgs[i].len, msgs[i].flags);
343 if (msgs[i].addr == DDC_SEGMENT_ADDR && msgs[i].len == 1) {
344 i2c->is_segment = true;
345 hdmi_writeb(hdmi, DDC_SEGMENT_ADDR, HDMI_I2CM_SEGADDR);
346 hdmi_writeb(hdmi, *msgs[i].buf, HDMI_I2CM_SEGPTR);
347 } else {
348 if (msgs[i].flags & I2C_M_RD)
349 ret = dw_hdmi_i2c_read(hdmi, msgs[i].buf,
350 msgs[i].len);
351 else
352 ret = dw_hdmi_i2c_write(hdmi, msgs[i].buf,
353 msgs[i].len);
354 }
355 if (ret < 0)
356 break;
357 }
358
359 if (!ret)
360 ret = num;
361
362 /* Mute DONE and ERROR interrupts */
363 hdmi_writeb(hdmi, HDMI_IH_I2CM_STAT0_ERROR | HDMI_IH_I2CM_STAT0_DONE,
364 HDMI_IH_MUTE_I2CM_STAT0);
365
366 mutex_unlock(&i2c->lock);
367
368 return ret;
369 }
370
371 static u32 dw_hdmi_i2c_func(struct i2c_adapter *adapter)
372 {
373 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
374 }
375
376 static const struct i2c_algorithm dw_hdmi_algorithm = {
377 .master_xfer = dw_hdmi_i2c_xfer,
378 .functionality = dw_hdmi_i2c_func,
379 };
380
381 static struct i2c_adapter *dw_hdmi_i2c_adapter(struct dw_hdmi *hdmi)
382 {
383 struct i2c_adapter *adap;
384 struct dw_hdmi_i2c *i2c;
385 int ret;
386
387 i2c = devm_kzalloc(hdmi->dev, sizeof(*i2c), GFP_KERNEL);
388 if (!i2c)
389 return ERR_PTR(-ENOMEM);
390
391 mutex_init(&i2c->lock);
392 init_completion(&i2c->cmp);
393
394 adap = &i2c->adap;
395 adap->class = I2C_CLASS_DDC;
396 adap->owner = THIS_MODULE;
397 adap->dev.parent = hdmi->dev;
398 adap->algo = &dw_hdmi_algorithm;
399 strlcpy(adap->name, "DesignWare HDMI", sizeof(adap->name));
400 i2c_set_adapdata(adap, hdmi);
401
402 ret = i2c_add_adapter(adap);
403 if (ret) {
404 dev_warn(hdmi->dev, "cannot add %s I2C adapter\n", adap->name);
405 devm_kfree(hdmi->dev, i2c);
406 return ERR_PTR(ret);
407 }
408
409 hdmi->i2c = i2c;
410
411 dev_info(hdmi->dev, "registered %s I2C bus driver\n", adap->name);
412
413 return adap;
414 }
415
416 static void hdmi_set_cts_n(struct dw_hdmi *hdmi, unsigned int cts,
417 unsigned int n)
418 {
419 /* Must be set/cleared first */
420 hdmi_modb(hdmi, 0, HDMI_AUD_CTS3_CTS_MANUAL, HDMI_AUD_CTS3);
421
422 /* nshift factor = 0 */
423 hdmi_modb(hdmi, 0, HDMI_AUD_CTS3_N_SHIFT_MASK, HDMI_AUD_CTS3);
424
425 hdmi_writeb(hdmi, ((cts >> 16) & HDMI_AUD_CTS3_AUDCTS19_16_MASK) |
426 HDMI_AUD_CTS3_CTS_MANUAL, HDMI_AUD_CTS3);
427 hdmi_writeb(hdmi, (cts >> 8) & 0xff, HDMI_AUD_CTS2);
428 hdmi_writeb(hdmi, cts & 0xff, HDMI_AUD_CTS1);
429
430 hdmi_writeb(hdmi, (n >> 16) & 0x0f, HDMI_AUD_N3);
431 hdmi_writeb(hdmi, (n >> 8) & 0xff, HDMI_AUD_N2);
432 hdmi_writeb(hdmi, n & 0xff, HDMI_AUD_N1);
433 }
434
435 static unsigned int hdmi_compute_n(unsigned int freq, unsigned long pixel_clk)
436 {
437 unsigned int n = (128 * freq) / 1000;
438 unsigned int mult = 1;
439
440 while (freq > 48000) {
441 mult *= 2;
442 freq /= 2;
443 }
444
445 switch (freq) {
446 case 32000:
447 if (pixel_clk == 25175000)
448 n = 4576;
449 else if (pixel_clk == 27027000)
450 n = 4096;
451 else if (pixel_clk == 74176000 || pixel_clk == 148352000)
452 n = 11648;
453 else
454 n = 4096;
455 n *= mult;
456 break;
457
458 case 44100:
459 if (pixel_clk == 25175000)
460 n = 7007;
461 else if (pixel_clk == 74176000)
462 n = 17836;
463 else if (pixel_clk == 148352000)
464 n = 8918;
465 else
466 n = 6272;
467 n *= mult;
468 break;
469
470 case 48000:
471 if (pixel_clk == 25175000)
472 n = 6864;
473 else if (pixel_clk == 27027000)
474 n = 6144;
475 else if (pixel_clk == 74176000)
476 n = 11648;
477 else if (pixel_clk == 148352000)
478 n = 5824;
479 else
480 n = 6144;
481 n *= mult;
482 break;
483
484 default:
485 break;
486 }
487
488 return n;
489 }
490
491 static void hdmi_set_clk_regenerator(struct dw_hdmi *hdmi,
492 unsigned long pixel_clk, unsigned int sample_rate)
493 {
494 unsigned long ftdms = pixel_clk;
495 unsigned int n, cts;
496 u64 tmp;
497
498 n = hdmi_compute_n(sample_rate, pixel_clk);
499
500 /*
501 * Compute the CTS value from the N value. Note that CTS and N
502 * can be up to 20 bits in total, so we need 64-bit math. Also
503 * note that our TDMS clock is not fully accurate; it is accurate
504 * to kHz. This can introduce an unnecessary remainder in the
505 * calculation below, so we don't try to warn about that.
506 */
507 tmp = (u64)ftdms * n;
508 do_div(tmp, 128 * sample_rate);
509 cts = tmp;
510
511 dev_dbg(hdmi->dev, "%s: fs=%uHz ftdms=%lu.%03luMHz N=%d cts=%d\n",
512 __func__, sample_rate, ftdms / 1000000, (ftdms / 1000) % 1000,
513 n, cts);
514
515 spin_lock_irq(&hdmi->audio_lock);
516 hdmi->audio_n = n;
517 hdmi->audio_cts = cts;
518 hdmi_set_cts_n(hdmi, cts, hdmi->audio_enable ? n : 0);
519 spin_unlock_irq(&hdmi->audio_lock);
520 }
521
522 static void hdmi_init_clk_regenerator(struct dw_hdmi *hdmi)
523 {
524 mutex_lock(&hdmi->audio_mutex);
525 hdmi_set_clk_regenerator(hdmi, 74250000, hdmi->sample_rate);
526 mutex_unlock(&hdmi->audio_mutex);
527 }
528
529 static void hdmi_clk_regenerator_update_pixel_clock(struct dw_hdmi *hdmi)
530 {
531 mutex_lock(&hdmi->audio_mutex);
532 hdmi_set_clk_regenerator(hdmi, hdmi->hdmi_data.video_mode.mpixelclock,
533 hdmi->sample_rate);
534 mutex_unlock(&hdmi->audio_mutex);
535 }
536
537 void dw_hdmi_set_sample_rate(struct dw_hdmi *hdmi, unsigned int rate)
538 {
539 mutex_lock(&hdmi->audio_mutex);
540 hdmi->sample_rate = rate;
541 hdmi_set_clk_regenerator(hdmi, hdmi->hdmi_data.video_mode.mpixelclock,
542 hdmi->sample_rate);
543 mutex_unlock(&hdmi->audio_mutex);
544 }
545 EXPORT_SYMBOL_GPL(dw_hdmi_set_sample_rate);
546
547 static void hdmi_enable_audio_clk(struct dw_hdmi *hdmi, bool enable)
548 {
549 hdmi_modb(hdmi, enable ? 0 : HDMI_MC_CLKDIS_AUDCLK_DISABLE,
550 HDMI_MC_CLKDIS_AUDCLK_DISABLE, HDMI_MC_CLKDIS);
551 }
552
553 static void dw_hdmi_ahb_audio_enable(struct dw_hdmi *hdmi)
554 {
555 hdmi_set_cts_n(hdmi, hdmi->audio_cts, hdmi->audio_n);
556 }
557
558 static void dw_hdmi_ahb_audio_disable(struct dw_hdmi *hdmi)
559 {
560 hdmi_set_cts_n(hdmi, hdmi->audio_cts, 0);
561 }
562
563 static void dw_hdmi_i2s_audio_enable(struct dw_hdmi *hdmi)
564 {
565 hdmi_set_cts_n(hdmi, hdmi->audio_cts, hdmi->audio_n);
566 hdmi_enable_audio_clk(hdmi, true);
567 }
568
569 static void dw_hdmi_i2s_audio_disable(struct dw_hdmi *hdmi)
570 {
571 hdmi_enable_audio_clk(hdmi, false);
572 }
573
574 void dw_hdmi_audio_enable(struct dw_hdmi *hdmi)
575 {
576 unsigned long flags;
577
578 spin_lock_irqsave(&hdmi->audio_lock, flags);
579 hdmi->audio_enable = true;
580 if (hdmi->enable_audio)
581 hdmi->enable_audio(hdmi);
582 spin_unlock_irqrestore(&hdmi->audio_lock, flags);
583 }
584 EXPORT_SYMBOL_GPL(dw_hdmi_audio_enable);
585
586 void dw_hdmi_audio_disable(struct dw_hdmi *hdmi)
587 {
588 unsigned long flags;
589
590 spin_lock_irqsave(&hdmi->audio_lock, flags);
591 hdmi->audio_enable = false;
592 if (hdmi->disable_audio)
593 hdmi->disable_audio(hdmi);
594 spin_unlock_irqrestore(&hdmi->audio_lock, flags);
595 }
596 EXPORT_SYMBOL_GPL(dw_hdmi_audio_disable);
597
598 static bool hdmi_bus_fmt_is_rgb(unsigned int bus_format)
599 {
600 switch (bus_format) {
601 case MEDIA_BUS_FMT_RGB888_1X24:
602 case MEDIA_BUS_FMT_RGB101010_1X30:
603 case MEDIA_BUS_FMT_RGB121212_1X36:
604 case MEDIA_BUS_FMT_RGB161616_1X48:
605 return true;
606
607 default:
608 return false;
609 }
610 }
611
612 static bool hdmi_bus_fmt_is_yuv444(unsigned int bus_format)
613 {
614 switch (bus_format) {
615 case MEDIA_BUS_FMT_YUV8_1X24:
616 case MEDIA_BUS_FMT_YUV10_1X30:
617 case MEDIA_BUS_FMT_YUV12_1X36:
618 case MEDIA_BUS_FMT_YUV16_1X48:
619 return true;
620
621 default:
622 return false;
623 }
624 }
625
626 static bool hdmi_bus_fmt_is_yuv422(unsigned int bus_format)
627 {
628 switch (bus_format) {
629 case MEDIA_BUS_FMT_UYVY8_1X16:
630 case MEDIA_BUS_FMT_UYVY10_1X20:
631 case MEDIA_BUS_FMT_UYVY12_1X24:
632 return true;
633
634 default:
635 return false;
636 }
637 }
638
639 static int hdmi_bus_fmt_color_depth(unsigned int bus_format)
640 {
641 switch (bus_format) {
642 case MEDIA_BUS_FMT_RGB888_1X24:
643 case MEDIA_BUS_FMT_YUV8_1X24:
644 case MEDIA_BUS_FMT_UYVY8_1X16:
645 case MEDIA_BUS_FMT_UYYVYY8_0_5X24:
646 return 8;
647
648 case MEDIA_BUS_FMT_RGB101010_1X30:
649 case MEDIA_BUS_FMT_YUV10_1X30:
650 case MEDIA_BUS_FMT_UYVY10_1X20:
651 case MEDIA_BUS_FMT_UYYVYY10_0_5X30:
652 return 10;
653
654 case MEDIA_BUS_FMT_RGB121212_1X36:
655 case MEDIA_BUS_FMT_YUV12_1X36:
656 case MEDIA_BUS_FMT_UYVY12_1X24:
657 case MEDIA_BUS_FMT_UYYVYY12_0_5X36:
658 return 12;
659
660 case MEDIA_BUS_FMT_RGB161616_1X48:
661 case MEDIA_BUS_FMT_YUV16_1X48:
662 case MEDIA_BUS_FMT_UYYVYY16_0_5X48:
663 return 16;
664
665 default:
666 return 0;
667 }
668 }
669
670 /*
671 * this submodule is responsible for the video data synchronization.
672 * for example, for RGB 4:4:4 input, the data map is defined as
673 * pin{47~40} <==> R[7:0]
674 * pin{31~24} <==> G[7:0]
675 * pin{15~8} <==> B[7:0]
676 */
677 static void hdmi_video_sample(struct dw_hdmi *hdmi)
678 {
679 int color_format = 0;
680 u8 val;
681
682 switch (hdmi->hdmi_data.enc_in_bus_format) {
683 case MEDIA_BUS_FMT_RGB888_1X24:
684 color_format = 0x01;
685 break;
686 case MEDIA_BUS_FMT_RGB101010_1X30:
687 color_format = 0x03;
688 break;
689 case MEDIA_BUS_FMT_RGB121212_1X36:
690 color_format = 0x05;
691 break;
692 case MEDIA_BUS_FMT_RGB161616_1X48:
693 color_format = 0x07;
694 break;
695
696 case MEDIA_BUS_FMT_YUV8_1X24:
697 case MEDIA_BUS_FMT_UYYVYY8_0_5X24:
698 color_format = 0x09;
699 break;
700 case MEDIA_BUS_FMT_YUV10_1X30:
701 case MEDIA_BUS_FMT_UYYVYY10_0_5X30:
702 color_format = 0x0B;
703 break;
704 case MEDIA_BUS_FMT_YUV12_1X36:
705 case MEDIA_BUS_FMT_UYYVYY12_0_5X36:
706 color_format = 0x0D;
707 break;
708 case MEDIA_BUS_FMT_YUV16_1X48:
709 case MEDIA_BUS_FMT_UYYVYY16_0_5X48:
710 color_format = 0x0F;
711 break;
712
713 case MEDIA_BUS_FMT_UYVY8_1X16:
714 color_format = 0x16;
715 break;
716 case MEDIA_BUS_FMT_UYVY10_1X20:
717 color_format = 0x14;
718 break;
719 case MEDIA_BUS_FMT_UYVY12_1X24:
720 color_format = 0x12;
721 break;
722
723 default:
724 return;
725 }
726
727 val = HDMI_TX_INVID0_INTERNAL_DE_GENERATOR_DISABLE |
728 ((color_format << HDMI_TX_INVID0_VIDEO_MAPPING_OFFSET) &
729 HDMI_TX_INVID0_VIDEO_MAPPING_MASK);
730 hdmi_writeb(hdmi, val, HDMI_TX_INVID0);
731
732 /* Enable TX stuffing: When DE is inactive, fix the output data to 0 */
733 val = HDMI_TX_INSTUFFING_BDBDATA_STUFFING_ENABLE |
734 HDMI_TX_INSTUFFING_RCRDATA_STUFFING_ENABLE |
735 HDMI_TX_INSTUFFING_GYDATA_STUFFING_ENABLE;
736 hdmi_writeb(hdmi, val, HDMI_TX_INSTUFFING);
737 hdmi_writeb(hdmi, 0x0, HDMI_TX_GYDATA0);
738 hdmi_writeb(hdmi, 0x0, HDMI_TX_GYDATA1);
739 hdmi_writeb(hdmi, 0x0, HDMI_TX_RCRDATA0);
740 hdmi_writeb(hdmi, 0x0, HDMI_TX_RCRDATA1);
741 hdmi_writeb(hdmi, 0x0, HDMI_TX_BCBDATA0);
742 hdmi_writeb(hdmi, 0x0, HDMI_TX_BCBDATA1);
743 }
744
745 static int is_color_space_conversion(struct dw_hdmi *hdmi)
746 {
747 return hdmi->hdmi_data.enc_in_bus_format != hdmi->hdmi_data.enc_out_bus_format;
748 }
749
750 static int is_color_space_decimation(struct dw_hdmi *hdmi)
751 {
752 if (!hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format))
753 return 0;
754
755 if (hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_in_bus_format) ||
756 hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_in_bus_format))
757 return 1;
758
759 return 0;
760 }
761
762 static int is_color_space_interpolation(struct dw_hdmi *hdmi)
763 {
764 if (!hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_in_bus_format))
765 return 0;
766
767 if (hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format) ||
768 hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_out_bus_format))
769 return 1;
770
771 return 0;
772 }
773
774 static void dw_hdmi_update_csc_coeffs(struct dw_hdmi *hdmi)
775 {
776 const u16 (*csc_coeff)[3][4] = &csc_coeff_default;
777 unsigned i;
778 u32 csc_scale = 1;
779
780 if (is_color_space_conversion(hdmi)) {
781 if (hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format)) {
782 if (hdmi->hdmi_data.enc_out_encoding ==
783 V4L2_YCBCR_ENC_601)
784 csc_coeff = &csc_coeff_rgb_out_eitu601;
785 else
786 csc_coeff = &csc_coeff_rgb_out_eitu709;
787 } else if (hdmi_bus_fmt_is_rgb(
788 hdmi->hdmi_data.enc_in_bus_format)) {
789 if (hdmi->hdmi_data.enc_out_encoding ==
790 V4L2_YCBCR_ENC_601)
791 csc_coeff = &csc_coeff_rgb_in_eitu601;
792 else
793 csc_coeff = &csc_coeff_rgb_in_eitu709;
794 csc_scale = 0;
795 }
796 }
797
798 /* The CSC registers are sequential, alternating MSB then LSB */
799 for (i = 0; i < ARRAY_SIZE(csc_coeff_default[0]); i++) {
800 u16 coeff_a = (*csc_coeff)[0][i];
801 u16 coeff_b = (*csc_coeff)[1][i];
802 u16 coeff_c = (*csc_coeff)[2][i];
803
804 hdmi_writeb(hdmi, coeff_a & 0xff, HDMI_CSC_COEF_A1_LSB + i * 2);
805 hdmi_writeb(hdmi, coeff_a >> 8, HDMI_CSC_COEF_A1_MSB + i * 2);
806 hdmi_writeb(hdmi, coeff_b & 0xff, HDMI_CSC_COEF_B1_LSB + i * 2);
807 hdmi_writeb(hdmi, coeff_b >> 8, HDMI_CSC_COEF_B1_MSB + i * 2);
808 hdmi_writeb(hdmi, coeff_c & 0xff, HDMI_CSC_COEF_C1_LSB + i * 2);
809 hdmi_writeb(hdmi, coeff_c >> 8, HDMI_CSC_COEF_C1_MSB + i * 2);
810 }
811
812 hdmi_modb(hdmi, csc_scale, HDMI_CSC_SCALE_CSCSCALE_MASK,
813 HDMI_CSC_SCALE);
814 }
815
816 static void hdmi_video_csc(struct dw_hdmi *hdmi)
817 {
818 int color_depth = 0;
819 int interpolation = HDMI_CSC_CFG_INTMODE_DISABLE;
820 int decimation = 0;
821
822 /* YCC422 interpolation to 444 mode */
823 if (is_color_space_interpolation(hdmi))
824 interpolation = HDMI_CSC_CFG_INTMODE_CHROMA_INT_FORMULA1;
825 else if (is_color_space_decimation(hdmi))
826 decimation = HDMI_CSC_CFG_DECMODE_CHROMA_INT_FORMULA3;
827
828 switch (hdmi_bus_fmt_color_depth(hdmi->hdmi_data.enc_out_bus_format)) {
829 case 8:
830 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_24BPP;
831 break;
832 case 10:
833 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_30BPP;
834 break;
835 case 12:
836 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_36BPP;
837 break;
838 case 16:
839 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_48BPP;
840 break;
841
842 default:
843 return;
844 }
845
846 /* Configure the CSC registers */
847 hdmi_writeb(hdmi, interpolation | decimation, HDMI_CSC_CFG);
848 hdmi_modb(hdmi, color_depth, HDMI_CSC_SCALE_CSC_COLORDE_PTH_MASK,
849 HDMI_CSC_SCALE);
850
851 dw_hdmi_update_csc_coeffs(hdmi);
852 }
853
854 /*
855 * HDMI video packetizer is used to packetize the data.
856 * for example, if input is YCC422 mode or repeater is used,
857 * data should be repacked this module can be bypassed.
858 */
859 static void hdmi_video_packetize(struct dw_hdmi *hdmi)
860 {
861 unsigned int color_depth = 0;
862 unsigned int remap_size = HDMI_VP_REMAP_YCC422_16bit;
863 unsigned int output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_PP;
864 struct hdmi_data_info *hdmi_data = &hdmi->hdmi_data;
865 u8 val, vp_conf;
866
867 if (hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format) ||
868 hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_out_bus_format)) {
869 switch (hdmi_bus_fmt_color_depth(
870 hdmi->hdmi_data.enc_out_bus_format)) {
871 case 8:
872 color_depth = 4;
873 output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS;
874 break;
875 case 10:
876 color_depth = 5;
877 break;
878 case 12:
879 color_depth = 6;
880 break;
881 case 16:
882 color_depth = 7;
883 break;
884 default:
885 output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS;
886 }
887 } else if (hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format)) {
888 switch (hdmi_bus_fmt_color_depth(
889 hdmi->hdmi_data.enc_out_bus_format)) {
890 case 0:
891 case 8:
892 remap_size = HDMI_VP_REMAP_YCC422_16bit;
893 break;
894 case 10:
895 remap_size = HDMI_VP_REMAP_YCC422_20bit;
896 break;
897 case 12:
898 remap_size = HDMI_VP_REMAP_YCC422_24bit;
899 break;
900
901 default:
902 return;
903 }
904 output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_YCC422;
905 } else {
906 return;
907 }
908
909 /* set the packetizer registers */
910 val = ((color_depth << HDMI_VP_PR_CD_COLOR_DEPTH_OFFSET) &
911 HDMI_VP_PR_CD_COLOR_DEPTH_MASK) |
912 ((hdmi_data->pix_repet_factor <<
913 HDMI_VP_PR_CD_DESIRED_PR_FACTOR_OFFSET) &
914 HDMI_VP_PR_CD_DESIRED_PR_FACTOR_MASK);
915 hdmi_writeb(hdmi, val, HDMI_VP_PR_CD);
916
917 hdmi_modb(hdmi, HDMI_VP_STUFF_PR_STUFFING_STUFFING_MODE,
918 HDMI_VP_STUFF_PR_STUFFING_MASK, HDMI_VP_STUFF);
919
920 /* Data from pixel repeater block */
921 if (hdmi_data->pix_repet_factor > 1) {
922 vp_conf = HDMI_VP_CONF_PR_EN_ENABLE |
923 HDMI_VP_CONF_BYPASS_SELECT_PIX_REPEATER;
924 } else { /* data from packetizer block */
925 vp_conf = HDMI_VP_CONF_PR_EN_DISABLE |
926 HDMI_VP_CONF_BYPASS_SELECT_VID_PACKETIZER;
927 }
928
929 hdmi_modb(hdmi, vp_conf,
930 HDMI_VP_CONF_PR_EN_MASK |
931 HDMI_VP_CONF_BYPASS_SELECT_MASK, HDMI_VP_CONF);
932
933 hdmi_modb(hdmi, 1 << HDMI_VP_STUFF_IDEFAULT_PHASE_OFFSET,
934 HDMI_VP_STUFF_IDEFAULT_PHASE_MASK, HDMI_VP_STUFF);
935
936 hdmi_writeb(hdmi, remap_size, HDMI_VP_REMAP);
937
938 if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_PP) {
939 vp_conf = HDMI_VP_CONF_BYPASS_EN_DISABLE |
940 HDMI_VP_CONF_PP_EN_ENABLE |
941 HDMI_VP_CONF_YCC422_EN_DISABLE;
942 } else if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_YCC422) {
943 vp_conf = HDMI_VP_CONF_BYPASS_EN_DISABLE |
944 HDMI_VP_CONF_PP_EN_DISABLE |
945 HDMI_VP_CONF_YCC422_EN_ENABLE;
946 } else if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS) {
947 vp_conf = HDMI_VP_CONF_BYPASS_EN_ENABLE |
948 HDMI_VP_CONF_PP_EN_DISABLE |
949 HDMI_VP_CONF_YCC422_EN_DISABLE;
950 } else {
951 return;
952 }
953
954 hdmi_modb(hdmi, vp_conf,
955 HDMI_VP_CONF_BYPASS_EN_MASK | HDMI_VP_CONF_PP_EN_ENMASK |
956 HDMI_VP_CONF_YCC422_EN_MASK, HDMI_VP_CONF);
957
958 hdmi_modb(hdmi, HDMI_VP_STUFF_PP_STUFFING_STUFFING_MODE |
959 HDMI_VP_STUFF_YCC422_STUFFING_STUFFING_MODE,
960 HDMI_VP_STUFF_PP_STUFFING_MASK |
961 HDMI_VP_STUFF_YCC422_STUFFING_MASK, HDMI_VP_STUFF);
962
963 hdmi_modb(hdmi, output_select, HDMI_VP_CONF_OUTPUT_SELECTOR_MASK,
964 HDMI_VP_CONF);
965 }
966
967 /* -----------------------------------------------------------------------------
968 * Synopsys PHY Handling
969 */
970
971 static inline void hdmi_phy_test_clear(struct dw_hdmi *hdmi,
972 unsigned char bit)
973 {
974 hdmi_modb(hdmi, bit << HDMI_PHY_TST0_TSTCLR_OFFSET,
975 HDMI_PHY_TST0_TSTCLR_MASK, HDMI_PHY_TST0);
976 }
977
978 static bool hdmi_phy_wait_i2c_done(struct dw_hdmi *hdmi, int msec)
979 {
980 u32 val;
981
982 while ((val = hdmi_readb(hdmi, HDMI_IH_I2CMPHY_STAT0) & 0x3) == 0) {
983 if (msec-- == 0)
984 return false;
985 udelay(1000);
986 }
987 hdmi_writeb(hdmi, val, HDMI_IH_I2CMPHY_STAT0);
988
989 return true;
990 }
991
992 void dw_hdmi_phy_i2c_write(struct dw_hdmi *hdmi, unsigned short data,
993 unsigned char addr)
994 {
995 hdmi_writeb(hdmi, 0xFF, HDMI_IH_I2CMPHY_STAT0);
996 hdmi_writeb(hdmi, addr, HDMI_PHY_I2CM_ADDRESS_ADDR);
997 hdmi_writeb(hdmi, (unsigned char)(data >> 8),
998 HDMI_PHY_I2CM_DATAO_1_ADDR);
999 hdmi_writeb(hdmi, (unsigned char)(data >> 0),
1000 HDMI_PHY_I2CM_DATAO_0_ADDR);
1001 hdmi_writeb(hdmi, HDMI_PHY_I2CM_OPERATION_ADDR_WRITE,
1002 HDMI_PHY_I2CM_OPERATION_ADDR);
1003 hdmi_phy_wait_i2c_done(hdmi, 1000);
1004 }
1005 EXPORT_SYMBOL_GPL(dw_hdmi_phy_i2c_write);
1006
1007 static void dw_hdmi_phy_enable_powerdown(struct dw_hdmi *hdmi, bool enable)
1008 {
1009 hdmi_mask_writeb(hdmi, !enable, HDMI_PHY_CONF0,
1010 HDMI_PHY_CONF0_PDZ_OFFSET,
1011 HDMI_PHY_CONF0_PDZ_MASK);
1012 }
1013
1014 static void dw_hdmi_phy_enable_tmds(struct dw_hdmi *hdmi, u8 enable)
1015 {
1016 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
1017 HDMI_PHY_CONF0_ENTMDS_OFFSET,
1018 HDMI_PHY_CONF0_ENTMDS_MASK);
1019 }
1020
1021 static void dw_hdmi_phy_enable_svsret(struct dw_hdmi *hdmi, u8 enable)
1022 {
1023 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
1024 HDMI_PHY_CONF0_SVSRET_OFFSET,
1025 HDMI_PHY_CONF0_SVSRET_MASK);
1026 }
1027
1028 static void dw_hdmi_phy_gen2_pddq(struct dw_hdmi *hdmi, u8 enable)
1029 {
1030 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
1031 HDMI_PHY_CONF0_GEN2_PDDQ_OFFSET,
1032 HDMI_PHY_CONF0_GEN2_PDDQ_MASK);
1033 }
1034
1035 static void dw_hdmi_phy_gen2_txpwron(struct dw_hdmi *hdmi, u8 enable)
1036 {
1037 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
1038 HDMI_PHY_CONF0_GEN2_TXPWRON_OFFSET,
1039 HDMI_PHY_CONF0_GEN2_TXPWRON_MASK);
1040 }
1041
1042 static void dw_hdmi_phy_sel_data_en_pol(struct dw_hdmi *hdmi, u8 enable)
1043 {
1044 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
1045 HDMI_PHY_CONF0_SELDATAENPOL_OFFSET,
1046 HDMI_PHY_CONF0_SELDATAENPOL_MASK);
1047 }
1048
1049 static void dw_hdmi_phy_sel_interface_control(struct dw_hdmi *hdmi, u8 enable)
1050 {
1051 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
1052 HDMI_PHY_CONF0_SELDIPIF_OFFSET,
1053 HDMI_PHY_CONF0_SELDIPIF_MASK);
1054 }
1055
1056 static void dw_hdmi_phy_power_off(struct dw_hdmi *hdmi)
1057 {
1058 const struct dw_hdmi_phy_data *phy = hdmi->phy.data;
1059 unsigned int i;
1060 u16 val;
1061
1062 if (phy->gen == 1) {
1063 dw_hdmi_phy_enable_tmds(hdmi, 0);
1064 dw_hdmi_phy_enable_powerdown(hdmi, true);
1065 return;
1066 }
1067
1068 dw_hdmi_phy_gen2_txpwron(hdmi, 0);
1069
1070 /*
1071 * Wait for TX_PHY_LOCK to be deasserted to indicate that the PHY went
1072 * to low power mode.
1073 */
1074 for (i = 0; i < 5; ++i) {
1075 val = hdmi_readb(hdmi, HDMI_PHY_STAT0);
1076 if (!(val & HDMI_PHY_TX_PHY_LOCK))
1077 break;
1078
1079 usleep_range(1000, 2000);
1080 }
1081
1082 if (val & HDMI_PHY_TX_PHY_LOCK)
1083 dev_warn(hdmi->dev, "PHY failed to power down\n");
1084 else
1085 dev_dbg(hdmi->dev, "PHY powered down in %u iterations\n", i);
1086
1087 dw_hdmi_phy_gen2_pddq(hdmi, 1);
1088 }
1089
1090 static int dw_hdmi_phy_power_on(struct dw_hdmi *hdmi)
1091 {
1092 const struct dw_hdmi_phy_data *phy = hdmi->phy.data;
1093 unsigned int i;
1094 u8 val;
1095
1096 if (phy->gen == 1) {
1097 dw_hdmi_phy_enable_powerdown(hdmi, false);
1098
1099 /* Toggle TMDS enable. */
1100 dw_hdmi_phy_enable_tmds(hdmi, 0);
1101 dw_hdmi_phy_enable_tmds(hdmi, 1);
1102 return 0;
1103 }
1104
1105 dw_hdmi_phy_gen2_txpwron(hdmi, 1);
1106 dw_hdmi_phy_gen2_pddq(hdmi, 0);
1107
1108 /* Wait for PHY PLL lock */
1109 for (i = 0; i < 5; ++i) {
1110 val = hdmi_readb(hdmi, HDMI_PHY_STAT0) & HDMI_PHY_TX_PHY_LOCK;
1111 if (val)
1112 break;
1113
1114 usleep_range(1000, 2000);
1115 }
1116
1117 if (!val) {
1118 dev_err(hdmi->dev, "PHY PLL failed to lock\n");
1119 return -ETIMEDOUT;
1120 }
1121
1122 dev_dbg(hdmi->dev, "PHY PLL locked %u iterations\n", i);
1123 return 0;
1124 }
1125
1126 /*
1127 * PHY configuration function for the DWC HDMI 3D TX PHY. Based on the available
1128 * information the DWC MHL PHY has the same register layout and is thus also
1129 * supported by this function.
1130 */
1131 static int hdmi_phy_configure_dwc_hdmi_3d_tx(struct dw_hdmi *hdmi,
1132 const struct dw_hdmi_plat_data *pdata,
1133 unsigned long mpixelclock)
1134 {
1135 const struct dw_hdmi_mpll_config *mpll_config = pdata->mpll_cfg;
1136 const struct dw_hdmi_curr_ctrl *curr_ctrl = pdata->cur_ctr;
1137 const struct dw_hdmi_phy_config *phy_config = pdata->phy_config;
1138
1139 /* PLL/MPLL Cfg - always match on final entry */
1140 for (; mpll_config->mpixelclock != ~0UL; mpll_config++)
1141 if (mpixelclock <= mpll_config->mpixelclock)
1142 break;
1143
1144 for (; curr_ctrl->mpixelclock != ~0UL; curr_ctrl++)
1145 if (mpixelclock <= curr_ctrl->mpixelclock)
1146 break;
1147
1148 for (; phy_config->mpixelclock != ~0UL; phy_config++)
1149 if (mpixelclock <= phy_config->mpixelclock)
1150 break;
1151
1152 if (mpll_config->mpixelclock == ~0UL ||
1153 curr_ctrl->mpixelclock == ~0UL ||
1154 phy_config->mpixelclock == ~0UL)
1155 return -EINVAL;
1156
1157 dw_hdmi_phy_i2c_write(hdmi, mpll_config->res[0].cpce,
1158 HDMI_3D_TX_PHY_CPCE_CTRL);
1159 dw_hdmi_phy_i2c_write(hdmi, mpll_config->res[0].gmp,
1160 HDMI_3D_TX_PHY_GMPCTRL);
1161 dw_hdmi_phy_i2c_write(hdmi, curr_ctrl->curr[0],
1162 HDMI_3D_TX_PHY_CURRCTRL);
1163
1164 dw_hdmi_phy_i2c_write(hdmi, 0, HDMI_3D_TX_PHY_PLLPHBYCTRL);
1165 dw_hdmi_phy_i2c_write(hdmi, HDMI_3D_TX_PHY_MSM_CTRL_CKO_SEL_FB_CLK,
1166 HDMI_3D_TX_PHY_MSM_CTRL);
1167
1168 dw_hdmi_phy_i2c_write(hdmi, phy_config->term, HDMI_3D_TX_PHY_TXTERM);
1169 dw_hdmi_phy_i2c_write(hdmi, phy_config->sym_ctr,
1170 HDMI_3D_TX_PHY_CKSYMTXCTRL);
1171 dw_hdmi_phy_i2c_write(hdmi, phy_config->vlev_ctr,
1172 HDMI_3D_TX_PHY_VLEVCTRL);
1173
1174 /* Override and disable clock termination. */
1175 dw_hdmi_phy_i2c_write(hdmi, HDMI_3D_TX_PHY_CKCALCTRL_OVERRIDE,
1176 HDMI_3D_TX_PHY_CKCALCTRL);
1177
1178 return 0;
1179 }
1180
1181 static int hdmi_phy_configure(struct dw_hdmi *hdmi)
1182 {
1183 const struct dw_hdmi_phy_data *phy = hdmi->phy.data;
1184 const struct dw_hdmi_plat_data *pdata = hdmi->plat_data;
1185 unsigned long mpixelclock = hdmi->hdmi_data.video_mode.mpixelclock;
1186 int ret;
1187
1188 dw_hdmi_phy_power_off(hdmi);
1189
1190 /* Leave low power consumption mode by asserting SVSRET. */
1191 if (phy->has_svsret)
1192 dw_hdmi_phy_enable_svsret(hdmi, 1);
1193
1194 /* PHY reset. The reset signal is active high on Gen2 PHYs. */
1195 hdmi_writeb(hdmi, HDMI_MC_PHYRSTZ_PHYRSTZ, HDMI_MC_PHYRSTZ);
1196 hdmi_writeb(hdmi, 0, HDMI_MC_PHYRSTZ);
1197
1198 hdmi_writeb(hdmi, HDMI_MC_HEACPHY_RST_ASSERT, HDMI_MC_HEACPHY_RST);
1199
1200 hdmi_phy_test_clear(hdmi, 1);
1201 hdmi_writeb(hdmi, HDMI_PHY_I2CM_SLAVE_ADDR_PHY_GEN2,
1202 HDMI_PHY_I2CM_SLAVE_ADDR);
1203 hdmi_phy_test_clear(hdmi, 0);
1204
1205 /* Write to the PHY as configured by the platform */
1206 if (pdata->configure_phy)
1207 ret = pdata->configure_phy(hdmi, pdata, mpixelclock);
1208 else
1209 ret = phy->configure(hdmi, pdata, mpixelclock);
1210 if (ret) {
1211 dev_err(hdmi->dev, "PHY configuration failed (clock %lu)\n",
1212 mpixelclock);
1213 return ret;
1214 }
1215
1216 return dw_hdmi_phy_power_on(hdmi);
1217 }
1218
1219 static int dw_hdmi_phy_init(struct dw_hdmi *hdmi, void *data,
1220 struct drm_display_mode *mode)
1221 {
1222 int i, ret;
1223
1224 /* HDMI Phy spec says to do the phy initialization sequence twice */
1225 for (i = 0; i < 2; i++) {
1226 dw_hdmi_phy_sel_data_en_pol(hdmi, 1);
1227 dw_hdmi_phy_sel_interface_control(hdmi, 0);
1228
1229 ret = hdmi_phy_configure(hdmi);
1230 if (ret)
1231 return ret;
1232 }
1233
1234 return 0;
1235 }
1236
1237 static void dw_hdmi_phy_disable(struct dw_hdmi *hdmi, void *data)
1238 {
1239 dw_hdmi_phy_power_off(hdmi);
1240 }
1241
1242 static enum drm_connector_status dw_hdmi_phy_read_hpd(struct dw_hdmi *hdmi,
1243 void *data)
1244 {
1245 return hdmi_readb(hdmi, HDMI_PHY_STAT0) & HDMI_PHY_HPD ?
1246 connector_status_connected : connector_status_disconnected;
1247 }
1248
1249 static void dw_hdmi_phy_update_hpd(struct dw_hdmi *hdmi, void *data,
1250 bool force, bool disabled, bool rxsense)
1251 {
1252 u8 old_mask = hdmi->phy_mask;
1253
1254 if (force || disabled || !rxsense)
1255 hdmi->phy_mask |= HDMI_PHY_RX_SENSE;
1256 else
1257 hdmi->phy_mask &= ~HDMI_PHY_RX_SENSE;
1258
1259 if (old_mask != hdmi->phy_mask)
1260 hdmi_writeb(hdmi, hdmi->phy_mask, HDMI_PHY_MASK0);
1261 }
1262
1263 static void dw_hdmi_phy_setup_hpd(struct dw_hdmi *hdmi, void *data)
1264 {
1265 /*
1266 * Configure the PHY RX SENSE and HPD interrupts polarities and clear
1267 * any pending interrupt.
1268 */
1269 hdmi_writeb(hdmi, HDMI_PHY_HPD | HDMI_PHY_RX_SENSE, HDMI_PHY_POL0);
1270 hdmi_writeb(hdmi, HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE,
1271 HDMI_IH_PHY_STAT0);
1272
1273 /* Enable cable hot plug irq. */
1274 hdmi_writeb(hdmi, hdmi->phy_mask, HDMI_PHY_MASK0);
1275
1276 /* Clear and unmute interrupts. */
1277 hdmi_writeb(hdmi, HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE,
1278 HDMI_IH_PHY_STAT0);
1279 hdmi_writeb(hdmi, ~(HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE),
1280 HDMI_IH_MUTE_PHY_STAT0);
1281 }
1282
1283 static const struct dw_hdmi_phy_ops dw_hdmi_synopsys_phy_ops = {
1284 .init = dw_hdmi_phy_init,
1285 .disable = dw_hdmi_phy_disable,
1286 .read_hpd = dw_hdmi_phy_read_hpd,
1287 .update_hpd = dw_hdmi_phy_update_hpd,
1288 .setup_hpd = dw_hdmi_phy_setup_hpd,
1289 };
1290
1291 /* -----------------------------------------------------------------------------
1292 * HDMI TX Setup
1293 */
1294
1295 static void hdmi_tx_hdcp_config(struct dw_hdmi *hdmi)
1296 {
1297 u8 de;
1298
1299 if (hdmi->hdmi_data.video_mode.mdataenablepolarity)
1300 de = HDMI_A_VIDPOLCFG_DATAENPOL_ACTIVE_HIGH;
1301 else
1302 de = HDMI_A_VIDPOLCFG_DATAENPOL_ACTIVE_LOW;
1303
1304 /* disable rx detect */
1305 hdmi_modb(hdmi, HDMI_A_HDCPCFG0_RXDETECT_DISABLE,
1306 HDMI_A_HDCPCFG0_RXDETECT_MASK, HDMI_A_HDCPCFG0);
1307
1308 hdmi_modb(hdmi, de, HDMI_A_VIDPOLCFG_DATAENPOL_MASK, HDMI_A_VIDPOLCFG);
1309
1310 hdmi_modb(hdmi, HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_DISABLE,
1311 HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_MASK, HDMI_A_HDCPCFG1);
1312 }
1313
1314 static void hdmi_config_AVI(struct dw_hdmi *hdmi, struct drm_display_mode *mode)
1315 {
1316 struct hdmi_avi_infoframe frame;
1317 u8 val;
1318
1319 /* Initialise info frame from DRM mode */
1320 drm_hdmi_avi_infoframe_from_display_mode(&frame, mode);
1321
1322 if (hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_out_bus_format))
1323 frame.colorspace = HDMI_COLORSPACE_YUV444;
1324 else if (hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format))
1325 frame.colorspace = HDMI_COLORSPACE_YUV422;
1326 else
1327 frame.colorspace = HDMI_COLORSPACE_RGB;
1328
1329 /* Set up colorimetry */
1330 switch (hdmi->hdmi_data.enc_out_encoding) {
1331 case V4L2_YCBCR_ENC_601:
1332 if (hdmi->hdmi_data.enc_in_encoding == V4L2_YCBCR_ENC_XV601)
1333 frame.colorimetry = HDMI_COLORIMETRY_EXTENDED;
1334 else
1335 frame.colorimetry = HDMI_COLORIMETRY_ITU_601;
1336 frame.extended_colorimetry =
1337 HDMI_EXTENDED_COLORIMETRY_XV_YCC_601;
1338 break;
1339 case V4L2_YCBCR_ENC_709:
1340 if (hdmi->hdmi_data.enc_in_encoding == V4L2_YCBCR_ENC_XV709)
1341 frame.colorimetry = HDMI_COLORIMETRY_EXTENDED;
1342 else
1343 frame.colorimetry = HDMI_COLORIMETRY_ITU_709;
1344 frame.extended_colorimetry =
1345 HDMI_EXTENDED_COLORIMETRY_XV_YCC_709;
1346 break;
1347 default: /* Carries no data */
1348 frame.colorimetry = HDMI_COLORIMETRY_ITU_601;
1349 frame.extended_colorimetry =
1350 HDMI_EXTENDED_COLORIMETRY_XV_YCC_601;
1351 break;
1352 }
1353
1354 frame.scan_mode = HDMI_SCAN_MODE_NONE;
1355
1356 /*
1357 * The Designware IP uses a different byte format from standard
1358 * AVI info frames, though generally the bits are in the correct
1359 * bytes.
1360 */
1361
1362 /*
1363 * AVI data byte 1 differences: Colorspace in bits 0,1 rather than 5,6,
1364 * scan info in bits 4,5 rather than 0,1 and active aspect present in
1365 * bit 6 rather than 4.
1366 */
1367 val = (frame.scan_mode & 3) << 4 | (frame.colorspace & 3);
1368 if (frame.active_aspect & 15)
1369 val |= HDMI_FC_AVICONF0_ACTIVE_FMT_INFO_PRESENT;
1370 if (frame.top_bar || frame.bottom_bar)
1371 val |= HDMI_FC_AVICONF0_BAR_DATA_HORIZ_BAR;
1372 if (frame.left_bar || frame.right_bar)
1373 val |= HDMI_FC_AVICONF0_BAR_DATA_VERT_BAR;
1374 hdmi_writeb(hdmi, val, HDMI_FC_AVICONF0);
1375
1376 /* AVI data byte 2 differences: none */
1377 val = ((frame.colorimetry & 0x3) << 6) |
1378 ((frame.picture_aspect & 0x3) << 4) |
1379 (frame.active_aspect & 0xf);
1380 hdmi_writeb(hdmi, val, HDMI_FC_AVICONF1);
1381
1382 /* AVI data byte 3 differences: none */
1383 val = ((frame.extended_colorimetry & 0x7) << 4) |
1384 ((frame.quantization_range & 0x3) << 2) |
1385 (frame.nups & 0x3);
1386 if (frame.itc)
1387 val |= HDMI_FC_AVICONF2_IT_CONTENT_VALID;
1388 hdmi_writeb(hdmi, val, HDMI_FC_AVICONF2);
1389
1390 /* AVI data byte 4 differences: none */
1391 val = frame.video_code & 0x7f;
1392 hdmi_writeb(hdmi, val, HDMI_FC_AVIVID);
1393
1394 /* AVI Data Byte 5- set up input and output pixel repetition */
1395 val = (((hdmi->hdmi_data.video_mode.mpixelrepetitioninput + 1) <<
1396 HDMI_FC_PRCONF_INCOMING_PR_FACTOR_OFFSET) &
1397 HDMI_FC_PRCONF_INCOMING_PR_FACTOR_MASK) |
1398 ((hdmi->hdmi_data.video_mode.mpixelrepetitionoutput <<
1399 HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_OFFSET) &
1400 HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_MASK);
1401 hdmi_writeb(hdmi, val, HDMI_FC_PRCONF);
1402
1403 /*
1404 * AVI data byte 5 differences: content type in 0,1 rather than 4,5,
1405 * ycc range in bits 2,3 rather than 6,7
1406 */
1407 val = ((frame.ycc_quantization_range & 0x3) << 2) |
1408 (frame.content_type & 0x3);
1409 hdmi_writeb(hdmi, val, HDMI_FC_AVICONF3);
1410
1411 /* AVI Data Bytes 6-13 */
1412 hdmi_writeb(hdmi, frame.top_bar & 0xff, HDMI_FC_AVIETB0);
1413 hdmi_writeb(hdmi, (frame.top_bar >> 8) & 0xff, HDMI_FC_AVIETB1);
1414 hdmi_writeb(hdmi, frame.bottom_bar & 0xff, HDMI_FC_AVISBB0);
1415 hdmi_writeb(hdmi, (frame.bottom_bar >> 8) & 0xff, HDMI_FC_AVISBB1);
1416 hdmi_writeb(hdmi, frame.left_bar & 0xff, HDMI_FC_AVIELB0);
1417 hdmi_writeb(hdmi, (frame.left_bar >> 8) & 0xff, HDMI_FC_AVIELB1);
1418 hdmi_writeb(hdmi, frame.right_bar & 0xff, HDMI_FC_AVISRB0);
1419 hdmi_writeb(hdmi, (frame.right_bar >> 8) & 0xff, HDMI_FC_AVISRB1);
1420 }
1421
1422 static void hdmi_config_vendor_specific_infoframe(struct dw_hdmi *hdmi,
1423 struct drm_display_mode *mode)
1424 {
1425 struct hdmi_vendor_infoframe frame;
1426 u8 buffer[10];
1427 ssize_t err;
1428
1429 err = drm_hdmi_vendor_infoframe_from_display_mode(&frame, mode);
1430 if (err < 0)
1431 /*
1432 * Going into that statement does not means vendor infoframe
1433 * fails. It just informed us that vendor infoframe is not
1434 * needed for the selected mode. Only 4k or stereoscopic 3D
1435 * mode requires vendor infoframe. So just simply return.
1436 */
1437 return;
1438
1439 err = hdmi_vendor_infoframe_pack(&frame, buffer, sizeof(buffer));
1440 if (err < 0) {
1441 dev_err(hdmi->dev, "Failed to pack vendor infoframe: %zd\n",
1442 err);
1443 return;
1444 }
1445 hdmi_mask_writeb(hdmi, 0, HDMI_FC_DATAUTO0, HDMI_FC_DATAUTO0_VSD_OFFSET,
1446 HDMI_FC_DATAUTO0_VSD_MASK);
1447
1448 /* Set the length of HDMI vendor specific InfoFrame payload */
1449 hdmi_writeb(hdmi, buffer[2], HDMI_FC_VSDSIZE);
1450
1451 /* Set 24bit IEEE Registration Identifier */
1452 hdmi_writeb(hdmi, buffer[4], HDMI_FC_VSDIEEEID0);
1453 hdmi_writeb(hdmi, buffer[5], HDMI_FC_VSDIEEEID1);
1454 hdmi_writeb(hdmi, buffer[6], HDMI_FC_VSDIEEEID2);
1455
1456 /* Set HDMI_Video_Format and HDMI_VIC/3D_Structure */
1457 hdmi_writeb(hdmi, buffer[7], HDMI_FC_VSDPAYLOAD0);
1458 hdmi_writeb(hdmi, buffer[8], HDMI_FC_VSDPAYLOAD1);
1459
1460 if (frame.s3d_struct >= HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF)
1461 hdmi_writeb(hdmi, buffer[9], HDMI_FC_VSDPAYLOAD2);
1462
1463 /* Packet frame interpolation */
1464 hdmi_writeb(hdmi, 1, HDMI_FC_DATAUTO1);
1465
1466 /* Auto packets per frame and line spacing */
1467 hdmi_writeb(hdmi, 0x11, HDMI_FC_DATAUTO2);
1468
1469 /* Configures the Frame Composer On RDRB mode */
1470 hdmi_mask_writeb(hdmi, 1, HDMI_FC_DATAUTO0, HDMI_FC_DATAUTO0_VSD_OFFSET,
1471 HDMI_FC_DATAUTO0_VSD_MASK);
1472 }
1473
1474 static void hdmi_av_composer(struct dw_hdmi *hdmi,
1475 const struct drm_display_mode *mode)
1476 {
1477 u8 inv_val;
1478 struct hdmi_vmode *vmode = &hdmi->hdmi_data.video_mode;
1479 int hblank, vblank, h_de_hs, v_de_vs, hsync_len, vsync_len;
1480 unsigned int vdisplay;
1481
1482 vmode->mpixelclock = mode->clock * 1000;
1483
1484 dev_dbg(hdmi->dev, "final pixclk = %d\n", vmode->mpixelclock);
1485
1486 /* Set up HDMI_FC_INVIDCONF */
1487 inv_val = (hdmi->hdmi_data.hdcp_enable ?
1488 HDMI_FC_INVIDCONF_HDCP_KEEPOUT_ACTIVE :
1489 HDMI_FC_INVIDCONF_HDCP_KEEPOUT_INACTIVE);
1490
1491 inv_val |= mode->flags & DRM_MODE_FLAG_PVSYNC ?
1492 HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_HIGH :
1493 HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_LOW;
1494
1495 inv_val |= mode->flags & DRM_MODE_FLAG_PHSYNC ?
1496 HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_HIGH :
1497 HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_LOW;
1498
1499 inv_val |= (vmode->mdataenablepolarity ?
1500 HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_HIGH :
1501 HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_LOW);
1502
1503 if (hdmi->vic == 39)
1504 inv_val |= HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH;
1505 else
1506 inv_val |= mode->flags & DRM_MODE_FLAG_INTERLACE ?
1507 HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH :
1508 HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_LOW;
1509
1510 inv_val |= mode->flags & DRM_MODE_FLAG_INTERLACE ?
1511 HDMI_FC_INVIDCONF_IN_I_P_INTERLACED :
1512 HDMI_FC_INVIDCONF_IN_I_P_PROGRESSIVE;
1513
1514 inv_val |= hdmi->sink_is_hdmi ?
1515 HDMI_FC_INVIDCONF_DVI_MODEZ_HDMI_MODE :
1516 HDMI_FC_INVIDCONF_DVI_MODEZ_DVI_MODE;
1517
1518 hdmi_writeb(hdmi, inv_val, HDMI_FC_INVIDCONF);
1519
1520 vdisplay = mode->vdisplay;
1521 vblank = mode->vtotal - mode->vdisplay;
1522 v_de_vs = mode->vsync_start - mode->vdisplay;
1523 vsync_len = mode->vsync_end - mode->vsync_start;
1524
1525 /*
1526 * When we're setting an interlaced mode, we need
1527 * to adjust the vertical timing to suit.
1528 */
1529 if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
1530 vdisplay /= 2;
1531 vblank /= 2;
1532 v_de_vs /= 2;
1533 vsync_len /= 2;
1534 }
1535
1536 /* Set up horizontal active pixel width */
1537 hdmi_writeb(hdmi, mode->hdisplay >> 8, HDMI_FC_INHACTV1);
1538 hdmi_writeb(hdmi, mode->hdisplay, HDMI_FC_INHACTV0);
1539
1540 /* Set up vertical active lines */
1541 hdmi_writeb(hdmi, vdisplay >> 8, HDMI_FC_INVACTV1);
1542 hdmi_writeb(hdmi, vdisplay, HDMI_FC_INVACTV0);
1543
1544 /* Set up horizontal blanking pixel region width */
1545 hblank = mode->htotal - mode->hdisplay;
1546 hdmi_writeb(hdmi, hblank >> 8, HDMI_FC_INHBLANK1);
1547 hdmi_writeb(hdmi, hblank, HDMI_FC_INHBLANK0);
1548
1549 /* Set up vertical blanking pixel region width */
1550 hdmi_writeb(hdmi, vblank, HDMI_FC_INVBLANK);
1551
1552 /* Set up HSYNC active edge delay width (in pixel clks) */
1553 h_de_hs = mode->hsync_start - mode->hdisplay;
1554 hdmi_writeb(hdmi, h_de_hs >> 8, HDMI_FC_HSYNCINDELAY1);
1555 hdmi_writeb(hdmi, h_de_hs, HDMI_FC_HSYNCINDELAY0);
1556
1557 /* Set up VSYNC active edge delay (in lines) */
1558 hdmi_writeb(hdmi, v_de_vs, HDMI_FC_VSYNCINDELAY);
1559
1560 /* Set up HSYNC active pulse width (in pixel clks) */
1561 hsync_len = mode->hsync_end - mode->hsync_start;
1562 hdmi_writeb(hdmi, hsync_len >> 8, HDMI_FC_HSYNCINWIDTH1);
1563 hdmi_writeb(hdmi, hsync_len, HDMI_FC_HSYNCINWIDTH0);
1564
1565 /* Set up VSYNC active edge delay (in lines) */
1566 hdmi_writeb(hdmi, vsync_len, HDMI_FC_VSYNCINWIDTH);
1567 }
1568
1569 /* HDMI Initialization Step B.4 */
1570 static void dw_hdmi_enable_video_path(struct dw_hdmi *hdmi)
1571 {
1572 u8 clkdis;
1573
1574 /* control period minimum duration */
1575 hdmi_writeb(hdmi, 12, HDMI_FC_CTRLDUR);
1576 hdmi_writeb(hdmi, 32, HDMI_FC_EXCTRLDUR);
1577 hdmi_writeb(hdmi, 1, HDMI_FC_EXCTRLSPAC);
1578
1579 /* Set to fill TMDS data channels */
1580 hdmi_writeb(hdmi, 0x0B, HDMI_FC_CH0PREAM);
1581 hdmi_writeb(hdmi, 0x16, HDMI_FC_CH1PREAM);
1582 hdmi_writeb(hdmi, 0x21, HDMI_FC_CH2PREAM);
1583
1584 /* Enable pixel clock and tmds data path */
1585 clkdis = 0x7F;
1586 clkdis &= ~HDMI_MC_CLKDIS_PIXELCLK_DISABLE;
1587 hdmi_writeb(hdmi, clkdis, HDMI_MC_CLKDIS);
1588
1589 clkdis &= ~HDMI_MC_CLKDIS_TMDSCLK_DISABLE;
1590 hdmi_writeb(hdmi, clkdis, HDMI_MC_CLKDIS);
1591
1592 /* Enable csc path */
1593 if (is_color_space_conversion(hdmi)) {
1594 clkdis &= ~HDMI_MC_CLKDIS_CSCCLK_DISABLE;
1595 hdmi_writeb(hdmi, clkdis, HDMI_MC_CLKDIS);
1596 }
1597
1598 /* Enable color space conversion if needed */
1599 if (is_color_space_conversion(hdmi))
1600 hdmi_writeb(hdmi, HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_IN_PATH,
1601 HDMI_MC_FLOWCTRL);
1602 else
1603 hdmi_writeb(hdmi, HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_BYPASS,
1604 HDMI_MC_FLOWCTRL);
1605 }
1606
1607 /* Workaround to clear the overflow condition */
1608 static void dw_hdmi_clear_overflow(struct dw_hdmi *hdmi)
1609 {
1610 unsigned int count;
1611 unsigned int i;
1612 u8 val;
1613
1614 /*
1615 * Under some circumstances the Frame Composer arithmetic unit can miss
1616 * an FC register write due to being busy processing the previous one.
1617 * The issue can be worked around by issuing a TMDS software reset and
1618 * then write one of the FC registers several times.
1619 *
1620 * The number of iterations matters and depends on the HDMI TX revision
1621 * (and possibly on the platform). So far only i.MX6Q (v1.30a) and
1622 * i.MX6DL (v1.31a) have been identified as needing the workaround, with
1623 * 4 and 1 iterations respectively.
1624 */
1625
1626 switch (hdmi->version) {
1627 case 0x130a:
1628 count = 4;
1629 break;
1630 case 0x131a:
1631 count = 1;
1632 break;
1633 default:
1634 return;
1635 }
1636
1637 /* TMDS software reset */
1638 hdmi_writeb(hdmi, (u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ, HDMI_MC_SWRSTZ);
1639
1640 val = hdmi_readb(hdmi, HDMI_FC_INVIDCONF);
1641 for (i = 0; i < count; i++)
1642 hdmi_writeb(hdmi, val, HDMI_FC_INVIDCONF);
1643 }
1644
1645 static void hdmi_enable_overflow_interrupts(struct dw_hdmi *hdmi)
1646 {
1647 hdmi_writeb(hdmi, 0, HDMI_FC_MASK2);
1648 hdmi_writeb(hdmi, 0, HDMI_IH_MUTE_FC_STAT2);
1649 }
1650
1651 static void hdmi_disable_overflow_interrupts(struct dw_hdmi *hdmi)
1652 {
1653 hdmi_writeb(hdmi, HDMI_IH_MUTE_FC_STAT2_OVERFLOW_MASK,
1654 HDMI_IH_MUTE_FC_STAT2);
1655 }
1656
1657 static int dw_hdmi_setup(struct dw_hdmi *hdmi, struct drm_display_mode *mode)
1658 {
1659 int ret;
1660
1661 hdmi_disable_overflow_interrupts(hdmi);
1662
1663 hdmi->vic = drm_match_cea_mode(mode);
1664
1665 if (!hdmi->vic) {
1666 dev_dbg(hdmi->dev, "Non-CEA mode used in HDMI\n");
1667 } else {
1668 dev_dbg(hdmi->dev, "CEA mode used vic=%d\n", hdmi->vic);
1669 }
1670
1671 if ((hdmi->vic == 6) || (hdmi->vic == 7) ||
1672 (hdmi->vic == 21) || (hdmi->vic == 22) ||
1673 (hdmi->vic == 2) || (hdmi->vic == 3) ||
1674 (hdmi->vic == 17) || (hdmi->vic == 18))
1675 hdmi->hdmi_data.enc_out_encoding = V4L2_YCBCR_ENC_601;
1676 else
1677 hdmi->hdmi_data.enc_out_encoding = V4L2_YCBCR_ENC_709;
1678
1679 hdmi->hdmi_data.video_mode.mpixelrepetitionoutput = 0;
1680 hdmi->hdmi_data.video_mode.mpixelrepetitioninput = 0;
1681
1682 /* TOFIX: Get input format from plat data or fallback to RGB888 */
1683 if (hdmi->plat_data->input_bus_format)
1684 hdmi->hdmi_data.enc_in_bus_format =
1685 hdmi->plat_data->input_bus_format;
1686 else
1687 hdmi->hdmi_data.enc_in_bus_format = MEDIA_BUS_FMT_RGB888_1X24;
1688
1689 /* TOFIX: Get input encoding from plat data or fallback to none */
1690 if (hdmi->plat_data->input_bus_encoding)
1691 hdmi->hdmi_data.enc_in_encoding =
1692 hdmi->plat_data->input_bus_encoding;
1693 else
1694 hdmi->hdmi_data.enc_in_encoding = V4L2_YCBCR_ENC_DEFAULT;
1695
1696 /* TOFIX: Default to RGB888 output format */
1697 hdmi->hdmi_data.enc_out_bus_format = MEDIA_BUS_FMT_RGB888_1X24;
1698
1699 hdmi->hdmi_data.pix_repet_factor = 0;
1700 hdmi->hdmi_data.hdcp_enable = 0;
1701 hdmi->hdmi_data.video_mode.mdataenablepolarity = true;
1702
1703 /* HDMI Initialization Step B.1 */
1704 hdmi_av_composer(hdmi, mode);
1705
1706 /* HDMI Initializateion Step B.2 */
1707 ret = hdmi->phy.ops->init(hdmi, hdmi->phy.data, &hdmi->previous_mode);
1708 if (ret)
1709 return ret;
1710 hdmi->phy.enabled = true;
1711
1712 /* HDMI Initialization Step B.3 */
1713 dw_hdmi_enable_video_path(hdmi);
1714
1715 if (hdmi->sink_has_audio) {
1716 dev_dbg(hdmi->dev, "sink has audio support\n");
1717
1718 /* HDMI Initialization Step E - Configure audio */
1719 hdmi_clk_regenerator_update_pixel_clock(hdmi);
1720 hdmi_enable_audio_clk(hdmi, true);
1721 }
1722
1723 /* not for DVI mode */
1724 if (hdmi->sink_is_hdmi) {
1725 dev_dbg(hdmi->dev, "%s HDMI mode\n", __func__);
1726
1727 /* HDMI Initialization Step F - Configure AVI InfoFrame */
1728 hdmi_config_AVI(hdmi, mode);
1729 hdmi_config_vendor_specific_infoframe(hdmi, mode);
1730 } else {
1731 dev_dbg(hdmi->dev, "%s DVI mode\n", __func__);
1732 }
1733
1734 hdmi_video_packetize(hdmi);
1735 hdmi_video_csc(hdmi);
1736 hdmi_video_sample(hdmi);
1737 hdmi_tx_hdcp_config(hdmi);
1738
1739 dw_hdmi_clear_overflow(hdmi);
1740 if (hdmi->cable_plugin && hdmi->sink_is_hdmi)
1741 hdmi_enable_overflow_interrupts(hdmi);
1742
1743 return 0;
1744 }
1745
1746 static void dw_hdmi_setup_i2c(struct dw_hdmi *hdmi)
1747 {
1748 hdmi_writeb(hdmi, HDMI_PHY_I2CM_INT_ADDR_DONE_POL,
1749 HDMI_PHY_I2CM_INT_ADDR);
1750
1751 hdmi_writeb(hdmi, HDMI_PHY_I2CM_CTLINT_ADDR_NAC_POL |
1752 HDMI_PHY_I2CM_CTLINT_ADDR_ARBITRATION_POL,
1753 HDMI_PHY_I2CM_CTLINT_ADDR);
1754 }
1755
1756 static void initialize_hdmi_ih_mutes(struct dw_hdmi *hdmi)
1757 {
1758 u8 ih_mute;
1759
1760 /*
1761 * Boot up defaults are:
1762 * HDMI_IH_MUTE = 0x03 (disabled)
1763 * HDMI_IH_MUTE_* = 0x00 (enabled)
1764 *
1765 * Disable top level interrupt bits in HDMI block
1766 */
1767 ih_mute = hdmi_readb(hdmi, HDMI_IH_MUTE) |
1768 HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT |
1769 HDMI_IH_MUTE_MUTE_ALL_INTERRUPT;
1770
1771 hdmi_writeb(hdmi, ih_mute, HDMI_IH_MUTE);
1772
1773 /* by default mask all interrupts */
1774 hdmi_writeb(hdmi, 0xff, HDMI_VP_MASK);
1775 hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK0);
1776 hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK1);
1777 hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK2);
1778 hdmi_writeb(hdmi, 0xff, HDMI_PHY_MASK0);
1779 hdmi_writeb(hdmi, 0xff, HDMI_PHY_I2CM_INT_ADDR);
1780 hdmi_writeb(hdmi, 0xff, HDMI_PHY_I2CM_CTLINT_ADDR);
1781 hdmi_writeb(hdmi, 0xff, HDMI_AUD_INT);
1782 hdmi_writeb(hdmi, 0xff, HDMI_AUD_SPDIFINT);
1783 hdmi_writeb(hdmi, 0xff, HDMI_AUD_HBR_MASK);
1784 hdmi_writeb(hdmi, 0xff, HDMI_GP_MASK);
1785 hdmi_writeb(hdmi, 0xff, HDMI_A_APIINTMSK);
1786 hdmi_writeb(hdmi, 0xff, HDMI_CEC_MASK);
1787 hdmi_writeb(hdmi, 0xff, HDMI_I2CM_INT);
1788 hdmi_writeb(hdmi, 0xff, HDMI_I2CM_CTLINT);
1789
1790 /* Disable interrupts in the IH_MUTE_* registers */
1791 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT0);
1792 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT1);
1793 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT2);
1794 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_AS_STAT0);
1795 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_PHY_STAT0);
1796 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_I2CM_STAT0);
1797 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_CEC_STAT0);
1798 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_VP_STAT0);
1799 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_I2CMPHY_STAT0);
1800 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_AHBDMAAUD_STAT0);
1801
1802 /* Enable top level interrupt bits in HDMI block */
1803 ih_mute &= ~(HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT |
1804 HDMI_IH_MUTE_MUTE_ALL_INTERRUPT);
1805 hdmi_writeb(hdmi, ih_mute, HDMI_IH_MUTE);
1806 }
1807
1808 static void dw_hdmi_poweron(struct dw_hdmi *hdmi)
1809 {
1810 hdmi->bridge_is_on = true;
1811 dw_hdmi_setup(hdmi, &hdmi->previous_mode);
1812 }
1813
1814 static void dw_hdmi_poweroff(struct dw_hdmi *hdmi)
1815 {
1816 if (hdmi->phy.enabled) {
1817 hdmi->phy.ops->disable(hdmi, hdmi->phy.data);
1818 hdmi->phy.enabled = false;
1819 }
1820
1821 hdmi->bridge_is_on = false;
1822 }
1823
1824 static void dw_hdmi_update_power(struct dw_hdmi *hdmi)
1825 {
1826 int force = hdmi->force;
1827
1828 if (hdmi->disabled) {
1829 force = DRM_FORCE_OFF;
1830 } else if (force == DRM_FORCE_UNSPECIFIED) {
1831 if (hdmi->rxsense)
1832 force = DRM_FORCE_ON;
1833 else
1834 force = DRM_FORCE_OFF;
1835 }
1836
1837 if (force == DRM_FORCE_OFF) {
1838 if (hdmi->bridge_is_on)
1839 dw_hdmi_poweroff(hdmi);
1840 } else {
1841 if (!hdmi->bridge_is_on)
1842 dw_hdmi_poweron(hdmi);
1843 }
1844 }
1845
1846 /*
1847 * Adjust the detection of RXSENSE according to whether we have a forced
1848 * connection mode enabled, or whether we have been disabled. There is
1849 * no point processing RXSENSE interrupts if we have a forced connection
1850 * state, or DRM has us disabled.
1851 *
1852 * We also disable rxsense interrupts when we think we're disconnected
1853 * to avoid floating TDMS signals giving false rxsense interrupts.
1854 *
1855 * Note: we still need to listen for HPD interrupts even when DRM has us
1856 * disabled so that we can detect a connect event.
1857 */
1858 static void dw_hdmi_update_phy_mask(struct dw_hdmi *hdmi)
1859 {
1860 if (hdmi->phy.ops->update_hpd)
1861 hdmi->phy.ops->update_hpd(hdmi, hdmi->phy.data,
1862 hdmi->force, hdmi->disabled,
1863 hdmi->rxsense);
1864 }
1865
1866 static enum drm_connector_status
1867 dw_hdmi_connector_detect(struct drm_connector *connector, bool force)
1868 {
1869 struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi,
1870 connector);
1871
1872 mutex_lock(&hdmi->mutex);
1873 hdmi->force = DRM_FORCE_UNSPECIFIED;
1874 dw_hdmi_update_power(hdmi);
1875 dw_hdmi_update_phy_mask(hdmi);
1876 mutex_unlock(&hdmi->mutex);
1877
1878 return hdmi->phy.ops->read_hpd(hdmi, hdmi->phy.data);
1879 }
1880
1881 static int dw_hdmi_connector_get_modes(struct drm_connector *connector)
1882 {
1883 struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi,
1884 connector);
1885 struct edid *edid;
1886 int ret = 0;
1887
1888 if (!hdmi->ddc)
1889 return 0;
1890
1891 edid = drm_get_edid(connector, hdmi->ddc);
1892 if (edid) {
1893 dev_dbg(hdmi->dev, "got edid: width[%d] x height[%d]\n",
1894 edid->width_cm, edid->height_cm);
1895
1896 hdmi->sink_is_hdmi = drm_detect_hdmi_monitor(edid);
1897 hdmi->sink_has_audio = drm_detect_monitor_audio(edid);
1898 drm_mode_connector_update_edid_property(connector, edid);
1899 ret = drm_add_edid_modes(connector, edid);
1900 /* Store the ELD */
1901 drm_edid_to_eld(connector, edid);
1902 kfree(edid);
1903 } else {
1904 dev_dbg(hdmi->dev, "failed to get edid\n");
1905 }
1906
1907 return ret;
1908 }
1909
1910 static void dw_hdmi_connector_force(struct drm_connector *connector)
1911 {
1912 struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi,
1913 connector);
1914
1915 mutex_lock(&hdmi->mutex);
1916 hdmi->force = connector->force;
1917 dw_hdmi_update_power(hdmi);
1918 dw_hdmi_update_phy_mask(hdmi);
1919 mutex_unlock(&hdmi->mutex);
1920 }
1921
1922 static const struct drm_connector_funcs dw_hdmi_connector_funcs = {
1923 .dpms = drm_atomic_helper_connector_dpms,
1924 .fill_modes = drm_helper_probe_single_connector_modes,
1925 .detect = dw_hdmi_connector_detect,
1926 .destroy = drm_connector_cleanup,
1927 .force = dw_hdmi_connector_force,
1928 .reset = drm_atomic_helper_connector_reset,
1929 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
1930 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1931 };
1932
1933 static const struct drm_connector_helper_funcs dw_hdmi_connector_helper_funcs = {
1934 .get_modes = dw_hdmi_connector_get_modes,
1935 .best_encoder = drm_atomic_helper_best_encoder,
1936 };
1937
1938 static int dw_hdmi_bridge_attach(struct drm_bridge *bridge)
1939 {
1940 struct dw_hdmi *hdmi = bridge->driver_private;
1941 struct drm_encoder *encoder = bridge->encoder;
1942 struct drm_connector *connector = &hdmi->connector;
1943
1944 connector->interlace_allowed = 1;
1945 connector->polled = DRM_CONNECTOR_POLL_HPD;
1946
1947 drm_connector_helper_add(connector, &dw_hdmi_connector_helper_funcs);
1948
1949 drm_connector_init(bridge->dev, connector, &dw_hdmi_connector_funcs,
1950 DRM_MODE_CONNECTOR_HDMIA);
1951
1952 drm_mode_connector_attach_encoder(connector, encoder);
1953
1954 return 0;
1955 }
1956
1957 static enum drm_mode_status
1958 dw_hdmi_bridge_mode_valid(struct drm_bridge *bridge,
1959 const struct drm_display_mode *mode)
1960 {
1961 struct dw_hdmi *hdmi = bridge->driver_private;
1962 struct drm_connector *connector = &hdmi->connector;
1963 enum drm_mode_status mode_status = MODE_OK;
1964
1965 /* We don't support double-clocked modes */
1966 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
1967 return MODE_BAD;
1968
1969 if (hdmi->plat_data->mode_valid)
1970 mode_status = hdmi->plat_data->mode_valid(connector, mode);
1971
1972 return mode_status;
1973 }
1974
1975 static void dw_hdmi_bridge_mode_set(struct drm_bridge *bridge,
1976 struct drm_display_mode *orig_mode,
1977 struct drm_display_mode *mode)
1978 {
1979 struct dw_hdmi *hdmi = bridge->driver_private;
1980
1981 mutex_lock(&hdmi->mutex);
1982
1983 /* Store the display mode for plugin/DKMS poweron events */
1984 memcpy(&hdmi->previous_mode, mode, sizeof(hdmi->previous_mode));
1985
1986 mutex_unlock(&hdmi->mutex);
1987 }
1988
1989 static void dw_hdmi_bridge_disable(struct drm_bridge *bridge)
1990 {
1991 struct dw_hdmi *hdmi = bridge->driver_private;
1992
1993 mutex_lock(&hdmi->mutex);
1994 hdmi->disabled = true;
1995 dw_hdmi_update_power(hdmi);
1996 dw_hdmi_update_phy_mask(hdmi);
1997 mutex_unlock(&hdmi->mutex);
1998 }
1999
2000 static void dw_hdmi_bridge_enable(struct drm_bridge *bridge)
2001 {
2002 struct dw_hdmi *hdmi = bridge->driver_private;
2003
2004 mutex_lock(&hdmi->mutex);
2005 hdmi->disabled = false;
2006 dw_hdmi_update_power(hdmi);
2007 dw_hdmi_update_phy_mask(hdmi);
2008 mutex_unlock(&hdmi->mutex);
2009 }
2010
2011 static const struct drm_bridge_funcs dw_hdmi_bridge_funcs = {
2012 .attach = dw_hdmi_bridge_attach,
2013 .enable = dw_hdmi_bridge_enable,
2014 .disable = dw_hdmi_bridge_disable,
2015 .mode_set = dw_hdmi_bridge_mode_set,
2016 .mode_valid = dw_hdmi_bridge_mode_valid,
2017 };
2018
2019 static irqreturn_t dw_hdmi_i2c_irq(struct dw_hdmi *hdmi)
2020 {
2021 struct dw_hdmi_i2c *i2c = hdmi->i2c;
2022 unsigned int stat;
2023
2024 stat = hdmi_readb(hdmi, HDMI_IH_I2CM_STAT0);
2025 if (!stat)
2026 return IRQ_NONE;
2027
2028 hdmi_writeb(hdmi, stat, HDMI_IH_I2CM_STAT0);
2029
2030 i2c->stat = stat;
2031
2032 complete(&i2c->cmp);
2033
2034 return IRQ_HANDLED;
2035 }
2036
2037 static irqreturn_t dw_hdmi_hardirq(int irq, void *dev_id)
2038 {
2039 struct dw_hdmi *hdmi = dev_id;
2040 u8 intr_stat;
2041 irqreturn_t ret = IRQ_NONE;
2042
2043 if (hdmi->i2c)
2044 ret = dw_hdmi_i2c_irq(hdmi);
2045
2046 intr_stat = hdmi_readb(hdmi, HDMI_IH_PHY_STAT0);
2047 if (intr_stat) {
2048 hdmi_writeb(hdmi, ~0, HDMI_IH_MUTE_PHY_STAT0);
2049 return IRQ_WAKE_THREAD;
2050 }
2051
2052 return ret;
2053 }
2054
2055 void __dw_hdmi_setup_rx_sense(struct dw_hdmi *hdmi, bool hpd, bool rx_sense)
2056 {
2057 mutex_lock(&hdmi->mutex);
2058
2059 if (!hdmi->force) {
2060 /*
2061 * If the RX sense status indicates we're disconnected,
2062 * clear the software rxsense status.
2063 */
2064 if (!rx_sense)
2065 hdmi->rxsense = false;
2066
2067 /*
2068 * Only set the software rxsense status when both
2069 * rxsense and hpd indicates we're connected.
2070 * This avoids what seems to be bad behaviour in
2071 * at least iMX6S versions of the phy.
2072 */
2073 if (hpd)
2074 hdmi->rxsense = true;
2075
2076 dw_hdmi_update_power(hdmi);
2077 dw_hdmi_update_phy_mask(hdmi);
2078 }
2079 mutex_unlock(&hdmi->mutex);
2080 }
2081
2082 void dw_hdmi_setup_rx_sense(struct device *dev, bool hpd, bool rx_sense)
2083 {
2084 struct dw_hdmi *hdmi = dev_get_drvdata(dev);
2085
2086 __dw_hdmi_setup_rx_sense(hdmi, hpd, rx_sense);
2087 }
2088 EXPORT_SYMBOL_GPL(dw_hdmi_setup_rx_sense);
2089
2090 static irqreturn_t dw_hdmi_irq(int irq, void *dev_id)
2091 {
2092 struct dw_hdmi *hdmi = dev_id;
2093 u8 intr_stat, phy_int_pol, phy_pol_mask, phy_stat;
2094
2095 intr_stat = hdmi_readb(hdmi, HDMI_IH_PHY_STAT0);
2096 phy_int_pol = hdmi_readb(hdmi, HDMI_PHY_POL0);
2097 phy_stat = hdmi_readb(hdmi, HDMI_PHY_STAT0);
2098
2099 phy_pol_mask = 0;
2100 if (intr_stat & HDMI_IH_PHY_STAT0_HPD)
2101 phy_pol_mask |= HDMI_PHY_HPD;
2102 if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE0)
2103 phy_pol_mask |= HDMI_PHY_RX_SENSE0;
2104 if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE1)
2105 phy_pol_mask |= HDMI_PHY_RX_SENSE1;
2106 if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE2)
2107 phy_pol_mask |= HDMI_PHY_RX_SENSE2;
2108 if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE3)
2109 phy_pol_mask |= HDMI_PHY_RX_SENSE3;
2110
2111 if (phy_pol_mask)
2112 hdmi_modb(hdmi, ~phy_int_pol, phy_pol_mask, HDMI_PHY_POL0);
2113
2114 /*
2115 * RX sense tells us whether the TDMS transmitters are detecting
2116 * load - in other words, there's something listening on the
2117 * other end of the link. Use this to decide whether we should
2118 * power on the phy as HPD may be toggled by the sink to merely
2119 * ask the source to re-read the EDID.
2120 */
2121 if (intr_stat &
2122 (HDMI_IH_PHY_STAT0_RX_SENSE | HDMI_IH_PHY_STAT0_HPD))
2123 __dw_hdmi_setup_rx_sense(hdmi,
2124 phy_stat & HDMI_PHY_HPD,
2125 phy_stat & HDMI_PHY_RX_SENSE);
2126
2127 if (intr_stat & HDMI_IH_PHY_STAT0_HPD) {
2128 dev_dbg(hdmi->dev, "EVENT=%s\n",
2129 phy_int_pol & HDMI_PHY_HPD ? "plugin" : "plugout");
2130 if (hdmi->bridge.dev)
2131 drm_helper_hpd_irq_event(hdmi->bridge.dev);
2132 }
2133
2134 hdmi_writeb(hdmi, intr_stat, HDMI_IH_PHY_STAT0);
2135 hdmi_writeb(hdmi, ~(HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE),
2136 HDMI_IH_MUTE_PHY_STAT0);
2137
2138 return IRQ_HANDLED;
2139 }
2140
2141 static const struct dw_hdmi_phy_data dw_hdmi_phys[] = {
2142 {
2143 .type = DW_HDMI_PHY_DWC_HDMI_TX_PHY,
2144 .name = "DWC HDMI TX PHY",
2145 .gen = 1,
2146 }, {
2147 .type = DW_HDMI_PHY_DWC_MHL_PHY_HEAC,
2148 .name = "DWC MHL PHY + HEAC PHY",
2149 .gen = 2,
2150 .has_svsret = true,
2151 .configure = hdmi_phy_configure_dwc_hdmi_3d_tx,
2152 }, {
2153 .type = DW_HDMI_PHY_DWC_MHL_PHY,
2154 .name = "DWC MHL PHY",
2155 .gen = 2,
2156 .has_svsret = true,
2157 .configure = hdmi_phy_configure_dwc_hdmi_3d_tx,
2158 }, {
2159 .type = DW_HDMI_PHY_DWC_HDMI_3D_TX_PHY_HEAC,
2160 .name = "DWC HDMI 3D TX PHY + HEAC PHY",
2161 .gen = 2,
2162 .configure = hdmi_phy_configure_dwc_hdmi_3d_tx,
2163 }, {
2164 .type = DW_HDMI_PHY_DWC_HDMI_3D_TX_PHY,
2165 .name = "DWC HDMI 3D TX PHY",
2166 .gen = 2,
2167 .configure = hdmi_phy_configure_dwc_hdmi_3d_tx,
2168 }, {
2169 .type = DW_HDMI_PHY_DWC_HDMI20_TX_PHY,
2170 .name = "DWC HDMI 2.0 TX PHY",
2171 .gen = 2,
2172 .has_svsret = true,
2173 }, {
2174 .type = DW_HDMI_PHY_VENDOR_PHY,
2175 .name = "Vendor PHY",
2176 }
2177 };
2178
2179 static int dw_hdmi_detect_phy(struct dw_hdmi *hdmi)
2180 {
2181 unsigned int i;
2182 u8 phy_type;
2183
2184 phy_type = hdmi_readb(hdmi, HDMI_CONFIG2_ID);
2185
2186 if (phy_type == DW_HDMI_PHY_VENDOR_PHY) {
2187 /* Vendor PHYs require support from the glue layer. */
2188 if (!hdmi->plat_data->phy_ops || !hdmi->plat_data->phy_name) {
2189 dev_err(hdmi->dev,
2190 "Vendor HDMI PHY not supported by glue layer\n");
2191 return -ENODEV;
2192 }
2193
2194 hdmi->phy.ops = hdmi->plat_data->phy_ops;
2195 hdmi->phy.data = hdmi->plat_data->phy_data;
2196 hdmi->phy.name = hdmi->plat_data->phy_name;
2197 return 0;
2198 }
2199
2200 /* Synopsys PHYs are handled internally. */
2201 for (i = 0; i < ARRAY_SIZE(dw_hdmi_phys); ++i) {
2202 if (dw_hdmi_phys[i].type == phy_type) {
2203 hdmi->phy.ops = &dw_hdmi_synopsys_phy_ops;
2204 hdmi->phy.name = dw_hdmi_phys[i].name;
2205 hdmi->phy.data = (void *)&dw_hdmi_phys[i];
2206
2207 if (!dw_hdmi_phys[i].configure &&
2208 !hdmi->plat_data->configure_phy) {
2209 dev_err(hdmi->dev, "%s requires platform support\n",
2210 hdmi->phy.name);
2211 return -ENODEV;
2212 }
2213
2214 return 0;
2215 }
2216 }
2217
2218 dev_err(hdmi->dev, "Unsupported HDMI PHY type (%02x)\n", phy_type);
2219 return -ENODEV;
2220 }
2221
2222 static const struct regmap_config hdmi_regmap_8bit_config = {
2223 .reg_bits = 32,
2224 .val_bits = 8,
2225 .reg_stride = 1,
2226 .max_register = HDMI_I2CM_FS_SCL_LCNT_0_ADDR,
2227 };
2228
2229 static const struct regmap_config hdmi_regmap_32bit_config = {
2230 .reg_bits = 32,
2231 .val_bits = 32,
2232 .reg_stride = 4,
2233 .max_register = HDMI_I2CM_FS_SCL_LCNT_0_ADDR << 2,
2234 };
2235
2236 static struct dw_hdmi *
2237 __dw_hdmi_probe(struct platform_device *pdev,
2238 const struct dw_hdmi_plat_data *plat_data)
2239 {
2240 struct device *dev = &pdev->dev;
2241 struct device_node *np = dev->of_node;
2242 struct platform_device_info pdevinfo;
2243 struct device_node *ddc_node;
2244 struct dw_hdmi *hdmi;
2245 struct resource *iores = NULL;
2246 int irq;
2247 int ret;
2248 u32 val = 1;
2249 u8 prod_id0;
2250 u8 prod_id1;
2251 u8 config0;
2252 u8 config3;
2253
2254 hdmi = devm_kzalloc(dev, sizeof(*hdmi), GFP_KERNEL);
2255 if (!hdmi)
2256 return ERR_PTR(-ENOMEM);
2257
2258 hdmi->plat_data = plat_data;
2259 hdmi->dev = dev;
2260 hdmi->sample_rate = 48000;
2261 hdmi->disabled = true;
2262 hdmi->rxsense = true;
2263 hdmi->phy_mask = (u8)~(HDMI_PHY_HPD | HDMI_PHY_RX_SENSE);
2264
2265 mutex_init(&hdmi->mutex);
2266 mutex_init(&hdmi->audio_mutex);
2267 spin_lock_init(&hdmi->audio_lock);
2268
2269 ddc_node = of_parse_phandle(np, "ddc-i2c-bus", 0);
2270 if (ddc_node) {
2271 hdmi->ddc = of_get_i2c_adapter_by_node(ddc_node);
2272 of_node_put(ddc_node);
2273 if (!hdmi->ddc) {
2274 dev_dbg(hdmi->dev, "failed to read ddc node\n");
2275 return ERR_PTR(-EPROBE_DEFER);
2276 }
2277
2278 } else {
2279 dev_dbg(hdmi->dev, "no ddc property found\n");
2280 }
2281
2282 if (!plat_data->regm) {
2283 const struct regmap_config *reg_config;
2284
2285 of_property_read_u32(np, "reg-io-width", &val);
2286 switch (val) {
2287 case 4:
2288 reg_config = &hdmi_regmap_32bit_config;
2289 hdmi->reg_shift = 2;
2290 break;
2291 case 1:
2292 reg_config = &hdmi_regmap_8bit_config;
2293 break;
2294 default:
2295 dev_err(dev, "reg-io-width must be 1 or 4\n");
2296 return ERR_PTR(-EINVAL);
2297 }
2298
2299 iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2300 hdmi->regs = devm_ioremap_resource(dev, iores);
2301 if (IS_ERR(hdmi->regs)) {
2302 ret = PTR_ERR(hdmi->regs);
2303 goto err_res;
2304 }
2305
2306 hdmi->regm = devm_regmap_init_mmio(dev, hdmi->regs, reg_config);
2307 if (IS_ERR(hdmi->regm)) {
2308 dev_err(dev, "Failed to configure regmap\n");
2309 ret = PTR_ERR(hdmi->regm);
2310 goto err_res;
2311 }
2312 } else {
2313 hdmi->regm = plat_data->regm;
2314 }
2315
2316 hdmi->isfr_clk = devm_clk_get(hdmi->dev, "isfr");
2317 if (IS_ERR(hdmi->isfr_clk)) {
2318 ret = PTR_ERR(hdmi->isfr_clk);
2319 dev_err(hdmi->dev, "Unable to get HDMI isfr clk: %d\n", ret);
2320 goto err_res;
2321 }
2322
2323 ret = clk_prepare_enable(hdmi->isfr_clk);
2324 if (ret) {
2325 dev_err(hdmi->dev, "Cannot enable HDMI isfr clock: %d\n", ret);
2326 goto err_res;
2327 }
2328
2329 hdmi->iahb_clk = devm_clk_get(hdmi->dev, "iahb");
2330 if (IS_ERR(hdmi->iahb_clk)) {
2331 ret = PTR_ERR(hdmi->iahb_clk);
2332 dev_err(hdmi->dev, "Unable to get HDMI iahb clk: %d\n", ret);
2333 goto err_isfr;
2334 }
2335
2336 ret = clk_prepare_enable(hdmi->iahb_clk);
2337 if (ret) {
2338 dev_err(hdmi->dev, "Cannot enable HDMI iahb clock: %d\n", ret);
2339 goto err_isfr;
2340 }
2341
2342 /* Product and revision IDs */
2343 hdmi->version = (hdmi_readb(hdmi, HDMI_DESIGN_ID) << 8)
2344 | (hdmi_readb(hdmi, HDMI_REVISION_ID) << 0);
2345 prod_id0 = hdmi_readb(hdmi, HDMI_PRODUCT_ID0);
2346 prod_id1 = hdmi_readb(hdmi, HDMI_PRODUCT_ID1);
2347
2348 if (prod_id0 != HDMI_PRODUCT_ID0_HDMI_TX ||
2349 (prod_id1 & ~HDMI_PRODUCT_ID1_HDCP) != HDMI_PRODUCT_ID1_HDMI_TX) {
2350 dev_err(dev, "Unsupported HDMI controller (%04x:%02x:%02x)\n",
2351 hdmi->version, prod_id0, prod_id1);
2352 ret = -ENODEV;
2353 goto err_iahb;
2354 }
2355
2356 ret = dw_hdmi_detect_phy(hdmi);
2357 if (ret < 0)
2358 goto err_iahb;
2359
2360 dev_info(dev, "Detected HDMI TX controller v%x.%03x %s HDCP (%s)\n",
2361 hdmi->version >> 12, hdmi->version & 0xfff,
2362 prod_id1 & HDMI_PRODUCT_ID1_HDCP ? "with" : "without",
2363 hdmi->phy.name);
2364
2365 initialize_hdmi_ih_mutes(hdmi);
2366
2367 irq = platform_get_irq(pdev, 0);
2368 if (irq < 0) {
2369 ret = irq;
2370 goto err_iahb;
2371 }
2372
2373 ret = devm_request_threaded_irq(dev, irq, dw_hdmi_hardirq,
2374 dw_hdmi_irq, IRQF_SHARED,
2375 dev_name(dev), hdmi);
2376 if (ret)
2377 goto err_iahb;
2378
2379 /*
2380 * To prevent overflows in HDMI_IH_FC_STAT2, set the clk regenerator
2381 * N and cts values before enabling phy
2382 */
2383 hdmi_init_clk_regenerator(hdmi);
2384
2385 /* If DDC bus is not specified, try to register HDMI I2C bus */
2386 if (!hdmi->ddc) {
2387 hdmi->ddc = dw_hdmi_i2c_adapter(hdmi);
2388 if (IS_ERR(hdmi->ddc))
2389 hdmi->ddc = NULL;
2390 }
2391
2392 hdmi->bridge.driver_private = hdmi;
2393 hdmi->bridge.funcs = &dw_hdmi_bridge_funcs;
2394 #ifdef CONFIG_OF
2395 hdmi->bridge.of_node = pdev->dev.of_node;
2396 #endif
2397
2398 dw_hdmi_setup_i2c(hdmi);
2399 if (hdmi->phy.ops->setup_hpd)
2400 hdmi->phy.ops->setup_hpd(hdmi, hdmi->phy.data);
2401
2402 memset(&pdevinfo, 0, sizeof(pdevinfo));
2403 pdevinfo.parent = dev;
2404 pdevinfo.id = PLATFORM_DEVID_AUTO;
2405
2406 config0 = hdmi_readb(hdmi, HDMI_CONFIG0_ID);
2407 config3 = hdmi_readb(hdmi, HDMI_CONFIG3_ID);
2408
2409 if (iores && config3 & HDMI_CONFIG3_AHBAUDDMA) {
2410 struct dw_hdmi_audio_data audio;
2411
2412 audio.phys = iores->start;
2413 audio.base = hdmi->regs;
2414 audio.irq = irq;
2415 audio.hdmi = hdmi;
2416 audio.eld = hdmi->connector.eld;
2417 hdmi->enable_audio = dw_hdmi_ahb_audio_enable;
2418 hdmi->disable_audio = dw_hdmi_ahb_audio_disable;
2419
2420 pdevinfo.name = "dw-hdmi-ahb-audio";
2421 pdevinfo.data = &audio;
2422 pdevinfo.size_data = sizeof(audio);
2423 pdevinfo.dma_mask = DMA_BIT_MASK(32);
2424 hdmi->audio = platform_device_register_full(&pdevinfo);
2425 } else if (config0 & HDMI_CONFIG0_I2S) {
2426 struct dw_hdmi_i2s_audio_data audio;
2427
2428 audio.hdmi = hdmi;
2429 audio.write = hdmi_writeb;
2430 audio.read = hdmi_readb;
2431 hdmi->enable_audio = dw_hdmi_i2s_audio_enable;
2432 hdmi->disable_audio = dw_hdmi_i2s_audio_disable;
2433
2434 pdevinfo.name = "dw-hdmi-i2s-audio";
2435 pdevinfo.data = &audio;
2436 pdevinfo.size_data = sizeof(audio);
2437 pdevinfo.dma_mask = DMA_BIT_MASK(32);
2438 hdmi->audio = platform_device_register_full(&pdevinfo);
2439 }
2440
2441 /* Reset HDMI DDC I2C master controller and mute I2CM interrupts */
2442 if (hdmi->i2c)
2443 dw_hdmi_i2c_init(hdmi);
2444
2445 platform_set_drvdata(pdev, hdmi);
2446
2447 return hdmi;
2448
2449 err_iahb:
2450 if (hdmi->i2c) {
2451 i2c_del_adapter(&hdmi->i2c->adap);
2452 hdmi->ddc = NULL;
2453 }
2454
2455 clk_disable_unprepare(hdmi->iahb_clk);
2456 err_isfr:
2457 clk_disable_unprepare(hdmi->isfr_clk);
2458 err_res:
2459 i2c_put_adapter(hdmi->ddc);
2460
2461 return ERR_PTR(ret);
2462 }
2463
2464 static void __dw_hdmi_remove(struct dw_hdmi *hdmi)
2465 {
2466 if (hdmi->audio && !IS_ERR(hdmi->audio))
2467 platform_device_unregister(hdmi->audio);
2468
2469 /* Disable all interrupts */
2470 hdmi_writeb(hdmi, ~0, HDMI_IH_MUTE_PHY_STAT0);
2471
2472 clk_disable_unprepare(hdmi->iahb_clk);
2473 clk_disable_unprepare(hdmi->isfr_clk);
2474
2475 if (hdmi->i2c)
2476 i2c_del_adapter(&hdmi->i2c->adap);
2477 else
2478 i2c_put_adapter(hdmi->ddc);
2479 }
2480
2481 /* -----------------------------------------------------------------------------
2482 * Probe/remove API, used from platforms based on the DRM bridge API.
2483 */
2484 int dw_hdmi_probe(struct platform_device *pdev,
2485 const struct dw_hdmi_plat_data *plat_data)
2486 {
2487 struct dw_hdmi *hdmi;
2488 int ret;
2489
2490 hdmi = __dw_hdmi_probe(pdev, plat_data);
2491 if (IS_ERR(hdmi))
2492 return PTR_ERR(hdmi);
2493
2494 ret = drm_bridge_add(&hdmi->bridge);
2495 if (ret < 0) {
2496 __dw_hdmi_remove(hdmi);
2497 return ret;
2498 }
2499
2500 return 0;
2501 }
2502 EXPORT_SYMBOL_GPL(dw_hdmi_probe);
2503
2504 void dw_hdmi_remove(struct platform_device *pdev)
2505 {
2506 struct dw_hdmi *hdmi = platform_get_drvdata(pdev);
2507
2508 drm_bridge_remove(&hdmi->bridge);
2509
2510 __dw_hdmi_remove(hdmi);
2511 }
2512 EXPORT_SYMBOL_GPL(dw_hdmi_remove);
2513
2514 /* -----------------------------------------------------------------------------
2515 * Bind/unbind API, used from platforms based on the component framework.
2516 */
2517 int dw_hdmi_bind(struct platform_device *pdev, struct drm_encoder *encoder,
2518 const struct dw_hdmi_plat_data *plat_data)
2519 {
2520 struct dw_hdmi *hdmi;
2521 int ret;
2522
2523 hdmi = __dw_hdmi_probe(pdev, plat_data);
2524 if (IS_ERR(hdmi))
2525 return PTR_ERR(hdmi);
2526
2527 ret = drm_bridge_attach(encoder, &hdmi->bridge, NULL);
2528 if (ret) {
2529 dw_hdmi_remove(pdev);
2530 DRM_ERROR("Failed to initialize bridge with drm\n");
2531 return ret;
2532 }
2533
2534 return 0;
2535 }
2536 EXPORT_SYMBOL_GPL(dw_hdmi_bind);
2537
2538 void dw_hdmi_unbind(struct device *dev)
2539 {
2540 struct dw_hdmi *hdmi = dev_get_drvdata(dev);
2541
2542 __dw_hdmi_remove(hdmi);
2543 }
2544 EXPORT_SYMBOL_GPL(dw_hdmi_unbind);
2545
2546 MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>");
2547 MODULE_AUTHOR("Andy Yan <andy.yan@rock-chips.com>");
2548 MODULE_AUTHOR("Yakir Yang <ykk@rock-chips.com>");
2549 MODULE_AUTHOR("Vladimir Zapolskiy <vladimir_zapolskiy@mentor.com>");
2550 MODULE_DESCRIPTION("DW HDMI transmitter driver");
2551 MODULE_LICENSE("GPL");
2552 MODULE_ALIAS("platform:dw-hdmi");
Linux with added FPC-III support