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rcutorture: Eliminate unused ts_rem local from rcu_trace_clock_local()
[linux/fpc-iii.git] / drivers / gpu / drm / bridge / tc358767.c
blob5c26488e7a2d7a0320ddf321375b8ff4c200185f
1 /*
2 * tc358767 eDP bridge driver
3 *
4 * Copyright (C) 2016 CogentEmbedded Inc
5 * Author: Andrey Gusakov <andrey.gusakov@cogentembedded.com>
6 *
7 * Copyright (C) 2016 Pengutronix, Philipp Zabel <p.zabel@pengutronix.de>
8 *
9 * Initially based on: drivers/gpu/drm/i2c/tda998x_drv.c
10 *
11 * Copyright (C) 2012 Texas Instruments
12 * Author: Rob Clark <robdclark@gmail.com>
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 */
24
25 #include <linux/clk.h>
26 #include <linux/device.h>
27 #include <linux/gpio/consumer.h>
28 #include <linux/i2c.h>
29 #include <linux/kernel.h>
30 #include <linux/module.h>
31 #include <linux/regmap.h>
32 #include <linux/slab.h>
33
34 #include <drm/drm_atomic_helper.h>
35 #include <drm/drm_crtc_helper.h>
36 #include <drm/drm_dp_helper.h>
37 #include <drm/drm_edid.h>
38 #include <drm/drm_of.h>
39 #include <drm/drm_panel.h>
40
41 /* Registers */
42
43 /* Display Parallel Interface */
44 #define DPIPXLFMT 0x0440
45 #define VS_POL_ACTIVE_LOW (1 << 10)
46 #define HS_POL_ACTIVE_LOW (1 << 9)
47 #define DE_POL_ACTIVE_HIGH (0 << 8)
48 #define SUB_CFG_TYPE_CONFIG1 (0 << 2) /* LSB aligned */
49 #define SUB_CFG_TYPE_CONFIG2 (1 << 2) /* Loosely Packed */
50 #define SUB_CFG_TYPE_CONFIG3 (2 << 2) /* LSB aligned 8-bit */
51 #define DPI_BPP_RGB888 (0 << 0)
52 #define DPI_BPP_RGB666 (1 << 0)
53 #define DPI_BPP_RGB565 (2 << 0)
54
55 /* Video Path */
56 #define VPCTRL0 0x0450
57 #define OPXLFMT_RGB666 (0 << 8)
58 #define OPXLFMT_RGB888 (1 << 8)
59 #define FRMSYNC_DISABLED (0 << 4) /* Video Timing Gen Disabled */
60 #define FRMSYNC_ENABLED (1 << 4) /* Video Timing Gen Enabled */
61 #define MSF_DISABLED (0 << 0) /* Magic Square FRC disabled */
62 #define MSF_ENABLED (1 << 0) /* Magic Square FRC enabled */
63 #define HTIM01 0x0454
64 #define HTIM02 0x0458
65 #define VTIM01 0x045c
66 #define VTIM02 0x0460
67 #define VFUEN0 0x0464
68 #define VFUEN BIT(0) /* Video Frame Timing Upload */
69
70 /* System */
71 #define TC_IDREG 0x0500
72 #define SYSCTRL 0x0510
73 #define DP0_AUDSRC_NO_INPUT (0 << 3)
74 #define DP0_AUDSRC_I2S_RX (1 << 3)
75 #define DP0_VIDSRC_NO_INPUT (0 << 0)
76 #define DP0_VIDSRC_DSI_RX (1 << 0)
77 #define DP0_VIDSRC_DPI_RX (2 << 0)
78 #define DP0_VIDSRC_COLOR_BAR (3 << 0)
79
80 /* Control */
81 #define DP0CTL 0x0600
82 #define VID_MN_GEN BIT(6) /* Auto-generate M/N values */
83 #define EF_EN BIT(5) /* Enable Enhanced Framing */
84 #define VID_EN BIT(1) /* Video transmission enable */
85 #define DP_EN BIT(0) /* Enable DPTX function */
86
87 /* Clocks */
88 #define DP0_VIDMNGEN0 0x0610
89 #define DP0_VIDMNGEN1 0x0614
90 #define DP0_VMNGENSTATUS 0x0618
91
92 /* Main Channel */
93 #define DP0_SECSAMPLE 0x0640
94 #define DP0_VIDSYNCDELAY 0x0644
95 #define DP0_TOTALVAL 0x0648
96 #define DP0_STARTVAL 0x064c
97 #define DP0_ACTIVEVAL 0x0650
98 #define DP0_SYNCVAL 0x0654
99 #define DP0_MISC 0x0658
100 #define TU_SIZE_RECOMMENDED (0x3f << 16) /* LSCLK cycles per TU */
101 #define BPC_6 (0 << 5)
102 #define BPC_8 (1 << 5)
103
104 /* AUX channel */
105 #define DP0_AUXCFG0 0x0660
106 #define DP0_AUXCFG1 0x0664
107 #define AUX_RX_FILTER_EN BIT(16)
108
109 #define DP0_AUXADDR 0x0668
110 #define DP0_AUXWDATA(i) (0x066c + (i) * 4)
111 #define DP0_AUXRDATA(i) (0x067c + (i) * 4)
112 #define DP0_AUXSTATUS 0x068c
113 #define AUX_STATUS_MASK 0xf0
114 #define AUX_STATUS_SHIFT 4
115 #define AUX_TIMEOUT BIT(1)
116 #define AUX_BUSY BIT(0)
117 #define DP0_AUXI2CADR 0x0698
118
119 /* Link Training */
120 #define DP0_SRCCTRL 0x06a0
121 #define DP0_SRCCTRL_SCRMBLDIS BIT(13)
122 #define DP0_SRCCTRL_EN810B BIT(12)
123 #define DP0_SRCCTRL_NOTP (0 << 8)
124 #define DP0_SRCCTRL_TP1 (1 << 8)
125 #define DP0_SRCCTRL_TP2 (2 << 8)
126 #define DP0_SRCCTRL_LANESKEW BIT(7)
127 #define DP0_SRCCTRL_SSCG BIT(3)
128 #define DP0_SRCCTRL_LANES_1 (0 << 2)
129 #define DP0_SRCCTRL_LANES_2 (1 << 2)
130 #define DP0_SRCCTRL_BW27 (1 << 1)
131 #define DP0_SRCCTRL_BW162 (0 << 1)
132 #define DP0_SRCCTRL_AUTOCORRECT BIT(0)
133 #define DP0_LTSTAT 0x06d0
134 #define LT_LOOPDONE BIT(13)
135 #define LT_STATUS_MASK (0x1f << 8)
136 #define LT_CHANNEL1_EQ_BITS (DP_CHANNEL_EQ_BITS << 4)
137 #define LT_INTERLANE_ALIGN_DONE BIT(3)
138 #define LT_CHANNEL0_EQ_BITS (DP_CHANNEL_EQ_BITS)
139 #define DP0_SNKLTCHGREQ 0x06d4
140 #define DP0_LTLOOPCTRL 0x06d8
141 #define DP0_SNKLTCTRL 0x06e4
142
143 /* PHY */
144 #define DP_PHY_CTRL 0x0800
145 #define DP_PHY_RST BIT(28) /* DP PHY Global Soft Reset */
146 #define BGREN BIT(25) /* AUX PHY BGR Enable */
147 #define PWR_SW_EN BIT(24) /* PHY Power Switch Enable */
148 #define PHY_M1_RST BIT(12) /* Reset PHY1 Main Channel */
149 #define PHY_RDY BIT(16) /* PHY Main Channels Ready */
150 #define PHY_M0_RST BIT(8) /* Reset PHY0 Main Channel */
151 #define PHY_A0_EN BIT(1) /* PHY Aux Channel0 Enable */
152 #define PHY_M0_EN BIT(0) /* PHY Main Channel0 Enable */
153
154 /* PLL */
155 #define DP0_PLLCTRL 0x0900
156 #define DP1_PLLCTRL 0x0904 /* not defined in DS */
157 #define PXL_PLLCTRL 0x0908
158 #define PLLUPDATE BIT(2)
159 #define PLLBYP BIT(1)
160 #define PLLEN BIT(0)
161 #define PXL_PLLPARAM 0x0914
162 #define IN_SEL_REFCLK (0 << 14)
163 #define SYS_PLLPARAM 0x0918
164 #define REF_FREQ_38M4 (0 << 8) /* 38.4 MHz */
165 #define REF_FREQ_19M2 (1 << 8) /* 19.2 MHz */
166 #define REF_FREQ_26M (2 << 8) /* 26 MHz */
167 #define REF_FREQ_13M (3 << 8) /* 13 MHz */
168 #define SYSCLK_SEL_LSCLK (0 << 4)
169 #define LSCLK_DIV_1 (0 << 0)
170 #define LSCLK_DIV_2 (1 << 0)
171
172 /* Test & Debug */
173 #define TSTCTL 0x0a00
174 #define PLL_DBG 0x0a04
175
176 static bool tc_test_pattern;
177 module_param_named(test, tc_test_pattern, bool, 0644);
178
179 struct tc_edp_link {
180 struct drm_dp_link base;
181 u8 assr;
182 int scrambler_dis;
183 int spread;
184 int coding8b10b;
185 u8 swing;
186 u8 preemp;
187 };
188
189 struct tc_data {
190 struct device *dev;
191 struct regmap *regmap;
192 struct drm_dp_aux aux;
193
194 struct drm_bridge bridge;
195 struct drm_connector connector;
196 struct drm_panel *panel;
197
198 /* link settings */
199 struct tc_edp_link link;
200
201 /* display edid */
202 struct edid *edid;
203 /* current mode */
204 struct drm_display_mode *mode;
205
206 u32 rev;
207 u8 assr;
208
209 struct gpio_desc *sd_gpio;
210 struct gpio_desc *reset_gpio;
211 struct clk *refclk;
212 };
213
214 static inline struct tc_data *aux_to_tc(struct drm_dp_aux *a)
215 {
216 return container_of(a, struct tc_data, aux);
217 }
218
219 static inline struct tc_data *bridge_to_tc(struct drm_bridge *b)
220 {
221 return container_of(b, struct tc_data, bridge);
222 }
223
224 static inline struct tc_data *connector_to_tc(struct drm_connector *c)
225 {
226 return container_of(c, struct tc_data, connector);
227 }
228
229 /* Simple macros to avoid repeated error checks */
230 #define tc_write(reg, var) \
231 do { \
232 ret = regmap_write(tc->regmap, reg, var); \
233 if (ret) \
234 goto err; \
235 } while (0)
236 #define tc_read(reg, var) \
237 do { \
238 ret = regmap_read(tc->regmap, reg, var); \
239 if (ret) \
240 goto err; \
241 } while (0)
242
243 static inline int tc_poll_timeout(struct regmap *map, unsigned int addr,
244 unsigned int cond_mask,
245 unsigned int cond_value,
246 unsigned long sleep_us, u64 timeout_us)
247 {
248 ktime_t timeout = ktime_add_us(ktime_get(), timeout_us);
249 unsigned int val;
250 int ret;
251
252 for (;;) {
253 ret = regmap_read(map, addr, &val);
254 if (ret)
255 break;
256 if ((val & cond_mask) == cond_value)
257 break;
258 if (timeout_us && ktime_compare(ktime_get(), timeout) > 0) {
259 ret = regmap_read(map, addr, &val);
260 break;
261 }
262 if (sleep_us)
263 usleep_range((sleep_us >> 2) + 1, sleep_us);
264 }
265 return ret ?: (((val & cond_mask) == cond_value) ? 0 : -ETIMEDOUT);
266 }
267
268 static int tc_aux_wait_busy(struct tc_data *tc, unsigned int timeout_ms)
269 {
270 return tc_poll_timeout(tc->regmap, DP0_AUXSTATUS, AUX_BUSY, 0,
271 1000, 1000 * timeout_ms);
272 }
273
274 static int tc_aux_get_status(struct tc_data *tc, u8 *reply)
275 {
276 int ret;
277 u32 value;
278
279 ret = regmap_read(tc->regmap, DP0_AUXSTATUS, &value);
280 if (ret < 0)
281 return ret;
282 if (value & AUX_BUSY) {
283 if (value & AUX_TIMEOUT) {
284 dev_err(tc->dev, "i2c access timeout!\n");
285 return -ETIMEDOUT;
286 }
287 return -EBUSY;
288 }
289
290 *reply = (value & AUX_STATUS_MASK) >> AUX_STATUS_SHIFT;
291 return 0;
292 }
293
294 static ssize_t tc_aux_transfer(struct drm_dp_aux *aux,
295 struct drm_dp_aux_msg *msg)
296 {
297 struct tc_data *tc = aux_to_tc(aux);
298 size_t size = min_t(size_t, 8, msg->size);
299 u8 request = msg->request & ~DP_AUX_I2C_MOT;
300 u8 *buf = msg->buffer;
301 u32 tmp = 0;
302 int i = 0;
303 int ret;
304
305 if (size == 0)
306 return 0;
307
308 ret = tc_aux_wait_busy(tc, 100);
309 if (ret)
310 goto err;
311
312 if (request == DP_AUX_I2C_WRITE || request == DP_AUX_NATIVE_WRITE) {
313 /* Store data */
314 while (i < size) {
315 if (request == DP_AUX_NATIVE_WRITE)
316 tmp = tmp | (buf[i] << (8 * (i & 0x3)));
317 else
318 tmp = (tmp << 8) | buf[i];
319 i++;
320 if (((i % 4) == 0) || (i == size)) {
321 tc_write(DP0_AUXWDATA(i >> 2), tmp);
322 tmp = 0;
323 }
324 }
325 } else if (request != DP_AUX_I2C_READ &&
326 request != DP_AUX_NATIVE_READ) {
327 return -EINVAL;
328 }
329
330 /* Store address */
331 tc_write(DP0_AUXADDR, msg->address);
332 /* Start transfer */
333 tc_write(DP0_AUXCFG0, ((size - 1) << 8) | request);
334
335 ret = tc_aux_wait_busy(tc, 100);
336 if (ret)
337 goto err;
338
339 ret = tc_aux_get_status(tc, &msg->reply);
340 if (ret)
341 goto err;
342
343 if (request == DP_AUX_I2C_READ || request == DP_AUX_NATIVE_READ) {
344 /* Read data */
345 while (i < size) {
346 if ((i % 4) == 0)
347 tc_read(DP0_AUXRDATA(i >> 2), &tmp);
348 buf[i] = tmp & 0xff;
349 tmp = tmp >> 8;
350 i++;
351 }
352 }
353
354 return size;
355 err:
356 return ret;
357 }
358
359 static const char * const training_pattern1_errors[] = {
360 "No errors",
361 "Aux write error",
362 "Aux read error",
363 "Max voltage reached error",
364 "Loop counter expired error",
365 "res", "res", "res"
366 };
367
368 static const char * const training_pattern2_errors[] = {
369 "No errors",
370 "Aux write error",
371 "Aux read error",
372 "Clock recovery failed error",
373 "Loop counter expired error",
374 "res", "res", "res"
375 };
376
377 static u32 tc_srcctrl(struct tc_data *tc)
378 {
379 /*
380 * No training pattern, skew lane 1 data by two LSCLK cycles with
381 * respect to lane 0 data, AutoCorrect Mode = 0
382 */
383 u32 reg = DP0_SRCCTRL_NOTP | DP0_SRCCTRL_LANESKEW;
384
385 if (tc->link.scrambler_dis)
386 reg |= DP0_SRCCTRL_SCRMBLDIS; /* Scrambler Disabled */
387 if (tc->link.coding8b10b)
388 /* Enable 8/10B Encoder (TxData[19:16] not used) */
389 reg |= DP0_SRCCTRL_EN810B;
390 if (tc->link.spread)
391 reg |= DP0_SRCCTRL_SSCG; /* Spread Spectrum Enable */
392 if (tc->link.base.num_lanes == 2)
393 reg |= DP0_SRCCTRL_LANES_2; /* Two Main Channel Lanes */
394 if (tc->link.base.rate != 162000)
395 reg |= DP0_SRCCTRL_BW27; /* 2.7 Gbps link */
396 return reg;
397 }
398
399 static void tc_wait_pll_lock(struct tc_data *tc)
400 {
401 /* Wait for PLL to lock: up to 2.09 ms, depending on refclk */
402 usleep_range(3000, 6000);
403 }
404
405 static int tc_pxl_pll_en(struct tc_data *tc, u32 refclk, u32 pixelclock)
406 {
407 int ret;
408 int i_pre, best_pre = 1;
409 int i_post, best_post = 1;
410 int div, best_div = 1;
411 int mul, best_mul = 1;
412 int delta, best_delta;
413 int ext_div[] = {1, 2, 3, 5, 7};
414 int best_pixelclock = 0;
415 int vco_hi = 0;
416
417 dev_dbg(tc->dev, "PLL: requested %d pixelclock, ref %d\n", pixelclock,
418 refclk);
419 best_delta = pixelclock;
420 /* Loop over all possible ext_divs, skipping invalid configurations */
421 for (i_pre = 0; i_pre < ARRAY_SIZE(ext_div); i_pre++) {
422 /*
423 * refclk / ext_pre_div should be in the 1 to 200 MHz range.
424 * We don't allow any refclk > 200 MHz, only check lower bounds.
425 */
426 if (refclk / ext_div[i_pre] < 1000000)
427 continue;
428 for (i_post = 0; i_post < ARRAY_SIZE(ext_div); i_post++) {
429 for (div = 1; div <= 16; div++) {
430 u32 clk;
431 u64 tmp;
432
433 tmp = pixelclock * ext_div[i_pre] *
434 ext_div[i_post] * div;
435 do_div(tmp, refclk);
436 mul = tmp;
437
438 /* Check limits */
439 if ((mul < 1) || (mul > 128))
440 continue;
441
442 clk = (refclk / ext_div[i_pre] / div) * mul;
443 /*
444 * refclk * mul / (ext_pre_div * pre_div)
445 * should be in the 150 to 650 MHz range
446 */
447 if ((clk > 650000000) || (clk < 150000000))
448 continue;
449
450 clk = clk / ext_div[i_post];
451 delta = clk - pixelclock;
452
453 if (abs(delta) < abs(best_delta)) {
454 best_pre = i_pre;
455 best_post = i_post;
456 best_div = div;
457 best_mul = mul;
458 best_delta = delta;
459 best_pixelclock = clk;
460 }
461 }
462 }
463 }
464 if (best_pixelclock == 0) {
465 dev_err(tc->dev, "Failed to calc clock for %d pixelclock\n",
466 pixelclock);
467 return -EINVAL;
468 }
469
470 dev_dbg(tc->dev, "PLL: got %d, delta %d\n", best_pixelclock,
471 best_delta);
472 dev_dbg(tc->dev, "PLL: %d / %d / %d * %d / %d\n", refclk,
473 ext_div[best_pre], best_div, best_mul, ext_div[best_post]);
474
475 /* if VCO >= 300 MHz */
476 if (refclk / ext_div[best_pre] / best_div * best_mul >= 300000000)
477 vco_hi = 1;
478 /* see DS */
479 if (best_div == 16)
480 best_div = 0;
481 if (best_mul == 128)
482 best_mul = 0;
483
484 /* Power up PLL and switch to bypass */
485 tc_write(PXL_PLLCTRL, PLLBYP | PLLEN);
486
487 tc_write(PXL_PLLPARAM,
488 (vco_hi << 24) | /* For PLL VCO >= 300 MHz = 1 */
489 (ext_div[best_pre] << 20) | /* External Pre-divider */
490 (ext_div[best_post] << 16) | /* External Post-divider */
491 IN_SEL_REFCLK | /* Use RefClk as PLL input */
492 (best_div << 8) | /* Divider for PLL RefClk */
493 (best_mul << 0)); /* Multiplier for PLL */
494
495 /* Force PLL parameter update and disable bypass */
496 tc_write(PXL_PLLCTRL, PLLUPDATE | PLLEN);
497
498 tc_wait_pll_lock(tc);
499
500 return 0;
501 err:
502 return ret;
503 }
504
505 static int tc_pxl_pll_dis(struct tc_data *tc)
506 {
507 /* Enable PLL bypass, power down PLL */
508 return regmap_write(tc->regmap, PXL_PLLCTRL, PLLBYP);
509 }
510
511 static int tc_stream_clock_calc(struct tc_data *tc)
512 {
513 int ret;
514 /*
515 * If the Stream clock and Link Symbol clock are
516 * asynchronous with each other, the value of M changes over
517 * time. This way of generating link clock and stream
518 * clock is called Asynchronous Clock mode. The value M
519 * must change while the value N stays constant. The
520 * value of N in this Asynchronous Clock mode must be set
521 * to 2^15 or 32,768.
522 *
523 * LSCLK = 1/10 of high speed link clock
524 *
525 * f_STRMCLK = M/N * f_LSCLK
526 * M/N = f_STRMCLK / f_LSCLK
527 *
528 */
529 tc_write(DP0_VIDMNGEN1, 32768);
530
531 return 0;
532 err:
533 return ret;
534 }
535
536 static int tc_aux_link_setup(struct tc_data *tc)
537 {
538 unsigned long rate;
539 u32 value;
540 int ret;
541
542 rate = clk_get_rate(tc->refclk);
543 switch (rate) {
544 case 38400000:
545 value = REF_FREQ_38M4;
546 break;
547 case 26000000:
548 value = REF_FREQ_26M;
549 break;
550 case 19200000:
551 value = REF_FREQ_19M2;
552 break;
553 case 13000000:
554 value = REF_FREQ_13M;
555 break;
556 default:
557 dev_err(tc->dev, "Invalid refclk rate: %lu Hz\n", rate);
558 return -EINVAL;
559 }
560
561 /* Setup DP-PHY / PLL */
562 value |= SYSCLK_SEL_LSCLK | LSCLK_DIV_2;
563 tc_write(SYS_PLLPARAM, value);
564
565 tc_write(DP_PHY_CTRL, BGREN | PWR_SW_EN | BIT(2) | PHY_A0_EN);
566
567 /*
568 * Initially PLLs are in bypass. Force PLL parameter update,
569 * disable PLL bypass, enable PLL
570 */
571 tc_write(DP0_PLLCTRL, PLLUPDATE | PLLEN);
572 tc_wait_pll_lock(tc);
573
574 tc_write(DP1_PLLCTRL, PLLUPDATE | PLLEN);
575 tc_wait_pll_lock(tc);
576
577 ret = tc_poll_timeout(tc->regmap, DP_PHY_CTRL, PHY_RDY, PHY_RDY, 1,
578 1000);
579 if (ret == -ETIMEDOUT) {
580 dev_err(tc->dev, "Timeout waiting for PHY to become ready");
581 return ret;
582 } else if (ret)
583 goto err;
584
585 /* Setup AUX link */
586 tc_write(DP0_AUXCFG1, AUX_RX_FILTER_EN |
587 (0x06 << 8) | /* Aux Bit Period Calculator Threshold */
588 (0x3f << 0)); /* Aux Response Timeout Timer */
589
590 return 0;
591 err:
592 dev_err(tc->dev, "tc_aux_link_setup failed: %d\n", ret);
593 return ret;
594 }
595
596 static int tc_get_display_props(struct tc_data *tc)
597 {
598 int ret;
599 /* temp buffer */
600 u8 tmp[8];
601
602 /* Read DP Rx Link Capability */
603 ret = drm_dp_link_probe(&tc->aux, &tc->link.base);
604 if (ret < 0)
605 goto err_dpcd_read;
606 if ((tc->link.base.rate != 162000) && (tc->link.base.rate != 270000))
607 goto err_dpcd_inval;
608
609 ret = drm_dp_dpcd_readb(&tc->aux, DP_MAX_DOWNSPREAD, tmp);
610 if (ret < 0)
611 goto err_dpcd_read;
612 tc->link.spread = tmp[0] & BIT(0); /* 0.5% down spread */
613
614 ret = drm_dp_dpcd_readb(&tc->aux, DP_MAIN_LINK_CHANNEL_CODING, tmp);
615 if (ret < 0)
616 goto err_dpcd_read;
617 tc->link.coding8b10b = tmp[0] & BIT(0);
618 tc->link.scrambler_dis = 0;
619 /* read assr */
620 ret = drm_dp_dpcd_readb(&tc->aux, DP_EDP_CONFIGURATION_SET, tmp);
621 if (ret < 0)
622 goto err_dpcd_read;
623 tc->link.assr = tmp[0] & DP_ALTERNATE_SCRAMBLER_RESET_ENABLE;
624
625 dev_dbg(tc->dev, "DPCD rev: %d.%d, rate: %s, lanes: %d, framing: %s\n",
626 tc->link.base.revision >> 4, tc->link.base.revision & 0x0f,
627 (tc->link.base.rate == 162000) ? "1.62Gbps" : "2.7Gbps",
628 tc->link.base.num_lanes,
629 (tc->link.base.capabilities & DP_LINK_CAP_ENHANCED_FRAMING) ?
630 "enhanced" : "non-enhanced");
631 dev_dbg(tc->dev, "ANSI 8B/10B: %d\n", tc->link.coding8b10b);
632 dev_dbg(tc->dev, "Display ASSR: %d, TC358767 ASSR: %d\n",
633 tc->link.assr, tc->assr);
634
635 return 0;
636
637 err_dpcd_read:
638 dev_err(tc->dev, "failed to read DPCD: %d\n", ret);
639 return ret;
640 err_dpcd_inval:
641 dev_err(tc->dev, "invalid DPCD\n");
642 return -EINVAL;
643 }
644
645 static int tc_set_video_mode(struct tc_data *tc, struct drm_display_mode *mode)
646 {
647 int ret;
648 int vid_sync_dly;
649 int max_tu_symbol;
650
651 int left_margin = mode->htotal - mode->hsync_end;
652 int right_margin = mode->hsync_start - mode->hdisplay;
653 int hsync_len = mode->hsync_end - mode->hsync_start;
654 int upper_margin = mode->vtotal - mode->vsync_end;
655 int lower_margin = mode->vsync_start - mode->vdisplay;
656 int vsync_len = mode->vsync_end - mode->vsync_start;
657
658 dev_dbg(tc->dev, "set mode %dx%d\n",
659 mode->hdisplay, mode->vdisplay);
660 dev_dbg(tc->dev, "H margin %d,%d sync %d\n",
661 left_margin, right_margin, hsync_len);
662 dev_dbg(tc->dev, "V margin %d,%d sync %d\n",
663 upper_margin, lower_margin, vsync_len);
664 dev_dbg(tc->dev, "total: %dx%d\n", mode->htotal, mode->vtotal);
665
666
667 /* LCD Ctl Frame Size */
668 tc_write(VPCTRL0, (0x40 << 20) /* VSDELAY */ |
669 OPXLFMT_RGB888 | FRMSYNC_DISABLED | MSF_DISABLED);
670 tc_write(HTIM01, (left_margin << 16) | /* H back porch */
671 (hsync_len << 0)); /* Hsync */
672 tc_write(HTIM02, (right_margin << 16) | /* H front porch */
673 (mode->hdisplay << 0)); /* width */
674 tc_write(VTIM01, (upper_margin << 16) | /* V back porch */
675 (vsync_len << 0)); /* Vsync */
676 tc_write(VTIM02, (lower_margin << 16) | /* V front porch */
677 (mode->vdisplay << 0)); /* height */
678 tc_write(VFUEN0, VFUEN); /* update settings */
679
680 /* Test pattern settings */
681 tc_write(TSTCTL,
682 (120 << 24) | /* Red Color component value */
683 (20 << 16) | /* Green Color component value */
684 (99 << 8) | /* Blue Color component value */
685 (1 << 4) | /* Enable I2C Filter */
686 (2 << 0) | /* Color bar Mode */
687 0);
688
689 /* DP Main Stream Attributes */
690 vid_sync_dly = hsync_len + left_margin + mode->hdisplay;
691 tc_write(DP0_VIDSYNCDELAY,
692 (0x003e << 16) | /* thresh_dly */
693 (vid_sync_dly << 0));
694
695 tc_write(DP0_TOTALVAL, (mode->vtotal << 16) | (mode->htotal));
696
697 tc_write(DP0_STARTVAL,
698 ((upper_margin + vsync_len) << 16) |
699 ((left_margin + hsync_len) << 0));
700
701 tc_write(DP0_ACTIVEVAL, (mode->vdisplay << 16) | (mode->hdisplay));
702
703 tc_write(DP0_SYNCVAL, (vsync_len << 16) | (hsync_len << 0));
704
705 tc_write(DPIPXLFMT, VS_POL_ACTIVE_LOW | HS_POL_ACTIVE_LOW |
706 DE_POL_ACTIVE_HIGH | SUB_CFG_TYPE_CONFIG1 | DPI_BPP_RGB888);
707
708 /*
709 * Recommended maximum number of symbols transferred in a transfer unit:
710 * DIV_ROUND_UP((input active video bandwidth in bytes) * tu_size,
711 * (output active video bandwidth in bytes))
712 * Must be less than tu_size.
713 */
714 max_tu_symbol = TU_SIZE_RECOMMENDED - 1;
715 tc_write(DP0_MISC, (max_tu_symbol << 23) | TU_SIZE_RECOMMENDED | BPC_8);
716
717 return 0;
718 err:
719 return ret;
720 }
721
722 static int tc_link_training(struct tc_data *tc, int pattern)
723 {
724 const char * const *errors;
725 u32 srcctrl = tc_srcctrl(tc) | DP0_SRCCTRL_SCRMBLDIS |
726 DP0_SRCCTRL_AUTOCORRECT;
727 int timeout;
728 int retry;
729 u32 value;
730 int ret;
731
732 if (pattern == DP_TRAINING_PATTERN_1) {
733 srcctrl |= DP0_SRCCTRL_TP1;
734 errors = training_pattern1_errors;
735 } else {
736 srcctrl |= DP0_SRCCTRL_TP2;
737 errors = training_pattern2_errors;
738 }
739
740 /* Set DPCD 0x102 for Training Part 1 or 2 */
741 tc_write(DP0_SNKLTCTRL, DP_LINK_SCRAMBLING_DISABLE | pattern);
742
743 tc_write(DP0_LTLOOPCTRL,
744 (0x0f << 28) | /* Defer Iteration Count */
745 (0x0f << 24) | /* Loop Iteration Count */
746 (0x0d << 0)); /* Loop Timer Delay */
747
748 retry = 5;
749 do {
750 /* Set DP0 Training Pattern */
751 tc_write(DP0_SRCCTRL, srcctrl);
752
753 /* Enable DP0 to start Link Training */
754 tc_write(DP0CTL, DP_EN);
755
756 /* wait */
757 timeout = 1000;
758 do {
759 tc_read(DP0_LTSTAT, &value);
760 udelay(1);
761 } while ((!(value & LT_LOOPDONE)) && (--timeout));
762 if (timeout == 0) {
763 dev_err(tc->dev, "Link training timeout!\n");
764 } else {
765 int pattern = (value >> 11) & 0x3;
766 int error = (value >> 8) & 0x7;
767
768 dev_dbg(tc->dev,
769 "Link training phase %d done after %d uS: %s\n",
770 pattern, 1000 - timeout, errors[error]);
771 if (pattern == DP_TRAINING_PATTERN_1 && error == 0)
772 break;
773 if (pattern == DP_TRAINING_PATTERN_2) {
774 value &= LT_CHANNEL1_EQ_BITS |
775 LT_INTERLANE_ALIGN_DONE |
776 LT_CHANNEL0_EQ_BITS;
777 /* in case of two lanes */
778 if ((tc->link.base.num_lanes == 2) &&
779 (value == (LT_CHANNEL1_EQ_BITS |
780 LT_INTERLANE_ALIGN_DONE |
781 LT_CHANNEL0_EQ_BITS)))
782 break;
783 /* in case of one line */
784 if ((tc->link.base.num_lanes == 1) &&
785 (value == (LT_INTERLANE_ALIGN_DONE |
786 LT_CHANNEL0_EQ_BITS)))
787 break;
788 }
789 }
790 /* restart */
791 tc_write(DP0CTL, 0);
792 usleep_range(10, 20);
793 } while (--retry);
794 if (retry == 0) {
795 dev_err(tc->dev, "Failed to finish training phase %d\n",
796 pattern);
797 }
798
799 return 0;
800 err:
801 return ret;
802 }
803
804 static int tc_main_link_setup(struct tc_data *tc)
805 {
806 struct drm_dp_aux *aux = &tc->aux;
807 struct device *dev = tc->dev;
808 unsigned int rate;
809 u32 dp_phy_ctrl;
810 int timeout;
811 bool aligned;
812 bool ready;
813 u32 value;
814 int ret;
815 u8 tmp[8];
816
817 /* display mode should be set at this point */
818 if (!tc->mode)
819 return -EINVAL;
820
821 /* from excel file - DP0_SrcCtrl */
822 tc_write(DP0_SRCCTRL, DP0_SRCCTRL_SCRMBLDIS | DP0_SRCCTRL_EN810B |
823 DP0_SRCCTRL_LANESKEW | DP0_SRCCTRL_LANES_2 |
824 DP0_SRCCTRL_BW27 | DP0_SRCCTRL_AUTOCORRECT);
825 /* from excel file - DP1_SrcCtrl */
826 tc_write(0x07a0, 0x00003083);
827
828 rate = clk_get_rate(tc->refclk);
829 switch (rate) {
830 case 38400000:
831 value = REF_FREQ_38M4;
832 break;
833 case 26000000:
834 value = REF_FREQ_26M;
835 break;
836 case 19200000:
837 value = REF_FREQ_19M2;
838 break;
839 case 13000000:
840 value = REF_FREQ_13M;
841 break;
842 default:
843 return -EINVAL;
844 }
845 value |= SYSCLK_SEL_LSCLK | LSCLK_DIV_2;
846 tc_write(SYS_PLLPARAM, value);
847 /* Setup Main Link */
848 dp_phy_ctrl = BGREN | PWR_SW_EN | BIT(2) | PHY_A0_EN | PHY_M0_EN;
849 tc_write(DP_PHY_CTRL, dp_phy_ctrl);
850 msleep(100);
851
852 /* PLL setup */
853 tc_write(DP0_PLLCTRL, PLLUPDATE | PLLEN);
854 tc_wait_pll_lock(tc);
855
856 tc_write(DP1_PLLCTRL, PLLUPDATE | PLLEN);
857 tc_wait_pll_lock(tc);
858
859 /* PXL PLL setup */
860 if (tc_test_pattern) {
861 ret = tc_pxl_pll_en(tc, clk_get_rate(tc->refclk),
862 1000 * tc->mode->clock);
863 if (ret)
864 goto err;
865 }
866
867 /* Reset/Enable Main Links */
868 dp_phy_ctrl |= DP_PHY_RST | PHY_M1_RST | PHY_M0_RST;
869 tc_write(DP_PHY_CTRL, dp_phy_ctrl);
870 usleep_range(100, 200);
871 dp_phy_ctrl &= ~(DP_PHY_RST | PHY_M1_RST | PHY_M0_RST);
872 tc_write(DP_PHY_CTRL, dp_phy_ctrl);
873
874 timeout = 1000;
875 do {
876 tc_read(DP_PHY_CTRL, &value);
877 udelay(1);
878 } while ((!(value & PHY_RDY)) && (--timeout));
879
880 if (timeout == 0) {
881 dev_err(dev, "timeout waiting for phy become ready");
882 return -ETIMEDOUT;
883 }
884
885 /* Set misc: 8 bits per color */
886 ret = regmap_update_bits(tc->regmap, DP0_MISC, BPC_8, BPC_8);
887 if (ret)
888 goto err;
889
890 /*
891 * ASSR mode
892 * on TC358767 side ASSR configured through strap pin
893 * seems there is no way to change this setting from SW
894 *
895 * check is tc configured for same mode
896 */
897 if (tc->assr != tc->link.assr) {
898 dev_dbg(dev, "Trying to set display to ASSR: %d\n",
899 tc->assr);
900 /* try to set ASSR on display side */
901 tmp[0] = tc->assr;
902 ret = drm_dp_dpcd_writeb(aux, DP_EDP_CONFIGURATION_SET, tmp[0]);
903 if (ret < 0)
904 goto err_dpcd_read;
905 /* read back */
906 ret = drm_dp_dpcd_readb(aux, DP_EDP_CONFIGURATION_SET, tmp);
907 if (ret < 0)
908 goto err_dpcd_read;
909
910 if (tmp[0] != tc->assr) {
911 dev_dbg(dev, "Failed to switch display ASSR to %d, falling back to unscrambled mode\n",
912 tc->assr);
913 /* trying with disabled scrambler */
914 tc->link.scrambler_dis = 1;
915 }
916 }
917
918 /* Setup Link & DPRx Config for Training */
919 ret = drm_dp_link_configure(aux, &tc->link.base);
920 if (ret < 0)
921 goto err_dpcd_write;
922
923 /* DOWNSPREAD_CTRL */
924 tmp[0] = tc->link.spread ? DP_SPREAD_AMP_0_5 : 0x00;
925 /* MAIN_LINK_CHANNEL_CODING_SET */
926 tmp[1] = tc->link.coding8b10b ? DP_SET_ANSI_8B10B : 0x00;
927 ret = drm_dp_dpcd_write(aux, DP_DOWNSPREAD_CTRL, tmp, 2);
928 if (ret < 0)
929 goto err_dpcd_write;
930
931 ret = tc_link_training(tc, DP_TRAINING_PATTERN_1);
932 if (ret)
933 goto err;
934
935 ret = tc_link_training(tc, DP_TRAINING_PATTERN_2);
936 if (ret)
937 goto err;
938
939 /* Clear DPCD 0x102 */
940 /* Note: Can Not use DP0_SNKLTCTRL (0x06E4) short cut */
941 tmp[0] = tc->link.scrambler_dis ? DP_LINK_SCRAMBLING_DISABLE : 0x00;
942 ret = drm_dp_dpcd_writeb(aux, DP_TRAINING_PATTERN_SET, tmp[0]);
943 if (ret < 0)
944 goto err_dpcd_write;
945
946 /* Clear Training Pattern, set AutoCorrect Mode = 1 */
947 tc_write(DP0_SRCCTRL, tc_srcctrl(tc) | DP0_SRCCTRL_AUTOCORRECT);
948
949 /* Wait */
950 timeout = 100;
951 do {
952 udelay(1);
953 /* Read DPCD 0x202-0x207 */
954 ret = drm_dp_dpcd_read_link_status(aux, tmp + 2);
955 if (ret < 0)
956 goto err_dpcd_read;
957 ready = (tmp[2] == ((DP_CHANNEL_EQ_BITS << 4) | /* Lane1 */
958 DP_CHANNEL_EQ_BITS)); /* Lane0 */
959 aligned = tmp[4] & DP_INTERLANE_ALIGN_DONE;
960 } while ((--timeout) && !(ready && aligned));
961
962 if (timeout == 0) {
963 /* Read DPCD 0x200-0x201 */
964 ret = drm_dp_dpcd_read(aux, DP_SINK_COUNT, tmp, 2);
965 if (ret < 0)
966 goto err_dpcd_read;
967 dev_info(dev, "0x0200 SINK_COUNT: 0x%02x\n", tmp[0]);
968 dev_info(dev, "0x0201 DEVICE_SERVICE_IRQ_VECTOR: 0x%02x\n",
969 tmp[1]);
970 dev_info(dev, "0x0202 LANE0_1_STATUS: 0x%02x\n", tmp[2]);
971 dev_info(dev, "0x0204 LANE_ALIGN_STATUS_UPDATED: 0x%02x\n",
972 tmp[4]);
973 dev_info(dev, "0x0205 SINK_STATUS: 0x%02x\n", tmp[5]);
974 dev_info(dev, "0x0206 ADJUST_REQUEST_LANE0_1: 0x%02x\n",
975 tmp[6]);
976
977 if (!ready)
978 dev_err(dev, "Lane0/1 not ready\n");
979 if (!aligned)
980 dev_err(dev, "Lane0/1 not aligned\n");
981 return -EAGAIN;
982 }
983
984 ret = tc_set_video_mode(tc, tc->mode);
985 if (ret)
986 goto err;
987
988 /* Set M/N */
989 ret = tc_stream_clock_calc(tc);
990 if (ret)
991 goto err;
992
993 return 0;
994 err_dpcd_read:
995 dev_err(tc->dev, "Failed to read DPCD: %d\n", ret);
996 return ret;
997 err_dpcd_write:
998 dev_err(tc->dev, "Failed to write DPCD: %d\n", ret);
999 err:
1000 return ret;
1001 }
1002
1003 static int tc_main_link_stream(struct tc_data *tc, int state)
1004 {
1005 int ret;
1006 u32 value;
1007
1008 dev_dbg(tc->dev, "stream: %d\n", state);
1009
1010 if (state) {
1011 value = VID_MN_GEN | DP_EN;
1012 if (tc->link.base.capabilities & DP_LINK_CAP_ENHANCED_FRAMING)
1013 value |= EF_EN;
1014 tc_write(DP0CTL, value);
1015 /*
1016 * VID_EN assertion should be delayed by at least N * LSCLK
1017 * cycles from the time VID_MN_GEN is enabled in order to
1018 * generate stable values for VID_M. LSCLK is 270 MHz or
1019 * 162 MHz, VID_N is set to 32768 in tc_stream_clock_calc(),
1020 * so a delay of at least 203 us should suffice.
1021 */
1022 usleep_range(500, 1000);
1023 value |= VID_EN;
1024 tc_write(DP0CTL, value);
1025 /* Set input interface */
1026 value = DP0_AUDSRC_NO_INPUT;
1027 if (tc_test_pattern)
1028 value |= DP0_VIDSRC_COLOR_BAR;
1029 else
1030 value |= DP0_VIDSRC_DPI_RX;
1031 tc_write(SYSCTRL, value);
1032 } else {
1033 tc_write(DP0CTL, 0);
1034 }
1035
1036 return 0;
1037 err:
1038 return ret;
1039 }
1040
1041 static void tc_bridge_pre_enable(struct drm_bridge *bridge)
1042 {
1043 struct tc_data *tc = bridge_to_tc(bridge);
1044
1045 drm_panel_prepare(tc->panel);
1046 }
1047
1048 static void tc_bridge_enable(struct drm_bridge *bridge)
1049 {
1050 struct tc_data *tc = bridge_to_tc(bridge);
1051 int ret;
1052
1053 ret = tc_main_link_setup(tc);
1054 if (ret < 0) {
1055 dev_err(tc->dev, "main link setup error: %d\n", ret);
1056 return;
1057 }
1058
1059 ret = tc_main_link_stream(tc, 1);
1060 if (ret < 0) {
1061 dev_err(tc->dev, "main link stream start error: %d\n", ret);
1062 return;
1063 }
1064
1065 drm_panel_enable(tc->panel);
1066 }
1067
1068 static void tc_bridge_disable(struct drm_bridge *bridge)
1069 {
1070 struct tc_data *tc = bridge_to_tc(bridge);
1071 int ret;
1072
1073 drm_panel_disable(tc->panel);
1074
1075 ret = tc_main_link_stream(tc, 0);
1076 if (ret < 0)
1077 dev_err(tc->dev, "main link stream stop error: %d\n", ret);
1078 }
1079
1080 static void tc_bridge_post_disable(struct drm_bridge *bridge)
1081 {
1082 struct tc_data *tc = bridge_to_tc(bridge);
1083
1084 drm_panel_unprepare(tc->panel);
1085 }
1086
1087 static bool tc_bridge_mode_fixup(struct drm_bridge *bridge,
1088 const struct drm_display_mode *mode,
1089 struct drm_display_mode *adj)
1090 {
1091 /* Fixup sync polarities, both hsync and vsync are active low */
1092 adj->flags = mode->flags;
1093 adj->flags |= (DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC);
1094 adj->flags &= ~(DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC);
1095
1096 return true;
1097 }
1098
1099 static int tc_connector_mode_valid(struct drm_connector *connector,
1100 struct drm_display_mode *mode)
1101 {
1102 /* Accept any mode */
1103 return MODE_OK;
1104 }
1105
1106 static void tc_bridge_mode_set(struct drm_bridge *bridge,
1107 struct drm_display_mode *mode,
1108 struct drm_display_mode *adj)
1109 {
1110 struct tc_data *tc = bridge_to_tc(bridge);
1111
1112 tc->mode = mode;
1113 }
1114
1115 static int tc_connector_get_modes(struct drm_connector *connector)
1116 {
1117 struct tc_data *tc = connector_to_tc(connector);
1118 struct edid *edid;
1119 unsigned int count;
1120
1121 if (tc->panel && tc->panel->funcs && tc->panel->funcs->get_modes) {
1122 count = tc->panel->funcs->get_modes(tc->panel);
1123 if (count > 0)
1124 return count;
1125 }
1126
1127 edid = drm_get_edid(connector, &tc->aux.ddc);
1128
1129 kfree(tc->edid);
1130 tc->edid = edid;
1131 if (!edid)
1132 return 0;
1133
1134 drm_mode_connector_update_edid_property(connector, edid);
1135 count = drm_add_edid_modes(connector, edid);
1136
1137 return count;
1138 }
1139
1140 static void tc_connector_set_polling(struct tc_data *tc,
1141 struct drm_connector *connector)
1142 {
1143 /* TODO: add support for HPD */
1144 connector->polled = DRM_CONNECTOR_POLL_CONNECT |
1145 DRM_CONNECTOR_POLL_DISCONNECT;
1146 }
1147
1148 static struct drm_encoder *
1149 tc_connector_best_encoder(struct drm_connector *connector)
1150 {
1151 struct tc_data *tc = connector_to_tc(connector);
1152
1153 return tc->bridge.encoder;
1154 }
1155
1156 static const struct drm_connector_helper_funcs tc_connector_helper_funcs = {
1157 .get_modes = tc_connector_get_modes,
1158 .mode_valid = tc_connector_mode_valid,
1159 .best_encoder = tc_connector_best_encoder,
1160 };
1161
1162 static const struct drm_connector_funcs tc_connector_funcs = {
1163 .dpms = drm_atomic_helper_connector_dpms,
1164 .fill_modes = drm_helper_probe_single_connector_modes,
1165 .destroy = drm_connector_cleanup,
1166 .reset = drm_atomic_helper_connector_reset,
1167 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
1168 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1169 };
1170
1171 static int tc_bridge_attach(struct drm_bridge *bridge)
1172 {
1173 u32 bus_format = MEDIA_BUS_FMT_RGB888_1X24;
1174 struct tc_data *tc = bridge_to_tc(bridge);
1175 struct drm_device *drm = bridge->dev;
1176 int ret;
1177
1178 /* Create eDP connector */
1179 drm_connector_helper_add(&tc->connector, &tc_connector_helper_funcs);
1180 ret = drm_connector_init(drm, &tc->connector, &tc_connector_funcs,
1181 DRM_MODE_CONNECTOR_eDP);
1182 if (ret)
1183 return ret;
1184
1185 if (tc->panel)
1186 drm_panel_attach(tc->panel, &tc->connector);
1187
1188 drm_display_info_set_bus_formats(&tc->connector.display_info,
1189 &bus_format, 1);
1190 drm_mode_connector_attach_encoder(&tc->connector, tc->bridge.encoder);
1191
1192 return 0;
1193 }
1194
1195 static const struct drm_bridge_funcs tc_bridge_funcs = {
1196 .attach = tc_bridge_attach,
1197 .mode_set = tc_bridge_mode_set,
1198 .pre_enable = tc_bridge_pre_enable,
1199 .enable = tc_bridge_enable,
1200 .disable = tc_bridge_disable,
1201 .post_disable = tc_bridge_post_disable,
1202 .mode_fixup = tc_bridge_mode_fixup,
1203 };
1204
1205 static bool tc_readable_reg(struct device *dev, unsigned int reg)
1206 {
1207 return reg != SYSCTRL;
1208 }
1209
1210 static const struct regmap_range tc_volatile_ranges[] = {
1211 regmap_reg_range(DP0_AUXWDATA(0), DP0_AUXSTATUS),
1212 regmap_reg_range(DP0_LTSTAT, DP0_SNKLTCHGREQ),
1213 regmap_reg_range(DP_PHY_CTRL, DP_PHY_CTRL),
1214 regmap_reg_range(DP0_PLLCTRL, PXL_PLLCTRL),
1215 regmap_reg_range(VFUEN0, VFUEN0),
1216 };
1217
1218 static const struct regmap_access_table tc_volatile_table = {
1219 .yes_ranges = tc_volatile_ranges,
1220 .n_yes_ranges = ARRAY_SIZE(tc_volatile_ranges),
1221 };
1222
1223 static bool tc_writeable_reg(struct device *dev, unsigned int reg)
1224 {
1225 return (reg != TC_IDREG) &&
1226 (reg != DP0_LTSTAT) &&
1227 (reg != DP0_SNKLTCHGREQ);
1228 }
1229
1230 static const struct regmap_config tc_regmap_config = {
1231 .name = "tc358767",
1232 .reg_bits = 16,
1233 .val_bits = 32,
1234 .reg_stride = 4,
1235 .max_register = PLL_DBG,
1236 .cache_type = REGCACHE_RBTREE,
1237 .readable_reg = tc_readable_reg,
1238 .volatile_table = &tc_volatile_table,
1239 .writeable_reg = tc_writeable_reg,
1240 .reg_format_endian = REGMAP_ENDIAN_BIG,
1241 .val_format_endian = REGMAP_ENDIAN_LITTLE,
1242 };
1243
1244 static int tc_probe(struct i2c_client *client, const struct i2c_device_id *id)
1245 {
1246 struct device *dev = &client->dev;
1247 struct tc_data *tc;
1248 int ret;
1249
1250 tc = devm_kzalloc(dev, sizeof(*tc), GFP_KERNEL);
1251 if (!tc)
1252 return -ENOMEM;
1253
1254 tc->dev = dev;
1255
1256 /* port@2 is the output port */
1257 ret = drm_of_find_panel_or_bridge(dev->of_node, 2, 0, &tc->panel, NULL);
1258 if (ret)
1259 return ret;
1260
1261 /* Shut down GPIO is optional */
1262 tc->sd_gpio = devm_gpiod_get_optional(dev, "shutdown", GPIOD_OUT_HIGH);
1263 if (IS_ERR(tc->sd_gpio))
1264 return PTR_ERR(tc->sd_gpio);
1265
1266 if (tc->sd_gpio) {
1267 gpiod_set_value_cansleep(tc->sd_gpio, 0);
1268 usleep_range(5000, 10000);
1269 }
1270
1271 /* Reset GPIO is optional */
1272 tc->reset_gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW);
1273 if (IS_ERR(tc->reset_gpio))
1274 return PTR_ERR(tc->reset_gpio);
1275
1276 if (tc->reset_gpio) {
1277 gpiod_set_value_cansleep(tc->reset_gpio, 1);
1278 usleep_range(5000, 10000);
1279 }
1280
1281 tc->refclk = devm_clk_get(dev, "ref");
1282 if (IS_ERR(tc->refclk)) {
1283 ret = PTR_ERR(tc->refclk);
1284 dev_err(dev, "Failed to get refclk: %d\n", ret);
1285 return ret;
1286 }
1287
1288 tc->regmap = devm_regmap_init_i2c(client, &tc_regmap_config);
1289 if (IS_ERR(tc->regmap)) {
1290 ret = PTR_ERR(tc->regmap);
1291 dev_err(dev, "Failed to initialize regmap: %d\n", ret);
1292 return ret;
1293 }
1294
1295 ret = regmap_read(tc->regmap, TC_IDREG, &tc->rev);
1296 if (ret) {
1297 dev_err(tc->dev, "can not read device ID: %d\n", ret);
1298 return ret;
1299 }
1300
1301 if ((tc->rev != 0x6601) && (tc->rev != 0x6603)) {
1302 dev_err(tc->dev, "invalid device ID: 0x%08x\n", tc->rev);
1303 return -EINVAL;
1304 }
1305
1306 tc->assr = (tc->rev == 0x6601); /* Enable ASSR for eDP panels */
1307
1308 ret = tc_aux_link_setup(tc);
1309 if (ret)
1310 return ret;
1311
1312 /* Register DP AUX channel */
1313 tc->aux.name = "TC358767 AUX i2c adapter";
1314 tc->aux.dev = tc->dev;
1315 tc->aux.transfer = tc_aux_transfer;
1316 ret = drm_dp_aux_register(&tc->aux);
1317 if (ret)
1318 return ret;
1319
1320 ret = tc_get_display_props(tc);
1321 if (ret)
1322 goto err_unregister_aux;
1323
1324 tc_connector_set_polling(tc, &tc->connector);
1325
1326 tc->bridge.funcs = &tc_bridge_funcs;
1327 tc->bridge.of_node = dev->of_node;
1328 ret = drm_bridge_add(&tc->bridge);
1329 if (ret) {
1330 dev_err(dev, "Failed to add drm_bridge: %d\n", ret);
1331 goto err_unregister_aux;
1332 }
1333
1334 i2c_set_clientdata(client, tc);
1335
1336 return 0;
1337 err_unregister_aux:
1338 drm_dp_aux_unregister(&tc->aux);
1339 return ret;
1340 }
1341
1342 static int tc_remove(struct i2c_client *client)
1343 {
1344 struct tc_data *tc = i2c_get_clientdata(client);
1345
1346 drm_bridge_remove(&tc->bridge);
1347 drm_dp_aux_unregister(&tc->aux);
1348
1349 tc_pxl_pll_dis(tc);
1350
1351 return 0;
1352 }
1353
1354 static const struct i2c_device_id tc358767_i2c_ids[] = {
1355 { "tc358767", 0 },
1356 { }
1357 };
1358 MODULE_DEVICE_TABLE(i2c, tc358767_i2c_ids);
1359
1360 static const struct of_device_id tc358767_of_ids[] = {
1361 { .compatible = "toshiba,tc358767", },
1362 { }
1363 };
1364 MODULE_DEVICE_TABLE(of, tc358767_of_ids);
1365
1366 static struct i2c_driver tc358767_driver = {
1367 .driver = {
1368 .name = "tc358767",
1369 .of_match_table = tc358767_of_ids,
1370 },
1371 .id_table = tc358767_i2c_ids,
1372 .probe = tc_probe,
1373 .remove = tc_remove,
1374 };
1375 module_i2c_driver(tc358767_driver);
1376
1377 MODULE_AUTHOR("Andrey Gusakov <andrey.gusakov@cogentembedded.com>");
1378 MODULE_DESCRIPTION("tc358767 eDP encoder driver");
1379 MODULE_LICENSE("GPL");
Linux with added FPC-III support