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rcutorture: Eliminate unused ts_rem local from rcu_trace_clock_local()
[linux/fpc-iii.git] / drivers / gpu / drm / exynos / exynos5433_drm_decon.c
blob5792ca88ab7a3718a8e24e58003468ac95e9b46b
1 /* drivers/gpu/drm/exynos5433_drm_decon.c
2 *
3 * Copyright (C) 2015 Samsung Electronics Co.Ltd
4 * Authors:
5 * Joonyoung Shim <jy0922.shim@samsung.com>
6 * Hyungwon Hwang <human.hwang@samsung.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundationr
11 */
12
13 #include <linux/platform_device.h>
14 #include <linux/clk.h>
15 #include <linux/component.h>
16 #include <linux/mfd/syscon.h>
17 #include <linux/of_device.h>
18 #include <linux/of_gpio.h>
19 #include <linux/pm_runtime.h>
20 #include <linux/regmap.h>
21
22 #include <video/exynos5433_decon.h>
23
24 #include "exynos_drm_drv.h"
25 #include "exynos_drm_crtc.h"
26 #include "exynos_drm_fb.h"
27 #include "exynos_drm_plane.h"
28 #include "exynos_drm_iommu.h"
29
30 #define DSD_CFG_MUX 0x1004
31 #define DSD_CFG_MUX_TE_UNMASK_GLOBAL BIT(13)
32
33 #define WINDOWS_NR 3
34 #define MIN_FB_WIDTH_FOR_16WORD_BURST 128
35
36 #define IFTYPE_I80 (1 << 0)
37 #define I80_HW_TRG (1 << 1)
38 #define IFTYPE_HDMI (1 << 2)
39
40 static const char * const decon_clks_name[] = {
41 "pclk",
42 "aclk_decon",
43 "aclk_smmu_decon0x",
44 "aclk_xiu_decon0x",
45 "pclk_smmu_decon0x",
46 "sclk_decon_vclk",
47 "sclk_decon_eclk",
48 };
49
50 struct decon_context {
51 struct device *dev;
52 struct drm_device *drm_dev;
53 struct exynos_drm_crtc *crtc;
54 struct exynos_drm_plane planes[WINDOWS_NR];
55 struct exynos_drm_plane_config configs[WINDOWS_NR];
56 void __iomem *addr;
57 struct regmap *sysreg;
58 struct clk *clks[ARRAY_SIZE(decon_clks_name)];
59 unsigned int irq;
60 unsigned int te_irq;
61 unsigned long out_type;
62 int first_win;
63 spinlock_t vblank_lock;
64 u32 frame_id;
65 };
66
67 static const uint32_t decon_formats[] = {
68 DRM_FORMAT_XRGB1555,
69 DRM_FORMAT_RGB565,
70 DRM_FORMAT_XRGB8888,
71 DRM_FORMAT_ARGB8888,
72 };
73
74 static const enum drm_plane_type decon_win_types[WINDOWS_NR] = {
75 DRM_PLANE_TYPE_PRIMARY,
76 DRM_PLANE_TYPE_OVERLAY,
77 DRM_PLANE_TYPE_CURSOR,
78 };
79
80 static inline void decon_set_bits(struct decon_context *ctx, u32 reg, u32 mask,
81 u32 val)
82 {
83 val = (val & mask) | (readl(ctx->addr + reg) & ~mask);
84 writel(val, ctx->addr + reg);
85 }
86
87 static int decon_enable_vblank(struct exynos_drm_crtc *crtc)
88 {
89 struct decon_context *ctx = crtc->ctx;
90 u32 val;
91
92 val = VIDINTCON0_INTEN;
93 if (ctx->out_type & IFTYPE_I80)
94 val |= VIDINTCON0_FRAMEDONE;
95 else
96 val |= VIDINTCON0_INTFRMEN | VIDINTCON0_FRAMESEL_FP;
97
98 writel(val, ctx->addr + DECON_VIDINTCON0);
99
100 enable_irq(ctx->irq);
101 if (!(ctx->out_type & I80_HW_TRG))
102 enable_irq(ctx->te_irq);
103
104 return 0;
105 }
106
107 static void decon_disable_vblank(struct exynos_drm_crtc *crtc)
108 {
109 struct decon_context *ctx = crtc->ctx;
110
111 if (!(ctx->out_type & I80_HW_TRG))
112 disable_irq_nosync(ctx->te_irq);
113 disable_irq_nosync(ctx->irq);
114
115 writel(0, ctx->addr + DECON_VIDINTCON0);
116 }
117
118 /* return number of starts/ends of frame transmissions since reset */
119 static u32 decon_get_frame_count(struct decon_context *ctx, bool end)
120 {
121 u32 frm, pfrm, status, cnt = 2;
122
123 /* To get consistent result repeat read until frame id is stable.
124 * Usually the loop will be executed once, in rare cases when the loop
125 * is executed at frame change time 2nd pass will be needed.
126 */
127 frm = readl(ctx->addr + DECON_CRFMID);
128 do {
129 status = readl(ctx->addr + DECON_VIDCON1);
130 pfrm = frm;
131 frm = readl(ctx->addr + DECON_CRFMID);
132 } while (frm != pfrm && --cnt);
133
134 /* CRFMID is incremented on BPORCH in case of I80 and on VSYNC in case
135 * of RGB, it should be taken into account.
136 */
137 if (!frm)
138 return 0;
139
140 switch (status & (VIDCON1_VSTATUS_MASK | VIDCON1_I80_ACTIVE)) {
141 case VIDCON1_VSTATUS_VS:
142 if (!(ctx->out_type & IFTYPE_I80))
143 --frm;
144 break;
145 case VIDCON1_VSTATUS_BP:
146 --frm;
147 break;
148 case VIDCON1_I80_ACTIVE:
149 case VIDCON1_VSTATUS_AC:
150 if (end)
151 --frm;
152 break;
153 default:
154 break;
155 }
156
157 return frm;
158 }
159
160 static u32 decon_get_vblank_counter(struct exynos_drm_crtc *crtc)
161 {
162 struct decon_context *ctx = crtc->ctx;
163
164 return decon_get_frame_count(ctx, false);
165 }
166
167 static void decon_setup_trigger(struct decon_context *ctx)
168 {
169 if (!(ctx->out_type & (IFTYPE_I80 | I80_HW_TRG)))
170 return;
171
172 if (!(ctx->out_type & I80_HW_TRG)) {
173 writel(TRIGCON_TRIGEN_PER_F | TRIGCON_TRIGEN_F |
174 TRIGCON_TE_AUTO_MASK | TRIGCON_SWTRIGEN,
175 ctx->addr + DECON_TRIGCON);
176 return;
177 }
178
179 writel(TRIGCON_TRIGEN_PER_F | TRIGCON_TRIGEN_F | TRIGCON_HWTRIGMASK
180 | TRIGCON_HWTRIGEN, ctx->addr + DECON_TRIGCON);
181
182 if (regmap_update_bits(ctx->sysreg, DSD_CFG_MUX,
183 DSD_CFG_MUX_TE_UNMASK_GLOBAL, ~0))
184 DRM_ERROR("Cannot update sysreg.\n");
185 }
186
187 static void decon_commit(struct exynos_drm_crtc *crtc)
188 {
189 struct decon_context *ctx = crtc->ctx;
190 struct drm_display_mode *m = &crtc->base.mode;
191 bool interlaced = false;
192 u32 val;
193
194 if (ctx->out_type & IFTYPE_HDMI) {
195 m->crtc_hsync_start = m->crtc_hdisplay + 10;
196 m->crtc_hsync_end = m->crtc_htotal - 92;
197 m->crtc_vsync_start = m->crtc_vdisplay + 1;
198 m->crtc_vsync_end = m->crtc_vsync_start + 1;
199 if (m->flags & DRM_MODE_FLAG_INTERLACE)
200 interlaced = true;
201 }
202
203 decon_setup_trigger(ctx);
204
205 /* lcd on and use command if */
206 val = VIDOUT_LCD_ON;
207 if (interlaced)
208 val |= VIDOUT_INTERLACE_EN_F;
209 if (ctx->out_type & IFTYPE_I80) {
210 val |= VIDOUT_COMMAND_IF;
211 } else {
212 val |= VIDOUT_RGB_IF;
213 }
214
215 writel(val, ctx->addr + DECON_VIDOUTCON0);
216
217 if (interlaced)
218 val = VIDTCON2_LINEVAL(m->vdisplay / 2 - 1) |
219 VIDTCON2_HOZVAL(m->hdisplay - 1);
220 else
221 val = VIDTCON2_LINEVAL(m->vdisplay - 1) |
222 VIDTCON2_HOZVAL(m->hdisplay - 1);
223 writel(val, ctx->addr + DECON_VIDTCON2);
224
225 if (!(ctx->out_type & IFTYPE_I80)) {
226 int vbp = m->crtc_vtotal - m->crtc_vsync_end;
227 int vfp = m->crtc_vsync_start - m->crtc_vdisplay;
228
229 if (interlaced)
230 vbp = vbp / 2 - 1;
231 val = VIDTCON00_VBPD_F(vbp - 1) | VIDTCON00_VFPD_F(vfp - 1);
232 writel(val, ctx->addr + DECON_VIDTCON00);
233
234 val = VIDTCON01_VSPW_F(
235 m->crtc_vsync_end - m->crtc_vsync_start - 1);
236 writel(val, ctx->addr + DECON_VIDTCON01);
237
238 val = VIDTCON10_HBPD_F(
239 m->crtc_htotal - m->crtc_hsync_end - 1) |
240 VIDTCON10_HFPD_F(
241 m->crtc_hsync_start - m->crtc_hdisplay - 1);
242 writel(val, ctx->addr + DECON_VIDTCON10);
243
244 val = VIDTCON11_HSPW_F(
245 m->crtc_hsync_end - m->crtc_hsync_start - 1);
246 writel(val, ctx->addr + DECON_VIDTCON11);
247 }
248
249 /* enable output and display signal */
250 decon_set_bits(ctx, DECON_VIDCON0, VIDCON0_ENVID | VIDCON0_ENVID_F, ~0);
251
252 decon_set_bits(ctx, DECON_UPDATE, STANDALONE_UPDATE_F, ~0);
253 }
254
255 static void decon_win_set_pixfmt(struct decon_context *ctx, unsigned int win,
256 struct drm_framebuffer *fb)
257 {
258 unsigned long val;
259
260 val = readl(ctx->addr + DECON_WINCONx(win));
261 val &= ~WINCONx_BPPMODE_MASK;
262
263 switch (fb->format->format) {
264 case DRM_FORMAT_XRGB1555:
265 val |= WINCONx_BPPMODE_16BPP_I1555;
266 val |= WINCONx_HAWSWP_F;
267 val |= WINCONx_BURSTLEN_16WORD;
268 break;
269 case DRM_FORMAT_RGB565:
270 val |= WINCONx_BPPMODE_16BPP_565;
271 val |= WINCONx_HAWSWP_F;
272 val |= WINCONx_BURSTLEN_16WORD;
273 break;
274 case DRM_FORMAT_XRGB8888:
275 val |= WINCONx_BPPMODE_24BPP_888;
276 val |= WINCONx_WSWP_F;
277 val |= WINCONx_BURSTLEN_16WORD;
278 break;
279 case DRM_FORMAT_ARGB8888:
280 val |= WINCONx_BPPMODE_32BPP_A8888;
281 val |= WINCONx_WSWP_F | WINCONx_BLD_PIX_F | WINCONx_ALPHA_SEL_F;
282 val |= WINCONx_BURSTLEN_16WORD;
283 break;
284 default:
285 DRM_ERROR("Proper pixel format is not set\n");
286 return;
287 }
288
289 DRM_DEBUG_KMS("bpp = %u\n", fb->format->cpp[0] * 8);
290
291 /*
292 * In case of exynos, setting dma-burst to 16Word causes permanent
293 * tearing for very small buffers, e.g. cursor buffer. Burst Mode
294 * switching which is based on plane size is not recommended as
295 * plane size varies a lot towards the end of the screen and rapid
296 * movement causes unstable DMA which results into iommu crash/tear.
297 */
298
299 if (fb->width < MIN_FB_WIDTH_FOR_16WORD_BURST) {
300 val &= ~WINCONx_BURSTLEN_MASK;
301 val |= WINCONx_BURSTLEN_8WORD;
302 }
303
304 writel(val, ctx->addr + DECON_WINCONx(win));
305 }
306
307 static void decon_shadow_protect(struct decon_context *ctx, bool protect)
308 {
309 decon_set_bits(ctx, DECON_SHADOWCON, SHADOWCON_PROTECT_MASK,
310 protect ? ~0 : 0);
311 }
312
313 static void decon_atomic_begin(struct exynos_drm_crtc *crtc)
314 {
315 struct decon_context *ctx = crtc->ctx;
316
317 decon_shadow_protect(ctx, true);
318 }
319
320 #define BIT_VAL(x, e, s) (((x) & ((1 << ((e) - (s) + 1)) - 1)) << (s))
321 #define COORDINATE_X(x) BIT_VAL((x), 23, 12)
322 #define COORDINATE_Y(x) BIT_VAL((x), 11, 0)
323
324 static void decon_update_plane(struct exynos_drm_crtc *crtc,
325 struct exynos_drm_plane *plane)
326 {
327 struct exynos_drm_plane_state *state =
328 to_exynos_plane_state(plane->base.state);
329 struct decon_context *ctx = crtc->ctx;
330 struct drm_framebuffer *fb = state->base.fb;
331 unsigned int win = plane->index;
332 unsigned int bpp = fb->format->cpp[0];
333 unsigned int pitch = fb->pitches[0];
334 dma_addr_t dma_addr = exynos_drm_fb_dma_addr(fb, 0);
335 u32 val;
336
337 if (crtc->base.mode.flags & DRM_MODE_FLAG_INTERLACE) {
338 val = COORDINATE_X(state->crtc.x) |
339 COORDINATE_Y(state->crtc.y / 2);
340 writel(val, ctx->addr + DECON_VIDOSDxA(win));
341
342 val = COORDINATE_X(state->crtc.x + state->crtc.w - 1) |
343 COORDINATE_Y((state->crtc.y + state->crtc.h) / 2 - 1);
344 writel(val, ctx->addr + DECON_VIDOSDxB(win));
345 } else {
346 val = COORDINATE_X(state->crtc.x) | COORDINATE_Y(state->crtc.y);
347 writel(val, ctx->addr + DECON_VIDOSDxA(win));
348
349 val = COORDINATE_X(state->crtc.x + state->crtc.w - 1) |
350 COORDINATE_Y(state->crtc.y + state->crtc.h - 1);
351 writel(val, ctx->addr + DECON_VIDOSDxB(win));
352 }
353
354 val = VIDOSD_Wx_ALPHA_R_F(0x0) | VIDOSD_Wx_ALPHA_G_F(0x0) |
355 VIDOSD_Wx_ALPHA_B_F(0x0);
356 writel(val, ctx->addr + DECON_VIDOSDxC(win));
357
358 val = VIDOSD_Wx_ALPHA_R_F(0x0) | VIDOSD_Wx_ALPHA_G_F(0x0) |
359 VIDOSD_Wx_ALPHA_B_F(0x0);
360 writel(val, ctx->addr + DECON_VIDOSDxD(win));
361
362 writel(dma_addr, ctx->addr + DECON_VIDW0xADD0B0(win));
363
364 val = dma_addr + pitch * state->src.h;
365 writel(val, ctx->addr + DECON_VIDW0xADD1B0(win));
366
367 if (!(ctx->out_type & IFTYPE_HDMI))
368 val = BIT_VAL(pitch - state->crtc.w * bpp, 27, 14)
369 | BIT_VAL(state->crtc.w * bpp, 13, 0);
370 else
371 val = BIT_VAL(pitch - state->crtc.w * bpp, 29, 15)
372 | BIT_VAL(state->crtc.w * bpp, 14, 0);
373 writel(val, ctx->addr + DECON_VIDW0xADD2(win));
374
375 decon_win_set_pixfmt(ctx, win, fb);
376
377 /* window enable */
378 decon_set_bits(ctx, DECON_WINCONx(win), WINCONx_ENWIN_F, ~0);
379 }
380
381 static void decon_disable_plane(struct exynos_drm_crtc *crtc,
382 struct exynos_drm_plane *plane)
383 {
384 struct decon_context *ctx = crtc->ctx;
385 unsigned int win = plane->index;
386
387 decon_set_bits(ctx, DECON_WINCONx(win), WINCONx_ENWIN_F, 0);
388 }
389
390 static void decon_atomic_flush(struct exynos_drm_crtc *crtc)
391 {
392 struct decon_context *ctx = crtc->ctx;
393 unsigned long flags;
394
395 spin_lock_irqsave(&ctx->vblank_lock, flags);
396
397 decon_shadow_protect(ctx, false);
398
399 decon_set_bits(ctx, DECON_UPDATE, STANDALONE_UPDATE_F, ~0);
400
401 ctx->frame_id = decon_get_frame_count(ctx, true);
402
403 exynos_crtc_handle_event(crtc);
404
405 spin_unlock_irqrestore(&ctx->vblank_lock, flags);
406 }
407
408 static void decon_swreset(struct decon_context *ctx)
409 {
410 unsigned int tries;
411 unsigned long flags;
412
413 writel(0, ctx->addr + DECON_VIDCON0);
414 for (tries = 2000; tries; --tries) {
415 if (~readl(ctx->addr + DECON_VIDCON0) & VIDCON0_STOP_STATUS)
416 break;
417 udelay(10);
418 }
419
420 writel(VIDCON0_SWRESET, ctx->addr + DECON_VIDCON0);
421 for (tries = 2000; tries; --tries) {
422 if (~readl(ctx->addr + DECON_VIDCON0) & VIDCON0_SWRESET)
423 break;
424 udelay(10);
425 }
426
427 WARN(tries == 0, "failed to software reset DECON\n");
428
429 spin_lock_irqsave(&ctx->vblank_lock, flags);
430 ctx->frame_id = 0;
431 spin_unlock_irqrestore(&ctx->vblank_lock, flags);
432
433 if (!(ctx->out_type & IFTYPE_HDMI))
434 return;
435
436 writel(VIDCON0_CLKVALUP | VIDCON0_VLCKFREE, ctx->addr + DECON_VIDCON0);
437 decon_set_bits(ctx, DECON_CMU,
438 CMU_CLKGAGE_MODE_SFR_F | CMU_CLKGAGE_MODE_MEM_F, ~0);
439 writel(VIDCON1_VCLK_RUN_VDEN_DISABLE, ctx->addr + DECON_VIDCON1);
440 writel(CRCCTRL_CRCEN | CRCCTRL_CRCSTART_F | CRCCTRL_CRCCLKEN,
441 ctx->addr + DECON_CRCCTRL);
442 }
443
444 static void decon_enable(struct exynos_drm_crtc *crtc)
445 {
446 struct decon_context *ctx = crtc->ctx;
447
448 pm_runtime_get_sync(ctx->dev);
449
450 exynos_drm_pipe_clk_enable(crtc, true);
451
452 decon_swreset(ctx);
453
454 decon_commit(ctx->crtc);
455 }
456
457 static void decon_disable(struct exynos_drm_crtc *crtc)
458 {
459 struct decon_context *ctx = crtc->ctx;
460 int i;
461
462 if (!(ctx->out_type & I80_HW_TRG))
463 synchronize_irq(ctx->te_irq);
464 synchronize_irq(ctx->irq);
465
466 /*
467 * We need to make sure that all windows are disabled before we
468 * suspend that connector. Otherwise we might try to scan from
469 * a destroyed buffer later.
470 */
471 for (i = ctx->first_win; i < WINDOWS_NR; i++)
472 decon_disable_plane(crtc, &ctx->planes[i]);
473
474 decon_swreset(ctx);
475
476 exynos_drm_pipe_clk_enable(crtc, false);
477
478 pm_runtime_put_sync(ctx->dev);
479 }
480
481 static irqreturn_t decon_te_irq_handler(int irq, void *dev_id)
482 {
483 struct decon_context *ctx = dev_id;
484
485 decon_set_bits(ctx, DECON_TRIGCON, TRIGCON_SWTRIGCMD, ~0);
486
487 return IRQ_HANDLED;
488 }
489
490 static void decon_clear_channels(struct exynos_drm_crtc *crtc)
491 {
492 struct decon_context *ctx = crtc->ctx;
493 int win, i, ret;
494
495 DRM_DEBUG_KMS("%s\n", __FILE__);
496
497 for (i = 0; i < ARRAY_SIZE(decon_clks_name); i++) {
498 ret = clk_prepare_enable(ctx->clks[i]);
499 if (ret < 0)
500 goto err;
501 }
502
503 decon_shadow_protect(ctx, true);
504 for (win = 0; win < WINDOWS_NR; win++)
505 decon_set_bits(ctx, DECON_WINCONx(win), WINCONx_ENWIN_F, 0);
506 decon_shadow_protect(ctx, false);
507
508 decon_set_bits(ctx, DECON_UPDATE, STANDALONE_UPDATE_F, ~0);
509
510 /* TODO: wait for possible vsync */
511 msleep(50);
512
513 err:
514 while (--i >= 0)
515 clk_disable_unprepare(ctx->clks[i]);
516 }
517
518 static const struct exynos_drm_crtc_ops decon_crtc_ops = {
519 .enable = decon_enable,
520 .disable = decon_disable,
521 .enable_vblank = decon_enable_vblank,
522 .disable_vblank = decon_disable_vblank,
523 .get_vblank_counter = decon_get_vblank_counter,
524 .atomic_begin = decon_atomic_begin,
525 .update_plane = decon_update_plane,
526 .disable_plane = decon_disable_plane,
527 .atomic_flush = decon_atomic_flush,
528 };
529
530 static int decon_bind(struct device *dev, struct device *master, void *data)
531 {
532 struct decon_context *ctx = dev_get_drvdata(dev);
533 struct drm_device *drm_dev = data;
534 struct exynos_drm_plane *exynos_plane;
535 enum exynos_drm_output_type out_type;
536 unsigned int win;
537 int ret;
538
539 ctx->drm_dev = drm_dev;
540 drm_dev->max_vblank_count = 0xffffffff;
541
542 for (win = ctx->first_win; win < WINDOWS_NR; win++) {
543 int tmp = (win == ctx->first_win) ? 0 : win;
544
545 ctx->configs[win].pixel_formats = decon_formats;
546 ctx->configs[win].num_pixel_formats = ARRAY_SIZE(decon_formats);
547 ctx->configs[win].zpos = win;
548 ctx->configs[win].type = decon_win_types[tmp];
549
550 ret = exynos_plane_init(drm_dev, &ctx->planes[win], win,
551 &ctx->configs[win]);
552 if (ret)
553 return ret;
554 }
555
556 exynos_plane = &ctx->planes[ctx->first_win];
557 out_type = (ctx->out_type & IFTYPE_HDMI) ? EXYNOS_DISPLAY_TYPE_HDMI
558 : EXYNOS_DISPLAY_TYPE_LCD;
559 ctx->crtc = exynos_drm_crtc_create(drm_dev, &exynos_plane->base,
560 out_type, &decon_crtc_ops, ctx);
561 if (IS_ERR(ctx->crtc))
562 return PTR_ERR(ctx->crtc);
563
564 decon_clear_channels(ctx->crtc);
565
566 return drm_iommu_attach_device(drm_dev, dev);
567 }
568
569 static void decon_unbind(struct device *dev, struct device *master, void *data)
570 {
571 struct decon_context *ctx = dev_get_drvdata(dev);
572
573 decon_disable(ctx->crtc);
574
575 /* detach this sub driver from iommu mapping if supported. */
576 drm_iommu_detach_device(ctx->drm_dev, ctx->dev);
577 }
578
579 static const struct component_ops decon_component_ops = {
580 .bind = decon_bind,
581 .unbind = decon_unbind,
582 };
583
584 static void decon_handle_vblank(struct decon_context *ctx)
585 {
586 u32 frm;
587
588 spin_lock(&ctx->vblank_lock);
589
590 frm = decon_get_frame_count(ctx, true);
591
592 if (frm != ctx->frame_id) {
593 /* handle only if incremented, take care of wrap-around */
594 if ((s32)(frm - ctx->frame_id) > 0)
595 drm_crtc_handle_vblank(&ctx->crtc->base);
596 ctx->frame_id = frm;
597 }
598
599 spin_unlock(&ctx->vblank_lock);
600 }
601
602 static irqreturn_t decon_irq_handler(int irq, void *dev_id)
603 {
604 struct decon_context *ctx = dev_id;
605 u32 val;
606
607 val = readl(ctx->addr + DECON_VIDINTCON1);
608 val &= VIDINTCON1_INTFRMDONEPEND | VIDINTCON1_INTFRMPEND;
609
610 if (val) {
611 writel(val, ctx->addr + DECON_VIDINTCON1);
612 if (ctx->out_type & IFTYPE_HDMI) {
613 val = readl(ctx->addr + DECON_VIDOUTCON0);
614 val &= VIDOUT_INTERLACE_EN_F | VIDOUT_INTERLACE_FIELD_F;
615 if (val ==
616 (VIDOUT_INTERLACE_EN_F | VIDOUT_INTERLACE_FIELD_F))
617 return IRQ_HANDLED;
618 }
619 decon_handle_vblank(ctx);
620 }
621
622 return IRQ_HANDLED;
623 }
624
625 #ifdef CONFIG_PM
626 static int exynos5433_decon_suspend(struct device *dev)
627 {
628 struct decon_context *ctx = dev_get_drvdata(dev);
629 int i = ARRAY_SIZE(decon_clks_name);
630
631 while (--i >= 0)
632 clk_disable_unprepare(ctx->clks[i]);
633
634 return 0;
635 }
636
637 static int exynos5433_decon_resume(struct device *dev)
638 {
639 struct decon_context *ctx = dev_get_drvdata(dev);
640 int i, ret;
641
642 for (i = 0; i < ARRAY_SIZE(decon_clks_name); i++) {
643 ret = clk_prepare_enable(ctx->clks[i]);
644 if (ret < 0)
645 goto err;
646 }
647
648 return 0;
649
650 err:
651 while (--i >= 0)
652 clk_disable_unprepare(ctx->clks[i]);
653
654 return ret;
655 }
656 #endif
657
658 static const struct dev_pm_ops exynos5433_decon_pm_ops = {
659 SET_RUNTIME_PM_OPS(exynos5433_decon_suspend, exynos5433_decon_resume,
660 NULL)
661 };
662
663 static const struct of_device_id exynos5433_decon_driver_dt_match[] = {
664 {
665 .compatible = "samsung,exynos5433-decon",
666 .data = (void *)I80_HW_TRG
667 },
668 {
669 .compatible = "samsung,exynos5433-decon-tv",
670 .data = (void *)(I80_HW_TRG | IFTYPE_HDMI)
671 },
672 {},
673 };
674 MODULE_DEVICE_TABLE(of, exynos5433_decon_driver_dt_match);
675
676 static int decon_conf_irq(struct decon_context *ctx, const char *name,
677 irq_handler_t handler, unsigned long int flags, bool required)
678 {
679 struct platform_device *pdev = to_platform_device(ctx->dev);
680 int ret, irq = platform_get_irq_byname(pdev, name);
681
682 if (irq < 0) {
683 if (irq == -EPROBE_DEFER)
684 return irq;
685 if (required)
686 dev_err(ctx->dev, "cannot get %s IRQ\n", name);
687 else
688 irq = 0;
689 return irq;
690 }
691 irq_set_status_flags(irq, IRQ_NOAUTOEN);
692 ret = devm_request_irq(ctx->dev, irq, handler, flags, "drm_decon", ctx);
693 if (ret < 0) {
694 dev_err(ctx->dev, "IRQ %s request failed\n", name);
695 return ret;
696 }
697
698 return irq;
699 }
700
701 static int exynos5433_decon_probe(struct platform_device *pdev)
702 {
703 struct device *dev = &pdev->dev;
704 struct decon_context *ctx;
705 struct resource *res;
706 int ret;
707 int i;
708
709 ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
710 if (!ctx)
711 return -ENOMEM;
712
713 ctx->dev = dev;
714 ctx->out_type = (unsigned long)of_device_get_match_data(dev);
715 spin_lock_init(&ctx->vblank_lock);
716
717 if (ctx->out_type & IFTYPE_HDMI) {
718 ctx->first_win = 1;
719 } else if (of_get_child_by_name(dev->of_node, "i80-if-timings")) {
720 ctx->out_type |= IFTYPE_I80;
721 }
722
723 for (i = 0; i < ARRAY_SIZE(decon_clks_name); i++) {
724 struct clk *clk;
725
726 clk = devm_clk_get(ctx->dev, decon_clks_name[i]);
727 if (IS_ERR(clk))
728 return PTR_ERR(clk);
729
730 ctx->clks[i] = clk;
731 }
732
733 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
734 if (!res) {
735 dev_err(dev, "cannot find IO resource\n");
736 return -ENXIO;
737 }
738
739 ctx->addr = devm_ioremap_resource(dev, res);
740 if (IS_ERR(ctx->addr)) {
741 dev_err(dev, "ioremap failed\n");
742 return PTR_ERR(ctx->addr);
743 }
744
745 if (ctx->out_type & IFTYPE_I80) {
746 ret = decon_conf_irq(ctx, "lcd_sys", decon_irq_handler, 0, true);
747 if (ret < 0)
748 return ret;
749 ctx->irq = ret;
750
751 ret = decon_conf_irq(ctx, "te", decon_te_irq_handler,
752 IRQF_TRIGGER_RISING, false);
753 if (ret < 0)
754 return ret;
755 if (ret) {
756 ctx->te_irq = ret;
757 ctx->out_type &= ~I80_HW_TRG;
758 }
759 } else {
760 ret = decon_conf_irq(ctx, "vsync", decon_irq_handler, 0, true);
761 if (ret < 0)
762 return ret;
763 ctx->irq = ret;
764 }
765
766 if (ctx->out_type & I80_HW_TRG) {
767 ctx->sysreg = syscon_regmap_lookup_by_phandle(dev->of_node,
768 "samsung,disp-sysreg");
769 if (IS_ERR(ctx->sysreg)) {
770 dev_err(dev, "failed to get system register\n");
771 return PTR_ERR(ctx->sysreg);
772 }
773 }
774
775 platform_set_drvdata(pdev, ctx);
776
777 pm_runtime_enable(dev);
778
779 ret = component_add(dev, &decon_component_ops);
780 if (ret)
781 goto err_disable_pm_runtime;
782
783 return 0;
784
785 err_disable_pm_runtime:
786 pm_runtime_disable(dev);
787
788 return ret;
789 }
790
791 static int exynos5433_decon_remove(struct platform_device *pdev)
792 {
793 pm_runtime_disable(&pdev->dev);
794
795 component_del(&pdev->dev, &decon_component_ops);
796
797 return 0;
798 }
799
800 struct platform_driver exynos5433_decon_driver = {
801 .probe = exynos5433_decon_probe,
802 .remove = exynos5433_decon_remove,
803 .driver = {
804 .name = "exynos5433-decon",
805 .pm = &exynos5433_decon_pm_ops,
806 .of_match_table = exynos5433_decon_driver_dt_match,
807 },
808 };
Linux with added FPC-III support