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rcutorture: Eliminate unused ts_rem local from rcu_trace_clock_local()
[linux/fpc-iii.git] / drivers / gpu / drm / exynos / exynos_drm_fimd.c
blob60f93cad6643d9881b25b5dbc25fa1ebaabf88b8
1 /* exynos_drm_fimd.c
2 *
3 * Copyright (C) 2011 Samsung Electronics Co.Ltd
4 * Authors:
5 * Joonyoung Shim <jy0922.shim@samsung.com>
6 * Inki Dae <inki.dae@samsung.com>
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 *
13 */
14 #include <drm/drmP.h>
15
16 #include <linux/kernel.h>
17 #include <linux/platform_device.h>
18 #include <linux/clk.h>
19 #include <linux/of.h>
20 #include <linux/of_device.h>
21 #include <linux/pm_runtime.h>
22 #include <linux/component.h>
23 #include <linux/mfd/syscon.h>
24 #include <linux/regmap.h>
25
26 #include <video/of_display_timing.h>
27 #include <video/of_videomode.h>
28 #include <video/samsung_fimd.h>
29 #include <drm/exynos_drm.h>
30
31 #include "exynos_drm_drv.h"
32 #include "exynos_drm_fb.h"
33 #include "exynos_drm_crtc.h"
34 #include "exynos_drm_plane.h"
35 #include "exynos_drm_iommu.h"
36
37 /*
38 * FIMD stands for Fully Interactive Mobile Display and
39 * as a display controller, it transfers contents drawn on memory
40 * to a LCD Panel through Display Interfaces such as RGB or
41 * CPU Interface.
42 */
43
44 #define MIN_FB_WIDTH_FOR_16WORD_BURST 128
45
46 /* position control register for hardware window 0, 2 ~ 4.*/
47 #define VIDOSD_A(win) (VIDOSD_BASE + 0x00 + (win) * 16)
48 #define VIDOSD_B(win) (VIDOSD_BASE + 0x04 + (win) * 16)
49 /*
50 * size control register for hardware windows 0 and alpha control register
51 * for hardware windows 1 ~ 4
52 */
53 #define VIDOSD_C(win) (VIDOSD_BASE + 0x08 + (win) * 16)
54 /* size control register for hardware windows 1 ~ 2. */
55 #define VIDOSD_D(win) (VIDOSD_BASE + 0x0C + (win) * 16)
56
57 #define VIDWnALPHA0(win) (VIDW_ALPHA + 0x00 + (win) * 8)
58 #define VIDWnALPHA1(win) (VIDW_ALPHA + 0x04 + (win) * 8)
59
60 #define VIDWx_BUF_START(win, buf) (VIDW_BUF_START(buf) + (win) * 8)
61 #define VIDWx_BUF_START_S(win, buf) (VIDW_BUF_START_S(buf) + (win) * 8)
62 #define VIDWx_BUF_END(win, buf) (VIDW_BUF_END(buf) + (win) * 8)
63 #define VIDWx_BUF_SIZE(win, buf) (VIDW_BUF_SIZE(buf) + (win) * 4)
64
65 /* color key control register for hardware window 1 ~ 4. */
66 #define WKEYCON0_BASE(x) ((WKEYCON0 + 0x140) + ((x - 1) * 8))
67 /* color key value register for hardware window 1 ~ 4. */
68 #define WKEYCON1_BASE(x) ((WKEYCON1 + 0x140) + ((x - 1) * 8))
69
70 /* I80 trigger control register */
71 #define TRIGCON 0x1A4
72 #define TRGMODE_ENABLE (1 << 0)
73 #define SWTRGCMD_ENABLE (1 << 1)
74 /* Exynos3250, 3472, 5260 5410, 5420 and 5422 only supported. */
75 #define HWTRGEN_ENABLE (1 << 3)
76 #define HWTRGMASK_ENABLE (1 << 4)
77 /* Exynos3250, 3472, 5260, 5420 and 5422 only supported. */
78 #define HWTRIGEN_PER_ENABLE (1 << 31)
79
80 /* display mode change control register except exynos4 */
81 #define VIDOUT_CON 0x000
82 #define VIDOUT_CON_F_I80_LDI0 (0x2 << 8)
83
84 /* I80 interface control for main LDI register */
85 #define I80IFCONFAx(x) (0x1B0 + (x) * 4)
86 #define I80IFCONFBx(x) (0x1B8 + (x) * 4)
87 #define LCD_CS_SETUP(x) ((x) << 16)
88 #define LCD_WR_SETUP(x) ((x) << 12)
89 #define LCD_WR_ACTIVE(x) ((x) << 8)
90 #define LCD_WR_HOLD(x) ((x) << 4)
91 #define I80IFEN_ENABLE (1 << 0)
92
93 /* FIMD has totally five hardware windows. */
94 #define WINDOWS_NR 5
95
96 /* HW trigger flag on i80 panel. */
97 #define I80_HW_TRG (1 << 1)
98
99 struct fimd_driver_data {
100 unsigned int timing_base;
101 unsigned int lcdblk_offset;
102 unsigned int lcdblk_vt_shift;
103 unsigned int lcdblk_bypass_shift;
104 unsigned int lcdblk_mic_bypass_shift;
105 unsigned int trg_type;
106
107 unsigned int has_shadowcon:1;
108 unsigned int has_clksel:1;
109 unsigned int has_limited_fmt:1;
110 unsigned int has_vidoutcon:1;
111 unsigned int has_vtsel:1;
112 unsigned int has_mic_bypass:1;
113 unsigned int has_dp_clk:1;
114 unsigned int has_hw_trigger:1;
115 unsigned int has_trigger_per_te:1;
116 };
117
118 static struct fimd_driver_data s3c64xx_fimd_driver_data = {
119 .timing_base = 0x0,
120 .has_clksel = 1,
121 .has_limited_fmt = 1,
122 };
123
124 static struct fimd_driver_data exynos3_fimd_driver_data = {
125 .timing_base = 0x20000,
126 .lcdblk_offset = 0x210,
127 .lcdblk_bypass_shift = 1,
128 .has_shadowcon = 1,
129 .has_vidoutcon = 1,
130 };
131
132 static struct fimd_driver_data exynos4_fimd_driver_data = {
133 .timing_base = 0x0,
134 .lcdblk_offset = 0x210,
135 .lcdblk_vt_shift = 10,
136 .lcdblk_bypass_shift = 1,
137 .has_shadowcon = 1,
138 .has_vtsel = 1,
139 };
140
141 static struct fimd_driver_data exynos5_fimd_driver_data = {
142 .timing_base = 0x20000,
143 .lcdblk_offset = 0x214,
144 .lcdblk_vt_shift = 24,
145 .lcdblk_bypass_shift = 15,
146 .has_shadowcon = 1,
147 .has_vidoutcon = 1,
148 .has_vtsel = 1,
149 .has_dp_clk = 1,
150 };
151
152 static struct fimd_driver_data exynos5420_fimd_driver_data = {
153 .timing_base = 0x20000,
154 .lcdblk_offset = 0x214,
155 .lcdblk_vt_shift = 24,
156 .lcdblk_bypass_shift = 15,
157 .lcdblk_mic_bypass_shift = 11,
158 .has_shadowcon = 1,
159 .has_vidoutcon = 1,
160 .has_vtsel = 1,
161 .has_mic_bypass = 1,
162 .has_dp_clk = 1,
163 };
164
165 struct fimd_context {
166 struct device *dev;
167 struct drm_device *drm_dev;
168 struct exynos_drm_crtc *crtc;
169 struct exynos_drm_plane planes[WINDOWS_NR];
170 struct exynos_drm_plane_config configs[WINDOWS_NR];
171 struct clk *bus_clk;
172 struct clk *lcd_clk;
173 void __iomem *regs;
174 struct regmap *sysreg;
175 unsigned long irq_flags;
176 u32 vidcon0;
177 u32 vidcon1;
178 u32 vidout_con;
179 u32 i80ifcon;
180 bool i80_if;
181 bool suspended;
182 wait_queue_head_t wait_vsync_queue;
183 atomic_t wait_vsync_event;
184 atomic_t win_updated;
185 atomic_t triggering;
186 u32 clkdiv;
187
188 const struct fimd_driver_data *driver_data;
189 struct drm_encoder *encoder;
190 struct exynos_drm_clk dp_clk;
191 };
192
193 static const struct of_device_id fimd_driver_dt_match[] = {
194 { .compatible = "samsung,s3c6400-fimd",
195 .data = &s3c64xx_fimd_driver_data },
196 { .compatible = "samsung,exynos3250-fimd",
197 .data = &exynos3_fimd_driver_data },
198 { .compatible = "samsung,exynos4210-fimd",
199 .data = &exynos4_fimd_driver_data },
200 { .compatible = "samsung,exynos5250-fimd",
201 .data = &exynos5_fimd_driver_data },
202 { .compatible = "samsung,exynos5420-fimd",
203 .data = &exynos5420_fimd_driver_data },
204 {},
205 };
206 MODULE_DEVICE_TABLE(of, fimd_driver_dt_match);
207
208 static const enum drm_plane_type fimd_win_types[WINDOWS_NR] = {
209 DRM_PLANE_TYPE_PRIMARY,
210 DRM_PLANE_TYPE_OVERLAY,
211 DRM_PLANE_TYPE_OVERLAY,
212 DRM_PLANE_TYPE_OVERLAY,
213 DRM_PLANE_TYPE_CURSOR,
214 };
215
216 static const uint32_t fimd_formats[] = {
217 DRM_FORMAT_C8,
218 DRM_FORMAT_XRGB1555,
219 DRM_FORMAT_RGB565,
220 DRM_FORMAT_XRGB8888,
221 DRM_FORMAT_ARGB8888,
222 };
223
224 static int fimd_enable_vblank(struct exynos_drm_crtc *crtc)
225 {
226 struct fimd_context *ctx = crtc->ctx;
227 u32 val;
228
229 if (ctx->suspended)
230 return -EPERM;
231
232 if (!test_and_set_bit(0, &ctx->irq_flags)) {
233 val = readl(ctx->regs + VIDINTCON0);
234
235 val |= VIDINTCON0_INT_ENABLE;
236
237 if (ctx->i80_if) {
238 val |= VIDINTCON0_INT_I80IFDONE;
239 val |= VIDINTCON0_INT_SYSMAINCON;
240 val &= ~VIDINTCON0_INT_SYSSUBCON;
241 } else {
242 val |= VIDINTCON0_INT_FRAME;
243
244 val &= ~VIDINTCON0_FRAMESEL0_MASK;
245 val |= VIDINTCON0_FRAMESEL0_FRONTPORCH;
246 val &= ~VIDINTCON0_FRAMESEL1_MASK;
247 val |= VIDINTCON0_FRAMESEL1_NONE;
248 }
249
250 writel(val, ctx->regs + VIDINTCON0);
251 }
252
253 return 0;
254 }
255
256 static void fimd_disable_vblank(struct exynos_drm_crtc *crtc)
257 {
258 struct fimd_context *ctx = crtc->ctx;
259 u32 val;
260
261 if (ctx->suspended)
262 return;
263
264 if (test_and_clear_bit(0, &ctx->irq_flags)) {
265 val = readl(ctx->regs + VIDINTCON0);
266
267 val &= ~VIDINTCON0_INT_ENABLE;
268
269 if (ctx->i80_if) {
270 val &= ~VIDINTCON0_INT_I80IFDONE;
271 val &= ~VIDINTCON0_INT_SYSMAINCON;
272 val &= ~VIDINTCON0_INT_SYSSUBCON;
273 } else
274 val &= ~VIDINTCON0_INT_FRAME;
275
276 writel(val, ctx->regs + VIDINTCON0);
277 }
278 }
279
280 static void fimd_wait_for_vblank(struct exynos_drm_crtc *crtc)
281 {
282 struct fimd_context *ctx = crtc->ctx;
283
284 if (ctx->suspended)
285 return;
286
287 atomic_set(&ctx->wait_vsync_event, 1);
288
289 /*
290 * wait for FIMD to signal VSYNC interrupt or return after
291 * timeout which is set to 50ms (refresh rate of 20).
292 */
293 if (!wait_event_timeout(ctx->wait_vsync_queue,
294 !atomic_read(&ctx->wait_vsync_event),
295 HZ/20))
296 DRM_DEBUG_KMS("vblank wait timed out.\n");
297 }
298
299 static void fimd_enable_video_output(struct fimd_context *ctx, unsigned int win,
300 bool enable)
301 {
302 u32 val = readl(ctx->regs + WINCON(win));
303
304 if (enable)
305 val |= WINCONx_ENWIN;
306 else
307 val &= ~WINCONx_ENWIN;
308
309 writel(val, ctx->regs + WINCON(win));
310 }
311
312 static void fimd_enable_shadow_channel_path(struct fimd_context *ctx,
313 unsigned int win,
314 bool enable)
315 {
316 u32 val = readl(ctx->regs + SHADOWCON);
317
318 if (enable)
319 val |= SHADOWCON_CHx_ENABLE(win);
320 else
321 val &= ~SHADOWCON_CHx_ENABLE(win);
322
323 writel(val, ctx->regs + SHADOWCON);
324 }
325
326 static void fimd_clear_channels(struct exynos_drm_crtc *crtc)
327 {
328 struct fimd_context *ctx = crtc->ctx;
329 unsigned int win, ch_enabled = 0;
330
331 DRM_DEBUG_KMS("%s\n", __FILE__);
332
333 /* Hardware is in unknown state, so ensure it gets enabled properly */
334 pm_runtime_get_sync(ctx->dev);
335
336 clk_prepare_enable(ctx->bus_clk);
337 clk_prepare_enable(ctx->lcd_clk);
338
339 /* Check if any channel is enabled. */
340 for (win = 0; win < WINDOWS_NR; win++) {
341 u32 val = readl(ctx->regs + WINCON(win));
342
343 if (val & WINCONx_ENWIN) {
344 fimd_enable_video_output(ctx, win, false);
345
346 if (ctx->driver_data->has_shadowcon)
347 fimd_enable_shadow_channel_path(ctx, win,
348 false);
349
350 ch_enabled = 1;
351 }
352 }
353
354 /* Wait for vsync, as disable channel takes effect at next vsync */
355 if (ch_enabled) {
356 ctx->suspended = false;
357
358 fimd_enable_vblank(ctx->crtc);
359 fimd_wait_for_vblank(ctx->crtc);
360 fimd_disable_vblank(ctx->crtc);
361
362 ctx->suspended = true;
363 }
364
365 clk_disable_unprepare(ctx->lcd_clk);
366 clk_disable_unprepare(ctx->bus_clk);
367
368 pm_runtime_put(ctx->dev);
369 }
370
371
372 static int fimd_atomic_check(struct exynos_drm_crtc *crtc,
373 struct drm_crtc_state *state)
374 {
375 struct drm_display_mode *mode = &state->adjusted_mode;
376 struct fimd_context *ctx = crtc->ctx;
377 unsigned long ideal_clk, lcd_rate;
378 u32 clkdiv;
379
380 if (mode->clock == 0) {
381 DRM_INFO("Mode has zero clock value.\n");
382 return -EINVAL;
383 }
384
385 ideal_clk = mode->clock * 1000;
386
387 if (ctx->i80_if) {
388 /*
389 * The frame done interrupt should be occurred prior to the
390 * next TE signal.
391 */
392 ideal_clk *= 2;
393 }
394
395 lcd_rate = clk_get_rate(ctx->lcd_clk);
396 if (2 * lcd_rate < ideal_clk) {
397 DRM_INFO("sclk_fimd clock too low(%lu) for requested pixel clock(%lu)\n",
398 lcd_rate, ideal_clk);
399 return -EINVAL;
400 }
401
402 /* Find the clock divider value that gets us closest to ideal_clk */
403 clkdiv = DIV_ROUND_CLOSEST(lcd_rate, ideal_clk);
404 if (clkdiv >= 0x200) {
405 DRM_INFO("requested pixel clock(%lu) too low\n", ideal_clk);
406 return -EINVAL;
407 }
408
409 ctx->clkdiv = (clkdiv < 0x100) ? clkdiv : 0xff;
410
411 return 0;
412 }
413
414 static void fimd_setup_trigger(struct fimd_context *ctx)
415 {
416 void __iomem *timing_base = ctx->regs + ctx->driver_data->timing_base;
417 u32 trg_type = ctx->driver_data->trg_type;
418 u32 val = readl(timing_base + TRIGCON);
419
420 val &= ~(TRGMODE_ENABLE);
421
422 if (trg_type == I80_HW_TRG) {
423 if (ctx->driver_data->has_hw_trigger)
424 val |= HWTRGEN_ENABLE | HWTRGMASK_ENABLE;
425 if (ctx->driver_data->has_trigger_per_te)
426 val |= HWTRIGEN_PER_ENABLE;
427 } else {
428 val |= TRGMODE_ENABLE;
429 }
430
431 writel(val, timing_base + TRIGCON);
432 }
433
434 static void fimd_commit(struct exynos_drm_crtc *crtc)
435 {
436 struct fimd_context *ctx = crtc->ctx;
437 struct drm_display_mode *mode = &crtc->base.state->adjusted_mode;
438 const struct fimd_driver_data *driver_data = ctx->driver_data;
439 void *timing_base = ctx->regs + driver_data->timing_base;
440 u32 val;
441
442 if (ctx->suspended)
443 return;
444
445 /* nothing to do if we haven't set the mode yet */
446 if (mode->htotal == 0 || mode->vtotal == 0)
447 return;
448
449 if (ctx->i80_if) {
450 val = ctx->i80ifcon | I80IFEN_ENABLE;
451 writel(val, timing_base + I80IFCONFAx(0));
452
453 /* disable auto frame rate */
454 writel(0, timing_base + I80IFCONFBx(0));
455
456 /* set video type selection to I80 interface */
457 if (driver_data->has_vtsel && ctx->sysreg &&
458 regmap_update_bits(ctx->sysreg,
459 driver_data->lcdblk_offset,
460 0x3 << driver_data->lcdblk_vt_shift,
461 0x1 << driver_data->lcdblk_vt_shift)) {
462 DRM_ERROR("Failed to update sysreg for I80 i/f.\n");
463 return;
464 }
465 } else {
466 int vsync_len, vbpd, vfpd, hsync_len, hbpd, hfpd;
467 u32 vidcon1;
468
469 /* setup polarity values */
470 vidcon1 = ctx->vidcon1;
471 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
472 vidcon1 |= VIDCON1_INV_VSYNC;
473 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
474 vidcon1 |= VIDCON1_INV_HSYNC;
475 writel(vidcon1, ctx->regs + driver_data->timing_base + VIDCON1);
476
477 /* setup vertical timing values. */
478 vsync_len = mode->crtc_vsync_end - mode->crtc_vsync_start;
479 vbpd = mode->crtc_vtotal - mode->crtc_vsync_end;
480 vfpd = mode->crtc_vsync_start - mode->crtc_vdisplay;
481
482 val = VIDTCON0_VBPD(vbpd - 1) |
483 VIDTCON0_VFPD(vfpd - 1) |
484 VIDTCON0_VSPW(vsync_len - 1);
485 writel(val, ctx->regs + driver_data->timing_base + VIDTCON0);
486
487 /* setup horizontal timing values. */
488 hsync_len = mode->crtc_hsync_end - mode->crtc_hsync_start;
489 hbpd = mode->crtc_htotal - mode->crtc_hsync_end;
490 hfpd = mode->crtc_hsync_start - mode->crtc_hdisplay;
491
492 val = VIDTCON1_HBPD(hbpd - 1) |
493 VIDTCON1_HFPD(hfpd - 1) |
494 VIDTCON1_HSPW(hsync_len - 1);
495 writel(val, ctx->regs + driver_data->timing_base + VIDTCON1);
496 }
497
498 if (driver_data->has_vidoutcon)
499 writel(ctx->vidout_con, timing_base + VIDOUT_CON);
500
501 /* set bypass selection */
502 if (ctx->sysreg && regmap_update_bits(ctx->sysreg,
503 driver_data->lcdblk_offset,
504 0x1 << driver_data->lcdblk_bypass_shift,
505 0x1 << driver_data->lcdblk_bypass_shift)) {
506 DRM_ERROR("Failed to update sysreg for bypass setting.\n");
507 return;
508 }
509
510 /* TODO: When MIC is enabled for display path, the lcdblk_mic_bypass
511 * bit should be cleared.
512 */
513 if (driver_data->has_mic_bypass && ctx->sysreg &&
514 regmap_update_bits(ctx->sysreg,
515 driver_data->lcdblk_offset,
516 0x1 << driver_data->lcdblk_mic_bypass_shift,
517 0x1 << driver_data->lcdblk_mic_bypass_shift)) {
518 DRM_ERROR("Failed to update sysreg for bypass mic.\n");
519 return;
520 }
521
522 /* setup horizontal and vertical display size. */
523 val = VIDTCON2_LINEVAL(mode->vdisplay - 1) |
524 VIDTCON2_HOZVAL(mode->hdisplay - 1) |
525 VIDTCON2_LINEVAL_E(mode->vdisplay - 1) |
526 VIDTCON2_HOZVAL_E(mode->hdisplay - 1);
527 writel(val, ctx->regs + driver_data->timing_base + VIDTCON2);
528
529 fimd_setup_trigger(ctx);
530
531 /*
532 * fields of register with prefix '_F' would be updated
533 * at vsync(same as dma start)
534 */
535 val = ctx->vidcon0;
536 val |= VIDCON0_ENVID | VIDCON0_ENVID_F;
537
538 if (ctx->driver_data->has_clksel)
539 val |= VIDCON0_CLKSEL_LCD;
540
541 if (ctx->clkdiv > 1)
542 val |= VIDCON0_CLKVAL_F(ctx->clkdiv - 1) | VIDCON0_CLKDIR;
543
544 writel(val, ctx->regs + VIDCON0);
545 }
546
547
548 static void fimd_win_set_pixfmt(struct fimd_context *ctx, unsigned int win,
549 uint32_t pixel_format, int width)
550 {
551 unsigned long val;
552
553 val = WINCONx_ENWIN;
554
555 /*
556 * In case of s3c64xx, window 0 doesn't support alpha channel.
557 * So the request format is ARGB8888 then change it to XRGB8888.
558 */
559 if (ctx->driver_data->has_limited_fmt && !win) {
560 if (pixel_format == DRM_FORMAT_ARGB8888)
561 pixel_format = DRM_FORMAT_XRGB8888;
562 }
563
564 switch (pixel_format) {
565 case DRM_FORMAT_C8:
566 val |= WINCON0_BPPMODE_8BPP_PALETTE;
567 val |= WINCONx_BURSTLEN_8WORD;
568 val |= WINCONx_BYTSWP;
569 break;
570 case DRM_FORMAT_XRGB1555:
571 val |= WINCON0_BPPMODE_16BPP_1555;
572 val |= WINCONx_HAWSWP;
573 val |= WINCONx_BURSTLEN_16WORD;
574 break;
575 case DRM_FORMAT_RGB565:
576 val |= WINCON0_BPPMODE_16BPP_565;
577 val |= WINCONx_HAWSWP;
578 val |= WINCONx_BURSTLEN_16WORD;
579 break;
580 case DRM_FORMAT_XRGB8888:
581 val |= WINCON0_BPPMODE_24BPP_888;
582 val |= WINCONx_WSWP;
583 val |= WINCONx_BURSTLEN_16WORD;
584 break;
585 case DRM_FORMAT_ARGB8888:
586 val |= WINCON1_BPPMODE_25BPP_A1888
587 | WINCON1_BLD_PIX | WINCON1_ALPHA_SEL;
588 val |= WINCONx_WSWP;
589 val |= WINCONx_BURSTLEN_16WORD;
590 break;
591 default:
592 DRM_DEBUG_KMS("invalid pixel size so using unpacked 24bpp.\n");
593
594 val |= WINCON0_BPPMODE_24BPP_888;
595 val |= WINCONx_WSWP;
596 val |= WINCONx_BURSTLEN_16WORD;
597 break;
598 }
599
600 /*
601 * Setting dma-burst to 16Word causes permanent tearing for very small
602 * buffers, e.g. cursor buffer. Burst Mode switching which based on
603 * plane size is not recommended as plane size varies alot towards the
604 * end of the screen and rapid movement causes unstable DMA, but it is
605 * still better to change dma-burst than displaying garbage.
606 */
607
608 if (width < MIN_FB_WIDTH_FOR_16WORD_BURST) {
609 val &= ~WINCONx_BURSTLEN_MASK;
610 val |= WINCONx_BURSTLEN_4WORD;
611 }
612
613 writel(val, ctx->regs + WINCON(win));
614
615 /* hardware window 0 doesn't support alpha channel. */
616 if (win != 0) {
617 /* OSD alpha */
618 val = VIDISD14C_ALPHA0_R(0xf) |
619 VIDISD14C_ALPHA0_G(0xf) |
620 VIDISD14C_ALPHA0_B(0xf) |
621 VIDISD14C_ALPHA1_R(0xf) |
622 VIDISD14C_ALPHA1_G(0xf) |
623 VIDISD14C_ALPHA1_B(0xf);
624
625 writel(val, ctx->regs + VIDOSD_C(win));
626
627 val = VIDW_ALPHA_R(0xf) | VIDW_ALPHA_G(0xf) |
628 VIDW_ALPHA_G(0xf);
629 writel(val, ctx->regs + VIDWnALPHA0(win));
630 writel(val, ctx->regs + VIDWnALPHA1(win));
631 }
632 }
633
634 static void fimd_win_set_colkey(struct fimd_context *ctx, unsigned int win)
635 {
636 unsigned int keycon0 = 0, keycon1 = 0;
637
638 keycon0 = ~(WxKEYCON0_KEYBL_EN | WxKEYCON0_KEYEN_F |
639 WxKEYCON0_DIRCON) | WxKEYCON0_COMPKEY(0);
640
641 keycon1 = WxKEYCON1_COLVAL(0xffffffff);
642
643 writel(keycon0, ctx->regs + WKEYCON0_BASE(win));
644 writel(keycon1, ctx->regs + WKEYCON1_BASE(win));
645 }
646
647 /**
648 * shadow_protect_win() - disable updating values from shadow registers at vsync
649 *
650 * @win: window to protect registers for
651 * @protect: 1 to protect (disable updates)
652 */
653 static void fimd_shadow_protect_win(struct fimd_context *ctx,
654 unsigned int win, bool protect)
655 {
656 u32 reg, bits, val;
657
658 /*
659 * SHADOWCON/PRTCON register is used for enabling timing.
660 *
661 * for example, once only width value of a register is set,
662 * if the dma is started then fimd hardware could malfunction so
663 * with protect window setting, the register fields with prefix '_F'
664 * wouldn't be updated at vsync also but updated once unprotect window
665 * is set.
666 */
667
668 if (ctx->driver_data->has_shadowcon) {
669 reg = SHADOWCON;
670 bits = SHADOWCON_WINx_PROTECT(win);
671 } else {
672 reg = PRTCON;
673 bits = PRTCON_PROTECT;
674 }
675
676 val = readl(ctx->regs + reg);
677 if (protect)
678 val |= bits;
679 else
680 val &= ~bits;
681 writel(val, ctx->regs + reg);
682 }
683
684 static void fimd_atomic_begin(struct exynos_drm_crtc *crtc)
685 {
686 struct fimd_context *ctx = crtc->ctx;
687 int i;
688
689 if (ctx->suspended)
690 return;
691
692 for (i = 0; i < WINDOWS_NR; i++)
693 fimd_shadow_protect_win(ctx, i, true);
694 }
695
696 static void fimd_atomic_flush(struct exynos_drm_crtc *crtc)
697 {
698 struct fimd_context *ctx = crtc->ctx;
699 int i;
700
701 if (ctx->suspended)
702 return;
703
704 for (i = 0; i < WINDOWS_NR; i++)
705 fimd_shadow_protect_win(ctx, i, false);
706
707 exynos_crtc_handle_event(crtc);
708 }
709
710 static void fimd_update_plane(struct exynos_drm_crtc *crtc,
711 struct exynos_drm_plane *plane)
712 {
713 struct exynos_drm_plane_state *state =
714 to_exynos_plane_state(plane->base.state);
715 struct fimd_context *ctx = crtc->ctx;
716 struct drm_framebuffer *fb = state->base.fb;
717 dma_addr_t dma_addr;
718 unsigned long val, size, offset;
719 unsigned int last_x, last_y, buf_offsize, line_size;
720 unsigned int win = plane->index;
721 unsigned int bpp = fb->format->cpp[0];
722 unsigned int pitch = fb->pitches[0];
723
724 if (ctx->suspended)
725 return;
726
727 offset = state->src.x * bpp;
728 offset += state->src.y * pitch;
729
730 /* buffer start address */
731 dma_addr = exynos_drm_fb_dma_addr(fb, 0) + offset;
732 val = (unsigned long)dma_addr;
733 writel(val, ctx->regs + VIDWx_BUF_START(win, 0));
734
735 /* buffer end address */
736 size = pitch * state->crtc.h;
737 val = (unsigned long)(dma_addr + size);
738 writel(val, ctx->regs + VIDWx_BUF_END(win, 0));
739
740 DRM_DEBUG_KMS("start addr = 0x%lx, end addr = 0x%lx, size = 0x%lx\n",
741 (unsigned long)dma_addr, val, size);
742 DRM_DEBUG_KMS("ovl_width = %d, ovl_height = %d\n",
743 state->crtc.w, state->crtc.h);
744
745 /* buffer size */
746 buf_offsize = pitch - (state->crtc.w * bpp);
747 line_size = state->crtc.w * bpp;
748 val = VIDW_BUF_SIZE_OFFSET(buf_offsize) |
749 VIDW_BUF_SIZE_PAGEWIDTH(line_size) |
750 VIDW_BUF_SIZE_OFFSET_E(buf_offsize) |
751 VIDW_BUF_SIZE_PAGEWIDTH_E(line_size);
752 writel(val, ctx->regs + VIDWx_BUF_SIZE(win, 0));
753
754 /* OSD position */
755 val = VIDOSDxA_TOPLEFT_X(state->crtc.x) |
756 VIDOSDxA_TOPLEFT_Y(state->crtc.y) |
757 VIDOSDxA_TOPLEFT_X_E(state->crtc.x) |
758 VIDOSDxA_TOPLEFT_Y_E(state->crtc.y);
759 writel(val, ctx->regs + VIDOSD_A(win));
760
761 last_x = state->crtc.x + state->crtc.w;
762 if (last_x)
763 last_x--;
764 last_y = state->crtc.y + state->crtc.h;
765 if (last_y)
766 last_y--;
767
768 val = VIDOSDxB_BOTRIGHT_X(last_x) | VIDOSDxB_BOTRIGHT_Y(last_y) |
769 VIDOSDxB_BOTRIGHT_X_E(last_x) | VIDOSDxB_BOTRIGHT_Y_E(last_y);
770
771 writel(val, ctx->regs + VIDOSD_B(win));
772
773 DRM_DEBUG_KMS("osd pos: tx = %d, ty = %d, bx = %d, by = %d\n",
774 state->crtc.x, state->crtc.y, last_x, last_y);
775
776 /* OSD size */
777 if (win != 3 && win != 4) {
778 u32 offset = VIDOSD_D(win);
779 if (win == 0)
780 offset = VIDOSD_C(win);
781 val = state->crtc.w * state->crtc.h;
782 writel(val, ctx->regs + offset);
783
784 DRM_DEBUG_KMS("osd size = 0x%x\n", (unsigned int)val);
785 }
786
787 fimd_win_set_pixfmt(ctx, win, fb->format->format, state->src.w);
788
789 /* hardware window 0 doesn't support color key. */
790 if (win != 0)
791 fimd_win_set_colkey(ctx, win);
792
793 fimd_enable_video_output(ctx, win, true);
794
795 if (ctx->driver_data->has_shadowcon)
796 fimd_enable_shadow_channel_path(ctx, win, true);
797
798 if (ctx->i80_if)
799 atomic_set(&ctx->win_updated, 1);
800 }
801
802 static void fimd_disable_plane(struct exynos_drm_crtc *crtc,
803 struct exynos_drm_plane *plane)
804 {
805 struct fimd_context *ctx = crtc->ctx;
806 unsigned int win = plane->index;
807
808 if (ctx->suspended)
809 return;
810
811 fimd_enable_video_output(ctx, win, false);
812
813 if (ctx->driver_data->has_shadowcon)
814 fimd_enable_shadow_channel_path(ctx, win, false);
815 }
816
817 static void fimd_enable(struct exynos_drm_crtc *crtc)
818 {
819 struct fimd_context *ctx = crtc->ctx;
820
821 if (!ctx->suspended)
822 return;
823
824 ctx->suspended = false;
825
826 pm_runtime_get_sync(ctx->dev);
827
828 /* if vblank was enabled status, enable it again. */
829 if (test_and_clear_bit(0, &ctx->irq_flags))
830 fimd_enable_vblank(ctx->crtc);
831
832 fimd_commit(ctx->crtc);
833 }
834
835 static void fimd_disable(struct exynos_drm_crtc *crtc)
836 {
837 struct fimd_context *ctx = crtc->ctx;
838 int i;
839
840 if (ctx->suspended)
841 return;
842
843 /*
844 * We need to make sure that all windows are disabled before we
845 * suspend that connector. Otherwise we might try to scan from
846 * a destroyed buffer later.
847 */
848 for (i = 0; i < WINDOWS_NR; i++)
849 fimd_disable_plane(crtc, &ctx->planes[i]);
850
851 fimd_enable_vblank(crtc);
852 fimd_wait_for_vblank(crtc);
853 fimd_disable_vblank(crtc);
854
855 writel(0, ctx->regs + VIDCON0);
856
857 pm_runtime_put_sync(ctx->dev);
858 ctx->suspended = true;
859 }
860
861 static void fimd_trigger(struct device *dev)
862 {
863 struct fimd_context *ctx = dev_get_drvdata(dev);
864 const struct fimd_driver_data *driver_data = ctx->driver_data;
865 void *timing_base = ctx->regs + driver_data->timing_base;
866 u32 reg;
867
868 /*
869 * Skips triggering if in triggering state, because multiple triggering
870 * requests can cause panel reset.
871 */
872 if (atomic_read(&ctx->triggering))
873 return;
874
875 /* Enters triggering mode */
876 atomic_set(&ctx->triggering, 1);
877
878 reg = readl(timing_base + TRIGCON);
879 reg |= (TRGMODE_ENABLE | SWTRGCMD_ENABLE);
880 writel(reg, timing_base + TRIGCON);
881
882 /*
883 * Exits triggering mode if vblank is not enabled yet, because when the
884 * VIDINTCON0 register is not set, it can not exit from triggering mode.
885 */
886 if (!test_bit(0, &ctx->irq_flags))
887 atomic_set(&ctx->triggering, 0);
888 }
889
890 static void fimd_te_handler(struct exynos_drm_crtc *crtc)
891 {
892 struct fimd_context *ctx = crtc->ctx;
893 u32 trg_type = ctx->driver_data->trg_type;
894
895 /* Checks the crtc is detached already from encoder */
896 if (!ctx->drm_dev)
897 return;
898
899 if (trg_type == I80_HW_TRG)
900 goto out;
901
902 /*
903 * If there is a page flip request, triggers and handles the page flip
904 * event so that current fb can be updated into panel GRAM.
905 */
906 if (atomic_add_unless(&ctx->win_updated, -1, 0))
907 fimd_trigger(ctx->dev);
908
909 out:
910 /* Wakes up vsync event queue */
911 if (atomic_read(&ctx->wait_vsync_event)) {
912 atomic_set(&ctx->wait_vsync_event, 0);
913 wake_up(&ctx->wait_vsync_queue);
914 }
915
916 if (test_bit(0, &ctx->irq_flags))
917 drm_crtc_handle_vblank(&ctx->crtc->base);
918 }
919
920 static void fimd_dp_clock_enable(struct exynos_drm_clk *clk, bool enable)
921 {
922 struct fimd_context *ctx = container_of(clk, struct fimd_context,
923 dp_clk);
924 u32 val = enable ? DP_MIE_CLK_DP_ENABLE : DP_MIE_CLK_DISABLE;
925 writel(val, ctx->regs + DP_MIE_CLKCON);
926 }
927
928 static const struct exynos_drm_crtc_ops fimd_crtc_ops = {
929 .enable = fimd_enable,
930 .disable = fimd_disable,
931 .enable_vblank = fimd_enable_vblank,
932 .disable_vblank = fimd_disable_vblank,
933 .atomic_begin = fimd_atomic_begin,
934 .update_plane = fimd_update_plane,
935 .disable_plane = fimd_disable_plane,
936 .atomic_flush = fimd_atomic_flush,
937 .atomic_check = fimd_atomic_check,
938 .te_handler = fimd_te_handler,
939 };
940
941 static irqreturn_t fimd_irq_handler(int irq, void *dev_id)
942 {
943 struct fimd_context *ctx = (struct fimd_context *)dev_id;
944 u32 val, clear_bit;
945
946 val = readl(ctx->regs + VIDINTCON1);
947
948 clear_bit = ctx->i80_if ? VIDINTCON1_INT_I80 : VIDINTCON1_INT_FRAME;
949 if (val & clear_bit)
950 writel(clear_bit, ctx->regs + VIDINTCON1);
951
952 /* check the crtc is detached already from encoder */
953 if (!ctx->drm_dev)
954 goto out;
955
956 if (!ctx->i80_if)
957 drm_crtc_handle_vblank(&ctx->crtc->base);
958
959 if (ctx->i80_if) {
960 /* Exits triggering mode */
961 atomic_set(&ctx->triggering, 0);
962 } else {
963 /* set wait vsync event to zero and wake up queue. */
964 if (atomic_read(&ctx->wait_vsync_event)) {
965 atomic_set(&ctx->wait_vsync_event, 0);
966 wake_up(&ctx->wait_vsync_queue);
967 }
968 }
969
970 out:
971 return IRQ_HANDLED;
972 }
973
974 static int fimd_bind(struct device *dev, struct device *master, void *data)
975 {
976 struct fimd_context *ctx = dev_get_drvdata(dev);
977 struct drm_device *drm_dev = data;
978 struct exynos_drm_plane *exynos_plane;
979 unsigned int i;
980 int ret;
981
982 ctx->drm_dev = drm_dev;
983
984 for (i = 0; i < WINDOWS_NR; i++) {
985 ctx->configs[i].pixel_formats = fimd_formats;
986 ctx->configs[i].num_pixel_formats = ARRAY_SIZE(fimd_formats);
987 ctx->configs[i].zpos = i;
988 ctx->configs[i].type = fimd_win_types[i];
989 ret = exynos_plane_init(drm_dev, &ctx->planes[i], i,
990 &ctx->configs[i]);
991 if (ret)
992 return ret;
993 }
994
995 exynos_plane = &ctx->planes[DEFAULT_WIN];
996 ctx->crtc = exynos_drm_crtc_create(drm_dev, &exynos_plane->base,
997 EXYNOS_DISPLAY_TYPE_LCD, &fimd_crtc_ops, ctx);
998 if (IS_ERR(ctx->crtc))
999 return PTR_ERR(ctx->crtc);
1000
1001 if (ctx->driver_data->has_dp_clk) {
1002 ctx->dp_clk.enable = fimd_dp_clock_enable;
1003 ctx->crtc->pipe_clk = &ctx->dp_clk;
1004 }
1005
1006 if (ctx->encoder)
1007 exynos_dpi_bind(drm_dev, ctx->encoder);
1008
1009 if (is_drm_iommu_supported(drm_dev))
1010 fimd_clear_channels(ctx->crtc);
1011
1012 return drm_iommu_attach_device(drm_dev, dev);
1013 }
1014
1015 static void fimd_unbind(struct device *dev, struct device *master,
1016 void *data)
1017 {
1018 struct fimd_context *ctx = dev_get_drvdata(dev);
1019
1020 fimd_disable(ctx->crtc);
1021
1022 drm_iommu_detach_device(ctx->drm_dev, ctx->dev);
1023
1024 if (ctx->encoder)
1025 exynos_dpi_remove(ctx->encoder);
1026 }
1027
1028 static const struct component_ops fimd_component_ops = {
1029 .bind = fimd_bind,
1030 .unbind = fimd_unbind,
1031 };
1032
1033 static int fimd_probe(struct platform_device *pdev)
1034 {
1035 struct device *dev = &pdev->dev;
1036 struct fimd_context *ctx;
1037 struct device_node *i80_if_timings;
1038 struct resource *res;
1039 int ret;
1040
1041 if (!dev->of_node)
1042 return -ENODEV;
1043
1044 ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
1045 if (!ctx)
1046 return -ENOMEM;
1047
1048 ctx->dev = dev;
1049 ctx->suspended = true;
1050 ctx->driver_data = of_device_get_match_data(dev);
1051
1052 if (of_property_read_bool(dev->of_node, "samsung,invert-vden"))
1053 ctx->vidcon1 |= VIDCON1_INV_VDEN;
1054 if (of_property_read_bool(dev->of_node, "samsung,invert-vclk"))
1055 ctx->vidcon1 |= VIDCON1_INV_VCLK;
1056
1057 i80_if_timings = of_get_child_by_name(dev->of_node, "i80-if-timings");
1058 if (i80_if_timings) {
1059 u32 val;
1060
1061 ctx->i80_if = true;
1062
1063 if (ctx->driver_data->has_vidoutcon)
1064 ctx->vidout_con |= VIDOUT_CON_F_I80_LDI0;
1065 else
1066 ctx->vidcon0 |= VIDCON0_VIDOUT_I80_LDI0;
1067 /*
1068 * The user manual describes that this "DSI_EN" bit is required
1069 * to enable I80 24-bit data interface.
1070 */
1071 ctx->vidcon0 |= VIDCON0_DSI_EN;
1072
1073 if (of_property_read_u32(i80_if_timings, "cs-setup", &val))
1074 val = 0;
1075 ctx->i80ifcon = LCD_CS_SETUP(val);
1076 if (of_property_read_u32(i80_if_timings, "wr-setup", &val))
1077 val = 0;
1078 ctx->i80ifcon |= LCD_WR_SETUP(val);
1079 if (of_property_read_u32(i80_if_timings, "wr-active", &val))
1080 val = 1;
1081 ctx->i80ifcon |= LCD_WR_ACTIVE(val);
1082 if (of_property_read_u32(i80_if_timings, "wr-hold", &val))
1083 val = 0;
1084 ctx->i80ifcon |= LCD_WR_HOLD(val);
1085 }
1086 of_node_put(i80_if_timings);
1087
1088 ctx->sysreg = syscon_regmap_lookup_by_phandle(dev->of_node,
1089 "samsung,sysreg");
1090 if (IS_ERR(ctx->sysreg)) {
1091 dev_warn(dev, "failed to get system register.\n");
1092 ctx->sysreg = NULL;
1093 }
1094
1095 ctx->bus_clk = devm_clk_get(dev, "fimd");
1096 if (IS_ERR(ctx->bus_clk)) {
1097 dev_err(dev, "failed to get bus clock\n");
1098 return PTR_ERR(ctx->bus_clk);
1099 }
1100
1101 ctx->lcd_clk = devm_clk_get(dev, "sclk_fimd");
1102 if (IS_ERR(ctx->lcd_clk)) {
1103 dev_err(dev, "failed to get lcd clock\n");
1104 return PTR_ERR(ctx->lcd_clk);
1105 }
1106
1107 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1108
1109 ctx->regs = devm_ioremap_resource(dev, res);
1110 if (IS_ERR(ctx->regs))
1111 return PTR_ERR(ctx->regs);
1112
1113 res = platform_get_resource_byname(pdev, IORESOURCE_IRQ,
1114 ctx->i80_if ? "lcd_sys" : "vsync");
1115 if (!res) {
1116 dev_err(dev, "irq request failed.\n");
1117 return -ENXIO;
1118 }
1119
1120 ret = devm_request_irq(dev, res->start, fimd_irq_handler,
1121 0, "drm_fimd", ctx);
1122 if (ret) {
1123 dev_err(dev, "irq request failed.\n");
1124 return ret;
1125 }
1126
1127 init_waitqueue_head(&ctx->wait_vsync_queue);
1128 atomic_set(&ctx->wait_vsync_event, 0);
1129
1130 platform_set_drvdata(pdev, ctx);
1131
1132 ctx->encoder = exynos_dpi_probe(dev);
1133 if (IS_ERR(ctx->encoder))
1134 return PTR_ERR(ctx->encoder);
1135
1136 pm_runtime_enable(dev);
1137
1138 ret = component_add(dev, &fimd_component_ops);
1139 if (ret)
1140 goto err_disable_pm_runtime;
1141
1142 return ret;
1143
1144 err_disable_pm_runtime:
1145 pm_runtime_disable(dev);
1146
1147 return ret;
1148 }
1149
1150 static int fimd_remove(struct platform_device *pdev)
1151 {
1152 pm_runtime_disable(&pdev->dev);
1153
1154 component_del(&pdev->dev, &fimd_component_ops);
1155
1156 return 0;
1157 }
1158
1159 #ifdef CONFIG_PM
1160 static int exynos_fimd_suspend(struct device *dev)
1161 {
1162 struct fimd_context *ctx = dev_get_drvdata(dev);
1163
1164 clk_disable_unprepare(ctx->lcd_clk);
1165 clk_disable_unprepare(ctx->bus_clk);
1166
1167 return 0;
1168 }
1169
1170 static int exynos_fimd_resume(struct device *dev)
1171 {
1172 struct fimd_context *ctx = dev_get_drvdata(dev);
1173 int ret;
1174
1175 ret = clk_prepare_enable(ctx->bus_clk);
1176 if (ret < 0) {
1177 DRM_ERROR("Failed to prepare_enable the bus clk [%d]\n", ret);
1178 return ret;
1179 }
1180
1181 ret = clk_prepare_enable(ctx->lcd_clk);
1182 if (ret < 0) {
1183 DRM_ERROR("Failed to prepare_enable the lcd clk [%d]\n", ret);
1184 return ret;
1185 }
1186
1187 return 0;
1188 }
1189 #endif
1190
1191 static const struct dev_pm_ops exynos_fimd_pm_ops = {
1192 SET_RUNTIME_PM_OPS(exynos_fimd_suspend, exynos_fimd_resume, NULL)
1193 };
1194
1195 struct platform_driver fimd_driver = {
1196 .probe = fimd_probe,
1197 .remove = fimd_remove,
1198 .driver = {
1199 .name = "exynos4-fb",
1200 .owner = THIS_MODULE,
1201 .pm = &exynos_fimd_pm_ops,
1202 .of_match_table = fimd_driver_dt_match,
1203 },
1204 };
Linux with added FPC-III support