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rcutorture: Eliminate unused ts_rem local from rcu_trace_clock_local()
[linux/fpc-iii.git] / drivers / gpu / drm / radeon / ci_dpm.c
blobc97fbb2ab48b45dc07e1f359caaf1a1df420794d
1 /*
2 * Copyright 2013 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24 #include <linux/firmware.h>
25 #include <drm/drmP.h>
26 #include "radeon.h"
27 #include "radeon_asic.h"
28 #include "radeon_ucode.h"
29 #include "cikd.h"
30 #include "r600_dpm.h"
31 #include "ci_dpm.h"
32 #include "atom.h"
33 #include <linux/seq_file.h>
34
35 #define MC_CG_ARB_FREQ_F0 0x0a
36 #define MC_CG_ARB_FREQ_F1 0x0b
37 #define MC_CG_ARB_FREQ_F2 0x0c
38 #define MC_CG_ARB_FREQ_F3 0x0d
39
40 #define SMC_RAM_END 0x40000
41
42 #define VOLTAGE_SCALE 4
43 #define VOLTAGE_VID_OFFSET_SCALE1 625
44 #define VOLTAGE_VID_OFFSET_SCALE2 100
45
46 static const struct ci_pt_defaults defaults_hawaii_xt =
47 {
48 1, 0xF, 0xFD, 0x19, 5, 0x14, 0, 0xB0000,
49 { 0x2E, 0x00, 0x00, 0x88, 0x00, 0x00, 0x72, 0x60, 0x51, 0xA7, 0x79, 0x6B, 0x90, 0xBD, 0x79 },
50 { 0x217, 0x217, 0x217, 0x242, 0x242, 0x242, 0x269, 0x269, 0x269, 0x2A1, 0x2A1, 0x2A1, 0x2C9, 0x2C9, 0x2C9 }
51 };
52
53 static const struct ci_pt_defaults defaults_hawaii_pro =
54 {
55 1, 0xF, 0xFD, 0x19, 5, 0x14, 0, 0x65062,
56 { 0x2E, 0x00, 0x00, 0x88, 0x00, 0x00, 0x72, 0x60, 0x51, 0xA7, 0x79, 0x6B, 0x90, 0xBD, 0x79 },
57 { 0x217, 0x217, 0x217, 0x242, 0x242, 0x242, 0x269, 0x269, 0x269, 0x2A1, 0x2A1, 0x2A1, 0x2C9, 0x2C9, 0x2C9 }
58 };
59
60 static const struct ci_pt_defaults defaults_bonaire_xt =
61 {
62 1, 0xF, 0xFD, 0x19, 5, 45, 0, 0xB0000,
63 { 0x79, 0x253, 0x25D, 0xAE, 0x72, 0x80, 0x83, 0x86, 0x6F, 0xC8, 0xC9, 0xC9, 0x2F, 0x4D, 0x61 },
64 { 0x17C, 0x172, 0x180, 0x1BC, 0x1B3, 0x1BD, 0x206, 0x200, 0x203, 0x25D, 0x25A, 0x255, 0x2C3, 0x2C5, 0x2B4 }
65 };
66
67 static const struct ci_pt_defaults defaults_bonaire_pro =
68 {
69 1, 0xF, 0xFD, 0x19, 5, 45, 0, 0x65062,
70 { 0x8C, 0x23F, 0x244, 0xA6, 0x83, 0x85, 0x86, 0x86, 0x83, 0xDB, 0xDB, 0xDA, 0x67, 0x60, 0x5F },
71 { 0x187, 0x193, 0x193, 0x1C7, 0x1D1, 0x1D1, 0x210, 0x219, 0x219, 0x266, 0x26C, 0x26C, 0x2C9, 0x2CB, 0x2CB }
72 };
73
74 static const struct ci_pt_defaults defaults_saturn_xt =
75 {
76 1, 0xF, 0xFD, 0x19, 5, 55, 0, 0x70000,
77 { 0x8C, 0x247, 0x249, 0xA6, 0x80, 0x81, 0x8B, 0x89, 0x86, 0xC9, 0xCA, 0xC9, 0x4D, 0x4D, 0x4D },
78 { 0x187, 0x187, 0x187, 0x1C7, 0x1C7, 0x1C7, 0x210, 0x210, 0x210, 0x266, 0x266, 0x266, 0x2C9, 0x2C9, 0x2C9 }
79 };
80
81 static const struct ci_pt_defaults defaults_saturn_pro =
82 {
83 1, 0xF, 0xFD, 0x19, 5, 55, 0, 0x30000,
84 { 0x96, 0x21D, 0x23B, 0xA1, 0x85, 0x87, 0x83, 0x84, 0x81, 0xE6, 0xE6, 0xE6, 0x71, 0x6A, 0x6A },
85 { 0x193, 0x19E, 0x19E, 0x1D2, 0x1DC, 0x1DC, 0x21A, 0x223, 0x223, 0x26E, 0x27E, 0x274, 0x2CF, 0x2D2, 0x2D2 }
86 };
87
88 static const struct ci_pt_config_reg didt_config_ci[] =
89 {
90 { 0x10, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
91 { 0x10, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
92 { 0x10, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
93 { 0x10, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
94 { 0x11, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
95 { 0x11, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
96 { 0x11, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
97 { 0x11, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
98 { 0x12, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
99 { 0x12, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
100 { 0x12, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
101 { 0x12, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
102 { 0x2, 0x00003fff, 0, 0x4, CISLANDS_CONFIGREG_DIDT_IND },
103 { 0x2, 0x03ff0000, 16, 0x80, CISLANDS_CONFIGREG_DIDT_IND },
104 { 0x2, 0x78000000, 27, 0x3, CISLANDS_CONFIGREG_DIDT_IND },
105 { 0x1, 0x0000ffff, 0, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
106 { 0x1, 0xffff0000, 16, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
107 { 0x0, 0x00000001, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
108 { 0x30, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
109 { 0x30, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
110 { 0x30, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
111 { 0x30, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
112 { 0x31, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
113 { 0x31, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
114 { 0x31, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
115 { 0x31, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
116 { 0x32, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
117 { 0x32, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
118 { 0x32, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
119 { 0x32, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
120 { 0x22, 0x00003fff, 0, 0x4, CISLANDS_CONFIGREG_DIDT_IND },
121 { 0x22, 0x03ff0000, 16, 0x80, CISLANDS_CONFIGREG_DIDT_IND },
122 { 0x22, 0x78000000, 27, 0x3, CISLANDS_CONFIGREG_DIDT_IND },
123 { 0x21, 0x0000ffff, 0, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
124 { 0x21, 0xffff0000, 16, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
125 { 0x20, 0x00000001, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
126 { 0x50, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
127 { 0x50, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
128 { 0x50, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
129 { 0x50, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
130 { 0x51, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
131 { 0x51, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
132 { 0x51, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
133 { 0x51, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
134 { 0x52, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
135 { 0x52, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
136 { 0x52, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
137 { 0x52, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
138 { 0x42, 0x00003fff, 0, 0x4, CISLANDS_CONFIGREG_DIDT_IND },
139 { 0x42, 0x03ff0000, 16, 0x80, CISLANDS_CONFIGREG_DIDT_IND },
140 { 0x42, 0x78000000, 27, 0x3, CISLANDS_CONFIGREG_DIDT_IND },
141 { 0x41, 0x0000ffff, 0, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
142 { 0x41, 0xffff0000, 16, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
143 { 0x40, 0x00000001, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
144 { 0x70, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
145 { 0x70, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
146 { 0x70, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
147 { 0x70, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
148 { 0x71, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
149 { 0x71, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
150 { 0x71, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
151 { 0x71, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
152 { 0x72, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
153 { 0x72, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
154 { 0x72, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
155 { 0x72, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
156 { 0x62, 0x00003fff, 0, 0x4, CISLANDS_CONFIGREG_DIDT_IND },
157 { 0x62, 0x03ff0000, 16, 0x80, CISLANDS_CONFIGREG_DIDT_IND },
158 { 0x62, 0x78000000, 27, 0x3, CISLANDS_CONFIGREG_DIDT_IND },
159 { 0x61, 0x0000ffff, 0, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
160 { 0x61, 0xffff0000, 16, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
161 { 0x60, 0x00000001, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
162 { 0xFFFFFFFF }
163 };
164
165 extern u8 rv770_get_memory_module_index(struct radeon_device *rdev);
166 extern int ni_copy_and_switch_arb_sets(struct radeon_device *rdev,
167 u32 arb_freq_src, u32 arb_freq_dest);
168 extern u8 si_get_ddr3_mclk_frequency_ratio(u32 memory_clock);
169 extern u8 si_get_mclk_frequency_ratio(u32 memory_clock, bool strobe_mode);
170 extern void si_trim_voltage_table_to_fit_state_table(struct radeon_device *rdev,
171 u32 max_voltage_steps,
172 struct atom_voltage_table *voltage_table);
173 extern void cik_enter_rlc_safe_mode(struct radeon_device *rdev);
174 extern void cik_exit_rlc_safe_mode(struct radeon_device *rdev);
175 extern int ci_mc_load_microcode(struct radeon_device *rdev);
176 extern void cik_update_cg(struct radeon_device *rdev,
177 u32 block, bool enable);
178
179 static int ci_get_std_voltage_value_sidd(struct radeon_device *rdev,
180 struct atom_voltage_table_entry *voltage_table,
181 u16 *std_voltage_hi_sidd, u16 *std_voltage_lo_sidd);
182 static int ci_set_power_limit(struct radeon_device *rdev, u32 n);
183 static int ci_set_overdrive_target_tdp(struct radeon_device *rdev,
184 u32 target_tdp);
185 static int ci_update_uvd_dpm(struct radeon_device *rdev, bool gate);
186
187 static PPSMC_Result ci_send_msg_to_smc_with_parameter(struct radeon_device *rdev,
188 PPSMC_Msg msg, u32 parameter);
189
190 static void ci_thermal_start_smc_fan_control(struct radeon_device *rdev);
191 static void ci_fan_ctrl_set_default_mode(struct radeon_device *rdev);
192
193 static struct ci_power_info *ci_get_pi(struct radeon_device *rdev)
194 {
195 struct ci_power_info *pi = rdev->pm.dpm.priv;
196
197 return pi;
198 }
199
200 static struct ci_ps *ci_get_ps(struct radeon_ps *rps)
201 {
202 struct ci_ps *ps = rps->ps_priv;
203
204 return ps;
205 }
206
207 static void ci_initialize_powertune_defaults(struct radeon_device *rdev)
208 {
209 struct ci_power_info *pi = ci_get_pi(rdev);
210
211 switch (rdev->pdev->device) {
212 case 0x6649:
213 case 0x6650:
214 case 0x6651:
215 case 0x6658:
216 case 0x665C:
217 case 0x665D:
218 default:
219 pi->powertune_defaults = &defaults_bonaire_xt;
220 break;
221 case 0x6640:
222 case 0x6641:
223 case 0x6646:
224 case 0x6647:
225 pi->powertune_defaults = &defaults_saturn_xt;
226 break;
227 case 0x67B8:
228 case 0x67B0:
229 pi->powertune_defaults = &defaults_hawaii_xt;
230 break;
231 case 0x67BA:
232 case 0x67B1:
233 pi->powertune_defaults = &defaults_hawaii_pro;
234 break;
235 case 0x67A0:
236 case 0x67A1:
237 case 0x67A2:
238 case 0x67A8:
239 case 0x67A9:
240 case 0x67AA:
241 case 0x67B9:
242 case 0x67BE:
243 pi->powertune_defaults = &defaults_bonaire_xt;
244 break;
245 }
246
247 pi->dte_tj_offset = 0;
248
249 pi->caps_power_containment = true;
250 pi->caps_cac = false;
251 pi->caps_sq_ramping = false;
252 pi->caps_db_ramping = false;
253 pi->caps_td_ramping = false;
254 pi->caps_tcp_ramping = false;
255
256 if (pi->caps_power_containment) {
257 pi->caps_cac = true;
258 if (rdev->family == CHIP_HAWAII)
259 pi->enable_bapm_feature = false;
260 else
261 pi->enable_bapm_feature = true;
262 pi->enable_tdc_limit_feature = true;
263 pi->enable_pkg_pwr_tracking_feature = true;
264 }
265 }
266
267 static u8 ci_convert_to_vid(u16 vddc)
268 {
269 return (6200 - (vddc * VOLTAGE_SCALE)) / 25;
270 }
271
272 static int ci_populate_bapm_vddc_vid_sidd(struct radeon_device *rdev)
273 {
274 struct ci_power_info *pi = ci_get_pi(rdev);
275 u8 *hi_vid = pi->smc_powertune_table.BapmVddCVidHiSidd;
276 u8 *lo_vid = pi->smc_powertune_table.BapmVddCVidLoSidd;
277 u8 *hi2_vid = pi->smc_powertune_table.BapmVddCVidHiSidd2;
278 u32 i;
279
280 if (rdev->pm.dpm.dyn_state.cac_leakage_table.entries == NULL)
281 return -EINVAL;
282 if (rdev->pm.dpm.dyn_state.cac_leakage_table.count > 8)
283 return -EINVAL;
284 if (rdev->pm.dpm.dyn_state.cac_leakage_table.count !=
285 rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count)
286 return -EINVAL;
287
288 for (i = 0; i < rdev->pm.dpm.dyn_state.cac_leakage_table.count; i++) {
289 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_EVV) {
290 lo_vid[i] = ci_convert_to_vid(rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc1);
291 hi_vid[i] = ci_convert_to_vid(rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc2);
292 hi2_vid[i] = ci_convert_to_vid(rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc3);
293 } else {
294 lo_vid[i] = ci_convert_to_vid(rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc);
295 hi_vid[i] = ci_convert_to_vid((u16)rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].leakage);
296 }
297 }
298 return 0;
299 }
300
301 static int ci_populate_vddc_vid(struct radeon_device *rdev)
302 {
303 struct ci_power_info *pi = ci_get_pi(rdev);
304 u8 *vid = pi->smc_powertune_table.VddCVid;
305 u32 i;
306
307 if (pi->vddc_voltage_table.count > 8)
308 return -EINVAL;
309
310 for (i = 0; i < pi->vddc_voltage_table.count; i++)
311 vid[i] = ci_convert_to_vid(pi->vddc_voltage_table.entries[i].value);
312
313 return 0;
314 }
315
316 static int ci_populate_svi_load_line(struct radeon_device *rdev)
317 {
318 struct ci_power_info *pi = ci_get_pi(rdev);
319 const struct ci_pt_defaults *pt_defaults = pi->powertune_defaults;
320
321 pi->smc_powertune_table.SviLoadLineEn = pt_defaults->svi_load_line_en;
322 pi->smc_powertune_table.SviLoadLineVddC = pt_defaults->svi_load_line_vddc;
323 pi->smc_powertune_table.SviLoadLineTrimVddC = 3;
324 pi->smc_powertune_table.SviLoadLineOffsetVddC = 0;
325
326 return 0;
327 }
328
329 static int ci_populate_tdc_limit(struct radeon_device *rdev)
330 {
331 struct ci_power_info *pi = ci_get_pi(rdev);
332 const struct ci_pt_defaults *pt_defaults = pi->powertune_defaults;
333 u16 tdc_limit;
334
335 tdc_limit = rdev->pm.dpm.dyn_state.cac_tdp_table->tdc * 256;
336 pi->smc_powertune_table.TDC_VDDC_PkgLimit = cpu_to_be16(tdc_limit);
337 pi->smc_powertune_table.TDC_VDDC_ThrottleReleaseLimitPerc =
338 pt_defaults->tdc_vddc_throttle_release_limit_perc;
339 pi->smc_powertune_table.TDC_MAWt = pt_defaults->tdc_mawt;
340
341 return 0;
342 }
343
344 static int ci_populate_dw8(struct radeon_device *rdev)
345 {
346 struct ci_power_info *pi = ci_get_pi(rdev);
347 const struct ci_pt_defaults *pt_defaults = pi->powertune_defaults;
348 int ret;
349
350 ret = ci_read_smc_sram_dword(rdev,
351 SMU7_FIRMWARE_HEADER_LOCATION +
352 offsetof(SMU7_Firmware_Header, PmFuseTable) +
353 offsetof(SMU7_Discrete_PmFuses, TdcWaterfallCtl),
354 (u32 *)&pi->smc_powertune_table.TdcWaterfallCtl,
355 pi->sram_end);
356 if (ret)
357 return -EINVAL;
358 else
359 pi->smc_powertune_table.TdcWaterfallCtl = pt_defaults->tdc_waterfall_ctl;
360
361 return 0;
362 }
363
364 static int ci_populate_fuzzy_fan(struct radeon_device *rdev)
365 {
366 struct ci_power_info *pi = ci_get_pi(rdev);
367
368 if ((rdev->pm.dpm.fan.fan_output_sensitivity & (1 << 15)) ||
369 (rdev->pm.dpm.fan.fan_output_sensitivity == 0))
370 rdev->pm.dpm.fan.fan_output_sensitivity =
371 rdev->pm.dpm.fan.default_fan_output_sensitivity;
372
373 pi->smc_powertune_table.FuzzyFan_PwmSetDelta =
374 cpu_to_be16(rdev->pm.dpm.fan.fan_output_sensitivity);
375
376 return 0;
377 }
378
379 static int ci_min_max_v_gnbl_pm_lid_from_bapm_vddc(struct radeon_device *rdev)
380 {
381 struct ci_power_info *pi = ci_get_pi(rdev);
382 u8 *hi_vid = pi->smc_powertune_table.BapmVddCVidHiSidd;
383 u8 *lo_vid = pi->smc_powertune_table.BapmVddCVidLoSidd;
384 int i, min, max;
385
386 min = max = hi_vid[0];
387 for (i = 0; i < 8; i++) {
388 if (0 != hi_vid[i]) {
389 if (min > hi_vid[i])
390 min = hi_vid[i];
391 if (max < hi_vid[i])
392 max = hi_vid[i];
393 }
394
395 if (0 != lo_vid[i]) {
396 if (min > lo_vid[i])
397 min = lo_vid[i];
398 if (max < lo_vid[i])
399 max = lo_vid[i];
400 }
401 }
402
403 if ((min == 0) || (max == 0))
404 return -EINVAL;
405 pi->smc_powertune_table.GnbLPMLMaxVid = (u8)max;
406 pi->smc_powertune_table.GnbLPMLMinVid = (u8)min;
407
408 return 0;
409 }
410
411 static int ci_populate_bapm_vddc_base_leakage_sidd(struct radeon_device *rdev)
412 {
413 struct ci_power_info *pi = ci_get_pi(rdev);
414 u16 hi_sidd = pi->smc_powertune_table.BapmVddCBaseLeakageHiSidd;
415 u16 lo_sidd = pi->smc_powertune_table.BapmVddCBaseLeakageLoSidd;
416 struct radeon_cac_tdp_table *cac_tdp_table =
417 rdev->pm.dpm.dyn_state.cac_tdp_table;
418
419 hi_sidd = cac_tdp_table->high_cac_leakage / 100 * 256;
420 lo_sidd = cac_tdp_table->low_cac_leakage / 100 * 256;
421
422 pi->smc_powertune_table.BapmVddCBaseLeakageHiSidd = cpu_to_be16(hi_sidd);
423 pi->smc_powertune_table.BapmVddCBaseLeakageLoSidd = cpu_to_be16(lo_sidd);
424
425 return 0;
426 }
427
428 static int ci_populate_bapm_parameters_in_dpm_table(struct radeon_device *rdev)
429 {
430 struct ci_power_info *pi = ci_get_pi(rdev);
431 const struct ci_pt_defaults *pt_defaults = pi->powertune_defaults;
432 SMU7_Discrete_DpmTable *dpm_table = &pi->smc_state_table;
433 struct radeon_cac_tdp_table *cac_tdp_table =
434 rdev->pm.dpm.dyn_state.cac_tdp_table;
435 struct radeon_ppm_table *ppm = rdev->pm.dpm.dyn_state.ppm_table;
436 int i, j, k;
437 const u16 *def1;
438 const u16 *def2;
439
440 dpm_table->DefaultTdp = cac_tdp_table->tdp * 256;
441 dpm_table->TargetTdp = cac_tdp_table->configurable_tdp * 256;
442
443 dpm_table->DTETjOffset = (u8)pi->dte_tj_offset;
444 dpm_table->GpuTjMax =
445 (u8)(pi->thermal_temp_setting.temperature_high / 1000);
446 dpm_table->GpuTjHyst = 8;
447
448 dpm_table->DTEAmbientTempBase = pt_defaults->dte_ambient_temp_base;
449
450 if (ppm) {
451 dpm_table->PPM_PkgPwrLimit = cpu_to_be16((u16)ppm->dgpu_tdp * 256 / 1000);
452 dpm_table->PPM_TemperatureLimit = cpu_to_be16((u16)ppm->tj_max * 256);
453 } else {
454 dpm_table->PPM_PkgPwrLimit = cpu_to_be16(0);
455 dpm_table->PPM_TemperatureLimit = cpu_to_be16(0);
456 }
457
458 dpm_table->BAPM_TEMP_GRADIENT = cpu_to_be32(pt_defaults->bapm_temp_gradient);
459 def1 = pt_defaults->bapmti_r;
460 def2 = pt_defaults->bapmti_rc;
461
462 for (i = 0; i < SMU7_DTE_ITERATIONS; i++) {
463 for (j = 0; j < SMU7_DTE_SOURCES; j++) {
464 for (k = 0; k < SMU7_DTE_SINKS; k++) {
465 dpm_table->BAPMTI_R[i][j][k] = cpu_to_be16(*def1);
466 dpm_table->BAPMTI_RC[i][j][k] = cpu_to_be16(*def2);
467 def1++;
468 def2++;
469 }
470 }
471 }
472
473 return 0;
474 }
475
476 static int ci_populate_pm_base(struct radeon_device *rdev)
477 {
478 struct ci_power_info *pi = ci_get_pi(rdev);
479 u32 pm_fuse_table_offset;
480 int ret;
481
482 if (pi->caps_power_containment) {
483 ret = ci_read_smc_sram_dword(rdev,
484 SMU7_FIRMWARE_HEADER_LOCATION +
485 offsetof(SMU7_Firmware_Header, PmFuseTable),
486 &pm_fuse_table_offset, pi->sram_end);
487 if (ret)
488 return ret;
489 ret = ci_populate_bapm_vddc_vid_sidd(rdev);
490 if (ret)
491 return ret;
492 ret = ci_populate_vddc_vid(rdev);
493 if (ret)
494 return ret;
495 ret = ci_populate_svi_load_line(rdev);
496 if (ret)
497 return ret;
498 ret = ci_populate_tdc_limit(rdev);
499 if (ret)
500 return ret;
501 ret = ci_populate_dw8(rdev);
502 if (ret)
503 return ret;
504 ret = ci_populate_fuzzy_fan(rdev);
505 if (ret)
506 return ret;
507 ret = ci_min_max_v_gnbl_pm_lid_from_bapm_vddc(rdev);
508 if (ret)
509 return ret;
510 ret = ci_populate_bapm_vddc_base_leakage_sidd(rdev);
511 if (ret)
512 return ret;
513 ret = ci_copy_bytes_to_smc(rdev, pm_fuse_table_offset,
514 (u8 *)&pi->smc_powertune_table,
515 sizeof(SMU7_Discrete_PmFuses), pi->sram_end);
516 if (ret)
517 return ret;
518 }
519
520 return 0;
521 }
522
523 static void ci_do_enable_didt(struct radeon_device *rdev, const bool enable)
524 {
525 struct ci_power_info *pi = ci_get_pi(rdev);
526 u32 data;
527
528 if (pi->caps_sq_ramping) {
529 data = RREG32_DIDT(DIDT_SQ_CTRL0);
530 if (enable)
531 data |= DIDT_CTRL_EN;
532 else
533 data &= ~DIDT_CTRL_EN;
534 WREG32_DIDT(DIDT_SQ_CTRL0, data);
535 }
536
537 if (pi->caps_db_ramping) {
538 data = RREG32_DIDT(DIDT_DB_CTRL0);
539 if (enable)
540 data |= DIDT_CTRL_EN;
541 else
542 data &= ~DIDT_CTRL_EN;
543 WREG32_DIDT(DIDT_DB_CTRL0, data);
544 }
545
546 if (pi->caps_td_ramping) {
547 data = RREG32_DIDT(DIDT_TD_CTRL0);
548 if (enable)
549 data |= DIDT_CTRL_EN;
550 else
551 data &= ~DIDT_CTRL_EN;
552 WREG32_DIDT(DIDT_TD_CTRL0, data);
553 }
554
555 if (pi->caps_tcp_ramping) {
556 data = RREG32_DIDT(DIDT_TCP_CTRL0);
557 if (enable)
558 data |= DIDT_CTRL_EN;
559 else
560 data &= ~DIDT_CTRL_EN;
561 WREG32_DIDT(DIDT_TCP_CTRL0, data);
562 }
563 }
564
565 static int ci_program_pt_config_registers(struct radeon_device *rdev,
566 const struct ci_pt_config_reg *cac_config_regs)
567 {
568 const struct ci_pt_config_reg *config_regs = cac_config_regs;
569 u32 data;
570 u32 cache = 0;
571
572 if (config_regs == NULL)
573 return -EINVAL;
574
575 while (config_regs->offset != 0xFFFFFFFF) {
576 if (config_regs->type == CISLANDS_CONFIGREG_CACHE) {
577 cache |= ((config_regs->value << config_regs->shift) & config_regs->mask);
578 } else {
579 switch (config_regs->type) {
580 case CISLANDS_CONFIGREG_SMC_IND:
581 data = RREG32_SMC(config_regs->offset);
582 break;
583 case CISLANDS_CONFIGREG_DIDT_IND:
584 data = RREG32_DIDT(config_regs->offset);
585 break;
586 default:
587 data = RREG32(config_regs->offset << 2);
588 break;
589 }
590
591 data &= ~config_regs->mask;
592 data |= ((config_regs->value << config_regs->shift) & config_regs->mask);
593 data |= cache;
594
595 switch (config_regs->type) {
596 case CISLANDS_CONFIGREG_SMC_IND:
597 WREG32_SMC(config_regs->offset, data);
598 break;
599 case CISLANDS_CONFIGREG_DIDT_IND:
600 WREG32_DIDT(config_regs->offset, data);
601 break;
602 default:
603 WREG32(config_regs->offset << 2, data);
604 break;
605 }
606 cache = 0;
607 }
608 config_regs++;
609 }
610 return 0;
611 }
612
613 static int ci_enable_didt(struct radeon_device *rdev, bool enable)
614 {
615 struct ci_power_info *pi = ci_get_pi(rdev);
616 int ret;
617
618 if (pi->caps_sq_ramping || pi->caps_db_ramping ||
619 pi->caps_td_ramping || pi->caps_tcp_ramping) {
620 cik_enter_rlc_safe_mode(rdev);
621
622 if (enable) {
623 ret = ci_program_pt_config_registers(rdev, didt_config_ci);
624 if (ret) {
625 cik_exit_rlc_safe_mode(rdev);
626 return ret;
627 }
628 }
629
630 ci_do_enable_didt(rdev, enable);
631
632 cik_exit_rlc_safe_mode(rdev);
633 }
634
635 return 0;
636 }
637
638 static int ci_enable_power_containment(struct radeon_device *rdev, bool enable)
639 {
640 struct ci_power_info *pi = ci_get_pi(rdev);
641 PPSMC_Result smc_result;
642 int ret = 0;
643
644 if (enable) {
645 pi->power_containment_features = 0;
646 if (pi->caps_power_containment) {
647 if (pi->enable_bapm_feature) {
648 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_EnableDTE);
649 if (smc_result != PPSMC_Result_OK)
650 ret = -EINVAL;
651 else
652 pi->power_containment_features |= POWERCONTAINMENT_FEATURE_BAPM;
653 }
654
655 if (pi->enable_tdc_limit_feature) {
656 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_TDCLimitEnable);
657 if (smc_result != PPSMC_Result_OK)
658 ret = -EINVAL;
659 else
660 pi->power_containment_features |= POWERCONTAINMENT_FEATURE_TDCLimit;
661 }
662
663 if (pi->enable_pkg_pwr_tracking_feature) {
664 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_PkgPwrLimitEnable);
665 if (smc_result != PPSMC_Result_OK) {
666 ret = -EINVAL;
667 } else {
668 struct radeon_cac_tdp_table *cac_tdp_table =
669 rdev->pm.dpm.dyn_state.cac_tdp_table;
670 u32 default_pwr_limit =
671 (u32)(cac_tdp_table->maximum_power_delivery_limit * 256);
672
673 pi->power_containment_features |= POWERCONTAINMENT_FEATURE_PkgPwrLimit;
674
675 ci_set_power_limit(rdev, default_pwr_limit);
676 }
677 }
678 }
679 } else {
680 if (pi->caps_power_containment && pi->power_containment_features) {
681 if (pi->power_containment_features & POWERCONTAINMENT_FEATURE_TDCLimit)
682 ci_send_msg_to_smc(rdev, PPSMC_MSG_TDCLimitDisable);
683
684 if (pi->power_containment_features & POWERCONTAINMENT_FEATURE_BAPM)
685 ci_send_msg_to_smc(rdev, PPSMC_MSG_DisableDTE);
686
687 if (pi->power_containment_features & POWERCONTAINMENT_FEATURE_PkgPwrLimit)
688 ci_send_msg_to_smc(rdev, PPSMC_MSG_PkgPwrLimitDisable);
689 pi->power_containment_features = 0;
690 }
691 }
692
693 return ret;
694 }
695
696 static int ci_enable_smc_cac(struct radeon_device *rdev, bool enable)
697 {
698 struct ci_power_info *pi = ci_get_pi(rdev);
699 PPSMC_Result smc_result;
700 int ret = 0;
701
702 if (pi->caps_cac) {
703 if (enable) {
704 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_EnableCac);
705 if (smc_result != PPSMC_Result_OK) {
706 ret = -EINVAL;
707 pi->cac_enabled = false;
708 } else {
709 pi->cac_enabled = true;
710 }
711 } else if (pi->cac_enabled) {
712 ci_send_msg_to_smc(rdev, PPSMC_MSG_DisableCac);
713 pi->cac_enabled = false;
714 }
715 }
716
717 return ret;
718 }
719
720 static int ci_enable_thermal_based_sclk_dpm(struct radeon_device *rdev,
721 bool enable)
722 {
723 struct ci_power_info *pi = ci_get_pi(rdev);
724 PPSMC_Result smc_result = PPSMC_Result_OK;
725
726 if (pi->thermal_sclk_dpm_enabled) {
727 if (enable)
728 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_ENABLE_THERMAL_DPM);
729 else
730 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_DISABLE_THERMAL_DPM);
731 }
732
733 if (smc_result == PPSMC_Result_OK)
734 return 0;
735 else
736 return -EINVAL;
737 }
738
739 static int ci_power_control_set_level(struct radeon_device *rdev)
740 {
741 struct ci_power_info *pi = ci_get_pi(rdev);
742 struct radeon_cac_tdp_table *cac_tdp_table =
743 rdev->pm.dpm.dyn_state.cac_tdp_table;
744 s32 adjust_percent;
745 s32 target_tdp;
746 int ret = 0;
747 bool adjust_polarity = false; /* ??? */
748
749 if (pi->caps_power_containment) {
750 adjust_percent = adjust_polarity ?
751 rdev->pm.dpm.tdp_adjustment : (-1 * rdev->pm.dpm.tdp_adjustment);
752 target_tdp = ((100 + adjust_percent) *
753 (s32)cac_tdp_table->configurable_tdp) / 100;
754
755 ret = ci_set_overdrive_target_tdp(rdev, (u32)target_tdp);
756 }
757
758 return ret;
759 }
760
761 void ci_dpm_powergate_uvd(struct radeon_device *rdev, bool gate)
762 {
763 struct ci_power_info *pi = ci_get_pi(rdev);
764
765 if (pi->uvd_power_gated == gate)
766 return;
767
768 pi->uvd_power_gated = gate;
769
770 ci_update_uvd_dpm(rdev, gate);
771 }
772
773 bool ci_dpm_vblank_too_short(struct radeon_device *rdev)
774 {
775 struct ci_power_info *pi = ci_get_pi(rdev);
776 u32 vblank_time = r600_dpm_get_vblank_time(rdev);
777 u32 switch_limit = pi->mem_gddr5 ? 450 : 300;
778
779 /* disable mclk switching if the refresh is >120Hz, even if the
780 * blanking period would allow it
781 */
782 if (r600_dpm_get_vrefresh(rdev) > 120)
783 return true;
784
785 if (vblank_time < switch_limit)
786 return true;
787 else
788 return false;
789
790 }
791
792 static void ci_apply_state_adjust_rules(struct radeon_device *rdev,
793 struct radeon_ps *rps)
794 {
795 struct ci_ps *ps = ci_get_ps(rps);
796 struct ci_power_info *pi = ci_get_pi(rdev);
797 struct radeon_clock_and_voltage_limits *max_limits;
798 bool disable_mclk_switching;
799 u32 sclk, mclk;
800 int i;
801
802 if (rps->vce_active) {
803 rps->evclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].evclk;
804 rps->ecclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].ecclk;
805 } else {
806 rps->evclk = 0;
807 rps->ecclk = 0;
808 }
809
810 if ((rdev->pm.dpm.new_active_crtc_count > 1) ||
811 ci_dpm_vblank_too_short(rdev))
812 disable_mclk_switching = true;
813 else
814 disable_mclk_switching = false;
815
816 if ((rps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) == ATOM_PPLIB_CLASSIFICATION_UI_BATTERY)
817 pi->battery_state = true;
818 else
819 pi->battery_state = false;
820
821 if (rdev->pm.dpm.ac_power)
822 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
823 else
824 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
825
826 if (rdev->pm.dpm.ac_power == false) {
827 for (i = 0; i < ps->performance_level_count; i++) {
828 if (ps->performance_levels[i].mclk > max_limits->mclk)
829 ps->performance_levels[i].mclk = max_limits->mclk;
830 if (ps->performance_levels[i].sclk > max_limits->sclk)
831 ps->performance_levels[i].sclk = max_limits->sclk;
832 }
833 }
834
835 /* XXX validate the min clocks required for display */
836
837 if (disable_mclk_switching) {
838 mclk = ps->performance_levels[ps->performance_level_count - 1].mclk;
839 sclk = ps->performance_levels[0].sclk;
840 } else {
841 mclk = ps->performance_levels[0].mclk;
842 sclk = ps->performance_levels[0].sclk;
843 }
844
845 if (rps->vce_active) {
846 if (sclk < rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].sclk)
847 sclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].sclk;
848 if (mclk < rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].mclk)
849 mclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].mclk;
850 }
851
852 ps->performance_levels[0].sclk = sclk;
853 ps->performance_levels[0].mclk = mclk;
854
855 if (ps->performance_levels[1].sclk < ps->performance_levels[0].sclk)
856 ps->performance_levels[1].sclk = ps->performance_levels[0].sclk;
857
858 if (disable_mclk_switching) {
859 if (ps->performance_levels[0].mclk < ps->performance_levels[1].mclk)
860 ps->performance_levels[0].mclk = ps->performance_levels[1].mclk;
861 } else {
862 if (ps->performance_levels[1].mclk < ps->performance_levels[0].mclk)
863 ps->performance_levels[1].mclk = ps->performance_levels[0].mclk;
864 }
865 }
866
867 static int ci_thermal_set_temperature_range(struct radeon_device *rdev,
868 int min_temp, int max_temp)
869 {
870 int low_temp = 0 * 1000;
871 int high_temp = 255 * 1000;
872 u32 tmp;
873
874 if (low_temp < min_temp)
875 low_temp = min_temp;
876 if (high_temp > max_temp)
877 high_temp = max_temp;
878 if (high_temp < low_temp) {
879 DRM_ERROR("invalid thermal range: %d - %d\n", low_temp, high_temp);
880 return -EINVAL;
881 }
882
883 tmp = RREG32_SMC(CG_THERMAL_INT);
884 tmp &= ~(CI_DIG_THERM_INTH_MASK | CI_DIG_THERM_INTL_MASK);
885 tmp |= CI_DIG_THERM_INTH(high_temp / 1000) |
886 CI_DIG_THERM_INTL(low_temp / 1000);
887 WREG32_SMC(CG_THERMAL_INT, tmp);
888
889 #if 0
890 /* XXX: need to figure out how to handle this properly */
891 tmp = RREG32_SMC(CG_THERMAL_CTRL);
892 tmp &= DIG_THERM_DPM_MASK;
893 tmp |= DIG_THERM_DPM(high_temp / 1000);
894 WREG32_SMC(CG_THERMAL_CTRL, tmp);
895 #endif
896
897 rdev->pm.dpm.thermal.min_temp = low_temp;
898 rdev->pm.dpm.thermal.max_temp = high_temp;
899
900 return 0;
901 }
902
903 static int ci_thermal_enable_alert(struct radeon_device *rdev,
904 bool enable)
905 {
906 u32 thermal_int = RREG32_SMC(CG_THERMAL_INT);
907 PPSMC_Result result;
908
909 if (enable) {
910 thermal_int &= ~(THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW);
911 WREG32_SMC(CG_THERMAL_INT, thermal_int);
912 rdev->irq.dpm_thermal = false;
913 result = ci_send_msg_to_smc(rdev, PPSMC_MSG_Thermal_Cntl_Enable);
914 if (result != PPSMC_Result_OK) {
915 DRM_DEBUG_KMS("Could not enable thermal interrupts.\n");
916 return -EINVAL;
917 }
918 } else {
919 thermal_int |= THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW;
920 WREG32_SMC(CG_THERMAL_INT, thermal_int);
921 rdev->irq.dpm_thermal = true;
922 result = ci_send_msg_to_smc(rdev, PPSMC_MSG_Thermal_Cntl_Disable);
923 if (result != PPSMC_Result_OK) {
924 DRM_DEBUG_KMS("Could not disable thermal interrupts.\n");
925 return -EINVAL;
926 }
927 }
928
929 return 0;
930 }
931
932 static void ci_fan_ctrl_set_static_mode(struct radeon_device *rdev, u32 mode)
933 {
934 struct ci_power_info *pi = ci_get_pi(rdev);
935 u32 tmp;
936
937 if (pi->fan_ctrl_is_in_default_mode) {
938 tmp = (RREG32_SMC(CG_FDO_CTRL2) & FDO_PWM_MODE_MASK) >> FDO_PWM_MODE_SHIFT;
939 pi->fan_ctrl_default_mode = tmp;
940 tmp = (RREG32_SMC(CG_FDO_CTRL2) & TMIN_MASK) >> TMIN_SHIFT;
941 pi->t_min = tmp;
942 pi->fan_ctrl_is_in_default_mode = false;
943 }
944
945 tmp = RREG32_SMC(CG_FDO_CTRL2) & ~TMIN_MASK;
946 tmp |= TMIN(0);
947 WREG32_SMC(CG_FDO_CTRL2, tmp);
948
949 tmp = RREG32_SMC(CG_FDO_CTRL2) & ~FDO_PWM_MODE_MASK;
950 tmp |= FDO_PWM_MODE(mode);
951 WREG32_SMC(CG_FDO_CTRL2, tmp);
952 }
953
954 static int ci_thermal_setup_fan_table(struct radeon_device *rdev)
955 {
956 struct ci_power_info *pi = ci_get_pi(rdev);
957 SMU7_Discrete_FanTable fan_table = { FDO_MODE_HARDWARE };
958 u32 duty100;
959 u32 t_diff1, t_diff2, pwm_diff1, pwm_diff2;
960 u16 fdo_min, slope1, slope2;
961 u32 reference_clock, tmp;
962 int ret;
963 u64 tmp64;
964
965 if (!pi->fan_table_start) {
966 rdev->pm.dpm.fan.ucode_fan_control = false;
967 return 0;
968 }
969
970 duty100 = (RREG32_SMC(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT;
971
972 if (duty100 == 0) {
973 rdev->pm.dpm.fan.ucode_fan_control = false;
974 return 0;
975 }
976
977 tmp64 = (u64)rdev->pm.dpm.fan.pwm_min * duty100;
978 do_div(tmp64, 10000);
979 fdo_min = (u16)tmp64;
980
981 t_diff1 = rdev->pm.dpm.fan.t_med - rdev->pm.dpm.fan.t_min;
982 t_diff2 = rdev->pm.dpm.fan.t_high - rdev->pm.dpm.fan.t_med;
983
984 pwm_diff1 = rdev->pm.dpm.fan.pwm_med - rdev->pm.dpm.fan.pwm_min;
985 pwm_diff2 = rdev->pm.dpm.fan.pwm_high - rdev->pm.dpm.fan.pwm_med;
986
987 slope1 = (u16)((50 + ((16 * duty100 * pwm_diff1) / t_diff1)) / 100);
988 slope2 = (u16)((50 + ((16 * duty100 * pwm_diff2) / t_diff2)) / 100);
989
990 fan_table.TempMin = cpu_to_be16((50 + rdev->pm.dpm.fan.t_min) / 100);
991 fan_table.TempMed = cpu_to_be16((50 + rdev->pm.dpm.fan.t_med) / 100);
992 fan_table.TempMax = cpu_to_be16((50 + rdev->pm.dpm.fan.t_max) / 100);
993
994 fan_table.Slope1 = cpu_to_be16(slope1);
995 fan_table.Slope2 = cpu_to_be16(slope2);
996
997 fan_table.FdoMin = cpu_to_be16(fdo_min);
998
999 fan_table.HystDown = cpu_to_be16(rdev->pm.dpm.fan.t_hyst);
1000
1001 fan_table.HystUp = cpu_to_be16(1);
1002
1003 fan_table.HystSlope = cpu_to_be16(1);
1004
1005 fan_table.TempRespLim = cpu_to_be16(5);
1006
1007 reference_clock = radeon_get_xclk(rdev);
1008
1009 fan_table.RefreshPeriod = cpu_to_be32((rdev->pm.dpm.fan.cycle_delay *
1010 reference_clock) / 1600);
1011
1012 fan_table.FdoMax = cpu_to_be16((u16)duty100);
1013
1014 tmp = (RREG32_SMC(CG_MULT_THERMAL_CTRL) & TEMP_SEL_MASK) >> TEMP_SEL_SHIFT;
1015 fan_table.TempSrc = (uint8_t)tmp;
1016
1017 ret = ci_copy_bytes_to_smc(rdev,
1018 pi->fan_table_start,
1019 (u8 *)(&fan_table),
1020 sizeof(fan_table),
1021 pi->sram_end);
1022
1023 if (ret) {
1024 DRM_ERROR("Failed to load fan table to the SMC.");
1025 rdev->pm.dpm.fan.ucode_fan_control = false;
1026 }
1027
1028 return 0;
1029 }
1030
1031 static int ci_fan_ctrl_start_smc_fan_control(struct radeon_device *rdev)
1032 {
1033 struct ci_power_info *pi = ci_get_pi(rdev);
1034 PPSMC_Result ret;
1035
1036 if (pi->caps_od_fuzzy_fan_control_support) {
1037 ret = ci_send_msg_to_smc_with_parameter(rdev,
1038 PPSMC_StartFanControl,
1039 FAN_CONTROL_FUZZY);
1040 if (ret != PPSMC_Result_OK)
1041 return -EINVAL;
1042 ret = ci_send_msg_to_smc_with_parameter(rdev,
1043 PPSMC_MSG_SetFanPwmMax,
1044 rdev->pm.dpm.fan.default_max_fan_pwm);
1045 if (ret != PPSMC_Result_OK)
1046 return -EINVAL;
1047 } else {
1048 ret = ci_send_msg_to_smc_with_parameter(rdev,
1049 PPSMC_StartFanControl,
1050 FAN_CONTROL_TABLE);
1051 if (ret != PPSMC_Result_OK)
1052 return -EINVAL;
1053 }
1054
1055 pi->fan_is_controlled_by_smc = true;
1056 return 0;
1057 }
1058
1059 static int ci_fan_ctrl_stop_smc_fan_control(struct radeon_device *rdev)
1060 {
1061 PPSMC_Result ret;
1062 struct ci_power_info *pi = ci_get_pi(rdev);
1063
1064 ret = ci_send_msg_to_smc(rdev, PPSMC_StopFanControl);
1065 if (ret == PPSMC_Result_OK) {
1066 pi->fan_is_controlled_by_smc = false;
1067 return 0;
1068 } else
1069 return -EINVAL;
1070 }
1071
1072 int ci_fan_ctrl_get_fan_speed_percent(struct radeon_device *rdev,
1073 u32 *speed)
1074 {
1075 u32 duty, duty100;
1076 u64 tmp64;
1077
1078 if (rdev->pm.no_fan)
1079 return -ENOENT;
1080
1081 duty100 = (RREG32_SMC(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT;
1082 duty = (RREG32_SMC(CG_THERMAL_STATUS) & FDO_PWM_DUTY_MASK) >> FDO_PWM_DUTY_SHIFT;
1083
1084 if (duty100 == 0)
1085 return -EINVAL;
1086
1087 tmp64 = (u64)duty * 100;
1088 do_div(tmp64, duty100);
1089 *speed = (u32)tmp64;
1090
1091 if (*speed > 100)
1092 *speed = 100;
1093
1094 return 0;
1095 }
1096
1097 int ci_fan_ctrl_set_fan_speed_percent(struct radeon_device *rdev,
1098 u32 speed)
1099 {
1100 u32 tmp;
1101 u32 duty, duty100;
1102 u64 tmp64;
1103 struct ci_power_info *pi = ci_get_pi(rdev);
1104
1105 if (rdev->pm.no_fan)
1106 return -ENOENT;
1107
1108 if (pi->fan_is_controlled_by_smc)
1109 return -EINVAL;
1110
1111 if (speed > 100)
1112 return -EINVAL;
1113
1114 duty100 = (RREG32_SMC(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT;
1115
1116 if (duty100 == 0)
1117 return -EINVAL;
1118
1119 tmp64 = (u64)speed * duty100;
1120 do_div(tmp64, 100);
1121 duty = (u32)tmp64;
1122
1123 tmp = RREG32_SMC(CG_FDO_CTRL0) & ~FDO_STATIC_DUTY_MASK;
1124 tmp |= FDO_STATIC_DUTY(duty);
1125 WREG32_SMC(CG_FDO_CTRL0, tmp);
1126
1127 return 0;
1128 }
1129
1130 void ci_fan_ctrl_set_mode(struct radeon_device *rdev, u32 mode)
1131 {
1132 if (mode) {
1133 /* stop auto-manage */
1134 if (rdev->pm.dpm.fan.ucode_fan_control)
1135 ci_fan_ctrl_stop_smc_fan_control(rdev);
1136 ci_fan_ctrl_set_static_mode(rdev, mode);
1137 } else {
1138 /* restart auto-manage */
1139 if (rdev->pm.dpm.fan.ucode_fan_control)
1140 ci_thermal_start_smc_fan_control(rdev);
1141 else
1142 ci_fan_ctrl_set_default_mode(rdev);
1143 }
1144 }
1145
1146 u32 ci_fan_ctrl_get_mode(struct radeon_device *rdev)
1147 {
1148 struct ci_power_info *pi = ci_get_pi(rdev);
1149 u32 tmp;
1150
1151 if (pi->fan_is_controlled_by_smc)
1152 return 0;
1153
1154 tmp = RREG32_SMC(CG_FDO_CTRL2) & FDO_PWM_MODE_MASK;
1155 return (tmp >> FDO_PWM_MODE_SHIFT);
1156 }
1157
1158 #if 0
1159 static int ci_fan_ctrl_get_fan_speed_rpm(struct radeon_device *rdev,
1160 u32 *speed)
1161 {
1162 u32 tach_period;
1163 u32 xclk = radeon_get_xclk(rdev);
1164
1165 if (rdev->pm.no_fan)
1166 return -ENOENT;
1167
1168 if (rdev->pm.fan_pulses_per_revolution == 0)
1169 return -ENOENT;
1170
1171 tach_period = (RREG32_SMC(CG_TACH_STATUS) & TACH_PERIOD_MASK) >> TACH_PERIOD_SHIFT;
1172 if (tach_period == 0)
1173 return -ENOENT;
1174
1175 *speed = 60 * xclk * 10000 / tach_period;
1176
1177 return 0;
1178 }
1179
1180 static int ci_fan_ctrl_set_fan_speed_rpm(struct radeon_device *rdev,
1181 u32 speed)
1182 {
1183 u32 tach_period, tmp;
1184 u32 xclk = radeon_get_xclk(rdev);
1185
1186 if (rdev->pm.no_fan)
1187 return -ENOENT;
1188
1189 if (rdev->pm.fan_pulses_per_revolution == 0)
1190 return -ENOENT;
1191
1192 if ((speed < rdev->pm.fan_min_rpm) ||
1193 (speed > rdev->pm.fan_max_rpm))
1194 return -EINVAL;
1195
1196 if (rdev->pm.dpm.fan.ucode_fan_control)
1197 ci_fan_ctrl_stop_smc_fan_control(rdev);
1198
1199 tach_period = 60 * xclk * 10000 / (8 * speed);
1200 tmp = RREG32_SMC(CG_TACH_CTRL) & ~TARGET_PERIOD_MASK;
1201 tmp |= TARGET_PERIOD(tach_period);
1202 WREG32_SMC(CG_TACH_CTRL, tmp);
1203
1204 ci_fan_ctrl_set_static_mode(rdev, FDO_PWM_MODE_STATIC_RPM);
1205
1206 return 0;
1207 }
1208 #endif
1209
1210 static void ci_fan_ctrl_set_default_mode(struct radeon_device *rdev)
1211 {
1212 struct ci_power_info *pi = ci_get_pi(rdev);
1213 u32 tmp;
1214
1215 if (!pi->fan_ctrl_is_in_default_mode) {
1216 tmp = RREG32_SMC(CG_FDO_CTRL2) & ~FDO_PWM_MODE_MASK;
1217 tmp |= FDO_PWM_MODE(pi->fan_ctrl_default_mode);
1218 WREG32_SMC(CG_FDO_CTRL2, tmp);
1219
1220 tmp = RREG32_SMC(CG_FDO_CTRL2) & ~TMIN_MASK;
1221 tmp |= TMIN(pi->t_min);
1222 WREG32_SMC(CG_FDO_CTRL2, tmp);
1223 pi->fan_ctrl_is_in_default_mode = true;
1224 }
1225 }
1226
1227 static void ci_thermal_start_smc_fan_control(struct radeon_device *rdev)
1228 {
1229 if (rdev->pm.dpm.fan.ucode_fan_control) {
1230 ci_fan_ctrl_start_smc_fan_control(rdev);
1231 ci_fan_ctrl_set_static_mode(rdev, FDO_PWM_MODE_STATIC);
1232 }
1233 }
1234
1235 static void ci_thermal_initialize(struct radeon_device *rdev)
1236 {
1237 u32 tmp;
1238
1239 if (rdev->pm.fan_pulses_per_revolution) {
1240 tmp = RREG32_SMC(CG_TACH_CTRL) & ~EDGE_PER_REV_MASK;
1241 tmp |= EDGE_PER_REV(rdev->pm.fan_pulses_per_revolution -1);
1242 WREG32_SMC(CG_TACH_CTRL, tmp);
1243 }
1244
1245 tmp = RREG32_SMC(CG_FDO_CTRL2) & ~TACH_PWM_RESP_RATE_MASK;
1246 tmp |= TACH_PWM_RESP_RATE(0x28);
1247 WREG32_SMC(CG_FDO_CTRL2, tmp);
1248 }
1249
1250 static int ci_thermal_start_thermal_controller(struct radeon_device *rdev)
1251 {
1252 int ret;
1253
1254 ci_thermal_initialize(rdev);
1255 ret = ci_thermal_set_temperature_range(rdev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX);
1256 if (ret)
1257 return ret;
1258 ret = ci_thermal_enable_alert(rdev, true);
1259 if (ret)
1260 return ret;
1261 if (rdev->pm.dpm.fan.ucode_fan_control) {
1262 ret = ci_thermal_setup_fan_table(rdev);
1263 if (ret)
1264 return ret;
1265 ci_thermal_start_smc_fan_control(rdev);
1266 }
1267
1268 return 0;
1269 }
1270
1271 static void ci_thermal_stop_thermal_controller(struct radeon_device *rdev)
1272 {
1273 if (!rdev->pm.no_fan)
1274 ci_fan_ctrl_set_default_mode(rdev);
1275 }
1276
1277 #if 0
1278 static int ci_read_smc_soft_register(struct radeon_device *rdev,
1279 u16 reg_offset, u32 *value)
1280 {
1281 struct ci_power_info *pi = ci_get_pi(rdev);
1282
1283 return ci_read_smc_sram_dword(rdev,
1284 pi->soft_regs_start + reg_offset,
1285 value, pi->sram_end);
1286 }
1287 #endif
1288
1289 static int ci_write_smc_soft_register(struct radeon_device *rdev,
1290 u16 reg_offset, u32 value)
1291 {
1292 struct ci_power_info *pi = ci_get_pi(rdev);
1293
1294 return ci_write_smc_sram_dword(rdev,
1295 pi->soft_regs_start + reg_offset,
1296 value, pi->sram_end);
1297 }
1298
1299 static void ci_init_fps_limits(struct radeon_device *rdev)
1300 {
1301 struct ci_power_info *pi = ci_get_pi(rdev);
1302 SMU7_Discrete_DpmTable *table = &pi->smc_state_table;
1303
1304 if (pi->caps_fps) {
1305 u16 tmp;
1306
1307 tmp = 45;
1308 table->FpsHighT = cpu_to_be16(tmp);
1309
1310 tmp = 30;
1311 table->FpsLowT = cpu_to_be16(tmp);
1312 }
1313 }
1314
1315 static int ci_update_sclk_t(struct radeon_device *rdev)
1316 {
1317 struct ci_power_info *pi = ci_get_pi(rdev);
1318 int ret = 0;
1319 u32 low_sclk_interrupt_t = 0;
1320
1321 if (pi->caps_sclk_throttle_low_notification) {
1322 low_sclk_interrupt_t = cpu_to_be32(pi->low_sclk_interrupt_t);
1323
1324 ret = ci_copy_bytes_to_smc(rdev,
1325 pi->dpm_table_start +
1326 offsetof(SMU7_Discrete_DpmTable, LowSclkInterruptT),
1327 (u8 *)&low_sclk_interrupt_t,
1328 sizeof(u32), pi->sram_end);
1329
1330 }
1331
1332 return ret;
1333 }
1334
1335 static void ci_get_leakage_voltages(struct radeon_device *rdev)
1336 {
1337 struct ci_power_info *pi = ci_get_pi(rdev);
1338 u16 leakage_id, virtual_voltage_id;
1339 u16 vddc, vddci;
1340 int i;
1341
1342 pi->vddc_leakage.count = 0;
1343 pi->vddci_leakage.count = 0;
1344
1345 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_EVV) {
1346 for (i = 0; i < CISLANDS_MAX_LEAKAGE_COUNT; i++) {
1347 virtual_voltage_id = ATOM_VIRTUAL_VOLTAGE_ID0 + i;
1348 if (radeon_atom_get_voltage_evv(rdev, virtual_voltage_id, &vddc) != 0)
1349 continue;
1350 if (vddc != 0 && vddc != virtual_voltage_id) {
1351 pi->vddc_leakage.actual_voltage[pi->vddc_leakage.count] = vddc;
1352 pi->vddc_leakage.leakage_id[pi->vddc_leakage.count] = virtual_voltage_id;
1353 pi->vddc_leakage.count++;
1354 }
1355 }
1356 } else if (radeon_atom_get_leakage_id_from_vbios(rdev, &leakage_id) == 0) {
1357 for (i = 0; i < CISLANDS_MAX_LEAKAGE_COUNT; i++) {
1358 virtual_voltage_id = ATOM_VIRTUAL_VOLTAGE_ID0 + i;
1359 if (radeon_atom_get_leakage_vddc_based_on_leakage_params(rdev, &vddc, &vddci,
1360 virtual_voltage_id,
1361 leakage_id) == 0) {
1362 if (vddc != 0 && vddc != virtual_voltage_id) {
1363 pi->vddc_leakage.actual_voltage[pi->vddc_leakage.count] = vddc;
1364 pi->vddc_leakage.leakage_id[pi->vddc_leakage.count] = virtual_voltage_id;
1365 pi->vddc_leakage.count++;
1366 }
1367 if (vddci != 0 && vddci != virtual_voltage_id) {
1368 pi->vddci_leakage.actual_voltage[pi->vddci_leakage.count] = vddci;
1369 pi->vddci_leakage.leakage_id[pi->vddci_leakage.count] = virtual_voltage_id;
1370 pi->vddci_leakage.count++;
1371 }
1372 }
1373 }
1374 }
1375 }
1376
1377 static void ci_set_dpm_event_sources(struct radeon_device *rdev, u32 sources)
1378 {
1379 struct ci_power_info *pi = ci_get_pi(rdev);
1380 bool want_thermal_protection;
1381 enum radeon_dpm_event_src dpm_event_src;
1382 u32 tmp;
1383
1384 switch (sources) {
1385 case 0:
1386 default:
1387 want_thermal_protection = false;
1388 break;
1389 case (1 << RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL):
1390 want_thermal_protection = true;
1391 dpm_event_src = RADEON_DPM_EVENT_SRC_DIGITAL;
1392 break;
1393 case (1 << RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL):
1394 want_thermal_protection = true;
1395 dpm_event_src = RADEON_DPM_EVENT_SRC_EXTERNAL;
1396 break;
1397 case ((1 << RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL) |
1398 (1 << RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL)):
1399 want_thermal_protection = true;
1400 dpm_event_src = RADEON_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL;
1401 break;
1402 }
1403
1404 if (want_thermal_protection) {
1405 #if 0
1406 /* XXX: need to figure out how to handle this properly */
1407 tmp = RREG32_SMC(CG_THERMAL_CTRL);
1408 tmp &= DPM_EVENT_SRC_MASK;
1409 tmp |= DPM_EVENT_SRC(dpm_event_src);
1410 WREG32_SMC(CG_THERMAL_CTRL, tmp);
1411 #endif
1412
1413 tmp = RREG32_SMC(GENERAL_PWRMGT);
1414 if (pi->thermal_protection)
1415 tmp &= ~THERMAL_PROTECTION_DIS;
1416 else
1417 tmp |= THERMAL_PROTECTION_DIS;
1418 WREG32_SMC(GENERAL_PWRMGT, tmp);
1419 } else {
1420 tmp = RREG32_SMC(GENERAL_PWRMGT);
1421 tmp |= THERMAL_PROTECTION_DIS;
1422 WREG32_SMC(GENERAL_PWRMGT, tmp);
1423 }
1424 }
1425
1426 static void ci_enable_auto_throttle_source(struct radeon_device *rdev,
1427 enum radeon_dpm_auto_throttle_src source,
1428 bool enable)
1429 {
1430 struct ci_power_info *pi = ci_get_pi(rdev);
1431
1432 if (enable) {
1433 if (!(pi->active_auto_throttle_sources & (1 << source))) {
1434 pi->active_auto_throttle_sources |= 1 << source;
1435 ci_set_dpm_event_sources(rdev, pi->active_auto_throttle_sources);
1436 }
1437 } else {
1438 if (pi->active_auto_throttle_sources & (1 << source)) {
1439 pi->active_auto_throttle_sources &= ~(1 << source);
1440 ci_set_dpm_event_sources(rdev, pi->active_auto_throttle_sources);
1441 }
1442 }
1443 }
1444
1445 static void ci_enable_vr_hot_gpio_interrupt(struct radeon_device *rdev)
1446 {
1447 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REGULATOR_HOT)
1448 ci_send_msg_to_smc(rdev, PPSMC_MSG_EnableVRHotGPIOInterrupt);
1449 }
1450
1451 static int ci_unfreeze_sclk_mclk_dpm(struct radeon_device *rdev)
1452 {
1453 struct ci_power_info *pi = ci_get_pi(rdev);
1454 PPSMC_Result smc_result;
1455
1456 if (!pi->need_update_smu7_dpm_table)
1457 return 0;
1458
1459 if ((!pi->sclk_dpm_key_disabled) &&
1460 (pi->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_UPDATE_SCLK))) {
1461 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_SCLKDPM_UnfreezeLevel);
1462 if (smc_result != PPSMC_Result_OK)
1463 return -EINVAL;
1464 }
1465
1466 if ((!pi->mclk_dpm_key_disabled) &&
1467 (pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)) {
1468 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_MCLKDPM_UnfreezeLevel);
1469 if (smc_result != PPSMC_Result_OK)
1470 return -EINVAL;
1471 }
1472
1473 pi->need_update_smu7_dpm_table = 0;
1474 return 0;
1475 }
1476
1477 static int ci_enable_sclk_mclk_dpm(struct radeon_device *rdev, bool enable)
1478 {
1479 struct ci_power_info *pi = ci_get_pi(rdev);
1480 PPSMC_Result smc_result;
1481
1482 if (enable) {
1483 if (!pi->sclk_dpm_key_disabled) {
1484 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_DPM_Enable);
1485 if (smc_result != PPSMC_Result_OK)
1486 return -EINVAL;
1487 }
1488
1489 if (!pi->mclk_dpm_key_disabled) {
1490 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_MCLKDPM_Enable);
1491 if (smc_result != PPSMC_Result_OK)
1492 return -EINVAL;
1493
1494 WREG32_P(MC_SEQ_CNTL_3, CAC_EN, ~CAC_EN);
1495
1496 WREG32_SMC(LCAC_MC0_CNTL, 0x05);
1497 WREG32_SMC(LCAC_MC1_CNTL, 0x05);
1498 WREG32_SMC(LCAC_CPL_CNTL, 0x100005);
1499
1500 udelay(10);
1501
1502 WREG32_SMC(LCAC_MC0_CNTL, 0x400005);
1503 WREG32_SMC(LCAC_MC1_CNTL, 0x400005);
1504 WREG32_SMC(LCAC_CPL_CNTL, 0x500005);
1505 }
1506 } else {
1507 if (!pi->sclk_dpm_key_disabled) {
1508 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_DPM_Disable);
1509 if (smc_result != PPSMC_Result_OK)
1510 return -EINVAL;
1511 }
1512
1513 if (!pi->mclk_dpm_key_disabled) {
1514 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_MCLKDPM_Disable);
1515 if (smc_result != PPSMC_Result_OK)
1516 return -EINVAL;
1517 }
1518 }
1519
1520 return 0;
1521 }
1522
1523 static int ci_start_dpm(struct radeon_device *rdev)
1524 {
1525 struct ci_power_info *pi = ci_get_pi(rdev);
1526 PPSMC_Result smc_result;
1527 int ret;
1528 u32 tmp;
1529
1530 tmp = RREG32_SMC(GENERAL_PWRMGT);
1531 tmp |= GLOBAL_PWRMGT_EN;
1532 WREG32_SMC(GENERAL_PWRMGT, tmp);
1533
1534 tmp = RREG32_SMC(SCLK_PWRMGT_CNTL);
1535 tmp |= DYNAMIC_PM_EN;
1536 WREG32_SMC(SCLK_PWRMGT_CNTL, tmp);
1537
1538 ci_write_smc_soft_register(rdev, offsetof(SMU7_SoftRegisters, VoltageChangeTimeout), 0x1000);
1539
1540 WREG32_P(BIF_LNCNT_RESET, 0, ~RESET_LNCNT_EN);
1541
1542 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_Voltage_Cntl_Enable);
1543 if (smc_result != PPSMC_Result_OK)
1544 return -EINVAL;
1545
1546 ret = ci_enable_sclk_mclk_dpm(rdev, true);
1547 if (ret)
1548 return ret;
1549
1550 if (!pi->pcie_dpm_key_disabled) {
1551 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_PCIeDPM_Enable);
1552 if (smc_result != PPSMC_Result_OK)
1553 return -EINVAL;
1554 }
1555
1556 return 0;
1557 }
1558
1559 static int ci_freeze_sclk_mclk_dpm(struct radeon_device *rdev)
1560 {
1561 struct ci_power_info *pi = ci_get_pi(rdev);
1562 PPSMC_Result smc_result;
1563
1564 if (!pi->need_update_smu7_dpm_table)
1565 return 0;
1566
1567 if ((!pi->sclk_dpm_key_disabled) &&
1568 (pi->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_UPDATE_SCLK))) {
1569 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_SCLKDPM_FreezeLevel);
1570 if (smc_result != PPSMC_Result_OK)
1571 return -EINVAL;
1572 }
1573
1574 if ((!pi->mclk_dpm_key_disabled) &&
1575 (pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)) {
1576 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_MCLKDPM_FreezeLevel);
1577 if (smc_result != PPSMC_Result_OK)
1578 return -EINVAL;
1579 }
1580
1581 return 0;
1582 }
1583
1584 static int ci_stop_dpm(struct radeon_device *rdev)
1585 {
1586 struct ci_power_info *pi = ci_get_pi(rdev);
1587 PPSMC_Result smc_result;
1588 int ret;
1589 u32 tmp;
1590
1591 tmp = RREG32_SMC(GENERAL_PWRMGT);
1592 tmp &= ~GLOBAL_PWRMGT_EN;
1593 WREG32_SMC(GENERAL_PWRMGT, tmp);
1594
1595 tmp = RREG32_SMC(SCLK_PWRMGT_CNTL);
1596 tmp &= ~DYNAMIC_PM_EN;
1597 WREG32_SMC(SCLK_PWRMGT_CNTL, tmp);
1598
1599 if (!pi->pcie_dpm_key_disabled) {
1600 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_PCIeDPM_Disable);
1601 if (smc_result != PPSMC_Result_OK)
1602 return -EINVAL;
1603 }
1604
1605 ret = ci_enable_sclk_mclk_dpm(rdev, false);
1606 if (ret)
1607 return ret;
1608
1609 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_Voltage_Cntl_Disable);
1610 if (smc_result != PPSMC_Result_OK)
1611 return -EINVAL;
1612
1613 return 0;
1614 }
1615
1616 static void ci_enable_sclk_control(struct radeon_device *rdev, bool enable)
1617 {
1618 u32 tmp = RREG32_SMC(SCLK_PWRMGT_CNTL);
1619
1620 if (enable)
1621 tmp &= ~SCLK_PWRMGT_OFF;
1622 else
1623 tmp |= SCLK_PWRMGT_OFF;
1624 WREG32_SMC(SCLK_PWRMGT_CNTL, tmp);
1625 }
1626
1627 #if 0
1628 static int ci_notify_hw_of_power_source(struct radeon_device *rdev,
1629 bool ac_power)
1630 {
1631 struct ci_power_info *pi = ci_get_pi(rdev);
1632 struct radeon_cac_tdp_table *cac_tdp_table =
1633 rdev->pm.dpm.dyn_state.cac_tdp_table;
1634 u32 power_limit;
1635
1636 if (ac_power)
1637 power_limit = (u32)(cac_tdp_table->maximum_power_delivery_limit * 256);
1638 else
1639 power_limit = (u32)(cac_tdp_table->battery_power_limit * 256);
1640
1641 ci_set_power_limit(rdev, power_limit);
1642
1643 if (pi->caps_automatic_dc_transition) {
1644 if (ac_power)
1645 ci_send_msg_to_smc(rdev, PPSMC_MSG_RunningOnAC);
1646 else
1647 ci_send_msg_to_smc(rdev, PPSMC_MSG_Remove_DC_Clamp);
1648 }
1649
1650 return 0;
1651 }
1652 #endif
1653
1654 static PPSMC_Result ci_send_msg_to_smc_with_parameter(struct radeon_device *rdev,
1655 PPSMC_Msg msg, u32 parameter)
1656 {
1657 WREG32(SMC_MSG_ARG_0, parameter);
1658 return ci_send_msg_to_smc(rdev, msg);
1659 }
1660
1661 static PPSMC_Result ci_send_msg_to_smc_return_parameter(struct radeon_device *rdev,
1662 PPSMC_Msg msg, u32 *parameter)
1663 {
1664 PPSMC_Result smc_result;
1665
1666 smc_result = ci_send_msg_to_smc(rdev, msg);
1667
1668 if ((smc_result == PPSMC_Result_OK) && parameter)
1669 *parameter = RREG32(SMC_MSG_ARG_0);
1670
1671 return smc_result;
1672 }
1673
1674 static int ci_dpm_force_state_sclk(struct radeon_device *rdev, u32 n)
1675 {
1676 struct ci_power_info *pi = ci_get_pi(rdev);
1677
1678 if (!pi->sclk_dpm_key_disabled) {
1679 PPSMC_Result smc_result =
1680 ci_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SCLKDPM_SetEnabledMask, 1 << n);
1681 if (smc_result != PPSMC_Result_OK)
1682 return -EINVAL;
1683 }
1684
1685 return 0;
1686 }
1687
1688 static int ci_dpm_force_state_mclk(struct radeon_device *rdev, u32 n)
1689 {
1690 struct ci_power_info *pi = ci_get_pi(rdev);
1691
1692 if (!pi->mclk_dpm_key_disabled) {
1693 PPSMC_Result smc_result =
1694 ci_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_MCLKDPM_SetEnabledMask, 1 << n);
1695 if (smc_result != PPSMC_Result_OK)
1696 return -EINVAL;
1697 }
1698
1699 return 0;
1700 }
1701
1702 static int ci_dpm_force_state_pcie(struct radeon_device *rdev, u32 n)
1703 {
1704 struct ci_power_info *pi = ci_get_pi(rdev);
1705
1706 if (!pi->pcie_dpm_key_disabled) {
1707 PPSMC_Result smc_result =
1708 ci_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_PCIeDPM_ForceLevel, n);
1709 if (smc_result != PPSMC_Result_OK)
1710 return -EINVAL;
1711 }
1712
1713 return 0;
1714 }
1715
1716 static int ci_set_power_limit(struct radeon_device *rdev, u32 n)
1717 {
1718 struct ci_power_info *pi = ci_get_pi(rdev);
1719
1720 if (pi->power_containment_features & POWERCONTAINMENT_FEATURE_PkgPwrLimit) {
1721 PPSMC_Result smc_result =
1722 ci_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_PkgPwrSetLimit, n);
1723 if (smc_result != PPSMC_Result_OK)
1724 return -EINVAL;
1725 }
1726
1727 return 0;
1728 }
1729
1730 static int ci_set_overdrive_target_tdp(struct radeon_device *rdev,
1731 u32 target_tdp)
1732 {
1733 PPSMC_Result smc_result =
1734 ci_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_OverDriveSetTargetTdp, target_tdp);
1735 if (smc_result != PPSMC_Result_OK)
1736 return -EINVAL;
1737 return 0;
1738 }
1739
1740 #if 0
1741 static int ci_set_boot_state(struct radeon_device *rdev)
1742 {
1743 return ci_enable_sclk_mclk_dpm(rdev, false);
1744 }
1745 #endif
1746
1747 static u32 ci_get_average_sclk_freq(struct radeon_device *rdev)
1748 {
1749 u32 sclk_freq;
1750 PPSMC_Result smc_result =
1751 ci_send_msg_to_smc_return_parameter(rdev,
1752 PPSMC_MSG_API_GetSclkFrequency,
1753 &sclk_freq);
1754 if (smc_result != PPSMC_Result_OK)
1755 sclk_freq = 0;
1756
1757 return sclk_freq;
1758 }
1759
1760 static u32 ci_get_average_mclk_freq(struct radeon_device *rdev)
1761 {
1762 u32 mclk_freq;
1763 PPSMC_Result smc_result =
1764 ci_send_msg_to_smc_return_parameter(rdev,
1765 PPSMC_MSG_API_GetMclkFrequency,
1766 &mclk_freq);
1767 if (smc_result != PPSMC_Result_OK)
1768 mclk_freq = 0;
1769
1770 return mclk_freq;
1771 }
1772
1773 static void ci_dpm_start_smc(struct radeon_device *rdev)
1774 {
1775 int i;
1776
1777 ci_program_jump_on_start(rdev);
1778 ci_start_smc_clock(rdev);
1779 ci_start_smc(rdev);
1780 for (i = 0; i < rdev->usec_timeout; i++) {
1781 if (RREG32_SMC(FIRMWARE_FLAGS) & INTERRUPTS_ENABLED)
1782 break;
1783 }
1784 }
1785
1786 static void ci_dpm_stop_smc(struct radeon_device *rdev)
1787 {
1788 ci_reset_smc(rdev);
1789 ci_stop_smc_clock(rdev);
1790 }
1791
1792 static int ci_process_firmware_header(struct radeon_device *rdev)
1793 {
1794 struct ci_power_info *pi = ci_get_pi(rdev);
1795 u32 tmp;
1796 int ret;
1797
1798 ret = ci_read_smc_sram_dword(rdev,
1799 SMU7_FIRMWARE_HEADER_LOCATION +
1800 offsetof(SMU7_Firmware_Header, DpmTable),
1801 &tmp, pi->sram_end);
1802 if (ret)
1803 return ret;
1804
1805 pi->dpm_table_start = tmp;
1806
1807 ret = ci_read_smc_sram_dword(rdev,
1808 SMU7_FIRMWARE_HEADER_LOCATION +
1809 offsetof(SMU7_Firmware_Header, SoftRegisters),
1810 &tmp, pi->sram_end);
1811 if (ret)
1812 return ret;
1813
1814 pi->soft_regs_start = tmp;
1815
1816 ret = ci_read_smc_sram_dword(rdev,
1817 SMU7_FIRMWARE_HEADER_LOCATION +
1818 offsetof(SMU7_Firmware_Header, mcRegisterTable),
1819 &tmp, pi->sram_end);
1820 if (ret)
1821 return ret;
1822
1823 pi->mc_reg_table_start = tmp;
1824
1825 ret = ci_read_smc_sram_dword(rdev,
1826 SMU7_FIRMWARE_HEADER_LOCATION +
1827 offsetof(SMU7_Firmware_Header, FanTable),
1828 &tmp, pi->sram_end);
1829 if (ret)
1830 return ret;
1831
1832 pi->fan_table_start = tmp;
1833
1834 ret = ci_read_smc_sram_dword(rdev,
1835 SMU7_FIRMWARE_HEADER_LOCATION +
1836 offsetof(SMU7_Firmware_Header, mcArbDramTimingTable),
1837 &tmp, pi->sram_end);
1838 if (ret)
1839 return ret;
1840
1841 pi->arb_table_start = tmp;
1842
1843 return 0;
1844 }
1845
1846 static void ci_read_clock_registers(struct radeon_device *rdev)
1847 {
1848 struct ci_power_info *pi = ci_get_pi(rdev);
1849
1850 pi->clock_registers.cg_spll_func_cntl =
1851 RREG32_SMC(CG_SPLL_FUNC_CNTL);
1852 pi->clock_registers.cg_spll_func_cntl_2 =
1853 RREG32_SMC(CG_SPLL_FUNC_CNTL_2);
1854 pi->clock_registers.cg_spll_func_cntl_3 =
1855 RREG32_SMC(CG_SPLL_FUNC_CNTL_3);
1856 pi->clock_registers.cg_spll_func_cntl_4 =
1857 RREG32_SMC(CG_SPLL_FUNC_CNTL_4);
1858 pi->clock_registers.cg_spll_spread_spectrum =
1859 RREG32_SMC(CG_SPLL_SPREAD_SPECTRUM);
1860 pi->clock_registers.cg_spll_spread_spectrum_2 =
1861 RREG32_SMC(CG_SPLL_SPREAD_SPECTRUM_2);
1862 pi->clock_registers.dll_cntl = RREG32(DLL_CNTL);
1863 pi->clock_registers.mclk_pwrmgt_cntl = RREG32(MCLK_PWRMGT_CNTL);
1864 pi->clock_registers.mpll_ad_func_cntl = RREG32(MPLL_AD_FUNC_CNTL);
1865 pi->clock_registers.mpll_dq_func_cntl = RREG32(MPLL_DQ_FUNC_CNTL);
1866 pi->clock_registers.mpll_func_cntl = RREG32(MPLL_FUNC_CNTL);
1867 pi->clock_registers.mpll_func_cntl_1 = RREG32(MPLL_FUNC_CNTL_1);
1868 pi->clock_registers.mpll_func_cntl_2 = RREG32(MPLL_FUNC_CNTL_2);
1869 pi->clock_registers.mpll_ss1 = RREG32(MPLL_SS1);
1870 pi->clock_registers.mpll_ss2 = RREG32(MPLL_SS2);
1871 }
1872
1873 static void ci_init_sclk_t(struct radeon_device *rdev)
1874 {
1875 struct ci_power_info *pi = ci_get_pi(rdev);
1876
1877 pi->low_sclk_interrupt_t = 0;
1878 }
1879
1880 static void ci_enable_thermal_protection(struct radeon_device *rdev,
1881 bool enable)
1882 {
1883 u32 tmp = RREG32_SMC(GENERAL_PWRMGT);
1884
1885 if (enable)
1886 tmp &= ~THERMAL_PROTECTION_DIS;
1887 else
1888 tmp |= THERMAL_PROTECTION_DIS;
1889 WREG32_SMC(GENERAL_PWRMGT, tmp);
1890 }
1891
1892 static void ci_enable_acpi_power_management(struct radeon_device *rdev)
1893 {
1894 u32 tmp = RREG32_SMC(GENERAL_PWRMGT);
1895
1896 tmp |= STATIC_PM_EN;
1897
1898 WREG32_SMC(GENERAL_PWRMGT, tmp);
1899 }
1900
1901 #if 0
1902 static int ci_enter_ulp_state(struct radeon_device *rdev)
1903 {
1904
1905 WREG32(SMC_MESSAGE_0, PPSMC_MSG_SwitchToMinimumPower);
1906
1907 udelay(25000);
1908
1909 return 0;
1910 }
1911
1912 static int ci_exit_ulp_state(struct radeon_device *rdev)
1913 {
1914 int i;
1915
1916 WREG32(SMC_MESSAGE_0, PPSMC_MSG_ResumeFromMinimumPower);
1917
1918 udelay(7000);
1919
1920 for (i = 0; i < rdev->usec_timeout; i++) {
1921 if (RREG32(SMC_RESP_0) == 1)
1922 break;
1923 udelay(1000);
1924 }
1925
1926 return 0;
1927 }
1928 #endif
1929
1930 static int ci_notify_smc_display_change(struct radeon_device *rdev,
1931 bool has_display)
1932 {
1933 PPSMC_Msg msg = has_display ? PPSMC_MSG_HasDisplay : PPSMC_MSG_NoDisplay;
1934
1935 return (ci_send_msg_to_smc(rdev, msg) == PPSMC_Result_OK) ? 0 : -EINVAL;
1936 }
1937
1938 static int ci_enable_ds_master_switch(struct radeon_device *rdev,
1939 bool enable)
1940 {
1941 struct ci_power_info *pi = ci_get_pi(rdev);
1942
1943 if (enable) {
1944 if (pi->caps_sclk_ds) {
1945 if (ci_send_msg_to_smc(rdev, PPSMC_MSG_MASTER_DeepSleep_ON) != PPSMC_Result_OK)
1946 return -EINVAL;
1947 } else {
1948 if (ci_send_msg_to_smc(rdev, PPSMC_MSG_MASTER_DeepSleep_OFF) != PPSMC_Result_OK)
1949 return -EINVAL;
1950 }
1951 } else {
1952 if (pi->caps_sclk_ds) {
1953 if (ci_send_msg_to_smc(rdev, PPSMC_MSG_MASTER_DeepSleep_OFF) != PPSMC_Result_OK)
1954 return -EINVAL;
1955 }
1956 }
1957
1958 return 0;
1959 }
1960
1961 static void ci_program_display_gap(struct radeon_device *rdev)
1962 {
1963 u32 tmp = RREG32_SMC(CG_DISPLAY_GAP_CNTL);
1964 u32 pre_vbi_time_in_us;
1965 u32 frame_time_in_us;
1966 u32 ref_clock = rdev->clock.spll.reference_freq;
1967 u32 refresh_rate = r600_dpm_get_vrefresh(rdev);
1968 u32 vblank_time = r600_dpm_get_vblank_time(rdev);
1969
1970 tmp &= ~DISP_GAP_MASK;
1971 if (rdev->pm.dpm.new_active_crtc_count > 0)
1972 tmp |= DISP_GAP(R600_PM_DISPLAY_GAP_VBLANK_OR_WM);
1973 else
1974 tmp |= DISP_GAP(R600_PM_DISPLAY_GAP_IGNORE);
1975 WREG32_SMC(CG_DISPLAY_GAP_CNTL, tmp);
1976
1977 if (refresh_rate == 0)
1978 refresh_rate = 60;
1979 if (vblank_time == 0xffffffff)
1980 vblank_time = 500;
1981 frame_time_in_us = 1000000 / refresh_rate;
1982 pre_vbi_time_in_us =
1983 frame_time_in_us - 200 - vblank_time;
1984 tmp = pre_vbi_time_in_us * (ref_clock / 100);
1985
1986 WREG32_SMC(CG_DISPLAY_GAP_CNTL2, tmp);
1987 ci_write_smc_soft_register(rdev, offsetof(SMU7_SoftRegisters, PreVBlankGap), 0x64);
1988 ci_write_smc_soft_register(rdev, offsetof(SMU7_SoftRegisters, VBlankTimeout), (frame_time_in_us - pre_vbi_time_in_us));
1989
1990
1991 ci_notify_smc_display_change(rdev, (rdev->pm.dpm.new_active_crtc_count == 1));
1992
1993 }
1994
1995 static void ci_enable_spread_spectrum(struct radeon_device *rdev, bool enable)
1996 {
1997 struct ci_power_info *pi = ci_get_pi(rdev);
1998 u32 tmp;
1999
2000 if (enable) {
2001 if (pi->caps_sclk_ss_support) {
2002 tmp = RREG32_SMC(GENERAL_PWRMGT);
2003 tmp |= DYN_SPREAD_SPECTRUM_EN;
2004 WREG32_SMC(GENERAL_PWRMGT, tmp);
2005 }
2006 } else {
2007 tmp = RREG32_SMC(CG_SPLL_SPREAD_SPECTRUM);
2008 tmp &= ~SSEN;
2009 WREG32_SMC(CG_SPLL_SPREAD_SPECTRUM, tmp);
2010
2011 tmp = RREG32_SMC(GENERAL_PWRMGT);
2012 tmp &= ~DYN_SPREAD_SPECTRUM_EN;
2013 WREG32_SMC(GENERAL_PWRMGT, tmp);
2014 }
2015 }
2016
2017 static void ci_program_sstp(struct radeon_device *rdev)
2018 {
2019 WREG32_SMC(CG_SSP, (SSTU(R600_SSTU_DFLT) | SST(R600_SST_DFLT)));
2020 }
2021
2022 static void ci_enable_display_gap(struct radeon_device *rdev)
2023 {
2024 u32 tmp = RREG32_SMC(CG_DISPLAY_GAP_CNTL);
2025
2026 tmp &= ~(DISP_GAP_MASK | DISP_GAP_MCHG_MASK);
2027 tmp |= (DISP_GAP(R600_PM_DISPLAY_GAP_IGNORE) |
2028 DISP_GAP_MCHG(R600_PM_DISPLAY_GAP_VBLANK));
2029
2030 WREG32_SMC(CG_DISPLAY_GAP_CNTL, tmp);
2031 }
2032
2033 static void ci_program_vc(struct radeon_device *rdev)
2034 {
2035 u32 tmp;
2036
2037 tmp = RREG32_SMC(SCLK_PWRMGT_CNTL);
2038 tmp &= ~(RESET_SCLK_CNT | RESET_BUSY_CNT);
2039 WREG32_SMC(SCLK_PWRMGT_CNTL, tmp);
2040
2041 WREG32_SMC(CG_FTV_0, CISLANDS_VRC_DFLT0);
2042 WREG32_SMC(CG_FTV_1, CISLANDS_VRC_DFLT1);
2043 WREG32_SMC(CG_FTV_2, CISLANDS_VRC_DFLT2);
2044 WREG32_SMC(CG_FTV_3, CISLANDS_VRC_DFLT3);
2045 WREG32_SMC(CG_FTV_4, CISLANDS_VRC_DFLT4);
2046 WREG32_SMC(CG_FTV_5, CISLANDS_VRC_DFLT5);
2047 WREG32_SMC(CG_FTV_6, CISLANDS_VRC_DFLT6);
2048 WREG32_SMC(CG_FTV_7, CISLANDS_VRC_DFLT7);
2049 }
2050
2051 static void ci_clear_vc(struct radeon_device *rdev)
2052 {
2053 u32 tmp;
2054
2055 tmp = RREG32_SMC(SCLK_PWRMGT_CNTL);
2056 tmp |= (RESET_SCLK_CNT | RESET_BUSY_CNT);
2057 WREG32_SMC(SCLK_PWRMGT_CNTL, tmp);
2058
2059 WREG32_SMC(CG_FTV_0, 0);
2060 WREG32_SMC(CG_FTV_1, 0);
2061 WREG32_SMC(CG_FTV_2, 0);
2062 WREG32_SMC(CG_FTV_3, 0);
2063 WREG32_SMC(CG_FTV_4, 0);
2064 WREG32_SMC(CG_FTV_5, 0);
2065 WREG32_SMC(CG_FTV_6, 0);
2066 WREG32_SMC(CG_FTV_7, 0);
2067 }
2068
2069 static int ci_upload_firmware(struct radeon_device *rdev)
2070 {
2071 struct ci_power_info *pi = ci_get_pi(rdev);
2072 int i, ret;
2073
2074 for (i = 0; i < rdev->usec_timeout; i++) {
2075 if (RREG32_SMC(RCU_UC_EVENTS) & BOOT_SEQ_DONE)
2076 break;
2077 }
2078 WREG32_SMC(SMC_SYSCON_MISC_CNTL, 1);
2079
2080 ci_stop_smc_clock(rdev);
2081 ci_reset_smc(rdev);
2082
2083 ret = ci_load_smc_ucode(rdev, pi->sram_end);
2084
2085 return ret;
2086
2087 }
2088
2089 static int ci_get_svi2_voltage_table(struct radeon_device *rdev,
2090 struct radeon_clock_voltage_dependency_table *voltage_dependency_table,
2091 struct atom_voltage_table *voltage_table)
2092 {
2093 u32 i;
2094
2095 if (voltage_dependency_table == NULL)
2096 return -EINVAL;
2097
2098 voltage_table->mask_low = 0;
2099 voltage_table->phase_delay = 0;
2100
2101 voltage_table->count = voltage_dependency_table->count;
2102 for (i = 0; i < voltage_table->count; i++) {
2103 voltage_table->entries[i].value = voltage_dependency_table->entries[i].v;
2104 voltage_table->entries[i].smio_low = 0;
2105 }
2106
2107 return 0;
2108 }
2109
2110 static int ci_construct_voltage_tables(struct radeon_device *rdev)
2111 {
2112 struct ci_power_info *pi = ci_get_pi(rdev);
2113 int ret;
2114
2115 if (pi->voltage_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO) {
2116 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDC,
2117 VOLTAGE_OBJ_GPIO_LUT,
2118 &pi->vddc_voltage_table);
2119 if (ret)
2120 return ret;
2121 } else if (pi->voltage_control == CISLANDS_VOLTAGE_CONTROL_BY_SVID2) {
2122 ret = ci_get_svi2_voltage_table(rdev,
2123 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
2124 &pi->vddc_voltage_table);
2125 if (ret)
2126 return ret;
2127 }
2128
2129 if (pi->vddc_voltage_table.count > SMU7_MAX_LEVELS_VDDC)
2130 si_trim_voltage_table_to_fit_state_table(rdev, SMU7_MAX_LEVELS_VDDC,
2131 &pi->vddc_voltage_table);
2132
2133 if (pi->vddci_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO) {
2134 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDCI,
2135 VOLTAGE_OBJ_GPIO_LUT,
2136 &pi->vddci_voltage_table);
2137 if (ret)
2138 return ret;
2139 } else if (pi->vddci_control == CISLANDS_VOLTAGE_CONTROL_BY_SVID2) {
2140 ret = ci_get_svi2_voltage_table(rdev,
2141 &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
2142 &pi->vddci_voltage_table);
2143 if (ret)
2144 return ret;
2145 }
2146
2147 if (pi->vddci_voltage_table.count > SMU7_MAX_LEVELS_VDDCI)
2148 si_trim_voltage_table_to_fit_state_table(rdev, SMU7_MAX_LEVELS_VDDCI,
2149 &pi->vddci_voltage_table);
2150
2151 if (pi->mvdd_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO) {
2152 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_MVDDC,
2153 VOLTAGE_OBJ_GPIO_LUT,
2154 &pi->mvdd_voltage_table);
2155 if (ret)
2156 return ret;
2157 } else if (pi->mvdd_control == CISLANDS_VOLTAGE_CONTROL_BY_SVID2) {
2158 ret = ci_get_svi2_voltage_table(rdev,
2159 &rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk,
2160 &pi->mvdd_voltage_table);
2161 if (ret)
2162 return ret;
2163 }
2164
2165 if (pi->mvdd_voltage_table.count > SMU7_MAX_LEVELS_MVDD)
2166 si_trim_voltage_table_to_fit_state_table(rdev, SMU7_MAX_LEVELS_MVDD,
2167 &pi->mvdd_voltage_table);
2168
2169 return 0;
2170 }
2171
2172 static void ci_populate_smc_voltage_table(struct radeon_device *rdev,
2173 struct atom_voltage_table_entry *voltage_table,
2174 SMU7_Discrete_VoltageLevel *smc_voltage_table)
2175 {
2176 int ret;
2177
2178 ret = ci_get_std_voltage_value_sidd(rdev, voltage_table,
2179 &smc_voltage_table->StdVoltageHiSidd,
2180 &smc_voltage_table->StdVoltageLoSidd);
2181
2182 if (ret) {
2183 smc_voltage_table->StdVoltageHiSidd = voltage_table->value * VOLTAGE_SCALE;
2184 smc_voltage_table->StdVoltageLoSidd = voltage_table->value * VOLTAGE_SCALE;
2185 }
2186
2187 smc_voltage_table->Voltage = cpu_to_be16(voltage_table->value * VOLTAGE_SCALE);
2188 smc_voltage_table->StdVoltageHiSidd =
2189 cpu_to_be16(smc_voltage_table->StdVoltageHiSidd);
2190 smc_voltage_table->StdVoltageLoSidd =
2191 cpu_to_be16(smc_voltage_table->StdVoltageLoSidd);
2192 }
2193
2194 static int ci_populate_smc_vddc_table(struct radeon_device *rdev,
2195 SMU7_Discrete_DpmTable *table)
2196 {
2197 struct ci_power_info *pi = ci_get_pi(rdev);
2198 unsigned int count;
2199
2200 table->VddcLevelCount = pi->vddc_voltage_table.count;
2201 for (count = 0; count < table->VddcLevelCount; count++) {
2202 ci_populate_smc_voltage_table(rdev,
2203 &pi->vddc_voltage_table.entries[count],
2204 &table->VddcLevel[count]);
2205
2206 if (pi->voltage_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO)
2207 table->VddcLevel[count].Smio |=
2208 pi->vddc_voltage_table.entries[count].smio_low;
2209 else
2210 table->VddcLevel[count].Smio = 0;
2211 }
2212 table->VddcLevelCount = cpu_to_be32(table->VddcLevelCount);
2213
2214 return 0;
2215 }
2216
2217 static int ci_populate_smc_vddci_table(struct radeon_device *rdev,
2218 SMU7_Discrete_DpmTable *table)
2219 {
2220 unsigned int count;
2221 struct ci_power_info *pi = ci_get_pi(rdev);
2222
2223 table->VddciLevelCount = pi->vddci_voltage_table.count;
2224 for (count = 0; count < table->VddciLevelCount; count++) {
2225 ci_populate_smc_voltage_table(rdev,
2226 &pi->vddci_voltage_table.entries[count],
2227 &table->VddciLevel[count]);
2228
2229 if (pi->vddci_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO)
2230 table->VddciLevel[count].Smio |=
2231 pi->vddci_voltage_table.entries[count].smio_low;
2232 else
2233 table->VddciLevel[count].Smio = 0;
2234 }
2235 table->VddciLevelCount = cpu_to_be32(table->VddciLevelCount);
2236
2237 return 0;
2238 }
2239
2240 static int ci_populate_smc_mvdd_table(struct radeon_device *rdev,
2241 SMU7_Discrete_DpmTable *table)
2242 {
2243 struct ci_power_info *pi = ci_get_pi(rdev);
2244 unsigned int count;
2245
2246 table->MvddLevelCount = pi->mvdd_voltage_table.count;
2247 for (count = 0; count < table->MvddLevelCount; count++) {
2248 ci_populate_smc_voltage_table(rdev,
2249 &pi->mvdd_voltage_table.entries[count],
2250 &table->MvddLevel[count]);
2251
2252 if (pi->mvdd_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO)
2253 table->MvddLevel[count].Smio |=
2254 pi->mvdd_voltage_table.entries[count].smio_low;
2255 else
2256 table->MvddLevel[count].Smio = 0;
2257 }
2258 table->MvddLevelCount = cpu_to_be32(table->MvddLevelCount);
2259
2260 return 0;
2261 }
2262
2263 static int ci_populate_smc_voltage_tables(struct radeon_device *rdev,
2264 SMU7_Discrete_DpmTable *table)
2265 {
2266 int ret;
2267
2268 ret = ci_populate_smc_vddc_table(rdev, table);
2269 if (ret)
2270 return ret;
2271
2272 ret = ci_populate_smc_vddci_table(rdev, table);
2273 if (ret)
2274 return ret;
2275
2276 ret = ci_populate_smc_mvdd_table(rdev, table);
2277 if (ret)
2278 return ret;
2279
2280 return 0;
2281 }
2282
2283 static int ci_populate_mvdd_value(struct radeon_device *rdev, u32 mclk,
2284 SMU7_Discrete_VoltageLevel *voltage)
2285 {
2286 struct ci_power_info *pi = ci_get_pi(rdev);
2287 u32 i = 0;
2288
2289 if (pi->mvdd_control != CISLANDS_VOLTAGE_CONTROL_NONE) {
2290 for (i = 0; i < rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk.count; i++) {
2291 if (mclk <= rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk.entries[i].clk) {
2292 voltage->Voltage = pi->mvdd_voltage_table.entries[i].value;
2293 break;
2294 }
2295 }
2296
2297 if (i >= rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk.count)
2298 return -EINVAL;
2299 }
2300
2301 return -EINVAL;
2302 }
2303
2304 static int ci_get_std_voltage_value_sidd(struct radeon_device *rdev,
2305 struct atom_voltage_table_entry *voltage_table,
2306 u16 *std_voltage_hi_sidd, u16 *std_voltage_lo_sidd)
2307 {
2308 u16 v_index, idx;
2309 bool voltage_found = false;
2310 *std_voltage_hi_sidd = voltage_table->value * VOLTAGE_SCALE;
2311 *std_voltage_lo_sidd = voltage_table->value * VOLTAGE_SCALE;
2312
2313 if (rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries == NULL)
2314 return -EINVAL;
2315
2316 if (rdev->pm.dpm.dyn_state.cac_leakage_table.entries) {
2317 for (v_index = 0; (u32)v_index < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) {
2318 if (voltage_table->value ==
2319 rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) {
2320 voltage_found = true;
2321 if ((u32)v_index < rdev->pm.dpm.dyn_state.cac_leakage_table.count)
2322 idx = v_index;
2323 else
2324 idx = rdev->pm.dpm.dyn_state.cac_leakage_table.count - 1;
2325 *std_voltage_lo_sidd =
2326 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[idx].vddc * VOLTAGE_SCALE;
2327 *std_voltage_hi_sidd =
2328 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[idx].leakage * VOLTAGE_SCALE;
2329 break;
2330 }
2331 }
2332
2333 if (!voltage_found) {
2334 for (v_index = 0; (u32)v_index < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) {
2335 if (voltage_table->value <=
2336 rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) {
2337 voltage_found = true;
2338 if ((u32)v_index < rdev->pm.dpm.dyn_state.cac_leakage_table.count)
2339 idx = v_index;
2340 else
2341 idx = rdev->pm.dpm.dyn_state.cac_leakage_table.count - 1;
2342 *std_voltage_lo_sidd =
2343 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[idx].vddc * VOLTAGE_SCALE;
2344 *std_voltage_hi_sidd =
2345 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[idx].leakage * VOLTAGE_SCALE;
2346 break;
2347 }
2348 }
2349 }
2350 }
2351
2352 return 0;
2353 }
2354
2355 static void ci_populate_phase_value_based_on_sclk(struct radeon_device *rdev,
2356 const struct radeon_phase_shedding_limits_table *limits,
2357 u32 sclk,
2358 u32 *phase_shedding)
2359 {
2360 unsigned int i;
2361
2362 *phase_shedding = 1;
2363
2364 for (i = 0; i < limits->count; i++) {
2365 if (sclk < limits->entries[i].sclk) {
2366 *phase_shedding = i;
2367 break;
2368 }
2369 }
2370 }
2371
2372 static void ci_populate_phase_value_based_on_mclk(struct radeon_device *rdev,
2373 const struct radeon_phase_shedding_limits_table *limits,
2374 u32 mclk,
2375 u32 *phase_shedding)
2376 {
2377 unsigned int i;
2378
2379 *phase_shedding = 1;
2380
2381 for (i = 0; i < limits->count; i++) {
2382 if (mclk < limits->entries[i].mclk) {
2383 *phase_shedding = i;
2384 break;
2385 }
2386 }
2387 }
2388
2389 static int ci_init_arb_table_index(struct radeon_device *rdev)
2390 {
2391 struct ci_power_info *pi = ci_get_pi(rdev);
2392 u32 tmp;
2393 int ret;
2394
2395 ret = ci_read_smc_sram_dword(rdev, pi->arb_table_start,
2396 &tmp, pi->sram_end);
2397 if (ret)
2398 return ret;
2399
2400 tmp &= 0x00FFFFFF;
2401 tmp |= MC_CG_ARB_FREQ_F1 << 24;
2402
2403 return ci_write_smc_sram_dword(rdev, pi->arb_table_start,
2404 tmp, pi->sram_end);
2405 }
2406
2407 static int ci_get_dependency_volt_by_clk(struct radeon_device *rdev,
2408 struct radeon_clock_voltage_dependency_table *allowed_clock_voltage_table,
2409 u32 clock, u32 *voltage)
2410 {
2411 u32 i = 0;
2412
2413 if (allowed_clock_voltage_table->count == 0)
2414 return -EINVAL;
2415
2416 for (i = 0; i < allowed_clock_voltage_table->count; i++) {
2417 if (allowed_clock_voltage_table->entries[i].clk >= clock) {
2418 *voltage = allowed_clock_voltage_table->entries[i].v;
2419 return 0;
2420 }
2421 }
2422
2423 *voltage = allowed_clock_voltage_table->entries[i-1].v;
2424
2425 return 0;
2426 }
2427
2428 static u8 ci_get_sleep_divider_id_from_clock(struct radeon_device *rdev,
2429 u32 sclk, u32 min_sclk_in_sr)
2430 {
2431 u32 i;
2432 u32 tmp;
2433 u32 min = (min_sclk_in_sr > CISLAND_MINIMUM_ENGINE_CLOCK) ?
2434 min_sclk_in_sr : CISLAND_MINIMUM_ENGINE_CLOCK;
2435
2436 if (sclk < min)
2437 return 0;
2438
2439 for (i = CISLAND_MAX_DEEPSLEEP_DIVIDER_ID; ; i--) {
2440 tmp = sclk / (1 << i);
2441 if (tmp >= min || i == 0)
2442 break;
2443 }
2444
2445 return (u8)i;
2446 }
2447
2448 static int ci_initial_switch_from_arb_f0_to_f1(struct radeon_device *rdev)
2449 {
2450 return ni_copy_and_switch_arb_sets(rdev, MC_CG_ARB_FREQ_F0, MC_CG_ARB_FREQ_F1);
2451 }
2452
2453 static int ci_reset_to_default(struct radeon_device *rdev)
2454 {
2455 return (ci_send_msg_to_smc(rdev, PPSMC_MSG_ResetToDefaults) == PPSMC_Result_OK) ?
2456 0 : -EINVAL;
2457 }
2458
2459 static int ci_force_switch_to_arb_f0(struct radeon_device *rdev)
2460 {
2461 u32 tmp;
2462
2463 tmp = (RREG32_SMC(SMC_SCRATCH9) & 0x0000ff00) >> 8;
2464
2465 if (tmp == MC_CG_ARB_FREQ_F0)
2466 return 0;
2467
2468 return ni_copy_and_switch_arb_sets(rdev, tmp, MC_CG_ARB_FREQ_F0);
2469 }
2470
2471 static void ci_register_patching_mc_arb(struct radeon_device *rdev,
2472 const u32 engine_clock,
2473 const u32 memory_clock,
2474 u32 *dram_timimg2)
2475 {
2476 bool patch;
2477 u32 tmp, tmp2;
2478
2479 tmp = RREG32(MC_SEQ_MISC0);
2480 patch = ((tmp & 0x0000f00) == 0x300) ? true : false;
2481
2482 if (patch &&
2483 ((rdev->pdev->device == 0x67B0) ||
2484 (rdev->pdev->device == 0x67B1))) {
2485 if ((memory_clock > 100000) && (memory_clock <= 125000)) {
2486 tmp2 = (((0x31 * engine_clock) / 125000) - 1) & 0xff;
2487 *dram_timimg2 &= ~0x00ff0000;
2488 *dram_timimg2 |= tmp2 << 16;
2489 } else if ((memory_clock > 125000) && (memory_clock <= 137500)) {
2490 tmp2 = (((0x36 * engine_clock) / 137500) - 1) & 0xff;
2491 *dram_timimg2 &= ~0x00ff0000;
2492 *dram_timimg2 |= tmp2 << 16;
2493 }
2494 }
2495 }
2496
2497
2498 static int ci_populate_memory_timing_parameters(struct radeon_device *rdev,
2499 u32 sclk,
2500 u32 mclk,
2501 SMU7_Discrete_MCArbDramTimingTableEntry *arb_regs)
2502 {
2503 u32 dram_timing;
2504 u32 dram_timing2;
2505 u32 burst_time;
2506
2507 radeon_atom_set_engine_dram_timings(rdev, sclk, mclk);
2508
2509 dram_timing = RREG32(MC_ARB_DRAM_TIMING);
2510 dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2);
2511 burst_time = RREG32(MC_ARB_BURST_TIME) & STATE0_MASK;
2512
2513 ci_register_patching_mc_arb(rdev, sclk, mclk, &dram_timing2);
2514
2515 arb_regs->McArbDramTiming = cpu_to_be32(dram_timing);
2516 arb_regs->McArbDramTiming2 = cpu_to_be32(dram_timing2);
2517 arb_regs->McArbBurstTime = (u8)burst_time;
2518
2519 return 0;
2520 }
2521
2522 static int ci_do_program_memory_timing_parameters(struct radeon_device *rdev)
2523 {
2524 struct ci_power_info *pi = ci_get_pi(rdev);
2525 SMU7_Discrete_MCArbDramTimingTable arb_regs;
2526 u32 i, j;
2527 int ret = 0;
2528
2529 memset(&arb_regs, 0, sizeof(SMU7_Discrete_MCArbDramTimingTable));
2530
2531 for (i = 0; i < pi->dpm_table.sclk_table.count; i++) {
2532 for (j = 0; j < pi->dpm_table.mclk_table.count; j++) {
2533 ret = ci_populate_memory_timing_parameters(rdev,
2534 pi->dpm_table.sclk_table.dpm_levels[i].value,
2535 pi->dpm_table.mclk_table.dpm_levels[j].value,
2536 &arb_regs.entries[i][j]);
2537 if (ret)
2538 break;
2539 }
2540 }
2541
2542 if (ret == 0)
2543 ret = ci_copy_bytes_to_smc(rdev,
2544 pi->arb_table_start,
2545 (u8 *)&arb_regs,
2546 sizeof(SMU7_Discrete_MCArbDramTimingTable),
2547 pi->sram_end);
2548
2549 return ret;
2550 }
2551
2552 static int ci_program_memory_timing_parameters(struct radeon_device *rdev)
2553 {
2554 struct ci_power_info *pi = ci_get_pi(rdev);
2555
2556 if (pi->need_update_smu7_dpm_table == 0)
2557 return 0;
2558
2559 return ci_do_program_memory_timing_parameters(rdev);
2560 }
2561
2562 static void ci_populate_smc_initial_state(struct radeon_device *rdev,
2563 struct radeon_ps *radeon_boot_state)
2564 {
2565 struct ci_ps *boot_state = ci_get_ps(radeon_boot_state);
2566 struct ci_power_info *pi = ci_get_pi(rdev);
2567 u32 level = 0;
2568
2569 for (level = 0; level < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; level++) {
2570 if (rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[level].clk >=
2571 boot_state->performance_levels[0].sclk) {
2572 pi->smc_state_table.GraphicsBootLevel = level;
2573 break;
2574 }
2575 }
2576
2577 for (level = 0; level < rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk.count; level++) {
2578 if (rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk.entries[level].clk >=
2579 boot_state->performance_levels[0].mclk) {
2580 pi->smc_state_table.MemoryBootLevel = level;
2581 break;
2582 }
2583 }
2584 }
2585
2586 static u32 ci_get_dpm_level_enable_mask_value(struct ci_single_dpm_table *dpm_table)
2587 {
2588 u32 i;
2589 u32 mask_value = 0;
2590
2591 for (i = dpm_table->count; i > 0; i--) {
2592 mask_value = mask_value << 1;
2593 if (dpm_table->dpm_levels[i-1].enabled)
2594 mask_value |= 0x1;
2595 else
2596 mask_value &= 0xFFFFFFFE;
2597 }
2598
2599 return mask_value;
2600 }
2601
2602 static void ci_populate_smc_link_level(struct radeon_device *rdev,
2603 SMU7_Discrete_DpmTable *table)
2604 {
2605 struct ci_power_info *pi = ci_get_pi(rdev);
2606 struct ci_dpm_table *dpm_table = &pi->dpm_table;
2607 u32 i;
2608
2609 for (i = 0; i < dpm_table->pcie_speed_table.count; i++) {
2610 table->LinkLevel[i].PcieGenSpeed =
2611 (u8)dpm_table->pcie_speed_table.dpm_levels[i].value;
2612 table->LinkLevel[i].PcieLaneCount =
2613 r600_encode_pci_lane_width(dpm_table->pcie_speed_table.dpm_levels[i].param1);
2614 table->LinkLevel[i].EnabledForActivity = 1;
2615 table->LinkLevel[i].DownT = cpu_to_be32(5);
2616 table->LinkLevel[i].UpT = cpu_to_be32(30);
2617 }
2618
2619 pi->smc_state_table.LinkLevelCount = (u8)dpm_table->pcie_speed_table.count;
2620 pi->dpm_level_enable_mask.pcie_dpm_enable_mask =
2621 ci_get_dpm_level_enable_mask_value(&dpm_table->pcie_speed_table);
2622 }
2623
2624 static int ci_populate_smc_uvd_level(struct radeon_device *rdev,
2625 SMU7_Discrete_DpmTable *table)
2626 {
2627 u32 count;
2628 struct atom_clock_dividers dividers;
2629 int ret = -EINVAL;
2630
2631 table->UvdLevelCount =
2632 rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.count;
2633
2634 for (count = 0; count < table->UvdLevelCount; count++) {
2635 table->UvdLevel[count].VclkFrequency =
2636 rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[count].vclk;
2637 table->UvdLevel[count].DclkFrequency =
2638 rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[count].dclk;
2639 table->UvdLevel[count].MinVddc =
2640 rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[count].v * VOLTAGE_SCALE;
2641 table->UvdLevel[count].MinVddcPhases = 1;
2642
2643 ret = radeon_atom_get_clock_dividers(rdev,
2644 COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
2645 table->UvdLevel[count].VclkFrequency, false, &dividers);
2646 if (ret)
2647 return ret;
2648
2649 table->UvdLevel[count].VclkDivider = (u8)dividers.post_divider;
2650
2651 ret = radeon_atom_get_clock_dividers(rdev,
2652 COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
2653 table->UvdLevel[count].DclkFrequency, false, &dividers);
2654 if (ret)
2655 return ret;
2656
2657 table->UvdLevel[count].DclkDivider = (u8)dividers.post_divider;
2658
2659 table->UvdLevel[count].VclkFrequency = cpu_to_be32(table->UvdLevel[count].VclkFrequency);
2660 table->UvdLevel[count].DclkFrequency = cpu_to_be32(table->UvdLevel[count].DclkFrequency);
2661 table->UvdLevel[count].MinVddc = cpu_to_be16(table->UvdLevel[count].MinVddc);
2662 }
2663
2664 return ret;
2665 }
2666
2667 static int ci_populate_smc_vce_level(struct radeon_device *rdev,
2668 SMU7_Discrete_DpmTable *table)
2669 {
2670 u32 count;
2671 struct atom_clock_dividers dividers;
2672 int ret = -EINVAL;
2673
2674 table->VceLevelCount =
2675 rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.count;
2676
2677 for (count = 0; count < table->VceLevelCount; count++) {
2678 table->VceLevel[count].Frequency =
2679 rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries[count].evclk;
2680 table->VceLevel[count].MinVoltage =
2681 (u16)rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries[count].v * VOLTAGE_SCALE;
2682 table->VceLevel[count].MinPhases = 1;
2683
2684 ret = radeon_atom_get_clock_dividers(rdev,
2685 COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
2686 table->VceLevel[count].Frequency, false, &dividers);
2687 if (ret)
2688 return ret;
2689
2690 table->VceLevel[count].Divider = (u8)dividers.post_divider;
2691
2692 table->VceLevel[count].Frequency = cpu_to_be32(table->VceLevel[count].Frequency);
2693 table->VceLevel[count].MinVoltage = cpu_to_be16(table->VceLevel[count].MinVoltage);
2694 }
2695
2696 return ret;
2697
2698 }
2699
2700 static int ci_populate_smc_acp_level(struct radeon_device *rdev,
2701 SMU7_Discrete_DpmTable *table)
2702 {
2703 u32 count;
2704 struct atom_clock_dividers dividers;
2705 int ret = -EINVAL;
2706
2707 table->AcpLevelCount = (u8)
2708 (rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.count);
2709
2710 for (count = 0; count < table->AcpLevelCount; count++) {
2711 table->AcpLevel[count].Frequency =
2712 rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.entries[count].clk;
2713 table->AcpLevel[count].MinVoltage =
2714 rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.entries[count].v;
2715 table->AcpLevel[count].MinPhases = 1;
2716
2717 ret = radeon_atom_get_clock_dividers(rdev,
2718 COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
2719 table->AcpLevel[count].Frequency, false, &dividers);
2720 if (ret)
2721 return ret;
2722
2723 table->AcpLevel[count].Divider = (u8)dividers.post_divider;
2724
2725 table->AcpLevel[count].Frequency = cpu_to_be32(table->AcpLevel[count].Frequency);
2726 table->AcpLevel[count].MinVoltage = cpu_to_be16(table->AcpLevel[count].MinVoltage);
2727 }
2728
2729 return ret;
2730 }
2731
2732 static int ci_populate_smc_samu_level(struct radeon_device *rdev,
2733 SMU7_Discrete_DpmTable *table)
2734 {
2735 u32 count;
2736 struct atom_clock_dividers dividers;
2737 int ret = -EINVAL;
2738
2739 table->SamuLevelCount =
2740 rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.count;
2741
2742 for (count = 0; count < table->SamuLevelCount; count++) {
2743 table->SamuLevel[count].Frequency =
2744 rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.entries[count].clk;
2745 table->SamuLevel[count].MinVoltage =
2746 rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.entries[count].v * VOLTAGE_SCALE;
2747 table->SamuLevel[count].MinPhases = 1;
2748
2749 ret = radeon_atom_get_clock_dividers(rdev,
2750 COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
2751 table->SamuLevel[count].Frequency, false, &dividers);
2752 if (ret)
2753 return ret;
2754
2755 table->SamuLevel[count].Divider = (u8)dividers.post_divider;
2756
2757 table->SamuLevel[count].Frequency = cpu_to_be32(table->SamuLevel[count].Frequency);
2758 table->SamuLevel[count].MinVoltage = cpu_to_be16(table->SamuLevel[count].MinVoltage);
2759 }
2760
2761 return ret;
2762 }
2763
2764 static int ci_calculate_mclk_params(struct radeon_device *rdev,
2765 u32 memory_clock,
2766 SMU7_Discrete_MemoryLevel *mclk,
2767 bool strobe_mode,
2768 bool dll_state_on)
2769 {
2770 struct ci_power_info *pi = ci_get_pi(rdev);
2771 u32 dll_cntl = pi->clock_registers.dll_cntl;
2772 u32 mclk_pwrmgt_cntl = pi->clock_registers.mclk_pwrmgt_cntl;
2773 u32 mpll_ad_func_cntl = pi->clock_registers.mpll_ad_func_cntl;
2774 u32 mpll_dq_func_cntl = pi->clock_registers.mpll_dq_func_cntl;
2775 u32 mpll_func_cntl = pi->clock_registers.mpll_func_cntl;
2776 u32 mpll_func_cntl_1 = pi->clock_registers.mpll_func_cntl_1;
2777 u32 mpll_func_cntl_2 = pi->clock_registers.mpll_func_cntl_2;
2778 u32 mpll_ss1 = pi->clock_registers.mpll_ss1;
2779 u32 mpll_ss2 = pi->clock_registers.mpll_ss2;
2780 struct atom_mpll_param mpll_param;
2781 int ret;
2782
2783 ret = radeon_atom_get_memory_pll_dividers(rdev, memory_clock, strobe_mode, &mpll_param);
2784 if (ret)
2785 return ret;
2786
2787 mpll_func_cntl &= ~BWCTRL_MASK;
2788 mpll_func_cntl |= BWCTRL(mpll_param.bwcntl);
2789
2790 mpll_func_cntl_1 &= ~(CLKF_MASK | CLKFRAC_MASK | VCO_MODE_MASK);
2791 mpll_func_cntl_1 |= CLKF(mpll_param.clkf) |
2792 CLKFRAC(mpll_param.clkfrac) | VCO_MODE(mpll_param.vco_mode);
2793
2794 mpll_ad_func_cntl &= ~YCLK_POST_DIV_MASK;
2795 mpll_ad_func_cntl |= YCLK_POST_DIV(mpll_param.post_div);
2796
2797 if (pi->mem_gddr5) {
2798 mpll_dq_func_cntl &= ~(YCLK_SEL_MASK | YCLK_POST_DIV_MASK);
2799 mpll_dq_func_cntl |= YCLK_SEL(mpll_param.yclk_sel) |
2800 YCLK_POST_DIV(mpll_param.post_div);
2801 }
2802
2803 if (pi->caps_mclk_ss_support) {
2804 struct radeon_atom_ss ss;
2805 u32 freq_nom;
2806 u32 tmp;
2807 u32 reference_clock = rdev->clock.mpll.reference_freq;
2808
2809 if (mpll_param.qdr == 1)
2810 freq_nom = memory_clock * 4 * (1 << mpll_param.post_div);
2811 else
2812 freq_nom = memory_clock * 2 * (1 << mpll_param.post_div);
2813
2814 tmp = (freq_nom / reference_clock);
2815 tmp = tmp * tmp;
2816 if (radeon_atombios_get_asic_ss_info(rdev, &ss,
2817 ASIC_INTERNAL_MEMORY_SS, freq_nom)) {
2818 u32 clks = reference_clock * 5 / ss.rate;
2819 u32 clkv = (u32)((((131 * ss.percentage * ss.rate) / 100) * tmp) / freq_nom);
2820
2821 mpll_ss1 &= ~CLKV_MASK;
2822 mpll_ss1 |= CLKV(clkv);
2823
2824 mpll_ss2 &= ~CLKS_MASK;
2825 mpll_ss2 |= CLKS(clks);
2826 }
2827 }
2828
2829 mclk_pwrmgt_cntl &= ~DLL_SPEED_MASK;
2830 mclk_pwrmgt_cntl |= DLL_SPEED(mpll_param.dll_speed);
2831
2832 if (dll_state_on)
2833 mclk_pwrmgt_cntl |= MRDCK0_PDNB | MRDCK1_PDNB;
2834 else
2835 mclk_pwrmgt_cntl &= ~(MRDCK0_PDNB | MRDCK1_PDNB);
2836
2837 mclk->MclkFrequency = memory_clock;
2838 mclk->MpllFuncCntl = mpll_func_cntl;
2839 mclk->MpllFuncCntl_1 = mpll_func_cntl_1;
2840 mclk->MpllFuncCntl_2 = mpll_func_cntl_2;
2841 mclk->MpllAdFuncCntl = mpll_ad_func_cntl;
2842 mclk->MpllDqFuncCntl = mpll_dq_func_cntl;
2843 mclk->MclkPwrmgtCntl = mclk_pwrmgt_cntl;
2844 mclk->DllCntl = dll_cntl;
2845 mclk->MpllSs1 = mpll_ss1;
2846 mclk->MpllSs2 = mpll_ss2;
2847
2848 return 0;
2849 }
2850
2851 static int ci_populate_single_memory_level(struct radeon_device *rdev,
2852 u32 memory_clock,
2853 SMU7_Discrete_MemoryLevel *memory_level)
2854 {
2855 struct ci_power_info *pi = ci_get_pi(rdev);
2856 int ret;
2857 bool dll_state_on;
2858
2859 if (rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk.entries) {
2860 ret = ci_get_dependency_volt_by_clk(rdev,
2861 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
2862 memory_clock, &memory_level->MinVddc);
2863 if (ret)
2864 return ret;
2865 }
2866
2867 if (rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk.entries) {
2868 ret = ci_get_dependency_volt_by_clk(rdev,
2869 &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
2870 memory_clock, &memory_level->MinVddci);
2871 if (ret)
2872 return ret;
2873 }
2874
2875 if (rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk.entries) {
2876 ret = ci_get_dependency_volt_by_clk(rdev,
2877 &rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk,
2878 memory_clock, &memory_level->MinMvdd);
2879 if (ret)
2880 return ret;
2881 }
2882
2883 memory_level->MinVddcPhases = 1;
2884
2885 if (pi->vddc_phase_shed_control)
2886 ci_populate_phase_value_based_on_mclk(rdev,
2887 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table,
2888 memory_clock,
2889 &memory_level->MinVddcPhases);
2890
2891 memory_level->EnabledForThrottle = 1;
2892 memory_level->UpH = 0;
2893 memory_level->DownH = 100;
2894 memory_level->VoltageDownH = 0;
2895 memory_level->ActivityLevel = (u16)pi->mclk_activity_target;
2896
2897 memory_level->StutterEnable = false;
2898 memory_level->StrobeEnable = false;
2899 memory_level->EdcReadEnable = false;
2900 memory_level->EdcWriteEnable = false;
2901 memory_level->RttEnable = false;
2902
2903 memory_level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
2904
2905 if (pi->mclk_stutter_mode_threshold &&
2906 (memory_clock <= pi->mclk_stutter_mode_threshold) &&
2907 (pi->uvd_enabled == false) &&
2908 (RREG32(DPG_PIPE_STUTTER_CONTROL) & STUTTER_ENABLE) &&
2909 (rdev->pm.dpm.new_active_crtc_count <= 2))
2910 memory_level->StutterEnable = true;
2911
2912 if (pi->mclk_strobe_mode_threshold &&
2913 (memory_clock <= pi->mclk_strobe_mode_threshold))
2914 memory_level->StrobeEnable = 1;
2915
2916 if (pi->mem_gddr5) {
2917 memory_level->StrobeRatio =
2918 si_get_mclk_frequency_ratio(memory_clock, memory_level->StrobeEnable);
2919 if (pi->mclk_edc_enable_threshold &&
2920 (memory_clock > pi->mclk_edc_enable_threshold))
2921 memory_level->EdcReadEnable = true;
2922
2923 if (pi->mclk_edc_wr_enable_threshold &&
2924 (memory_clock > pi->mclk_edc_wr_enable_threshold))
2925 memory_level->EdcWriteEnable = true;
2926
2927 if (memory_level->StrobeEnable) {
2928 if (si_get_mclk_frequency_ratio(memory_clock, true) >=
2929 ((RREG32(MC_SEQ_MISC7) >> 16) & 0xf))
2930 dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false;
2931 else
2932 dll_state_on = ((RREG32(MC_SEQ_MISC6) >> 1) & 0x1) ? true : false;
2933 } else {
2934 dll_state_on = pi->dll_default_on;
2935 }
2936 } else {
2937 memory_level->StrobeRatio = si_get_ddr3_mclk_frequency_ratio(memory_clock);
2938 dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false;
2939 }
2940
2941 ret = ci_calculate_mclk_params(rdev, memory_clock, memory_level, memory_level->StrobeEnable, dll_state_on);
2942 if (ret)
2943 return ret;
2944
2945 memory_level->MinVddc = cpu_to_be32(memory_level->MinVddc * VOLTAGE_SCALE);
2946 memory_level->MinVddcPhases = cpu_to_be32(memory_level->MinVddcPhases);
2947 memory_level->MinVddci = cpu_to_be32(memory_level->MinVddci * VOLTAGE_SCALE);
2948 memory_level->MinMvdd = cpu_to_be32(memory_level->MinMvdd * VOLTAGE_SCALE);
2949
2950 memory_level->MclkFrequency = cpu_to_be32(memory_level->MclkFrequency);
2951 memory_level->ActivityLevel = cpu_to_be16(memory_level->ActivityLevel);
2952 memory_level->MpllFuncCntl = cpu_to_be32(memory_level->MpllFuncCntl);
2953 memory_level->MpllFuncCntl_1 = cpu_to_be32(memory_level->MpllFuncCntl_1);
2954 memory_level->MpllFuncCntl_2 = cpu_to_be32(memory_level->MpllFuncCntl_2);
2955 memory_level->MpllAdFuncCntl = cpu_to_be32(memory_level->MpllAdFuncCntl);
2956 memory_level->MpllDqFuncCntl = cpu_to_be32(memory_level->MpllDqFuncCntl);
2957 memory_level->MclkPwrmgtCntl = cpu_to_be32(memory_level->MclkPwrmgtCntl);
2958 memory_level->DllCntl = cpu_to_be32(memory_level->DllCntl);
2959 memory_level->MpllSs1 = cpu_to_be32(memory_level->MpllSs1);
2960 memory_level->MpllSs2 = cpu_to_be32(memory_level->MpllSs2);
2961
2962 return 0;
2963 }
2964
2965 static int ci_populate_smc_acpi_level(struct radeon_device *rdev,
2966 SMU7_Discrete_DpmTable *table)
2967 {
2968 struct ci_power_info *pi = ci_get_pi(rdev);
2969 struct atom_clock_dividers dividers;
2970 SMU7_Discrete_VoltageLevel voltage_level;
2971 u32 spll_func_cntl = pi->clock_registers.cg_spll_func_cntl;
2972 u32 spll_func_cntl_2 = pi->clock_registers.cg_spll_func_cntl_2;
2973 u32 dll_cntl = pi->clock_registers.dll_cntl;
2974 u32 mclk_pwrmgt_cntl = pi->clock_registers.mclk_pwrmgt_cntl;
2975 int ret;
2976
2977 table->ACPILevel.Flags &= ~PPSMC_SWSTATE_FLAG_DC;
2978
2979 if (pi->acpi_vddc)
2980 table->ACPILevel.MinVddc = cpu_to_be32(pi->acpi_vddc * VOLTAGE_SCALE);
2981 else
2982 table->ACPILevel.MinVddc = cpu_to_be32(pi->min_vddc_in_pp_table * VOLTAGE_SCALE);
2983
2984 table->ACPILevel.MinVddcPhases = pi->vddc_phase_shed_control ? 0 : 1;
2985
2986 table->ACPILevel.SclkFrequency = rdev->clock.spll.reference_freq;
2987
2988 ret = radeon_atom_get_clock_dividers(rdev,
2989 COMPUTE_GPUCLK_INPUT_FLAG_SCLK,
2990 table->ACPILevel.SclkFrequency, false, &dividers);
2991 if (ret)
2992 return ret;
2993
2994 table->ACPILevel.SclkDid = (u8)dividers.post_divider;
2995 table->ACPILevel.DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
2996 table->ACPILevel.DeepSleepDivId = 0;
2997
2998 spll_func_cntl &= ~SPLL_PWRON;
2999 spll_func_cntl |= SPLL_RESET;
3000
3001 spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK;
3002 spll_func_cntl_2 |= SCLK_MUX_SEL(4);
3003
3004 table->ACPILevel.CgSpllFuncCntl = spll_func_cntl;
3005 table->ACPILevel.CgSpllFuncCntl2 = spll_func_cntl_2;
3006 table->ACPILevel.CgSpllFuncCntl3 = pi->clock_registers.cg_spll_func_cntl_3;
3007 table->ACPILevel.CgSpllFuncCntl4 = pi->clock_registers.cg_spll_func_cntl_4;
3008 table->ACPILevel.SpllSpreadSpectrum = pi->clock_registers.cg_spll_spread_spectrum;
3009 table->ACPILevel.SpllSpreadSpectrum2 = pi->clock_registers.cg_spll_spread_spectrum_2;
3010 table->ACPILevel.CcPwrDynRm = 0;
3011 table->ACPILevel.CcPwrDynRm1 = 0;
3012
3013 table->ACPILevel.Flags = cpu_to_be32(table->ACPILevel.Flags);
3014 table->ACPILevel.MinVddcPhases = cpu_to_be32(table->ACPILevel.MinVddcPhases);
3015 table->ACPILevel.SclkFrequency = cpu_to_be32(table->ACPILevel.SclkFrequency);
3016 table->ACPILevel.CgSpllFuncCntl = cpu_to_be32(table->ACPILevel.CgSpllFuncCntl);
3017 table->ACPILevel.CgSpllFuncCntl2 = cpu_to_be32(table->ACPILevel.CgSpllFuncCntl2);
3018 table->ACPILevel.CgSpllFuncCntl3 = cpu_to_be32(table->ACPILevel.CgSpllFuncCntl3);
3019 table->ACPILevel.CgSpllFuncCntl4 = cpu_to_be32(table->ACPILevel.CgSpllFuncCntl4);
3020 table->ACPILevel.SpllSpreadSpectrum = cpu_to_be32(table->ACPILevel.SpllSpreadSpectrum);
3021 table->ACPILevel.SpllSpreadSpectrum2 = cpu_to_be32(table->ACPILevel.SpllSpreadSpectrum2);
3022 table->ACPILevel.CcPwrDynRm = cpu_to_be32(table->ACPILevel.CcPwrDynRm);
3023 table->ACPILevel.CcPwrDynRm1 = cpu_to_be32(table->ACPILevel.CcPwrDynRm1);
3024
3025 table->MemoryACPILevel.MinVddc = table->ACPILevel.MinVddc;
3026 table->MemoryACPILevel.MinVddcPhases = table->ACPILevel.MinVddcPhases;
3027
3028 if (pi->vddci_control != CISLANDS_VOLTAGE_CONTROL_NONE) {
3029 if (pi->acpi_vddci)
3030 table->MemoryACPILevel.MinVddci =
3031 cpu_to_be32(pi->acpi_vddci * VOLTAGE_SCALE);
3032 else
3033 table->MemoryACPILevel.MinVddci =
3034 cpu_to_be32(pi->min_vddci_in_pp_table * VOLTAGE_SCALE);
3035 }
3036
3037 if (ci_populate_mvdd_value(rdev, 0, &voltage_level))
3038 table->MemoryACPILevel.MinMvdd = 0;
3039 else
3040 table->MemoryACPILevel.MinMvdd =
3041 cpu_to_be32(voltage_level.Voltage * VOLTAGE_SCALE);
3042
3043 mclk_pwrmgt_cntl |= MRDCK0_RESET | MRDCK1_RESET;
3044 mclk_pwrmgt_cntl &= ~(MRDCK0_PDNB | MRDCK1_PDNB);
3045
3046 dll_cntl &= ~(MRDCK0_BYPASS | MRDCK1_BYPASS);
3047
3048 table->MemoryACPILevel.DllCntl = cpu_to_be32(dll_cntl);
3049 table->MemoryACPILevel.MclkPwrmgtCntl = cpu_to_be32(mclk_pwrmgt_cntl);
3050 table->MemoryACPILevel.MpllAdFuncCntl =
3051 cpu_to_be32(pi->clock_registers.mpll_ad_func_cntl);
3052 table->MemoryACPILevel.MpllDqFuncCntl =
3053 cpu_to_be32(pi->clock_registers.mpll_dq_func_cntl);
3054 table->MemoryACPILevel.MpllFuncCntl =
3055 cpu_to_be32(pi->clock_registers.mpll_func_cntl);
3056 table->MemoryACPILevel.MpllFuncCntl_1 =
3057 cpu_to_be32(pi->clock_registers.mpll_func_cntl_1);
3058 table->MemoryACPILevel.MpllFuncCntl_2 =
3059 cpu_to_be32(pi->clock_registers.mpll_func_cntl_2);
3060 table->MemoryACPILevel.MpllSs1 = cpu_to_be32(pi->clock_registers.mpll_ss1);
3061 table->MemoryACPILevel.MpllSs2 = cpu_to_be32(pi->clock_registers.mpll_ss2);
3062
3063 table->MemoryACPILevel.EnabledForThrottle = 0;
3064 table->MemoryACPILevel.EnabledForActivity = 0;
3065 table->MemoryACPILevel.UpH = 0;
3066 table->MemoryACPILevel.DownH = 100;
3067 table->MemoryACPILevel.VoltageDownH = 0;
3068 table->MemoryACPILevel.ActivityLevel =
3069 cpu_to_be16((u16)pi->mclk_activity_target);
3070
3071 table->MemoryACPILevel.StutterEnable = false;
3072 table->MemoryACPILevel.StrobeEnable = false;
3073 table->MemoryACPILevel.EdcReadEnable = false;
3074 table->MemoryACPILevel.EdcWriteEnable = false;
3075 table->MemoryACPILevel.RttEnable = false;
3076
3077 return 0;
3078 }
3079
3080
3081 static int ci_enable_ulv(struct radeon_device *rdev, bool enable)
3082 {
3083 struct ci_power_info *pi = ci_get_pi(rdev);
3084 struct ci_ulv_parm *ulv = &pi->ulv;
3085
3086 if (ulv->supported) {
3087 if (enable)
3088 return (ci_send_msg_to_smc(rdev, PPSMC_MSG_EnableULV) == PPSMC_Result_OK) ?
3089 0 : -EINVAL;
3090 else
3091 return (ci_send_msg_to_smc(rdev, PPSMC_MSG_DisableULV) == PPSMC_Result_OK) ?
3092 0 : -EINVAL;
3093 }
3094
3095 return 0;
3096 }
3097
3098 static int ci_populate_ulv_level(struct radeon_device *rdev,
3099 SMU7_Discrete_Ulv *state)
3100 {
3101 struct ci_power_info *pi = ci_get_pi(rdev);
3102 u16 ulv_voltage = rdev->pm.dpm.backbias_response_time;
3103
3104 state->CcPwrDynRm = 0;
3105 state->CcPwrDynRm1 = 0;
3106
3107 if (ulv_voltage == 0) {
3108 pi->ulv.supported = false;
3109 return 0;
3110 }
3111
3112 if (pi->voltage_control != CISLANDS_VOLTAGE_CONTROL_BY_SVID2) {
3113 if (ulv_voltage > rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[0].v)
3114 state->VddcOffset = 0;
3115 else
3116 state->VddcOffset =
3117 rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[0].v - ulv_voltage;
3118 } else {
3119 if (ulv_voltage > rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[0].v)
3120 state->VddcOffsetVid = 0;
3121 else
3122 state->VddcOffsetVid = (u8)
3123 ((rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[0].v - ulv_voltage) *
3124 VOLTAGE_VID_OFFSET_SCALE2 / VOLTAGE_VID_OFFSET_SCALE1);
3125 }
3126 state->VddcPhase = pi->vddc_phase_shed_control ? 0 : 1;
3127
3128 state->CcPwrDynRm = cpu_to_be32(state->CcPwrDynRm);
3129 state->CcPwrDynRm1 = cpu_to_be32(state->CcPwrDynRm1);
3130 state->VddcOffset = cpu_to_be16(state->VddcOffset);
3131
3132 return 0;
3133 }
3134
3135 static int ci_calculate_sclk_params(struct radeon_device *rdev,
3136 u32 engine_clock,
3137 SMU7_Discrete_GraphicsLevel *sclk)
3138 {
3139 struct ci_power_info *pi = ci_get_pi(rdev);
3140 struct atom_clock_dividers dividers;
3141 u32 spll_func_cntl_3 = pi->clock_registers.cg_spll_func_cntl_3;
3142 u32 spll_func_cntl_4 = pi->clock_registers.cg_spll_func_cntl_4;
3143 u32 cg_spll_spread_spectrum = pi->clock_registers.cg_spll_spread_spectrum;
3144 u32 cg_spll_spread_spectrum_2 = pi->clock_registers.cg_spll_spread_spectrum_2;
3145 u32 reference_clock = rdev->clock.spll.reference_freq;
3146 u32 reference_divider;
3147 u32 fbdiv;
3148 int ret;
3149
3150 ret = radeon_atom_get_clock_dividers(rdev,
3151 COMPUTE_GPUCLK_INPUT_FLAG_SCLK,
3152 engine_clock, false, &dividers);
3153 if (ret)
3154 return ret;
3155
3156 reference_divider = 1 + dividers.ref_div;
3157 fbdiv = dividers.fb_div & 0x3FFFFFF;
3158
3159 spll_func_cntl_3 &= ~SPLL_FB_DIV_MASK;
3160 spll_func_cntl_3 |= SPLL_FB_DIV(fbdiv);
3161 spll_func_cntl_3 |= SPLL_DITHEN;
3162
3163 if (pi->caps_sclk_ss_support) {
3164 struct radeon_atom_ss ss;
3165 u32 vco_freq = engine_clock * dividers.post_div;
3166
3167 if (radeon_atombios_get_asic_ss_info(rdev, &ss,
3168 ASIC_INTERNAL_ENGINE_SS, vco_freq)) {
3169 u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate);
3170 u32 clk_v = 4 * ss.percentage * fbdiv / (clk_s * 10000);
3171
3172 cg_spll_spread_spectrum &= ~CLK_S_MASK;
3173 cg_spll_spread_spectrum |= CLK_S(clk_s);
3174 cg_spll_spread_spectrum |= SSEN;
3175
3176 cg_spll_spread_spectrum_2 &= ~CLK_V_MASK;
3177 cg_spll_spread_spectrum_2 |= CLK_V(clk_v);
3178 }
3179 }
3180
3181 sclk->SclkFrequency = engine_clock;
3182 sclk->CgSpllFuncCntl3 = spll_func_cntl_3;
3183 sclk->CgSpllFuncCntl4 = spll_func_cntl_4;
3184 sclk->SpllSpreadSpectrum = cg_spll_spread_spectrum;
3185 sclk->SpllSpreadSpectrum2 = cg_spll_spread_spectrum_2;
3186 sclk->SclkDid = (u8)dividers.post_divider;
3187
3188 return 0;
3189 }
3190
3191 static int ci_populate_single_graphic_level(struct radeon_device *rdev,
3192 u32 engine_clock,
3193 u16 sclk_activity_level_t,
3194 SMU7_Discrete_GraphicsLevel *graphic_level)
3195 {
3196 struct ci_power_info *pi = ci_get_pi(rdev);
3197 int ret;
3198
3199 ret = ci_calculate_sclk_params(rdev, engine_clock, graphic_level);
3200 if (ret)
3201 return ret;
3202
3203 ret = ci_get_dependency_volt_by_clk(rdev,
3204 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk,
3205 engine_clock, &graphic_level->MinVddc);
3206 if (ret)
3207 return ret;
3208
3209 graphic_level->SclkFrequency = engine_clock;
3210
3211 graphic_level->Flags = 0;
3212 graphic_level->MinVddcPhases = 1;
3213
3214 if (pi->vddc_phase_shed_control)
3215 ci_populate_phase_value_based_on_sclk(rdev,
3216 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table,
3217 engine_clock,
3218 &graphic_level->MinVddcPhases);
3219
3220 graphic_level->ActivityLevel = sclk_activity_level_t;
3221
3222 graphic_level->CcPwrDynRm = 0;
3223 graphic_level->CcPwrDynRm1 = 0;
3224 graphic_level->EnabledForThrottle = 1;
3225 graphic_level->UpH = 0;
3226 graphic_level->DownH = 0;
3227 graphic_level->VoltageDownH = 0;
3228 graphic_level->PowerThrottle = 0;
3229
3230 if (pi->caps_sclk_ds)
3231 graphic_level->DeepSleepDivId = ci_get_sleep_divider_id_from_clock(rdev,
3232 engine_clock,
3233 CISLAND_MINIMUM_ENGINE_CLOCK);
3234
3235 graphic_level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
3236
3237 graphic_level->Flags = cpu_to_be32(graphic_level->Flags);
3238 graphic_level->MinVddc = cpu_to_be32(graphic_level->MinVddc * VOLTAGE_SCALE);
3239 graphic_level->MinVddcPhases = cpu_to_be32(graphic_level->MinVddcPhases);
3240 graphic_level->SclkFrequency = cpu_to_be32(graphic_level->SclkFrequency);
3241 graphic_level->ActivityLevel = cpu_to_be16(graphic_level->ActivityLevel);
3242 graphic_level->CgSpllFuncCntl3 = cpu_to_be32(graphic_level->CgSpllFuncCntl3);
3243 graphic_level->CgSpllFuncCntl4 = cpu_to_be32(graphic_level->CgSpllFuncCntl4);
3244 graphic_level->SpllSpreadSpectrum = cpu_to_be32(graphic_level->SpllSpreadSpectrum);
3245 graphic_level->SpllSpreadSpectrum2 = cpu_to_be32(graphic_level->SpllSpreadSpectrum2);
3246 graphic_level->CcPwrDynRm = cpu_to_be32(graphic_level->CcPwrDynRm);
3247 graphic_level->CcPwrDynRm1 = cpu_to_be32(graphic_level->CcPwrDynRm1);
3248
3249 return 0;
3250 }
3251
3252 static int ci_populate_all_graphic_levels(struct radeon_device *rdev)
3253 {
3254 struct ci_power_info *pi = ci_get_pi(rdev);
3255 struct ci_dpm_table *dpm_table = &pi->dpm_table;
3256 u32 level_array_address = pi->dpm_table_start +
3257 offsetof(SMU7_Discrete_DpmTable, GraphicsLevel);
3258 u32 level_array_size = sizeof(SMU7_Discrete_GraphicsLevel) *
3259 SMU7_MAX_LEVELS_GRAPHICS;
3260 SMU7_Discrete_GraphicsLevel *levels = pi->smc_state_table.GraphicsLevel;
3261 u32 i, ret;
3262
3263 memset(levels, 0, level_array_size);
3264
3265 for (i = 0; i < dpm_table->sclk_table.count; i++) {
3266 ret = ci_populate_single_graphic_level(rdev,
3267 dpm_table->sclk_table.dpm_levels[i].value,
3268 (u16)pi->activity_target[i],
3269 &pi->smc_state_table.GraphicsLevel[i]);
3270 if (ret)
3271 return ret;
3272 if (i > 1)
3273 pi->smc_state_table.GraphicsLevel[i].DeepSleepDivId = 0;
3274 if (i == (dpm_table->sclk_table.count - 1))
3275 pi->smc_state_table.GraphicsLevel[i].DisplayWatermark =
3276 PPSMC_DISPLAY_WATERMARK_HIGH;
3277 }
3278 pi->smc_state_table.GraphicsLevel[0].EnabledForActivity = 1;
3279
3280 pi->smc_state_table.GraphicsDpmLevelCount = (u8)dpm_table->sclk_table.count;
3281 pi->dpm_level_enable_mask.sclk_dpm_enable_mask =
3282 ci_get_dpm_level_enable_mask_value(&dpm_table->sclk_table);
3283
3284 ret = ci_copy_bytes_to_smc(rdev, level_array_address,
3285 (u8 *)levels, level_array_size,
3286 pi->sram_end);
3287 if (ret)
3288 return ret;
3289
3290 return 0;
3291 }
3292
3293 static int ci_populate_ulv_state(struct radeon_device *rdev,
3294 SMU7_Discrete_Ulv *ulv_level)
3295 {
3296 return ci_populate_ulv_level(rdev, ulv_level);
3297 }
3298
3299 static int ci_populate_all_memory_levels(struct radeon_device *rdev)
3300 {
3301 struct ci_power_info *pi = ci_get_pi(rdev);
3302 struct ci_dpm_table *dpm_table = &pi->dpm_table;
3303 u32 level_array_address = pi->dpm_table_start +
3304 offsetof(SMU7_Discrete_DpmTable, MemoryLevel);
3305 u32 level_array_size = sizeof(SMU7_Discrete_MemoryLevel) *
3306 SMU7_MAX_LEVELS_MEMORY;
3307 SMU7_Discrete_MemoryLevel *levels = pi->smc_state_table.MemoryLevel;
3308 u32 i, ret;
3309
3310 memset(levels, 0, level_array_size);
3311
3312 for (i = 0; i < dpm_table->mclk_table.count; i++) {
3313 if (dpm_table->mclk_table.dpm_levels[i].value == 0)
3314 return -EINVAL;
3315 ret = ci_populate_single_memory_level(rdev,
3316 dpm_table->mclk_table.dpm_levels[i].value,
3317 &pi->smc_state_table.MemoryLevel[i]);
3318 if (ret)
3319 return ret;
3320 }
3321
3322 pi->smc_state_table.MemoryLevel[0].EnabledForActivity = 1;
3323
3324 if ((dpm_table->mclk_table.count >= 2) &&
3325 ((rdev->pdev->device == 0x67B0) || (rdev->pdev->device == 0x67B1))) {
3326 pi->smc_state_table.MemoryLevel[1].MinVddc =
3327 pi->smc_state_table.MemoryLevel[0].MinVddc;
3328 pi->smc_state_table.MemoryLevel[1].MinVddcPhases =
3329 pi->smc_state_table.MemoryLevel[0].MinVddcPhases;
3330 }
3331
3332 pi->smc_state_table.MemoryLevel[0].ActivityLevel = cpu_to_be16(0x1F);
3333
3334 pi->smc_state_table.MemoryDpmLevelCount = (u8)dpm_table->mclk_table.count;
3335 pi->dpm_level_enable_mask.mclk_dpm_enable_mask =
3336 ci_get_dpm_level_enable_mask_value(&dpm_table->mclk_table);
3337
3338 pi->smc_state_table.MemoryLevel[dpm_table->mclk_table.count - 1].DisplayWatermark =
3339 PPSMC_DISPLAY_WATERMARK_HIGH;
3340
3341 ret = ci_copy_bytes_to_smc(rdev, level_array_address,
3342 (u8 *)levels, level_array_size,
3343 pi->sram_end);
3344 if (ret)
3345 return ret;
3346
3347 return 0;
3348 }
3349
3350 static void ci_reset_single_dpm_table(struct radeon_device *rdev,
3351 struct ci_single_dpm_table* dpm_table,
3352 u32 count)
3353 {
3354 u32 i;
3355
3356 dpm_table->count = count;
3357 for (i = 0; i < MAX_REGULAR_DPM_NUMBER; i++)
3358 dpm_table->dpm_levels[i].enabled = false;
3359 }
3360
3361 static void ci_setup_pcie_table_entry(struct ci_single_dpm_table* dpm_table,
3362 u32 index, u32 pcie_gen, u32 pcie_lanes)
3363 {
3364 dpm_table->dpm_levels[index].value = pcie_gen;
3365 dpm_table->dpm_levels[index].param1 = pcie_lanes;
3366 dpm_table->dpm_levels[index].enabled = true;
3367 }
3368
3369 static int ci_setup_default_pcie_tables(struct radeon_device *rdev)
3370 {
3371 struct ci_power_info *pi = ci_get_pi(rdev);
3372
3373 if (!pi->use_pcie_performance_levels && !pi->use_pcie_powersaving_levels)
3374 return -EINVAL;
3375
3376 if (pi->use_pcie_performance_levels && !pi->use_pcie_powersaving_levels) {
3377 pi->pcie_gen_powersaving = pi->pcie_gen_performance;
3378 pi->pcie_lane_powersaving = pi->pcie_lane_performance;
3379 } else if (!pi->use_pcie_performance_levels && pi->use_pcie_powersaving_levels) {
3380 pi->pcie_gen_performance = pi->pcie_gen_powersaving;
3381 pi->pcie_lane_performance = pi->pcie_lane_powersaving;
3382 }
3383
3384 ci_reset_single_dpm_table(rdev,
3385 &pi->dpm_table.pcie_speed_table,
3386 SMU7_MAX_LEVELS_LINK);
3387
3388 if (rdev->family == CHIP_BONAIRE)
3389 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 0,
3390 pi->pcie_gen_powersaving.min,
3391 pi->pcie_lane_powersaving.max);
3392 else
3393 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 0,
3394 pi->pcie_gen_powersaving.min,
3395 pi->pcie_lane_powersaving.min);
3396 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 1,
3397 pi->pcie_gen_performance.min,
3398 pi->pcie_lane_performance.min);
3399 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 2,
3400 pi->pcie_gen_powersaving.min,
3401 pi->pcie_lane_powersaving.max);
3402 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 3,
3403 pi->pcie_gen_performance.min,
3404 pi->pcie_lane_performance.max);
3405 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 4,
3406 pi->pcie_gen_powersaving.max,
3407 pi->pcie_lane_powersaving.max);
3408 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 5,
3409 pi->pcie_gen_performance.max,
3410 pi->pcie_lane_performance.max);
3411
3412 pi->dpm_table.pcie_speed_table.count = 6;
3413
3414 return 0;
3415 }
3416
3417 static int ci_setup_default_dpm_tables(struct radeon_device *rdev)
3418 {
3419 struct ci_power_info *pi = ci_get_pi(rdev);
3420 struct radeon_clock_voltage_dependency_table *allowed_sclk_vddc_table =
3421 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
3422 struct radeon_clock_voltage_dependency_table *allowed_mclk_table =
3423 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk;
3424 struct radeon_cac_leakage_table *std_voltage_table =
3425 &rdev->pm.dpm.dyn_state.cac_leakage_table;
3426 u32 i;
3427
3428 if (allowed_sclk_vddc_table == NULL)
3429 return -EINVAL;
3430 if (allowed_sclk_vddc_table->count < 1)
3431 return -EINVAL;
3432 if (allowed_mclk_table == NULL)
3433 return -EINVAL;
3434 if (allowed_mclk_table->count < 1)
3435 return -EINVAL;
3436
3437 memset(&pi->dpm_table, 0, sizeof(struct ci_dpm_table));
3438
3439 ci_reset_single_dpm_table(rdev,
3440 &pi->dpm_table.sclk_table,
3441 SMU7_MAX_LEVELS_GRAPHICS);
3442 ci_reset_single_dpm_table(rdev,
3443 &pi->dpm_table.mclk_table,
3444 SMU7_MAX_LEVELS_MEMORY);
3445 ci_reset_single_dpm_table(rdev,
3446 &pi->dpm_table.vddc_table,
3447 SMU7_MAX_LEVELS_VDDC);
3448 ci_reset_single_dpm_table(rdev,
3449 &pi->dpm_table.vddci_table,
3450 SMU7_MAX_LEVELS_VDDCI);
3451 ci_reset_single_dpm_table(rdev,
3452 &pi->dpm_table.mvdd_table,
3453 SMU7_MAX_LEVELS_MVDD);
3454
3455 pi->dpm_table.sclk_table.count = 0;
3456 for (i = 0; i < allowed_sclk_vddc_table->count; i++) {
3457 if ((i == 0) ||
3458 (pi->dpm_table.sclk_table.dpm_levels[pi->dpm_table.sclk_table.count-1].value !=
3459 allowed_sclk_vddc_table->entries[i].clk)) {
3460 pi->dpm_table.sclk_table.dpm_levels[pi->dpm_table.sclk_table.count].value =
3461 allowed_sclk_vddc_table->entries[i].clk;
3462 pi->dpm_table.sclk_table.dpm_levels[pi->dpm_table.sclk_table.count].enabled =
3463 (i == 0) ? true : false;
3464 pi->dpm_table.sclk_table.count++;
3465 }
3466 }
3467
3468 pi->dpm_table.mclk_table.count = 0;
3469 for (i = 0; i < allowed_mclk_table->count; i++) {
3470 if ((i == 0) ||
3471 (pi->dpm_table.mclk_table.dpm_levels[pi->dpm_table.mclk_table.count-1].value !=
3472 allowed_mclk_table->entries[i].clk)) {
3473 pi->dpm_table.mclk_table.dpm_levels[pi->dpm_table.mclk_table.count].value =
3474 allowed_mclk_table->entries[i].clk;
3475 pi->dpm_table.mclk_table.dpm_levels[pi->dpm_table.mclk_table.count].enabled =
3476 (i == 0) ? true : false;
3477 pi->dpm_table.mclk_table.count++;
3478 }
3479 }
3480
3481 for (i = 0; i < allowed_sclk_vddc_table->count; i++) {
3482 pi->dpm_table.vddc_table.dpm_levels[i].value =
3483 allowed_sclk_vddc_table->entries[i].v;
3484 pi->dpm_table.vddc_table.dpm_levels[i].param1 =
3485 std_voltage_table->entries[i].leakage;
3486 pi->dpm_table.vddc_table.dpm_levels[i].enabled = true;
3487 }
3488 pi->dpm_table.vddc_table.count = allowed_sclk_vddc_table->count;
3489
3490 allowed_mclk_table = &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk;
3491 if (allowed_mclk_table) {
3492 for (i = 0; i < allowed_mclk_table->count; i++) {
3493 pi->dpm_table.vddci_table.dpm_levels[i].value =
3494 allowed_mclk_table->entries[i].v;
3495 pi->dpm_table.vddci_table.dpm_levels[i].enabled = true;
3496 }
3497 pi->dpm_table.vddci_table.count = allowed_mclk_table->count;
3498 }
3499
3500 allowed_mclk_table = &rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk;
3501 if (allowed_mclk_table) {
3502 for (i = 0; i < allowed_mclk_table->count; i++) {
3503 pi->dpm_table.mvdd_table.dpm_levels[i].value =
3504 allowed_mclk_table->entries[i].v;
3505 pi->dpm_table.mvdd_table.dpm_levels[i].enabled = true;
3506 }
3507 pi->dpm_table.mvdd_table.count = allowed_mclk_table->count;
3508 }
3509
3510 ci_setup_default_pcie_tables(rdev);
3511
3512 return 0;
3513 }
3514
3515 static int ci_find_boot_level(struct ci_single_dpm_table *table,
3516 u32 value, u32 *boot_level)
3517 {
3518 u32 i;
3519 int ret = -EINVAL;
3520
3521 for(i = 0; i < table->count; i++) {
3522 if (value == table->dpm_levels[i].value) {
3523 *boot_level = i;
3524 ret = 0;
3525 }
3526 }
3527
3528 return ret;
3529 }
3530
3531 static int ci_init_smc_table(struct radeon_device *rdev)
3532 {
3533 struct ci_power_info *pi = ci_get_pi(rdev);
3534 struct ci_ulv_parm *ulv = &pi->ulv;
3535 struct radeon_ps *radeon_boot_state = rdev->pm.dpm.boot_ps;
3536 SMU7_Discrete_DpmTable *table = &pi->smc_state_table;
3537 int ret;
3538
3539 ret = ci_setup_default_dpm_tables(rdev);
3540 if (ret)
3541 return ret;
3542
3543 if (pi->voltage_control != CISLANDS_VOLTAGE_CONTROL_NONE)
3544 ci_populate_smc_voltage_tables(rdev, table);
3545
3546 ci_init_fps_limits(rdev);
3547
3548 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_HARDWAREDC)
3549 table->SystemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC;
3550
3551 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_STEPVDDC)
3552 table->SystemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC;
3553
3554 if (pi->mem_gddr5)
3555 table->SystemFlags |= PPSMC_SYSTEMFLAG_GDDR5;
3556
3557 if (ulv->supported) {
3558 ret = ci_populate_ulv_state(rdev, &pi->smc_state_table.Ulv);
3559 if (ret)
3560 return ret;
3561 WREG32_SMC(CG_ULV_PARAMETER, ulv->cg_ulv_parameter);
3562 }
3563
3564 ret = ci_populate_all_graphic_levels(rdev);
3565 if (ret)
3566 return ret;
3567
3568 ret = ci_populate_all_memory_levels(rdev);
3569 if (ret)
3570 return ret;
3571
3572 ci_populate_smc_link_level(rdev, table);
3573
3574 ret = ci_populate_smc_acpi_level(rdev, table);
3575 if (ret)
3576 return ret;
3577
3578 ret = ci_populate_smc_vce_level(rdev, table);
3579 if (ret)
3580 return ret;
3581
3582 ret = ci_populate_smc_acp_level(rdev, table);
3583 if (ret)
3584 return ret;
3585
3586 ret = ci_populate_smc_samu_level(rdev, table);
3587 if (ret)
3588 return ret;
3589
3590 ret = ci_do_program_memory_timing_parameters(rdev);
3591 if (ret)
3592 return ret;
3593
3594 ret = ci_populate_smc_uvd_level(rdev, table);
3595 if (ret)
3596 return ret;
3597
3598 table->UvdBootLevel = 0;
3599 table->VceBootLevel = 0;
3600 table->AcpBootLevel = 0;
3601 table->SamuBootLevel = 0;
3602 table->GraphicsBootLevel = 0;
3603 table->MemoryBootLevel = 0;
3604
3605 ret = ci_find_boot_level(&pi->dpm_table.sclk_table,
3606 pi->vbios_boot_state.sclk_bootup_value,
3607 (u32 *)&pi->smc_state_table.GraphicsBootLevel);
3608
3609 ret = ci_find_boot_level(&pi->dpm_table.mclk_table,
3610 pi->vbios_boot_state.mclk_bootup_value,
3611 (u32 *)&pi->smc_state_table.MemoryBootLevel);
3612
3613 table->BootVddc = pi->vbios_boot_state.vddc_bootup_value;
3614 table->BootVddci = pi->vbios_boot_state.vddci_bootup_value;
3615 table->BootMVdd = pi->vbios_boot_state.mvdd_bootup_value;
3616
3617 ci_populate_smc_initial_state(rdev, radeon_boot_state);
3618
3619 ret = ci_populate_bapm_parameters_in_dpm_table(rdev);
3620 if (ret)
3621 return ret;
3622
3623 table->UVDInterval = 1;
3624 table->VCEInterval = 1;
3625 table->ACPInterval = 1;
3626 table->SAMUInterval = 1;
3627 table->GraphicsVoltageChangeEnable = 1;
3628 table->GraphicsThermThrottleEnable = 1;
3629 table->GraphicsInterval = 1;
3630 table->VoltageInterval = 1;
3631 table->ThermalInterval = 1;
3632 table->TemperatureLimitHigh = (u16)((pi->thermal_temp_setting.temperature_high *
3633 CISLANDS_Q88_FORMAT_CONVERSION_UNIT) / 1000);
3634 table->TemperatureLimitLow = (u16)((pi->thermal_temp_setting.temperature_low *
3635 CISLANDS_Q88_FORMAT_CONVERSION_UNIT) / 1000);
3636 table->MemoryVoltageChangeEnable = 1;
3637 table->MemoryInterval = 1;
3638 table->VoltageResponseTime = 0;
3639 table->VddcVddciDelta = 4000;
3640 table->PhaseResponseTime = 0;
3641 table->MemoryThermThrottleEnable = 1;
3642 table->PCIeBootLinkLevel = pi->dpm_table.pcie_speed_table.count - 1;
3643 table->PCIeGenInterval = 1;
3644 if (pi->voltage_control == CISLANDS_VOLTAGE_CONTROL_BY_SVID2)
3645 table->SVI2Enable = 1;
3646 else
3647 table->SVI2Enable = 0;
3648
3649 table->ThermGpio = 17;
3650 table->SclkStepSize = 0x4000;
3651
3652 table->SystemFlags = cpu_to_be32(table->SystemFlags);
3653 table->SmioMaskVddcVid = cpu_to_be32(table->SmioMaskVddcVid);
3654 table->SmioMaskVddcPhase = cpu_to_be32(table->SmioMaskVddcPhase);
3655 table->SmioMaskVddciVid = cpu_to_be32(table->SmioMaskVddciVid);
3656 table->SmioMaskMvddVid = cpu_to_be32(table->SmioMaskMvddVid);
3657 table->SclkStepSize = cpu_to_be32(table->SclkStepSize);
3658 table->TemperatureLimitHigh = cpu_to_be16(table->TemperatureLimitHigh);
3659 table->TemperatureLimitLow = cpu_to_be16(table->TemperatureLimitLow);
3660 table->VddcVddciDelta = cpu_to_be16(table->VddcVddciDelta);
3661 table->VoltageResponseTime = cpu_to_be16(table->VoltageResponseTime);
3662 table->PhaseResponseTime = cpu_to_be16(table->PhaseResponseTime);
3663 table->BootVddc = cpu_to_be16(table->BootVddc * VOLTAGE_SCALE);
3664 table->BootVddci = cpu_to_be16(table->BootVddci * VOLTAGE_SCALE);
3665 table->BootMVdd = cpu_to_be16(table->BootMVdd * VOLTAGE_SCALE);
3666
3667 ret = ci_copy_bytes_to_smc(rdev,
3668 pi->dpm_table_start +
3669 offsetof(SMU7_Discrete_DpmTable, SystemFlags),
3670 (u8 *)&table->SystemFlags,
3671 sizeof(SMU7_Discrete_DpmTable) - 3 * sizeof(SMU7_PIDController),
3672 pi->sram_end);
3673 if (ret)
3674 return ret;
3675
3676 return 0;
3677 }
3678
3679 static void ci_trim_single_dpm_states(struct radeon_device *rdev,
3680 struct ci_single_dpm_table *dpm_table,
3681 u32 low_limit, u32 high_limit)
3682 {
3683 u32 i;
3684
3685 for (i = 0; i < dpm_table->count; i++) {
3686 if ((dpm_table->dpm_levels[i].value < low_limit) ||
3687 (dpm_table->dpm_levels[i].value > high_limit))
3688 dpm_table->dpm_levels[i].enabled = false;
3689 else
3690 dpm_table->dpm_levels[i].enabled = true;
3691 }
3692 }
3693
3694 static void ci_trim_pcie_dpm_states(struct radeon_device *rdev,
3695 u32 speed_low, u32 lanes_low,
3696 u32 speed_high, u32 lanes_high)
3697 {
3698 struct ci_power_info *pi = ci_get_pi(rdev);
3699 struct ci_single_dpm_table *pcie_table = &pi->dpm_table.pcie_speed_table;
3700 u32 i, j;
3701
3702 for (i = 0; i < pcie_table->count; i++) {
3703 if ((pcie_table->dpm_levels[i].value < speed_low) ||
3704 (pcie_table->dpm_levels[i].param1 < lanes_low) ||
3705 (pcie_table->dpm_levels[i].value > speed_high) ||
3706 (pcie_table->dpm_levels[i].param1 > lanes_high))
3707 pcie_table->dpm_levels[i].enabled = false;
3708 else
3709 pcie_table->dpm_levels[i].enabled = true;
3710 }
3711
3712 for (i = 0; i < pcie_table->count; i++) {
3713 if (pcie_table->dpm_levels[i].enabled) {
3714 for (j = i + 1; j < pcie_table->count; j++) {
3715 if (pcie_table->dpm_levels[j].enabled) {
3716 if ((pcie_table->dpm_levels[i].value == pcie_table->dpm_levels[j].value) &&
3717 (pcie_table->dpm_levels[i].param1 == pcie_table->dpm_levels[j].param1))
3718 pcie_table->dpm_levels[j].enabled = false;
3719 }
3720 }
3721 }
3722 }
3723 }
3724
3725 static int ci_trim_dpm_states(struct radeon_device *rdev,
3726 struct radeon_ps *radeon_state)
3727 {
3728 struct ci_ps *state = ci_get_ps(radeon_state);
3729 struct ci_power_info *pi = ci_get_pi(rdev);
3730 u32 high_limit_count;
3731
3732 if (state->performance_level_count < 1)
3733 return -EINVAL;
3734
3735 if (state->performance_level_count == 1)
3736 high_limit_count = 0;
3737 else
3738 high_limit_count = 1;
3739
3740 ci_trim_single_dpm_states(rdev,
3741 &pi->dpm_table.sclk_table,
3742 state->performance_levels[0].sclk,
3743 state->performance_levels[high_limit_count].sclk);
3744
3745 ci_trim_single_dpm_states(rdev,
3746 &pi->dpm_table.mclk_table,
3747 state->performance_levels[0].mclk,
3748 state->performance_levels[high_limit_count].mclk);
3749
3750 ci_trim_pcie_dpm_states(rdev,
3751 state->performance_levels[0].pcie_gen,
3752 state->performance_levels[0].pcie_lane,
3753 state->performance_levels[high_limit_count].pcie_gen,
3754 state->performance_levels[high_limit_count].pcie_lane);
3755
3756 return 0;
3757 }
3758
3759 static int ci_apply_disp_minimum_voltage_request(struct radeon_device *rdev)
3760 {
3761 struct radeon_clock_voltage_dependency_table *disp_voltage_table =
3762 &rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk;
3763 struct radeon_clock_voltage_dependency_table *vddc_table =
3764 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
3765 u32 requested_voltage = 0;
3766 u32 i;
3767
3768 if (disp_voltage_table == NULL)
3769 return -EINVAL;
3770 if (!disp_voltage_table->count)
3771 return -EINVAL;
3772
3773 for (i = 0; i < disp_voltage_table->count; i++) {
3774 if (rdev->clock.current_dispclk == disp_voltage_table->entries[i].clk)
3775 requested_voltage = disp_voltage_table->entries[i].v;
3776 }
3777
3778 for (i = 0; i < vddc_table->count; i++) {
3779 if (requested_voltage <= vddc_table->entries[i].v) {
3780 requested_voltage = vddc_table->entries[i].v;
3781 return (ci_send_msg_to_smc_with_parameter(rdev,
3782 PPSMC_MSG_VddC_Request,
3783 requested_voltage * VOLTAGE_SCALE) == PPSMC_Result_OK) ?
3784 0 : -EINVAL;
3785 }
3786 }
3787
3788 return -EINVAL;
3789 }
3790
3791 static int ci_upload_dpm_level_enable_mask(struct radeon_device *rdev)
3792 {
3793 struct ci_power_info *pi = ci_get_pi(rdev);
3794 PPSMC_Result result;
3795
3796 ci_apply_disp_minimum_voltage_request(rdev);
3797
3798 if (!pi->sclk_dpm_key_disabled) {
3799 if (pi->dpm_level_enable_mask.sclk_dpm_enable_mask) {
3800 result = ci_send_msg_to_smc_with_parameter(rdev,
3801 PPSMC_MSG_SCLKDPM_SetEnabledMask,
3802 pi->dpm_level_enable_mask.sclk_dpm_enable_mask);
3803 if (result != PPSMC_Result_OK)
3804 return -EINVAL;
3805 }
3806 }
3807
3808 if (!pi->mclk_dpm_key_disabled) {
3809 if (pi->dpm_level_enable_mask.mclk_dpm_enable_mask) {
3810 result = ci_send_msg_to_smc_with_parameter(rdev,
3811 PPSMC_MSG_MCLKDPM_SetEnabledMask,
3812 pi->dpm_level_enable_mask.mclk_dpm_enable_mask);
3813 if (result != PPSMC_Result_OK)
3814 return -EINVAL;
3815 }
3816 }
3817 #if 0
3818 if (!pi->pcie_dpm_key_disabled) {
3819 if (pi->dpm_level_enable_mask.pcie_dpm_enable_mask) {
3820 result = ci_send_msg_to_smc_with_parameter(rdev,
3821 PPSMC_MSG_PCIeDPM_SetEnabledMask,
3822 pi->dpm_level_enable_mask.pcie_dpm_enable_mask);
3823 if (result != PPSMC_Result_OK)
3824 return -EINVAL;
3825 }
3826 }
3827 #endif
3828 return 0;
3829 }
3830
3831 static void ci_find_dpm_states_clocks_in_dpm_table(struct radeon_device *rdev,
3832 struct radeon_ps *radeon_state)
3833 {
3834 struct ci_power_info *pi = ci_get_pi(rdev);
3835 struct ci_ps *state = ci_get_ps(radeon_state);
3836 struct ci_single_dpm_table *sclk_table = &pi->dpm_table.sclk_table;
3837 u32 sclk = state->performance_levels[state->performance_level_count-1].sclk;
3838 struct ci_single_dpm_table *mclk_table = &pi->dpm_table.mclk_table;
3839 u32 mclk = state->performance_levels[state->performance_level_count-1].mclk;
3840 u32 i;
3841
3842 pi->need_update_smu7_dpm_table = 0;
3843
3844 for (i = 0; i < sclk_table->count; i++) {
3845 if (sclk == sclk_table->dpm_levels[i].value)
3846 break;
3847 }
3848
3849 if (i >= sclk_table->count) {
3850 pi->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_SCLK;
3851 } else {
3852 /* XXX The current code always reprogrammed the sclk levels,
3853 * but we don't currently handle disp sclk requirements
3854 * so just skip it.
3855 */
3856 if (CISLAND_MINIMUM_ENGINE_CLOCK != CISLAND_MINIMUM_ENGINE_CLOCK)
3857 pi->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_SCLK;
3858 }
3859
3860 for (i = 0; i < mclk_table->count; i++) {
3861 if (mclk == mclk_table->dpm_levels[i].value)
3862 break;
3863 }
3864
3865 if (i >= mclk_table->count)
3866 pi->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_MCLK;
3867
3868 if (rdev->pm.dpm.current_active_crtc_count !=
3869 rdev->pm.dpm.new_active_crtc_count)
3870 pi->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_MCLK;
3871 }
3872
3873 static int ci_populate_and_upload_sclk_mclk_dpm_levels(struct radeon_device *rdev,
3874 struct radeon_ps *radeon_state)
3875 {
3876 struct ci_power_info *pi = ci_get_pi(rdev);
3877 struct ci_ps *state = ci_get_ps(radeon_state);
3878 u32 sclk = state->performance_levels[state->performance_level_count-1].sclk;
3879 u32 mclk = state->performance_levels[state->performance_level_count-1].mclk;
3880 struct ci_dpm_table *dpm_table = &pi->dpm_table;
3881 int ret;
3882
3883 if (!pi->need_update_smu7_dpm_table)
3884 return 0;
3885
3886 if (pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_SCLK)
3887 dpm_table->sclk_table.dpm_levels[dpm_table->sclk_table.count-1].value = sclk;
3888
3889 if (pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)
3890 dpm_table->mclk_table.dpm_levels[dpm_table->mclk_table.count-1].value = mclk;
3891
3892 if (pi->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_UPDATE_SCLK)) {
3893 ret = ci_populate_all_graphic_levels(rdev);
3894 if (ret)
3895 return ret;
3896 }
3897
3898 if (pi->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_MCLK | DPMTABLE_UPDATE_MCLK)) {
3899 ret = ci_populate_all_memory_levels(rdev);
3900 if (ret)
3901 return ret;
3902 }
3903
3904 return 0;
3905 }
3906
3907 static int ci_enable_uvd_dpm(struct radeon_device *rdev, bool enable)
3908 {
3909 struct ci_power_info *pi = ci_get_pi(rdev);
3910 const struct radeon_clock_and_voltage_limits *max_limits;
3911 int i;
3912
3913 if (rdev->pm.dpm.ac_power)
3914 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
3915 else
3916 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
3917
3918 if (enable) {
3919 pi->dpm_level_enable_mask.uvd_dpm_enable_mask = 0;
3920
3921 for (i = rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.count - 1; i >= 0; i--) {
3922 if (rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[i].v <= max_limits->vddc) {
3923 pi->dpm_level_enable_mask.uvd_dpm_enable_mask |= 1 << i;
3924
3925 if (!pi->caps_uvd_dpm)
3926 break;
3927 }
3928 }
3929
3930 ci_send_msg_to_smc_with_parameter(rdev,
3931 PPSMC_MSG_UVDDPM_SetEnabledMask,
3932 pi->dpm_level_enable_mask.uvd_dpm_enable_mask);
3933
3934 if (pi->last_mclk_dpm_enable_mask & 0x1) {
3935 pi->uvd_enabled = true;
3936 pi->dpm_level_enable_mask.mclk_dpm_enable_mask &= 0xFFFFFFFE;
3937 ci_send_msg_to_smc_with_parameter(rdev,
3938 PPSMC_MSG_MCLKDPM_SetEnabledMask,
3939 pi->dpm_level_enable_mask.mclk_dpm_enable_mask);
3940 }
3941 } else {
3942 if (pi->last_mclk_dpm_enable_mask & 0x1) {
3943 pi->uvd_enabled = false;
3944 pi->dpm_level_enable_mask.mclk_dpm_enable_mask |= 1;
3945 ci_send_msg_to_smc_with_parameter(rdev,
3946 PPSMC_MSG_MCLKDPM_SetEnabledMask,
3947 pi->dpm_level_enable_mask.mclk_dpm_enable_mask);
3948 }
3949 }
3950
3951 return (ci_send_msg_to_smc(rdev, enable ?
3952 PPSMC_MSG_UVDDPM_Enable : PPSMC_MSG_UVDDPM_Disable) == PPSMC_Result_OK) ?
3953 0 : -EINVAL;
3954 }
3955
3956 static int ci_enable_vce_dpm(struct radeon_device *rdev, bool enable)
3957 {
3958 struct ci_power_info *pi = ci_get_pi(rdev);
3959 const struct radeon_clock_and_voltage_limits *max_limits;
3960 int i;
3961
3962 if (rdev->pm.dpm.ac_power)
3963 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
3964 else
3965 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
3966
3967 if (enable) {
3968 pi->dpm_level_enable_mask.vce_dpm_enable_mask = 0;
3969 for (i = rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.count - 1; i >= 0; i--) {
3970 if (rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries[i].v <= max_limits->vddc) {
3971 pi->dpm_level_enable_mask.vce_dpm_enable_mask |= 1 << i;
3972
3973 if (!pi->caps_vce_dpm)
3974 break;
3975 }
3976 }
3977
3978 ci_send_msg_to_smc_with_parameter(rdev,
3979 PPSMC_MSG_VCEDPM_SetEnabledMask,
3980 pi->dpm_level_enable_mask.vce_dpm_enable_mask);
3981 }
3982
3983 return (ci_send_msg_to_smc(rdev, enable ?
3984 PPSMC_MSG_VCEDPM_Enable : PPSMC_MSG_VCEDPM_Disable) == PPSMC_Result_OK) ?
3985 0 : -EINVAL;
3986 }
3987
3988 #if 0
3989 static int ci_enable_samu_dpm(struct radeon_device *rdev, bool enable)
3990 {
3991 struct ci_power_info *pi = ci_get_pi(rdev);
3992 const struct radeon_clock_and_voltage_limits *max_limits;
3993 int i;
3994
3995 if (rdev->pm.dpm.ac_power)
3996 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
3997 else
3998 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
3999
4000 if (enable) {
4001 pi->dpm_level_enable_mask.samu_dpm_enable_mask = 0;
4002 for (i = rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.count - 1; i >= 0; i--) {
4003 if (rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.entries[i].v <= max_limits->vddc) {
4004 pi->dpm_level_enable_mask.samu_dpm_enable_mask |= 1 << i;
4005
4006 if (!pi->caps_samu_dpm)
4007 break;
4008 }
4009 }
4010
4011 ci_send_msg_to_smc_with_parameter(rdev,
4012 PPSMC_MSG_SAMUDPM_SetEnabledMask,
4013 pi->dpm_level_enable_mask.samu_dpm_enable_mask);
4014 }
4015 return (ci_send_msg_to_smc(rdev, enable ?
4016 PPSMC_MSG_SAMUDPM_Enable : PPSMC_MSG_SAMUDPM_Disable) == PPSMC_Result_OK) ?
4017 0 : -EINVAL;
4018 }
4019
4020 static int ci_enable_acp_dpm(struct radeon_device *rdev, bool enable)
4021 {
4022 struct ci_power_info *pi = ci_get_pi(rdev);
4023 const struct radeon_clock_and_voltage_limits *max_limits;
4024 int i;
4025
4026 if (rdev->pm.dpm.ac_power)
4027 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
4028 else
4029 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
4030
4031 if (enable) {
4032 pi->dpm_level_enable_mask.acp_dpm_enable_mask = 0;
4033 for (i = rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.count - 1; i >= 0; i--) {
4034 if (rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.entries[i].v <= max_limits->vddc) {
4035 pi->dpm_level_enable_mask.acp_dpm_enable_mask |= 1 << i;
4036
4037 if (!pi->caps_acp_dpm)
4038 break;
4039 }
4040 }
4041
4042 ci_send_msg_to_smc_with_parameter(rdev,
4043 PPSMC_MSG_ACPDPM_SetEnabledMask,
4044 pi->dpm_level_enable_mask.acp_dpm_enable_mask);
4045 }
4046
4047 return (ci_send_msg_to_smc(rdev, enable ?
4048 PPSMC_MSG_ACPDPM_Enable : PPSMC_MSG_ACPDPM_Disable) == PPSMC_Result_OK) ?
4049 0 : -EINVAL;
4050 }
4051 #endif
4052
4053 static int ci_update_uvd_dpm(struct radeon_device *rdev, bool gate)
4054 {
4055 struct ci_power_info *pi = ci_get_pi(rdev);
4056 u32 tmp;
4057
4058 if (!gate) {
4059 if (pi->caps_uvd_dpm ||
4060 (rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.count <= 0))
4061 pi->smc_state_table.UvdBootLevel = 0;
4062 else
4063 pi->smc_state_table.UvdBootLevel =
4064 rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.count - 1;
4065
4066 tmp = RREG32_SMC(DPM_TABLE_475);
4067 tmp &= ~UvdBootLevel_MASK;
4068 tmp |= UvdBootLevel(pi->smc_state_table.UvdBootLevel);
4069 WREG32_SMC(DPM_TABLE_475, tmp);
4070 }
4071
4072 return ci_enable_uvd_dpm(rdev, !gate);
4073 }
4074
4075 static u8 ci_get_vce_boot_level(struct radeon_device *rdev)
4076 {
4077 u8 i;
4078 u32 min_evclk = 30000; /* ??? */
4079 struct radeon_vce_clock_voltage_dependency_table *table =
4080 &rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table;
4081
4082 for (i = 0; i < table->count; i++) {
4083 if (table->entries[i].evclk >= min_evclk)
4084 return i;
4085 }
4086
4087 return table->count - 1;
4088 }
4089
4090 static int ci_update_vce_dpm(struct radeon_device *rdev,
4091 struct radeon_ps *radeon_new_state,
4092 struct radeon_ps *radeon_current_state)
4093 {
4094 struct ci_power_info *pi = ci_get_pi(rdev);
4095 int ret = 0;
4096 u32 tmp;
4097
4098 if (radeon_current_state->evclk != radeon_new_state->evclk) {
4099 if (radeon_new_state->evclk) {
4100 /* turn the clocks on when encoding */
4101 cik_update_cg(rdev, RADEON_CG_BLOCK_VCE, false);
4102
4103 pi->smc_state_table.VceBootLevel = ci_get_vce_boot_level(rdev);
4104 tmp = RREG32_SMC(DPM_TABLE_475);
4105 tmp &= ~VceBootLevel_MASK;
4106 tmp |= VceBootLevel(pi->smc_state_table.VceBootLevel);
4107 WREG32_SMC(DPM_TABLE_475, tmp);
4108
4109 ret = ci_enable_vce_dpm(rdev, true);
4110 } else {
4111 /* turn the clocks off when not encoding */
4112 cik_update_cg(rdev, RADEON_CG_BLOCK_VCE, true);
4113
4114 ret = ci_enable_vce_dpm(rdev, false);
4115 }
4116 }
4117 return ret;
4118 }
4119
4120 #if 0
4121 static int ci_update_samu_dpm(struct radeon_device *rdev, bool gate)
4122 {
4123 return ci_enable_samu_dpm(rdev, gate);
4124 }
4125
4126 static int ci_update_acp_dpm(struct radeon_device *rdev, bool gate)
4127 {
4128 struct ci_power_info *pi = ci_get_pi(rdev);
4129 u32 tmp;
4130
4131 if (!gate) {
4132 pi->smc_state_table.AcpBootLevel = 0;
4133
4134 tmp = RREG32_SMC(DPM_TABLE_475);
4135 tmp &= ~AcpBootLevel_MASK;
4136 tmp |= AcpBootLevel(pi->smc_state_table.AcpBootLevel);
4137 WREG32_SMC(DPM_TABLE_475, tmp);
4138 }
4139
4140 return ci_enable_acp_dpm(rdev, !gate);
4141 }
4142 #endif
4143
4144 static int ci_generate_dpm_level_enable_mask(struct radeon_device *rdev,
4145 struct radeon_ps *radeon_state)
4146 {
4147 struct ci_power_info *pi = ci_get_pi(rdev);
4148 int ret;
4149
4150 ret = ci_trim_dpm_states(rdev, radeon_state);
4151 if (ret)
4152 return ret;
4153
4154 pi->dpm_level_enable_mask.sclk_dpm_enable_mask =
4155 ci_get_dpm_level_enable_mask_value(&pi->dpm_table.sclk_table);
4156 pi->dpm_level_enable_mask.mclk_dpm_enable_mask =
4157 ci_get_dpm_level_enable_mask_value(&pi->dpm_table.mclk_table);
4158 pi->last_mclk_dpm_enable_mask =
4159 pi->dpm_level_enable_mask.mclk_dpm_enable_mask;
4160 if (pi->uvd_enabled) {
4161 if (pi->dpm_level_enable_mask.mclk_dpm_enable_mask & 1)
4162 pi->dpm_level_enable_mask.mclk_dpm_enable_mask &= 0xFFFFFFFE;
4163 }
4164 pi->dpm_level_enable_mask.pcie_dpm_enable_mask =
4165 ci_get_dpm_level_enable_mask_value(&pi->dpm_table.pcie_speed_table);
4166
4167 return 0;
4168 }
4169
4170 static u32 ci_get_lowest_enabled_level(struct radeon_device *rdev,
4171 u32 level_mask)
4172 {
4173 u32 level = 0;
4174
4175 while ((level_mask & (1 << level)) == 0)
4176 level++;
4177
4178 return level;
4179 }
4180
4181
4182 int ci_dpm_force_performance_level(struct radeon_device *rdev,
4183 enum radeon_dpm_forced_level level)
4184 {
4185 struct ci_power_info *pi = ci_get_pi(rdev);
4186 u32 tmp, levels, i;
4187 int ret;
4188
4189 if (level == RADEON_DPM_FORCED_LEVEL_HIGH) {
4190 if ((!pi->pcie_dpm_key_disabled) &&
4191 pi->dpm_level_enable_mask.pcie_dpm_enable_mask) {
4192 levels = 0;
4193 tmp = pi->dpm_level_enable_mask.pcie_dpm_enable_mask;
4194 while (tmp >>= 1)
4195 levels++;
4196 if (levels) {
4197 ret = ci_dpm_force_state_pcie(rdev, level);
4198 if (ret)
4199 return ret;
4200 for (i = 0; i < rdev->usec_timeout; i++) {
4201 tmp = (RREG32_SMC(TARGET_AND_CURRENT_PROFILE_INDEX_1) &
4202 CURR_PCIE_INDEX_MASK) >> CURR_PCIE_INDEX_SHIFT;
4203 if (tmp == levels)
4204 break;
4205 udelay(1);
4206 }
4207 }
4208 }
4209 if ((!pi->sclk_dpm_key_disabled) &&
4210 pi->dpm_level_enable_mask.sclk_dpm_enable_mask) {
4211 levels = 0;
4212 tmp = pi->dpm_level_enable_mask.sclk_dpm_enable_mask;
4213 while (tmp >>= 1)
4214 levels++;
4215 if (levels) {
4216 ret = ci_dpm_force_state_sclk(rdev, levels);
4217 if (ret)
4218 return ret;
4219 for (i = 0; i < rdev->usec_timeout; i++) {
4220 tmp = (RREG32_SMC(TARGET_AND_CURRENT_PROFILE_INDEX) &
4221 CURR_SCLK_INDEX_MASK) >> CURR_SCLK_INDEX_SHIFT;
4222 if (tmp == levels)
4223 break;
4224 udelay(1);
4225 }
4226 }
4227 }
4228 if ((!pi->mclk_dpm_key_disabled) &&
4229 pi->dpm_level_enable_mask.mclk_dpm_enable_mask) {
4230 levels = 0;
4231 tmp = pi->dpm_level_enable_mask.mclk_dpm_enable_mask;
4232 while (tmp >>= 1)
4233 levels++;
4234 if (levels) {
4235 ret = ci_dpm_force_state_mclk(rdev, levels);
4236 if (ret)
4237 return ret;
4238 for (i = 0; i < rdev->usec_timeout; i++) {
4239 tmp = (RREG32_SMC(TARGET_AND_CURRENT_PROFILE_INDEX) &
4240 CURR_MCLK_INDEX_MASK) >> CURR_MCLK_INDEX_SHIFT;
4241 if (tmp == levels)
4242 break;
4243 udelay(1);
4244 }
4245 }
4246 }
4247 } else if (level == RADEON_DPM_FORCED_LEVEL_LOW) {
4248 if ((!pi->sclk_dpm_key_disabled) &&
4249 pi->dpm_level_enable_mask.sclk_dpm_enable_mask) {
4250 levels = ci_get_lowest_enabled_level(rdev,
4251 pi->dpm_level_enable_mask.sclk_dpm_enable_mask);
4252 ret = ci_dpm_force_state_sclk(rdev, levels);
4253 if (ret)
4254 return ret;
4255 for (i = 0; i < rdev->usec_timeout; i++) {
4256 tmp = (RREG32_SMC(TARGET_AND_CURRENT_PROFILE_INDEX) &
4257 CURR_SCLK_INDEX_MASK) >> CURR_SCLK_INDEX_SHIFT;
4258 if (tmp == levels)
4259 break;
4260 udelay(1);
4261 }
4262 }
4263 if ((!pi->mclk_dpm_key_disabled) &&
4264 pi->dpm_level_enable_mask.mclk_dpm_enable_mask) {
4265 levels = ci_get_lowest_enabled_level(rdev,
4266 pi->dpm_level_enable_mask.mclk_dpm_enable_mask);
4267 ret = ci_dpm_force_state_mclk(rdev, levels);
4268 if (ret)
4269 return ret;
4270 for (i = 0; i < rdev->usec_timeout; i++) {
4271 tmp = (RREG32_SMC(TARGET_AND_CURRENT_PROFILE_INDEX) &
4272 CURR_MCLK_INDEX_MASK) >> CURR_MCLK_INDEX_SHIFT;
4273 if (tmp == levels)
4274 break;
4275 udelay(1);
4276 }
4277 }
4278 if ((!pi->pcie_dpm_key_disabled) &&
4279 pi->dpm_level_enable_mask.pcie_dpm_enable_mask) {
4280 levels = ci_get_lowest_enabled_level(rdev,
4281 pi->dpm_level_enable_mask.pcie_dpm_enable_mask);
4282 ret = ci_dpm_force_state_pcie(rdev, levels);
4283 if (ret)
4284 return ret;
4285 for (i = 0; i < rdev->usec_timeout; i++) {
4286 tmp = (RREG32_SMC(TARGET_AND_CURRENT_PROFILE_INDEX_1) &
4287 CURR_PCIE_INDEX_MASK) >> CURR_PCIE_INDEX_SHIFT;
4288 if (tmp == levels)
4289 break;
4290 udelay(1);
4291 }
4292 }
4293 } else if (level == RADEON_DPM_FORCED_LEVEL_AUTO) {
4294 if (!pi->pcie_dpm_key_disabled) {
4295 PPSMC_Result smc_result;
4296
4297 smc_result = ci_send_msg_to_smc(rdev,
4298 PPSMC_MSG_PCIeDPM_UnForceLevel);
4299 if (smc_result != PPSMC_Result_OK)
4300 return -EINVAL;
4301 }
4302 ret = ci_upload_dpm_level_enable_mask(rdev);
4303 if (ret)
4304 return ret;
4305 }
4306
4307 rdev->pm.dpm.forced_level = level;
4308
4309 return 0;
4310 }
4311
4312 static int ci_set_mc_special_registers(struct radeon_device *rdev,
4313 struct ci_mc_reg_table *table)
4314 {
4315 struct ci_power_info *pi = ci_get_pi(rdev);
4316 u8 i, j, k;
4317 u32 temp_reg;
4318
4319 for (i = 0, j = table->last; i < table->last; i++) {
4320 if (j >= SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)
4321 return -EINVAL;
4322 switch(table->mc_reg_address[i].s1 << 2) {
4323 case MC_SEQ_MISC1:
4324 temp_reg = RREG32(MC_PMG_CMD_EMRS);
4325 table->mc_reg_address[j].s1 = MC_PMG_CMD_EMRS >> 2;
4326 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_EMRS_LP >> 2;
4327 for (k = 0; k < table->num_entries; k++) {
4328 table->mc_reg_table_entry[k].mc_data[j] =
4329 ((temp_reg & 0xffff0000)) | ((table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16);
4330 }
4331 j++;
4332 if (j >= SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)
4333 return -EINVAL;
4334
4335 temp_reg = RREG32(MC_PMG_CMD_MRS);
4336 table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS >> 2;
4337 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS_LP >> 2;
4338 for (k = 0; k < table->num_entries; k++) {
4339 table->mc_reg_table_entry[k].mc_data[j] =
4340 (temp_reg & 0xffff0000) | (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
4341 if (!pi->mem_gddr5)
4342 table->mc_reg_table_entry[k].mc_data[j] |= 0x100;
4343 }
4344 j++;
4345 if (j > SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)
4346 return -EINVAL;
4347
4348 if (!pi->mem_gddr5) {
4349 table->mc_reg_address[j].s1 = MC_PMG_AUTO_CMD >> 2;
4350 table->mc_reg_address[j].s0 = MC_PMG_AUTO_CMD >> 2;
4351 for (k = 0; k < table->num_entries; k++) {
4352 table->mc_reg_table_entry[k].mc_data[j] =
4353 (table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16;
4354 }
4355 j++;
4356 if (j > SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)
4357 return -EINVAL;
4358 }
4359 break;
4360 case MC_SEQ_RESERVE_M:
4361 temp_reg = RREG32(MC_PMG_CMD_MRS1);
4362 table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS1 >> 2;
4363 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS1_LP >> 2;
4364 for (k = 0; k < table->num_entries; k++) {
4365 table->mc_reg_table_entry[k].mc_data[j] =
4366 (temp_reg & 0xffff0000) | (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
4367 }
4368 j++;
4369 if (j > SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)
4370 return -EINVAL;
4371 break;
4372 default:
4373 break;
4374 }
4375
4376 }
4377
4378 table->last = j;
4379
4380 return 0;
4381 }
4382
4383 static bool ci_check_s0_mc_reg_index(u16 in_reg, u16 *out_reg)
4384 {
4385 bool result = true;
4386
4387 switch(in_reg) {
4388 case MC_SEQ_RAS_TIMING >> 2:
4389 *out_reg = MC_SEQ_RAS_TIMING_LP >> 2;
4390 break;
4391 case MC_SEQ_DLL_STBY >> 2:
4392 *out_reg = MC_SEQ_DLL_STBY_LP >> 2;
4393 break;
4394 case MC_SEQ_G5PDX_CMD0 >> 2:
4395 *out_reg = MC_SEQ_G5PDX_CMD0_LP >> 2;
4396 break;
4397 case MC_SEQ_G5PDX_CMD1 >> 2:
4398 *out_reg = MC_SEQ_G5PDX_CMD1_LP >> 2;
4399 break;
4400 case MC_SEQ_G5PDX_CTRL >> 2:
4401 *out_reg = MC_SEQ_G5PDX_CTRL_LP >> 2;
4402 break;
4403 case MC_SEQ_CAS_TIMING >> 2:
4404 *out_reg = MC_SEQ_CAS_TIMING_LP >> 2;
4405 break;
4406 case MC_SEQ_MISC_TIMING >> 2:
4407 *out_reg = MC_SEQ_MISC_TIMING_LP >> 2;
4408 break;
4409 case MC_SEQ_MISC_TIMING2 >> 2:
4410 *out_reg = MC_SEQ_MISC_TIMING2_LP >> 2;
4411 break;
4412 case MC_SEQ_PMG_DVS_CMD >> 2:
4413 *out_reg = MC_SEQ_PMG_DVS_CMD_LP >> 2;
4414 break;
4415 case MC_SEQ_PMG_DVS_CTL >> 2:
4416 *out_reg = MC_SEQ_PMG_DVS_CTL_LP >> 2;
4417 break;
4418 case MC_SEQ_RD_CTL_D0 >> 2:
4419 *out_reg = MC_SEQ_RD_CTL_D0_LP >> 2;
4420 break;
4421 case MC_SEQ_RD_CTL_D1 >> 2:
4422 *out_reg = MC_SEQ_RD_CTL_D1_LP >> 2;
4423 break;
4424 case MC_SEQ_WR_CTL_D0 >> 2:
4425 *out_reg = MC_SEQ_WR_CTL_D0_LP >> 2;
4426 break;
4427 case MC_SEQ_WR_CTL_D1 >> 2:
4428 *out_reg = MC_SEQ_WR_CTL_D1_LP >> 2;
4429 break;
4430 case MC_PMG_CMD_EMRS >> 2:
4431 *out_reg = MC_SEQ_PMG_CMD_EMRS_LP >> 2;
4432 break;
4433 case MC_PMG_CMD_MRS >> 2:
4434 *out_reg = MC_SEQ_PMG_CMD_MRS_LP >> 2;
4435 break;
4436 case MC_PMG_CMD_MRS1 >> 2:
4437 *out_reg = MC_SEQ_PMG_CMD_MRS1_LP >> 2;
4438 break;
4439 case MC_SEQ_PMG_TIMING >> 2:
4440 *out_reg = MC_SEQ_PMG_TIMING_LP >> 2;
4441 break;
4442 case MC_PMG_CMD_MRS2 >> 2:
4443 *out_reg = MC_SEQ_PMG_CMD_MRS2_LP >> 2;
4444 break;
4445 case MC_SEQ_WR_CTL_2 >> 2:
4446 *out_reg = MC_SEQ_WR_CTL_2_LP >> 2;
4447 break;
4448 default:
4449 result = false;
4450 break;
4451 }
4452
4453 return result;
4454 }
4455
4456 static void ci_set_valid_flag(struct ci_mc_reg_table *table)
4457 {
4458 u8 i, j;
4459
4460 for (i = 0; i < table->last; i++) {
4461 for (j = 1; j < table->num_entries; j++) {
4462 if (table->mc_reg_table_entry[j-1].mc_data[i] !=
4463 table->mc_reg_table_entry[j].mc_data[i]) {
4464 table->valid_flag |= 1 << i;
4465 break;
4466 }
4467 }
4468 }
4469 }
4470
4471 static void ci_set_s0_mc_reg_index(struct ci_mc_reg_table *table)
4472 {
4473 u32 i;
4474 u16 address;
4475
4476 for (i = 0; i < table->last; i++) {
4477 table->mc_reg_address[i].s0 =
4478 ci_check_s0_mc_reg_index(table->mc_reg_address[i].s1, &address) ?
4479 address : table->mc_reg_address[i].s1;
4480 }
4481 }
4482
4483 static int ci_copy_vbios_mc_reg_table(const struct atom_mc_reg_table *table,
4484 struct ci_mc_reg_table *ci_table)
4485 {
4486 u8 i, j;
4487
4488 if (table->last > SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)
4489 return -EINVAL;
4490 if (table->num_entries > MAX_AC_TIMING_ENTRIES)
4491 return -EINVAL;
4492
4493 for (i = 0; i < table->last; i++)
4494 ci_table->mc_reg_address[i].s1 = table->mc_reg_address[i].s1;
4495
4496 ci_table->last = table->last;
4497
4498 for (i = 0; i < table->num_entries; i++) {
4499 ci_table->mc_reg_table_entry[i].mclk_max =
4500 table->mc_reg_table_entry[i].mclk_max;
4501 for (j = 0; j < table->last; j++)
4502 ci_table->mc_reg_table_entry[i].mc_data[j] =
4503 table->mc_reg_table_entry[i].mc_data[j];
4504 }
4505 ci_table->num_entries = table->num_entries;
4506
4507 return 0;
4508 }
4509
4510 static int ci_register_patching_mc_seq(struct radeon_device *rdev,
4511 struct ci_mc_reg_table *table)
4512 {
4513 u8 i, k;
4514 u32 tmp;
4515 bool patch;
4516
4517 tmp = RREG32(MC_SEQ_MISC0);
4518 patch = ((tmp & 0x0000f00) == 0x300) ? true : false;
4519
4520 if (patch &&
4521 ((rdev->pdev->device == 0x67B0) ||
4522 (rdev->pdev->device == 0x67B1))) {
4523 for (i = 0; i < table->last; i++) {
4524 if (table->last >= SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)
4525 return -EINVAL;
4526 switch(table->mc_reg_address[i].s1 >> 2) {
4527 case MC_SEQ_MISC1:
4528 for (k = 0; k < table->num_entries; k++) {
4529 if ((table->mc_reg_table_entry[k].mclk_max == 125000) ||
4530 (table->mc_reg_table_entry[k].mclk_max == 137500))
4531 table->mc_reg_table_entry[k].mc_data[i] =
4532 (table->mc_reg_table_entry[k].mc_data[i] & 0xFFFFFFF8) |
4533 0x00000007;
4534 }
4535 break;
4536 case MC_SEQ_WR_CTL_D0:
4537 for (k = 0; k < table->num_entries; k++) {
4538 if ((table->mc_reg_table_entry[k].mclk_max == 125000) ||
4539 (table->mc_reg_table_entry[k].mclk_max == 137500))
4540 table->mc_reg_table_entry[k].mc_data[i] =
4541 (table->mc_reg_table_entry[k].mc_data[i] & 0xFFFF0F00) |
4542 0x0000D0DD;
4543 }
4544 break;
4545 case MC_SEQ_WR_CTL_D1:
4546 for (k = 0; k < table->num_entries; k++) {
4547 if ((table->mc_reg_table_entry[k].mclk_max == 125000) ||
4548 (table->mc_reg_table_entry[k].mclk_max == 137500))
4549 table->mc_reg_table_entry[k].mc_data[i] =
4550 (table->mc_reg_table_entry[k].mc_data[i] & 0xFFFF0F00) |
4551 0x0000D0DD;
4552 }
4553 break;
4554 case MC_SEQ_WR_CTL_2:
4555 for (k = 0; k < table->num_entries; k++) {
4556 if ((table->mc_reg_table_entry[k].mclk_max == 125000) ||
4557 (table->mc_reg_table_entry[k].mclk_max == 137500))
4558 table->mc_reg_table_entry[k].mc_data[i] = 0;
4559 }
4560 break;
4561 case MC_SEQ_CAS_TIMING:
4562 for (k = 0; k < table->num_entries; k++) {
4563 if (table->mc_reg_table_entry[k].mclk_max == 125000)
4564 table->mc_reg_table_entry[k].mc_data[i] =
4565 (table->mc_reg_table_entry[k].mc_data[i] & 0xFFE0FE0F) |
4566 0x000C0140;
4567 else if (table->mc_reg_table_entry[k].mclk_max == 137500)
4568 table->mc_reg_table_entry[k].mc_data[i] =
4569 (table->mc_reg_table_entry[k].mc_data[i] & 0xFFE0FE0F) |
4570 0x000C0150;
4571 }
4572 break;
4573 case MC_SEQ_MISC_TIMING:
4574 for (k = 0; k < table->num_entries; k++) {
4575 if (table->mc_reg_table_entry[k].mclk_max == 125000)
4576 table->mc_reg_table_entry[k].mc_data[i] =
4577 (table->mc_reg_table_entry[k].mc_data[i] & 0xFFFFFFE0) |
4578 0x00000030;
4579 else if (table->mc_reg_table_entry[k].mclk_max == 137500)
4580 table->mc_reg_table_entry[k].mc_data[i] =
4581 (table->mc_reg_table_entry[k].mc_data[i] & 0xFFFFFFE0) |
4582 0x00000035;
4583 }
4584 break;
4585 default:
4586 break;
4587 }
4588 }
4589
4590 WREG32(MC_SEQ_IO_DEBUG_INDEX, 3);
4591 tmp = RREG32(MC_SEQ_IO_DEBUG_DATA);
4592 tmp = (tmp & 0xFFF8FFFF) | (1 << 16);
4593 WREG32(MC_SEQ_IO_DEBUG_INDEX, 3);
4594 WREG32(MC_SEQ_IO_DEBUG_DATA, tmp);
4595 }
4596
4597 return 0;
4598 }
4599
4600 static int ci_initialize_mc_reg_table(struct radeon_device *rdev)
4601 {
4602 struct ci_power_info *pi = ci_get_pi(rdev);
4603 struct atom_mc_reg_table *table;
4604 struct ci_mc_reg_table *ci_table = &pi->mc_reg_table;
4605 u8 module_index = rv770_get_memory_module_index(rdev);
4606 int ret;
4607
4608 table = kzalloc(sizeof(struct atom_mc_reg_table), GFP_KERNEL);
4609 if (!table)
4610 return -ENOMEM;
4611
4612 WREG32(MC_SEQ_RAS_TIMING_LP, RREG32(MC_SEQ_RAS_TIMING));
4613 WREG32(MC_SEQ_CAS_TIMING_LP, RREG32(MC_SEQ_CAS_TIMING));
4614 WREG32(MC_SEQ_DLL_STBY_LP, RREG32(MC_SEQ_DLL_STBY));
4615 WREG32(MC_SEQ_G5PDX_CMD0_LP, RREG32(MC_SEQ_G5PDX_CMD0));
4616 WREG32(MC_SEQ_G5PDX_CMD1_LP, RREG32(MC_SEQ_G5PDX_CMD1));
4617 WREG32(MC_SEQ_G5PDX_CTRL_LP, RREG32(MC_SEQ_G5PDX_CTRL));
4618 WREG32(MC_SEQ_PMG_DVS_CMD_LP, RREG32(MC_SEQ_PMG_DVS_CMD));
4619 WREG32(MC_SEQ_PMG_DVS_CTL_LP, RREG32(MC_SEQ_PMG_DVS_CTL));
4620 WREG32(MC_SEQ_MISC_TIMING_LP, RREG32(MC_SEQ_MISC_TIMING));
4621 WREG32(MC_SEQ_MISC_TIMING2_LP, RREG32(MC_SEQ_MISC_TIMING2));
4622 WREG32(MC_SEQ_PMG_CMD_EMRS_LP, RREG32(MC_PMG_CMD_EMRS));
4623 WREG32(MC_SEQ_PMG_CMD_MRS_LP, RREG32(MC_PMG_CMD_MRS));
4624 WREG32(MC_SEQ_PMG_CMD_MRS1_LP, RREG32(MC_PMG_CMD_MRS1));
4625 WREG32(MC_SEQ_WR_CTL_D0_LP, RREG32(MC_SEQ_WR_CTL_D0));
4626 WREG32(MC_SEQ_WR_CTL_D1_LP, RREG32(MC_SEQ_WR_CTL_D1));
4627 WREG32(MC_SEQ_RD_CTL_D0_LP, RREG32(MC_SEQ_RD_CTL_D0));
4628 WREG32(MC_SEQ_RD_CTL_D1_LP, RREG32(MC_SEQ_RD_CTL_D1));
4629 WREG32(MC_SEQ_PMG_TIMING_LP, RREG32(MC_SEQ_PMG_TIMING));
4630 WREG32(MC_SEQ_PMG_CMD_MRS2_LP, RREG32(MC_PMG_CMD_MRS2));
4631 WREG32(MC_SEQ_WR_CTL_2_LP, RREG32(MC_SEQ_WR_CTL_2));
4632
4633 ret = radeon_atom_init_mc_reg_table(rdev, module_index, table);
4634 if (ret)
4635 goto init_mc_done;
4636
4637 ret = ci_copy_vbios_mc_reg_table(table, ci_table);
4638 if (ret)
4639 goto init_mc_done;
4640
4641 ci_set_s0_mc_reg_index(ci_table);
4642
4643 ret = ci_register_patching_mc_seq(rdev, ci_table);
4644 if (ret)
4645 goto init_mc_done;
4646
4647 ret = ci_set_mc_special_registers(rdev, ci_table);
4648 if (ret)
4649 goto init_mc_done;
4650
4651 ci_set_valid_flag(ci_table);
4652
4653 init_mc_done:
4654 kfree(table);
4655
4656 return ret;
4657 }
4658
4659 static int ci_populate_mc_reg_addresses(struct radeon_device *rdev,
4660 SMU7_Discrete_MCRegisters *mc_reg_table)
4661 {
4662 struct ci_power_info *pi = ci_get_pi(rdev);
4663 u32 i, j;
4664
4665 for (i = 0, j = 0; j < pi->mc_reg_table.last; j++) {
4666 if (pi->mc_reg_table.valid_flag & (1 << j)) {
4667 if (i >= SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)
4668 return -EINVAL;
4669 mc_reg_table->address[i].s0 = cpu_to_be16(pi->mc_reg_table.mc_reg_address[j].s0);
4670 mc_reg_table->address[i].s1 = cpu_to_be16(pi->mc_reg_table.mc_reg_address[j].s1);
4671 i++;
4672 }
4673 }
4674
4675 mc_reg_table->last = (u8)i;
4676
4677 return 0;
4678 }
4679
4680 static void ci_convert_mc_registers(const struct ci_mc_reg_entry *entry,
4681 SMU7_Discrete_MCRegisterSet *data,
4682 u32 num_entries, u32 valid_flag)
4683 {
4684 u32 i, j;
4685
4686 for (i = 0, j = 0; j < num_entries; j++) {
4687 if (valid_flag & (1 << j)) {
4688 data->value[i] = cpu_to_be32(entry->mc_data[j]);
4689 i++;
4690 }
4691 }
4692 }
4693
4694 static void ci_convert_mc_reg_table_entry_to_smc(struct radeon_device *rdev,
4695 const u32 memory_clock,
4696 SMU7_Discrete_MCRegisterSet *mc_reg_table_data)
4697 {
4698 struct ci_power_info *pi = ci_get_pi(rdev);
4699 u32 i = 0;
4700
4701 for(i = 0; i < pi->mc_reg_table.num_entries; i++) {
4702 if (memory_clock <= pi->mc_reg_table.mc_reg_table_entry[i].mclk_max)
4703 break;
4704 }
4705
4706 if ((i == pi->mc_reg_table.num_entries) && (i > 0))
4707 --i;
4708
4709 ci_convert_mc_registers(&pi->mc_reg_table.mc_reg_table_entry[i],
4710 mc_reg_table_data, pi->mc_reg_table.last,
4711 pi->mc_reg_table.valid_flag);
4712 }
4713
4714 static void ci_convert_mc_reg_table_to_smc(struct radeon_device *rdev,
4715 SMU7_Discrete_MCRegisters *mc_reg_table)
4716 {
4717 struct ci_power_info *pi = ci_get_pi(rdev);
4718 u32 i;
4719
4720 for (i = 0; i < pi->dpm_table.mclk_table.count; i++)
4721 ci_convert_mc_reg_table_entry_to_smc(rdev,
4722 pi->dpm_table.mclk_table.dpm_levels[i].value,
4723 &mc_reg_table->data[i]);
4724 }
4725
4726 static int ci_populate_initial_mc_reg_table(struct radeon_device *rdev)
4727 {
4728 struct ci_power_info *pi = ci_get_pi(rdev);
4729 int ret;
4730
4731 memset(&pi->smc_mc_reg_table, 0, sizeof(SMU7_Discrete_MCRegisters));
4732
4733 ret = ci_populate_mc_reg_addresses(rdev, &pi->smc_mc_reg_table);
4734 if (ret)
4735 return ret;
4736 ci_convert_mc_reg_table_to_smc(rdev, &pi->smc_mc_reg_table);
4737
4738 return ci_copy_bytes_to_smc(rdev,
4739 pi->mc_reg_table_start,
4740 (u8 *)&pi->smc_mc_reg_table,
4741 sizeof(SMU7_Discrete_MCRegisters),
4742 pi->sram_end);
4743 }
4744
4745 static int ci_update_and_upload_mc_reg_table(struct radeon_device *rdev)
4746 {
4747 struct ci_power_info *pi = ci_get_pi(rdev);
4748
4749 if (!(pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK))
4750 return 0;
4751
4752 memset(&pi->smc_mc_reg_table, 0, sizeof(SMU7_Discrete_MCRegisters));
4753
4754 ci_convert_mc_reg_table_to_smc(rdev, &pi->smc_mc_reg_table);
4755
4756 return ci_copy_bytes_to_smc(rdev,
4757 pi->mc_reg_table_start +
4758 offsetof(SMU7_Discrete_MCRegisters, data[0]),
4759 (u8 *)&pi->smc_mc_reg_table.data[0],
4760 sizeof(SMU7_Discrete_MCRegisterSet) *
4761 pi->dpm_table.mclk_table.count,
4762 pi->sram_end);
4763 }
4764
4765 static void ci_enable_voltage_control(struct radeon_device *rdev)
4766 {
4767 u32 tmp = RREG32_SMC(GENERAL_PWRMGT);
4768
4769 tmp |= VOLT_PWRMGT_EN;
4770 WREG32_SMC(GENERAL_PWRMGT, tmp);
4771 }
4772
4773 static enum radeon_pcie_gen ci_get_maximum_link_speed(struct radeon_device *rdev,
4774 struct radeon_ps *radeon_state)
4775 {
4776 struct ci_ps *state = ci_get_ps(radeon_state);
4777 int i;
4778 u16 pcie_speed, max_speed = 0;
4779
4780 for (i = 0; i < state->performance_level_count; i++) {
4781 pcie_speed = state->performance_levels[i].pcie_gen;
4782 if (max_speed < pcie_speed)
4783 max_speed = pcie_speed;
4784 }
4785
4786 return max_speed;
4787 }
4788
4789 static u16 ci_get_current_pcie_speed(struct radeon_device *rdev)
4790 {
4791 u32 speed_cntl = 0;
4792
4793 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL) & LC_CURRENT_DATA_RATE_MASK;
4794 speed_cntl >>= LC_CURRENT_DATA_RATE_SHIFT;
4795
4796 return (u16)speed_cntl;
4797 }
4798
4799 static int ci_get_current_pcie_lane_number(struct radeon_device *rdev)
4800 {
4801 u32 link_width = 0;
4802
4803 link_width = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL) & LC_LINK_WIDTH_RD_MASK;
4804 link_width >>= LC_LINK_WIDTH_RD_SHIFT;
4805
4806 switch (link_width) {
4807 case RADEON_PCIE_LC_LINK_WIDTH_X1:
4808 return 1;
4809 case RADEON_PCIE_LC_LINK_WIDTH_X2:
4810 return 2;
4811 case RADEON_PCIE_LC_LINK_WIDTH_X4:
4812 return 4;
4813 case RADEON_PCIE_LC_LINK_WIDTH_X8:
4814 return 8;
4815 case RADEON_PCIE_LC_LINK_WIDTH_X12:
4816 /* not actually supported */
4817 return 12;
4818 case RADEON_PCIE_LC_LINK_WIDTH_X0:
4819 case RADEON_PCIE_LC_LINK_WIDTH_X16:
4820 default:
4821 return 16;
4822 }
4823 }
4824
4825 static void ci_request_link_speed_change_before_state_change(struct radeon_device *rdev,
4826 struct radeon_ps *radeon_new_state,
4827 struct radeon_ps *radeon_current_state)
4828 {
4829 struct ci_power_info *pi = ci_get_pi(rdev);
4830 enum radeon_pcie_gen target_link_speed =
4831 ci_get_maximum_link_speed(rdev, radeon_new_state);
4832 enum radeon_pcie_gen current_link_speed;
4833
4834 if (pi->force_pcie_gen == RADEON_PCIE_GEN_INVALID)
4835 current_link_speed = ci_get_maximum_link_speed(rdev, radeon_current_state);
4836 else
4837 current_link_speed = pi->force_pcie_gen;
4838
4839 pi->force_pcie_gen = RADEON_PCIE_GEN_INVALID;
4840 pi->pspp_notify_required = false;
4841 if (target_link_speed > current_link_speed) {
4842 switch (target_link_speed) {
4843 #ifdef CONFIG_ACPI
4844 case RADEON_PCIE_GEN3:
4845 if (radeon_acpi_pcie_performance_request(rdev, PCIE_PERF_REQ_PECI_GEN3, false) == 0)
4846 break;
4847 pi->force_pcie_gen = RADEON_PCIE_GEN2;
4848 if (current_link_speed == RADEON_PCIE_GEN2)
4849 break;
4850 case RADEON_PCIE_GEN2:
4851 if (radeon_acpi_pcie_performance_request(rdev, PCIE_PERF_REQ_PECI_GEN2, false) == 0)
4852 break;
4853 #endif
4854 default:
4855 pi->force_pcie_gen = ci_get_current_pcie_speed(rdev);
4856 break;
4857 }
4858 } else {
4859 if (target_link_speed < current_link_speed)
4860 pi->pspp_notify_required = true;
4861 }
4862 }
4863
4864 static void ci_notify_link_speed_change_after_state_change(struct radeon_device *rdev,
4865 struct radeon_ps *radeon_new_state,
4866 struct radeon_ps *radeon_current_state)
4867 {
4868 struct ci_power_info *pi = ci_get_pi(rdev);
4869 enum radeon_pcie_gen target_link_speed =
4870 ci_get_maximum_link_speed(rdev, radeon_new_state);
4871 u8 request;
4872
4873 if (pi->pspp_notify_required) {
4874 if (target_link_speed == RADEON_PCIE_GEN3)
4875 request = PCIE_PERF_REQ_PECI_GEN3;
4876 else if (target_link_speed == RADEON_PCIE_GEN2)
4877 request = PCIE_PERF_REQ_PECI_GEN2;
4878 else
4879 request = PCIE_PERF_REQ_PECI_GEN1;
4880
4881 if ((request == PCIE_PERF_REQ_PECI_GEN1) &&
4882 (ci_get_current_pcie_speed(rdev) > 0))
4883 return;
4884
4885 #ifdef CONFIG_ACPI
4886 radeon_acpi_pcie_performance_request(rdev, request, false);
4887 #endif
4888 }
4889 }
4890
4891 static int ci_set_private_data_variables_based_on_pptable(struct radeon_device *rdev)
4892 {
4893 struct ci_power_info *pi = ci_get_pi(rdev);
4894 struct radeon_clock_voltage_dependency_table *allowed_sclk_vddc_table =
4895 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
4896 struct radeon_clock_voltage_dependency_table *allowed_mclk_vddc_table =
4897 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk;
4898 struct radeon_clock_voltage_dependency_table *allowed_mclk_vddci_table =
4899 &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk;
4900
4901 if (allowed_sclk_vddc_table == NULL)
4902 return -EINVAL;
4903 if (allowed_sclk_vddc_table->count < 1)
4904 return -EINVAL;
4905 if (allowed_mclk_vddc_table == NULL)
4906 return -EINVAL;
4907 if (allowed_mclk_vddc_table->count < 1)
4908 return -EINVAL;
4909 if (allowed_mclk_vddci_table == NULL)
4910 return -EINVAL;
4911 if (allowed_mclk_vddci_table->count < 1)
4912 return -EINVAL;
4913
4914 pi->min_vddc_in_pp_table = allowed_sclk_vddc_table->entries[0].v;
4915 pi->max_vddc_in_pp_table =
4916 allowed_sclk_vddc_table->entries[allowed_sclk_vddc_table->count - 1].v;
4917
4918 pi->min_vddci_in_pp_table = allowed_mclk_vddci_table->entries[0].v;
4919 pi->max_vddci_in_pp_table =
4920 allowed_mclk_vddci_table->entries[allowed_mclk_vddci_table->count - 1].v;
4921
4922 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk =
4923 allowed_sclk_vddc_table->entries[allowed_sclk_vddc_table->count - 1].clk;
4924 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.mclk =
4925 allowed_mclk_vddc_table->entries[allowed_sclk_vddc_table->count - 1].clk;
4926 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddc =
4927 allowed_sclk_vddc_table->entries[allowed_sclk_vddc_table->count - 1].v;
4928 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddci =
4929 allowed_mclk_vddci_table->entries[allowed_mclk_vddci_table->count - 1].v;
4930
4931 return 0;
4932 }
4933
4934 static void ci_patch_with_vddc_leakage(struct radeon_device *rdev, u16 *vddc)
4935 {
4936 struct ci_power_info *pi = ci_get_pi(rdev);
4937 struct ci_leakage_voltage *leakage_table = &pi->vddc_leakage;
4938 u32 leakage_index;
4939
4940 for (leakage_index = 0; leakage_index < leakage_table->count; leakage_index++) {
4941 if (leakage_table->leakage_id[leakage_index] == *vddc) {
4942 *vddc = leakage_table->actual_voltage[leakage_index];
4943 break;
4944 }
4945 }
4946 }
4947
4948 static void ci_patch_with_vddci_leakage(struct radeon_device *rdev, u16 *vddci)
4949 {
4950 struct ci_power_info *pi = ci_get_pi(rdev);
4951 struct ci_leakage_voltage *leakage_table = &pi->vddci_leakage;
4952 u32 leakage_index;
4953
4954 for (leakage_index = 0; leakage_index < leakage_table->count; leakage_index++) {
4955 if (leakage_table->leakage_id[leakage_index] == *vddci) {
4956 *vddci = leakage_table->actual_voltage[leakage_index];
4957 break;
4958 }
4959 }
4960 }
4961
4962 static void ci_patch_clock_voltage_dependency_table_with_vddc_leakage(struct radeon_device *rdev,
4963 struct radeon_clock_voltage_dependency_table *table)
4964 {
4965 u32 i;
4966
4967 if (table) {
4968 for (i = 0; i < table->count; i++)
4969 ci_patch_with_vddc_leakage(rdev, &table->entries[i].v);
4970 }
4971 }
4972
4973 static void ci_patch_clock_voltage_dependency_table_with_vddci_leakage(struct radeon_device *rdev,
4974 struct radeon_clock_voltage_dependency_table *table)
4975 {
4976 u32 i;
4977
4978 if (table) {
4979 for (i = 0; i < table->count; i++)
4980 ci_patch_with_vddci_leakage(rdev, &table->entries[i].v);
4981 }
4982 }
4983
4984 static void ci_patch_vce_clock_voltage_dependency_table_with_vddc_leakage(struct radeon_device *rdev,
4985 struct radeon_vce_clock_voltage_dependency_table *table)
4986 {
4987 u32 i;
4988
4989 if (table) {
4990 for (i = 0; i < table->count; i++)
4991 ci_patch_with_vddc_leakage(rdev, &table->entries[i].v);
4992 }
4993 }
4994
4995 static void ci_patch_uvd_clock_voltage_dependency_table_with_vddc_leakage(struct radeon_device *rdev,
4996 struct radeon_uvd_clock_voltage_dependency_table *table)
4997 {
4998 u32 i;
4999
5000 if (table) {
5001 for (i = 0; i < table->count; i++)
5002 ci_patch_with_vddc_leakage(rdev, &table->entries[i].v);
5003 }
5004 }
5005
5006 static void ci_patch_vddc_phase_shed_limit_table_with_vddc_leakage(struct radeon_device *rdev,
5007 struct radeon_phase_shedding_limits_table *table)
5008 {
5009 u32 i;
5010
5011 if (table) {
5012 for (i = 0; i < table->count; i++)
5013 ci_patch_with_vddc_leakage(rdev, &table->entries[i].voltage);
5014 }
5015 }
5016
5017 static void ci_patch_clock_voltage_limits_with_vddc_leakage(struct radeon_device *rdev,
5018 struct radeon_clock_and_voltage_limits *table)
5019 {
5020 if (table) {
5021 ci_patch_with_vddc_leakage(rdev, (u16 *)&table->vddc);
5022 ci_patch_with_vddci_leakage(rdev, (u16 *)&table->vddci);
5023 }
5024 }
5025
5026 static void ci_patch_cac_leakage_table_with_vddc_leakage(struct radeon_device *rdev,
5027 struct radeon_cac_leakage_table *table)
5028 {
5029 u32 i;
5030
5031 if (table) {
5032 for (i = 0; i < table->count; i++)
5033 ci_patch_with_vddc_leakage(rdev, &table->entries[i].vddc);
5034 }
5035 }
5036
5037 static void ci_patch_dependency_tables_with_leakage(struct radeon_device *rdev)
5038 {
5039
5040 ci_patch_clock_voltage_dependency_table_with_vddc_leakage(rdev,
5041 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk);
5042 ci_patch_clock_voltage_dependency_table_with_vddc_leakage(rdev,
5043 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk);
5044 ci_patch_clock_voltage_dependency_table_with_vddc_leakage(rdev,
5045 &rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk);
5046 ci_patch_clock_voltage_dependency_table_with_vddci_leakage(rdev,
5047 &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk);
5048 ci_patch_vce_clock_voltage_dependency_table_with_vddc_leakage(rdev,
5049 &rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table);
5050 ci_patch_uvd_clock_voltage_dependency_table_with_vddc_leakage(rdev,
5051 &rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table);
5052 ci_patch_clock_voltage_dependency_table_with_vddc_leakage(rdev,
5053 &rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table);
5054 ci_patch_clock_voltage_dependency_table_with_vddc_leakage(rdev,
5055 &rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table);
5056 ci_patch_vddc_phase_shed_limit_table_with_vddc_leakage(rdev,
5057 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table);
5058 ci_patch_clock_voltage_limits_with_vddc_leakage(rdev,
5059 &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac);
5060 ci_patch_clock_voltage_limits_with_vddc_leakage(rdev,
5061 &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc);
5062 ci_patch_cac_leakage_table_with_vddc_leakage(rdev,
5063 &rdev->pm.dpm.dyn_state.cac_leakage_table);
5064
5065 }
5066
5067 static void ci_get_memory_type(struct radeon_device *rdev)
5068 {
5069 struct ci_power_info *pi = ci_get_pi(rdev);
5070 u32 tmp;
5071
5072 tmp = RREG32(MC_SEQ_MISC0);
5073
5074 if (((tmp & MC_SEQ_MISC0_GDDR5_MASK) >> MC_SEQ_MISC0_GDDR5_SHIFT) ==
5075 MC_SEQ_MISC0_GDDR5_VALUE)
5076 pi->mem_gddr5 = true;
5077 else
5078 pi->mem_gddr5 = false;
5079
5080 }
5081
5082 static void ci_update_current_ps(struct radeon_device *rdev,
5083 struct radeon_ps *rps)
5084 {
5085 struct ci_ps *new_ps = ci_get_ps(rps);
5086 struct ci_power_info *pi = ci_get_pi(rdev);
5087
5088 pi->current_rps = *rps;
5089 pi->current_ps = *new_ps;
5090 pi->current_rps.ps_priv = &pi->current_ps;
5091 }
5092
5093 static void ci_update_requested_ps(struct radeon_device *rdev,
5094 struct radeon_ps *rps)
5095 {
5096 struct ci_ps *new_ps = ci_get_ps(rps);
5097 struct ci_power_info *pi = ci_get_pi(rdev);
5098
5099 pi->requested_rps = *rps;
5100 pi->requested_ps = *new_ps;
5101 pi->requested_rps.ps_priv = &pi->requested_ps;
5102 }
5103
5104 int ci_dpm_pre_set_power_state(struct radeon_device *rdev)
5105 {
5106 struct ci_power_info *pi = ci_get_pi(rdev);
5107 struct radeon_ps requested_ps = *rdev->pm.dpm.requested_ps;
5108 struct radeon_ps *new_ps = &requested_ps;
5109
5110 ci_update_requested_ps(rdev, new_ps);
5111
5112 ci_apply_state_adjust_rules(rdev, &pi->requested_rps);
5113
5114 return 0;
5115 }
5116
5117 void ci_dpm_post_set_power_state(struct radeon_device *rdev)
5118 {
5119 struct ci_power_info *pi = ci_get_pi(rdev);
5120 struct radeon_ps *new_ps = &pi->requested_rps;
5121
5122 ci_update_current_ps(rdev, new_ps);
5123 }
5124
5125
5126 void ci_dpm_setup_asic(struct radeon_device *rdev)
5127 {
5128 int r;
5129
5130 r = ci_mc_load_microcode(rdev);
5131 if (r)
5132 DRM_ERROR("Failed to load MC firmware!\n");
5133 ci_read_clock_registers(rdev);
5134 ci_get_memory_type(rdev);
5135 ci_enable_acpi_power_management(rdev);
5136 ci_init_sclk_t(rdev);
5137 }
5138
5139 int ci_dpm_enable(struct radeon_device *rdev)
5140 {
5141 struct ci_power_info *pi = ci_get_pi(rdev);
5142 struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps;
5143 int ret;
5144
5145 if (ci_is_smc_running(rdev))
5146 return -EINVAL;
5147 if (pi->voltage_control != CISLANDS_VOLTAGE_CONTROL_NONE) {
5148 ci_enable_voltage_control(rdev);
5149 ret = ci_construct_voltage_tables(rdev);
5150 if (ret) {
5151 DRM_ERROR("ci_construct_voltage_tables failed\n");
5152 return ret;
5153 }
5154 }
5155 if (pi->caps_dynamic_ac_timing) {
5156 ret = ci_initialize_mc_reg_table(rdev);
5157 if (ret)
5158 pi->caps_dynamic_ac_timing = false;
5159 }
5160 if (pi->dynamic_ss)
5161 ci_enable_spread_spectrum(rdev, true);
5162 if (pi->thermal_protection)
5163 ci_enable_thermal_protection(rdev, true);
5164 ci_program_sstp(rdev);
5165 ci_enable_display_gap(rdev);
5166 ci_program_vc(rdev);
5167 ret = ci_upload_firmware(rdev);
5168 if (ret) {
5169 DRM_ERROR("ci_upload_firmware failed\n");
5170 return ret;
5171 }
5172 ret = ci_process_firmware_header(rdev);
5173 if (ret) {
5174 DRM_ERROR("ci_process_firmware_header failed\n");
5175 return ret;
5176 }
5177 ret = ci_initial_switch_from_arb_f0_to_f1(rdev);
5178 if (ret) {
5179 DRM_ERROR("ci_initial_switch_from_arb_f0_to_f1 failed\n");
5180 return ret;
5181 }
5182 ret = ci_init_smc_table(rdev);
5183 if (ret) {
5184 DRM_ERROR("ci_init_smc_table failed\n");
5185 return ret;
5186 }
5187 ret = ci_init_arb_table_index(rdev);
5188 if (ret) {
5189 DRM_ERROR("ci_init_arb_table_index failed\n");
5190 return ret;
5191 }
5192 if (pi->caps_dynamic_ac_timing) {
5193 ret = ci_populate_initial_mc_reg_table(rdev);
5194 if (ret) {
5195 DRM_ERROR("ci_populate_initial_mc_reg_table failed\n");
5196 return ret;
5197 }
5198 }
5199 ret = ci_populate_pm_base(rdev);
5200 if (ret) {
5201 DRM_ERROR("ci_populate_pm_base failed\n");
5202 return ret;
5203 }
5204 ci_dpm_start_smc(rdev);
5205 ci_enable_vr_hot_gpio_interrupt(rdev);
5206 ret = ci_notify_smc_display_change(rdev, false);
5207 if (ret) {
5208 DRM_ERROR("ci_notify_smc_display_change failed\n");
5209 return ret;
5210 }
5211 ci_enable_sclk_control(rdev, true);
5212 ret = ci_enable_ulv(rdev, true);
5213 if (ret) {
5214 DRM_ERROR("ci_enable_ulv failed\n");
5215 return ret;
5216 }
5217 ret = ci_enable_ds_master_switch(rdev, true);
5218 if (ret) {
5219 DRM_ERROR("ci_enable_ds_master_switch failed\n");
5220 return ret;
5221 }
5222 ret = ci_start_dpm(rdev);
5223 if (ret) {
5224 DRM_ERROR("ci_start_dpm failed\n");
5225 return ret;
5226 }
5227 ret = ci_enable_didt(rdev, true);
5228 if (ret) {
5229 DRM_ERROR("ci_enable_didt failed\n");
5230 return ret;
5231 }
5232 ret = ci_enable_smc_cac(rdev, true);
5233 if (ret) {
5234 DRM_ERROR("ci_enable_smc_cac failed\n");
5235 return ret;
5236 }
5237 ret = ci_enable_power_containment(rdev, true);
5238 if (ret) {
5239 DRM_ERROR("ci_enable_power_containment failed\n");
5240 return ret;
5241 }
5242
5243 ret = ci_power_control_set_level(rdev);
5244 if (ret) {
5245 DRM_ERROR("ci_power_control_set_level failed\n");
5246 return ret;
5247 }
5248
5249 ci_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, true);
5250
5251 ret = ci_enable_thermal_based_sclk_dpm(rdev, true);
5252 if (ret) {
5253 DRM_ERROR("ci_enable_thermal_based_sclk_dpm failed\n");
5254 return ret;
5255 }
5256
5257 ci_thermal_start_thermal_controller(rdev);
5258
5259 ci_update_current_ps(rdev, boot_ps);
5260
5261 return 0;
5262 }
5263
5264 static int ci_set_temperature_range(struct radeon_device *rdev)
5265 {
5266 int ret;
5267
5268 ret = ci_thermal_enable_alert(rdev, false);
5269 if (ret)
5270 return ret;
5271 ret = ci_thermal_set_temperature_range(rdev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX);
5272 if (ret)
5273 return ret;
5274 ret = ci_thermal_enable_alert(rdev, true);
5275 if (ret)
5276 return ret;
5277
5278 return ret;
5279 }
5280
5281 int ci_dpm_late_enable(struct radeon_device *rdev)
5282 {
5283 int ret;
5284
5285 ret = ci_set_temperature_range(rdev);
5286 if (ret)
5287 return ret;
5288
5289 ci_dpm_powergate_uvd(rdev, true);
5290
5291 return 0;
5292 }
5293
5294 void ci_dpm_disable(struct radeon_device *rdev)
5295 {
5296 struct ci_power_info *pi = ci_get_pi(rdev);
5297 struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps;
5298
5299 ci_dpm_powergate_uvd(rdev, false);
5300
5301 if (!ci_is_smc_running(rdev))
5302 return;
5303
5304 ci_thermal_stop_thermal_controller(rdev);
5305
5306 if (pi->thermal_protection)
5307 ci_enable_thermal_protection(rdev, false);
5308 ci_enable_power_containment(rdev, false);
5309 ci_enable_smc_cac(rdev, false);
5310 ci_enable_didt(rdev, false);
5311 ci_enable_spread_spectrum(rdev, false);
5312 ci_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, false);
5313 ci_stop_dpm(rdev);
5314 ci_enable_ds_master_switch(rdev, false);
5315 ci_enable_ulv(rdev, false);
5316 ci_clear_vc(rdev);
5317 ci_reset_to_default(rdev);
5318 ci_dpm_stop_smc(rdev);
5319 ci_force_switch_to_arb_f0(rdev);
5320 ci_enable_thermal_based_sclk_dpm(rdev, false);
5321
5322 ci_update_current_ps(rdev, boot_ps);
5323 }
5324
5325 int ci_dpm_set_power_state(struct radeon_device *rdev)
5326 {
5327 struct ci_power_info *pi = ci_get_pi(rdev);
5328 struct radeon_ps *new_ps = &pi->requested_rps;
5329 struct radeon_ps *old_ps = &pi->current_rps;
5330 int ret;
5331
5332 ci_find_dpm_states_clocks_in_dpm_table(rdev, new_ps);
5333 if (pi->pcie_performance_request)
5334 ci_request_link_speed_change_before_state_change(rdev, new_ps, old_ps);
5335 ret = ci_freeze_sclk_mclk_dpm(rdev);
5336 if (ret) {
5337 DRM_ERROR("ci_freeze_sclk_mclk_dpm failed\n");
5338 return ret;
5339 }
5340 ret = ci_populate_and_upload_sclk_mclk_dpm_levels(rdev, new_ps);
5341 if (ret) {
5342 DRM_ERROR("ci_populate_and_upload_sclk_mclk_dpm_levels failed\n");
5343 return ret;
5344 }
5345 ret = ci_generate_dpm_level_enable_mask(rdev, new_ps);
5346 if (ret) {
5347 DRM_ERROR("ci_generate_dpm_level_enable_mask failed\n");
5348 return ret;
5349 }
5350
5351 ret = ci_update_vce_dpm(rdev, new_ps, old_ps);
5352 if (ret) {
5353 DRM_ERROR("ci_update_vce_dpm failed\n");
5354 return ret;
5355 }
5356
5357 ret = ci_update_sclk_t(rdev);
5358 if (ret) {
5359 DRM_ERROR("ci_update_sclk_t failed\n");
5360 return ret;
5361 }
5362 if (pi->caps_dynamic_ac_timing) {
5363 ret = ci_update_and_upload_mc_reg_table(rdev);
5364 if (ret) {
5365 DRM_ERROR("ci_update_and_upload_mc_reg_table failed\n");
5366 return ret;
5367 }
5368 }
5369 ret = ci_program_memory_timing_parameters(rdev);
5370 if (ret) {
5371 DRM_ERROR("ci_program_memory_timing_parameters failed\n");
5372 return ret;
5373 }
5374 ret = ci_unfreeze_sclk_mclk_dpm(rdev);
5375 if (ret) {
5376 DRM_ERROR("ci_unfreeze_sclk_mclk_dpm failed\n");
5377 return ret;
5378 }
5379 ret = ci_upload_dpm_level_enable_mask(rdev);
5380 if (ret) {
5381 DRM_ERROR("ci_upload_dpm_level_enable_mask failed\n");
5382 return ret;
5383 }
5384 if (pi->pcie_performance_request)
5385 ci_notify_link_speed_change_after_state_change(rdev, new_ps, old_ps);
5386
5387 return 0;
5388 }
5389
5390 #if 0
5391 void ci_dpm_reset_asic(struct radeon_device *rdev)
5392 {
5393 ci_set_boot_state(rdev);
5394 }
5395 #endif
5396
5397 void ci_dpm_display_configuration_changed(struct radeon_device *rdev)
5398 {
5399 ci_program_display_gap(rdev);
5400 }
5401
5402 union power_info {
5403 struct _ATOM_POWERPLAY_INFO info;
5404 struct _ATOM_POWERPLAY_INFO_V2 info_2;
5405 struct _ATOM_POWERPLAY_INFO_V3 info_3;
5406 struct _ATOM_PPLIB_POWERPLAYTABLE pplib;
5407 struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2;
5408 struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3;
5409 };
5410
5411 union pplib_clock_info {
5412 struct _ATOM_PPLIB_R600_CLOCK_INFO r600;
5413 struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780;
5414 struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen;
5415 struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo;
5416 struct _ATOM_PPLIB_SI_CLOCK_INFO si;
5417 struct _ATOM_PPLIB_CI_CLOCK_INFO ci;
5418 };
5419
5420 union pplib_power_state {
5421 struct _ATOM_PPLIB_STATE v1;
5422 struct _ATOM_PPLIB_STATE_V2 v2;
5423 };
5424
5425 static void ci_parse_pplib_non_clock_info(struct radeon_device *rdev,
5426 struct radeon_ps *rps,
5427 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info,
5428 u8 table_rev)
5429 {
5430 rps->caps = le32_to_cpu(non_clock_info->ulCapsAndSettings);
5431 rps->class = le16_to_cpu(non_clock_info->usClassification);
5432 rps->class2 = le16_to_cpu(non_clock_info->usClassification2);
5433
5434 if (ATOM_PPLIB_NONCLOCKINFO_VER1 < table_rev) {
5435 rps->vclk = le32_to_cpu(non_clock_info->ulVCLK);
5436 rps->dclk = le32_to_cpu(non_clock_info->ulDCLK);
5437 } else {
5438 rps->vclk = 0;
5439 rps->dclk = 0;
5440 }
5441
5442 if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT)
5443 rdev->pm.dpm.boot_ps = rps;
5444 if (rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE)
5445 rdev->pm.dpm.uvd_ps = rps;
5446 }
5447
5448 static void ci_parse_pplib_clock_info(struct radeon_device *rdev,
5449 struct radeon_ps *rps, int index,
5450 union pplib_clock_info *clock_info)
5451 {
5452 struct ci_power_info *pi = ci_get_pi(rdev);
5453 struct ci_ps *ps = ci_get_ps(rps);
5454 struct ci_pl *pl = &ps->performance_levels[index];
5455
5456 ps->performance_level_count = index + 1;
5457
5458 pl->sclk = le16_to_cpu(clock_info->ci.usEngineClockLow);
5459 pl->sclk |= clock_info->ci.ucEngineClockHigh << 16;
5460 pl->mclk = le16_to_cpu(clock_info->ci.usMemoryClockLow);
5461 pl->mclk |= clock_info->ci.ucMemoryClockHigh << 16;
5462
5463 pl->pcie_gen = r600_get_pcie_gen_support(rdev,
5464 pi->sys_pcie_mask,
5465 pi->vbios_boot_state.pcie_gen_bootup_value,
5466 clock_info->ci.ucPCIEGen);
5467 pl->pcie_lane = r600_get_pcie_lane_support(rdev,
5468 pi->vbios_boot_state.pcie_lane_bootup_value,
5469 le16_to_cpu(clock_info->ci.usPCIELane));
5470
5471 if (rps->class & ATOM_PPLIB_CLASSIFICATION_ACPI) {
5472 pi->acpi_pcie_gen = pl->pcie_gen;
5473 }
5474
5475 if (rps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV) {
5476 pi->ulv.supported = true;
5477 pi->ulv.pl = *pl;
5478 pi->ulv.cg_ulv_parameter = CISLANDS_CGULVPARAMETER_DFLT;
5479 }
5480
5481 /* patch up boot state */
5482 if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) {
5483 pl->mclk = pi->vbios_boot_state.mclk_bootup_value;
5484 pl->sclk = pi->vbios_boot_state.sclk_bootup_value;
5485 pl->pcie_gen = pi->vbios_boot_state.pcie_gen_bootup_value;
5486 pl->pcie_lane = pi->vbios_boot_state.pcie_lane_bootup_value;
5487 }
5488
5489 switch (rps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) {
5490 case ATOM_PPLIB_CLASSIFICATION_UI_BATTERY:
5491 pi->use_pcie_powersaving_levels = true;
5492 if (pi->pcie_gen_powersaving.max < pl->pcie_gen)
5493 pi->pcie_gen_powersaving.max = pl->pcie_gen;
5494 if (pi->pcie_gen_powersaving.min > pl->pcie_gen)
5495 pi->pcie_gen_powersaving.min = pl->pcie_gen;
5496 if (pi->pcie_lane_powersaving.max < pl->pcie_lane)
5497 pi->pcie_lane_powersaving.max = pl->pcie_lane;
5498 if (pi->pcie_lane_powersaving.min > pl->pcie_lane)
5499 pi->pcie_lane_powersaving.min = pl->pcie_lane;
5500 break;
5501 case ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE:
5502 pi->use_pcie_performance_levels = true;
5503 if (pi->pcie_gen_performance.max < pl->pcie_gen)
5504 pi->pcie_gen_performance.max = pl->pcie_gen;
5505 if (pi->pcie_gen_performance.min > pl->pcie_gen)
5506 pi->pcie_gen_performance.min = pl->pcie_gen;
5507 if (pi->pcie_lane_performance.max < pl->pcie_lane)
5508 pi->pcie_lane_performance.max = pl->pcie_lane;
5509 if (pi->pcie_lane_performance.min > pl->pcie_lane)
5510 pi->pcie_lane_performance.min = pl->pcie_lane;
5511 break;
5512 default:
5513 break;
5514 }
5515 }
5516
5517 static int ci_parse_power_table(struct radeon_device *rdev)
5518 {
5519 struct radeon_mode_info *mode_info = &rdev->mode_info;
5520 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
5521 union pplib_power_state *power_state;
5522 int i, j, k, non_clock_array_index, clock_array_index;
5523 union pplib_clock_info *clock_info;
5524 struct _StateArray *state_array;
5525 struct _ClockInfoArray *clock_info_array;
5526 struct _NonClockInfoArray *non_clock_info_array;
5527 union power_info *power_info;
5528 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
5529 u16 data_offset;
5530 u8 frev, crev;
5531 u8 *power_state_offset;
5532 struct ci_ps *ps;
5533
5534 if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
5535 &frev, &crev, &data_offset))
5536 return -EINVAL;
5537 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
5538
5539 state_array = (struct _StateArray *)
5540 (mode_info->atom_context->bios + data_offset +
5541 le16_to_cpu(power_info->pplib.usStateArrayOffset));
5542 clock_info_array = (struct _ClockInfoArray *)
5543 (mode_info->atom_context->bios + data_offset +
5544 le16_to_cpu(power_info->pplib.usClockInfoArrayOffset));
5545 non_clock_info_array = (struct _NonClockInfoArray *)
5546 (mode_info->atom_context->bios + data_offset +
5547 le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset));
5548
5549 rdev->pm.dpm.ps = kzalloc(sizeof(struct radeon_ps) *
5550 state_array->ucNumEntries, GFP_KERNEL);
5551 if (!rdev->pm.dpm.ps)
5552 return -ENOMEM;
5553 power_state_offset = (u8 *)state_array->states;
5554 for (i = 0; i < state_array->ucNumEntries; i++) {
5555 u8 *idx;
5556 power_state = (union pplib_power_state *)power_state_offset;
5557 non_clock_array_index = power_state->v2.nonClockInfoIndex;
5558 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
5559 &non_clock_info_array->nonClockInfo[non_clock_array_index];
5560 if (!rdev->pm.power_state[i].clock_info)
5561 return -EINVAL;
5562 ps = kzalloc(sizeof(struct ci_ps), GFP_KERNEL);
5563 if (ps == NULL) {
5564 kfree(rdev->pm.dpm.ps);
5565 return -ENOMEM;
5566 }
5567 rdev->pm.dpm.ps[i].ps_priv = ps;
5568 ci_parse_pplib_non_clock_info(rdev, &rdev->pm.dpm.ps[i],
5569 non_clock_info,
5570 non_clock_info_array->ucEntrySize);
5571 k = 0;
5572 idx = (u8 *)&power_state->v2.clockInfoIndex[0];
5573 for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) {
5574 clock_array_index = idx[j];
5575 if (clock_array_index >= clock_info_array->ucNumEntries)
5576 continue;
5577 if (k >= CISLANDS_MAX_HARDWARE_POWERLEVELS)
5578 break;
5579 clock_info = (union pplib_clock_info *)
5580 ((u8 *)&clock_info_array->clockInfo[0] +
5581 (clock_array_index * clock_info_array->ucEntrySize));
5582 ci_parse_pplib_clock_info(rdev,
5583 &rdev->pm.dpm.ps[i], k,
5584 clock_info);
5585 k++;
5586 }
5587 power_state_offset += 2 + power_state->v2.ucNumDPMLevels;
5588 }
5589 rdev->pm.dpm.num_ps = state_array->ucNumEntries;
5590
5591 /* fill in the vce power states */
5592 for (i = 0; i < RADEON_MAX_VCE_LEVELS; i++) {
5593 u32 sclk, mclk;
5594 clock_array_index = rdev->pm.dpm.vce_states[i].clk_idx;
5595 clock_info = (union pplib_clock_info *)
5596 &clock_info_array->clockInfo[clock_array_index * clock_info_array->ucEntrySize];
5597 sclk = le16_to_cpu(clock_info->ci.usEngineClockLow);
5598 sclk |= clock_info->ci.ucEngineClockHigh << 16;
5599 mclk = le16_to_cpu(clock_info->ci.usMemoryClockLow);
5600 mclk |= clock_info->ci.ucMemoryClockHigh << 16;
5601 rdev->pm.dpm.vce_states[i].sclk = sclk;
5602 rdev->pm.dpm.vce_states[i].mclk = mclk;
5603 }
5604
5605 return 0;
5606 }
5607
5608 static int ci_get_vbios_boot_values(struct radeon_device *rdev,
5609 struct ci_vbios_boot_state *boot_state)
5610 {
5611 struct radeon_mode_info *mode_info = &rdev->mode_info;
5612 int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
5613 ATOM_FIRMWARE_INFO_V2_2 *firmware_info;
5614 u8 frev, crev;
5615 u16 data_offset;
5616
5617 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
5618 &frev, &crev, &data_offset)) {
5619 firmware_info =
5620 (ATOM_FIRMWARE_INFO_V2_2 *)(mode_info->atom_context->bios +
5621 data_offset);
5622 boot_state->mvdd_bootup_value = le16_to_cpu(firmware_info->usBootUpMVDDCVoltage);
5623 boot_state->vddc_bootup_value = le16_to_cpu(firmware_info->usBootUpVDDCVoltage);
5624 boot_state->vddci_bootup_value = le16_to_cpu(firmware_info->usBootUpVDDCIVoltage);
5625 boot_state->pcie_gen_bootup_value = ci_get_current_pcie_speed(rdev);
5626 boot_state->pcie_lane_bootup_value = ci_get_current_pcie_lane_number(rdev);
5627 boot_state->sclk_bootup_value = le32_to_cpu(firmware_info->ulDefaultEngineClock);
5628 boot_state->mclk_bootup_value = le32_to_cpu(firmware_info->ulDefaultMemoryClock);
5629
5630 return 0;
5631 }
5632 return -EINVAL;
5633 }
5634
5635 void ci_dpm_fini(struct radeon_device *rdev)
5636 {
5637 int i;
5638
5639 for (i = 0; i < rdev->pm.dpm.num_ps; i++) {
5640 kfree(rdev->pm.dpm.ps[i].ps_priv);
5641 }
5642 kfree(rdev->pm.dpm.ps);
5643 kfree(rdev->pm.dpm.priv);
5644 kfree(rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries);
5645 r600_free_extended_power_table(rdev);
5646 }
5647
5648 int ci_dpm_init(struct radeon_device *rdev)
5649 {
5650 int index = GetIndexIntoMasterTable(DATA, ASIC_InternalSS_Info);
5651 SMU7_Discrete_DpmTable *dpm_table;
5652 struct radeon_gpio_rec gpio;
5653 u16 data_offset, size;
5654 u8 frev, crev;
5655 struct ci_power_info *pi;
5656 int ret;
5657 u32 mask;
5658
5659 pi = kzalloc(sizeof(struct ci_power_info), GFP_KERNEL);
5660 if (pi == NULL)
5661 return -ENOMEM;
5662 rdev->pm.dpm.priv = pi;
5663
5664 ret = drm_pcie_get_speed_cap_mask(rdev->ddev, &mask);
5665 if (ret)
5666 pi->sys_pcie_mask = 0;
5667 else
5668 pi->sys_pcie_mask = mask;
5669 pi->force_pcie_gen = RADEON_PCIE_GEN_INVALID;
5670
5671 pi->pcie_gen_performance.max = RADEON_PCIE_GEN1;
5672 pi->pcie_gen_performance.min = RADEON_PCIE_GEN3;
5673 pi->pcie_gen_powersaving.max = RADEON_PCIE_GEN1;
5674 pi->pcie_gen_powersaving.min = RADEON_PCIE_GEN3;
5675
5676 pi->pcie_lane_performance.max = 0;
5677 pi->pcie_lane_performance.min = 16;
5678 pi->pcie_lane_powersaving.max = 0;
5679 pi->pcie_lane_powersaving.min = 16;
5680
5681 ret = ci_get_vbios_boot_values(rdev, &pi->vbios_boot_state);
5682 if (ret) {
5683 ci_dpm_fini(rdev);
5684 return ret;
5685 }
5686
5687 ret = r600_get_platform_caps(rdev);
5688 if (ret) {
5689 ci_dpm_fini(rdev);
5690 return ret;
5691 }
5692
5693 ret = r600_parse_extended_power_table(rdev);
5694 if (ret) {
5695 ci_dpm_fini(rdev);
5696 return ret;
5697 }
5698
5699 ret = ci_parse_power_table(rdev);
5700 if (ret) {
5701 ci_dpm_fini(rdev);
5702 return ret;
5703 }
5704
5705 pi->dll_default_on = false;
5706 pi->sram_end = SMC_RAM_END;
5707
5708 pi->activity_target[0] = CISLAND_TARGETACTIVITY_DFLT;
5709 pi->activity_target[1] = CISLAND_TARGETACTIVITY_DFLT;
5710 pi->activity_target[2] = CISLAND_TARGETACTIVITY_DFLT;
5711 pi->activity_target[3] = CISLAND_TARGETACTIVITY_DFLT;
5712 pi->activity_target[4] = CISLAND_TARGETACTIVITY_DFLT;
5713 pi->activity_target[5] = CISLAND_TARGETACTIVITY_DFLT;
5714 pi->activity_target[6] = CISLAND_TARGETACTIVITY_DFLT;
5715 pi->activity_target[7] = CISLAND_TARGETACTIVITY_DFLT;
5716
5717 pi->mclk_activity_target = CISLAND_MCLK_TARGETACTIVITY_DFLT;
5718
5719 pi->sclk_dpm_key_disabled = 0;
5720 pi->mclk_dpm_key_disabled = 0;
5721 pi->pcie_dpm_key_disabled = 0;
5722 pi->thermal_sclk_dpm_enabled = 0;
5723
5724 /* mclk dpm is unstable on some R7 260X cards with the old mc ucode */
5725 if ((rdev->pdev->device == 0x6658) &&
5726 (rdev->mc_fw->size == (BONAIRE_MC_UCODE_SIZE * 4))) {
5727 pi->mclk_dpm_key_disabled = 1;
5728 }
5729
5730 pi->caps_sclk_ds = true;
5731
5732 pi->mclk_strobe_mode_threshold = 40000;
5733 pi->mclk_stutter_mode_threshold = 40000;
5734 pi->mclk_edc_enable_threshold = 40000;
5735 pi->mclk_edc_wr_enable_threshold = 40000;
5736
5737 ci_initialize_powertune_defaults(rdev);
5738
5739 pi->caps_fps = false;
5740
5741 pi->caps_sclk_throttle_low_notification = false;
5742
5743 pi->caps_uvd_dpm = true;
5744 pi->caps_vce_dpm = true;
5745
5746 ci_get_leakage_voltages(rdev);
5747 ci_patch_dependency_tables_with_leakage(rdev);
5748 ci_set_private_data_variables_based_on_pptable(rdev);
5749
5750 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries =
5751 kzalloc(4 * sizeof(struct radeon_clock_voltage_dependency_entry), GFP_KERNEL);
5752 if (!rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries) {
5753 ci_dpm_fini(rdev);
5754 return -ENOMEM;
5755 }
5756 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count = 4;
5757 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].clk = 0;
5758 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].v = 0;
5759 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].clk = 36000;
5760 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].v = 720;
5761 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].clk = 54000;
5762 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].v = 810;
5763 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].clk = 72000;
5764 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].v = 900;
5765
5766 rdev->pm.dpm.dyn_state.mclk_sclk_ratio = 4;
5767 rdev->pm.dpm.dyn_state.sclk_mclk_delta = 15000;
5768 rdev->pm.dpm.dyn_state.vddc_vddci_delta = 200;
5769
5770 rdev->pm.dpm.dyn_state.valid_sclk_values.count = 0;
5771 rdev->pm.dpm.dyn_state.valid_sclk_values.values = NULL;
5772 rdev->pm.dpm.dyn_state.valid_mclk_values.count = 0;
5773 rdev->pm.dpm.dyn_state.valid_mclk_values.values = NULL;
5774
5775 if (rdev->family == CHIP_HAWAII) {
5776 pi->thermal_temp_setting.temperature_low = 94500;
5777 pi->thermal_temp_setting.temperature_high = 95000;
5778 pi->thermal_temp_setting.temperature_shutdown = 104000;
5779 } else {
5780 pi->thermal_temp_setting.temperature_low = 99500;
5781 pi->thermal_temp_setting.temperature_high = 100000;
5782 pi->thermal_temp_setting.temperature_shutdown = 104000;
5783 }
5784
5785 pi->uvd_enabled = false;
5786
5787 dpm_table = &pi->smc_state_table;
5788
5789 gpio = radeon_atombios_lookup_gpio(rdev, VDDC_VRHOT_GPIO_PINID);
5790 if (gpio.valid) {
5791 dpm_table->VRHotGpio = gpio.shift;
5792 rdev->pm.dpm.platform_caps |= ATOM_PP_PLATFORM_CAP_REGULATOR_HOT;
5793 } else {
5794 dpm_table->VRHotGpio = CISLANDS_UNUSED_GPIO_PIN;
5795 rdev->pm.dpm.platform_caps &= ~ATOM_PP_PLATFORM_CAP_REGULATOR_HOT;
5796 }
5797
5798 gpio = radeon_atombios_lookup_gpio(rdev, PP_AC_DC_SWITCH_GPIO_PINID);
5799 if (gpio.valid) {
5800 dpm_table->AcDcGpio = gpio.shift;
5801 rdev->pm.dpm.platform_caps |= ATOM_PP_PLATFORM_CAP_HARDWAREDC;
5802 } else {
5803 dpm_table->AcDcGpio = CISLANDS_UNUSED_GPIO_PIN;
5804 rdev->pm.dpm.platform_caps &= ~ATOM_PP_PLATFORM_CAP_HARDWAREDC;
5805 }
5806
5807 gpio = radeon_atombios_lookup_gpio(rdev, VDDC_PCC_GPIO_PINID);
5808 if (gpio.valid) {
5809 u32 tmp = RREG32_SMC(CNB_PWRMGT_CNTL);
5810
5811 switch (gpio.shift) {
5812 case 0:
5813 tmp &= ~GNB_SLOW_MODE_MASK;
5814 tmp |= GNB_SLOW_MODE(1);
5815 break;
5816 case 1:
5817 tmp &= ~GNB_SLOW_MODE_MASK;
5818 tmp |= GNB_SLOW_MODE(2);
5819 break;
5820 case 2:
5821 tmp |= GNB_SLOW;
5822 break;
5823 case 3:
5824 tmp |= FORCE_NB_PS1;
5825 break;
5826 case 4:
5827 tmp |= DPM_ENABLED;
5828 break;
5829 default:
5830 DRM_DEBUG("Invalid PCC GPIO: %u!\n", gpio.shift);
5831 break;
5832 }
5833 WREG32_SMC(CNB_PWRMGT_CNTL, tmp);
5834 }
5835
5836 pi->voltage_control = CISLANDS_VOLTAGE_CONTROL_NONE;
5837 pi->vddci_control = CISLANDS_VOLTAGE_CONTROL_NONE;
5838 pi->mvdd_control = CISLANDS_VOLTAGE_CONTROL_NONE;
5839 if (radeon_atom_is_voltage_gpio(rdev, VOLTAGE_TYPE_VDDC, VOLTAGE_OBJ_GPIO_LUT))
5840 pi->voltage_control = CISLANDS_VOLTAGE_CONTROL_BY_GPIO;
5841 else if (radeon_atom_is_voltage_gpio(rdev, VOLTAGE_TYPE_VDDC, VOLTAGE_OBJ_SVID2))
5842 pi->voltage_control = CISLANDS_VOLTAGE_CONTROL_BY_SVID2;
5843
5844 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_VDDCI_CONTROL) {
5845 if (radeon_atom_is_voltage_gpio(rdev, VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_GPIO_LUT))
5846 pi->vddci_control = CISLANDS_VOLTAGE_CONTROL_BY_GPIO;
5847 else if (radeon_atom_is_voltage_gpio(rdev, VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_SVID2))
5848 pi->vddci_control = CISLANDS_VOLTAGE_CONTROL_BY_SVID2;
5849 else
5850 rdev->pm.dpm.platform_caps &= ~ATOM_PP_PLATFORM_CAP_VDDCI_CONTROL;
5851 }
5852
5853 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_MVDDCONTROL) {
5854 if (radeon_atom_is_voltage_gpio(rdev, VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_GPIO_LUT))
5855 pi->mvdd_control = CISLANDS_VOLTAGE_CONTROL_BY_GPIO;
5856 else if (radeon_atom_is_voltage_gpio(rdev, VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_SVID2))
5857 pi->mvdd_control = CISLANDS_VOLTAGE_CONTROL_BY_SVID2;
5858 else
5859 rdev->pm.dpm.platform_caps &= ~ATOM_PP_PLATFORM_CAP_MVDDCONTROL;
5860 }
5861
5862 pi->vddc_phase_shed_control = true;
5863
5864 #if defined(CONFIG_ACPI)
5865 pi->pcie_performance_request =
5866 radeon_acpi_is_pcie_performance_request_supported(rdev);
5867 #else
5868 pi->pcie_performance_request = false;
5869 #endif
5870
5871 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
5872 &frev, &crev, &data_offset)) {
5873 pi->caps_sclk_ss_support = true;
5874 pi->caps_mclk_ss_support = true;
5875 pi->dynamic_ss = true;
5876 } else {
5877 pi->caps_sclk_ss_support = false;
5878 pi->caps_mclk_ss_support = false;
5879 pi->dynamic_ss = true;
5880 }
5881
5882 if (rdev->pm.int_thermal_type != THERMAL_TYPE_NONE)
5883 pi->thermal_protection = true;
5884 else
5885 pi->thermal_protection = false;
5886
5887 pi->caps_dynamic_ac_timing = true;
5888
5889 pi->uvd_power_gated = false;
5890
5891 /* make sure dc limits are valid */
5892 if ((rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.sclk == 0) ||
5893 (rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.mclk == 0))
5894 rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc =
5895 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
5896
5897 pi->fan_ctrl_is_in_default_mode = true;
5898
5899 return 0;
5900 }
5901
5902 void ci_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
5903 struct seq_file *m)
5904 {
5905 struct ci_power_info *pi = ci_get_pi(rdev);
5906 struct radeon_ps *rps = &pi->current_rps;
5907 u32 sclk = ci_get_average_sclk_freq(rdev);
5908 u32 mclk = ci_get_average_mclk_freq(rdev);
5909
5910 seq_printf(m, "uvd %sabled\n", pi->uvd_enabled ? "en" : "dis");
5911 seq_printf(m, "vce %sabled\n", rps->vce_active ? "en" : "dis");
5912 seq_printf(m, "power level avg sclk: %u mclk: %u\n",
5913 sclk, mclk);
5914 }
5915
5916 void ci_dpm_print_power_state(struct radeon_device *rdev,
5917 struct radeon_ps *rps)
5918 {
5919 struct ci_ps *ps = ci_get_ps(rps);
5920 struct ci_pl *pl;
5921 int i;
5922
5923 r600_dpm_print_class_info(rps->class, rps->class2);
5924 r600_dpm_print_cap_info(rps->caps);
5925 printk("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk);
5926 for (i = 0; i < ps->performance_level_count; i++) {
5927 pl = &ps->performance_levels[i];
5928 printk("\t\tpower level %d sclk: %u mclk: %u pcie gen: %u pcie lanes: %u\n",
5929 i, pl->sclk, pl->mclk, pl->pcie_gen + 1, pl->pcie_lane);
5930 }
5931 r600_dpm_print_ps_status(rdev, rps);
5932 }
5933
5934 u32 ci_dpm_get_current_sclk(struct radeon_device *rdev)
5935 {
5936 u32 sclk = ci_get_average_sclk_freq(rdev);
5937
5938 return sclk;
5939 }
5940
5941 u32 ci_dpm_get_current_mclk(struct radeon_device *rdev)
5942 {
5943 u32 mclk = ci_get_average_mclk_freq(rdev);
5944
5945 return mclk;
5946 }
5947
5948 u32 ci_dpm_get_sclk(struct radeon_device *rdev, bool low)
5949 {
5950 struct ci_power_info *pi = ci_get_pi(rdev);
5951 struct ci_ps *requested_state = ci_get_ps(&pi->requested_rps);
5952
5953 if (low)
5954 return requested_state->performance_levels[0].sclk;
5955 else
5956 return requested_state->performance_levels[requested_state->performance_level_count - 1].sclk;
5957 }
5958
5959 u32 ci_dpm_get_mclk(struct radeon_device *rdev, bool low)
5960 {
5961 struct ci_power_info *pi = ci_get_pi(rdev);
5962 struct ci_ps *requested_state = ci_get_ps(&pi->requested_rps);
5963
5964 if (low)
5965 return requested_state->performance_levels[0].mclk;
5966 else
5967 return requested_state->performance_levels[requested_state->performance_level_count - 1].mclk;
5968 }
Linux with added FPC-III support