drivers/gpu/drm/radeon/radeon_dp_mst.c

   1
   2 #include <drm/drmP.h>
   3 #include <drm/drm_dp_mst_helper.h>
   4 #include <drm/drm_fb_helper.h>
   5
   6 #include "radeon.h"
   7 #include "atom.h"
   8 #include "ni_reg.h"
   9
  10 static struct radeon_encoder *radeon_dp_create_fake_mst_encoder(struct radeon_connector *connector);
  11
  12 static int radeon_atom_set_enc_offset(int id)
  13 {
  14         static const int offsets[] = { EVERGREEN_CRTC0_REGISTER_OFFSET,
  15                                        EVERGREEN_CRTC1_REGISTER_OFFSET,
  16                                        EVERGREEN_CRTC2_REGISTER_OFFSET,
  17                                        EVERGREEN_CRTC3_REGISTER_OFFSET,
  18                                        EVERGREEN_CRTC4_REGISTER_OFFSET,
  19                                        EVERGREEN_CRTC5_REGISTER_OFFSET,
  20                                        0x13830 - 0x7030 };
  21
  22         return offsets[id];
  23 }
  24
  25 static int radeon_dp_mst_set_be_cntl(struct radeon_encoder *primary,
  26                                      struct radeon_encoder_mst *mst_enc,
  27                                      enum radeon_hpd_id hpd, bool enable)
  28 {
  29         struct drm_device *dev = primary->base.dev;
  30         struct radeon_device *rdev = dev->dev_private;
  31         uint32_t reg;
  32         int retries = 0;
  33         uint32_t temp;
  34
  35         reg = RREG32(NI_DIG_BE_CNTL + primary->offset);
  36
  37         /* set MST mode */
  38         reg &= ~NI_DIG_FE_DIG_MODE(7);
  39         reg |= NI_DIG_FE_DIG_MODE(NI_DIG_MODE_DP_MST);
  40
  41         if (enable)
  42                 reg |= NI_DIG_FE_SOURCE_SELECT(1 << mst_enc->fe);
  43         else
  44                 reg &= ~NI_DIG_FE_SOURCE_SELECT(1 << mst_enc->fe);
  45
  46         reg |= NI_DIG_HPD_SELECT(hpd);
  47         DRM_DEBUG_KMS("writing 0x%08x 0x%08x\n", NI_DIG_BE_CNTL + primary->offset, reg);
  48         WREG32(NI_DIG_BE_CNTL + primary->offset, reg);
  49
  50         if (enable) {
  51                 uint32_t offset = radeon_atom_set_enc_offset(mst_enc->fe);
  52
  53                 do {
  54                         temp = RREG32(NI_DIG_FE_CNTL + offset);
  55                 } while ((temp & NI_DIG_SYMCLK_FE_ON) && retries++ < 10000);
  56                 if (retries == 10000)
  57                         DRM_ERROR("timed out waiting for FE %d %d\n", primary->offset, mst_enc->fe);
  58         }
  59         return 0;
  60 }
  61
  62 static int radeon_dp_mst_set_stream_attrib(struct radeon_encoder *primary,
  63                                            int stream_number,
  64                                            int fe,
  65                                            int slots)
  66 {
  67         struct drm_device *dev = primary->base.dev;
  68         struct radeon_device *rdev = dev->dev_private;
  69         u32 temp, val;
  70         int retries  = 0;
  71         int satreg, satidx;
  72
  73         satreg = stream_number >> 1;
  74         satidx = stream_number & 1;
  75
  76         temp = RREG32(NI_DP_MSE_SAT0 + satreg + primary->offset);
  77
  78         val = NI_DP_MSE_SAT_SLOT_COUNT0(slots) | NI_DP_MSE_SAT_SRC0(fe);
  79
  80         val <<= (16 * satidx);
  81
  82         temp &= ~(0xffff << (16 * satidx));
  83
  84         temp |= val;
  85
  86         DRM_DEBUG_KMS("writing 0x%08x 0x%08x\n", NI_DP_MSE_SAT0 + satreg + primary->offset, temp);
  87         WREG32(NI_DP_MSE_SAT0 + satreg + primary->offset, temp);
  88
  89         WREG32(NI_DP_MSE_SAT_UPDATE + primary->offset, 1);
  90
  91         do {
  92                 unsigned value1, value2;
  93                 udelay(10);
  94                 temp = RREG32(NI_DP_MSE_SAT_UPDATE + primary->offset);
  95
  96                 value1 = temp & NI_DP_MSE_SAT_UPDATE_MASK;
  97                 value2 = temp & NI_DP_MSE_16_MTP_KEEPOUT;
  98
  99                 if (!value1 && !value2)
 100                         break;
 101         } while (retries++ < 50);
 102
 103         if (retries == 10000)
 104                 DRM_ERROR("timed out waitin for SAT update %d\n", primary->offset);
 105
 106         /* MTP 16 ? */
 107         return 0;
 108 }
 109
 110 static int radeon_dp_mst_update_stream_attribs(struct radeon_connector *mst_conn,
 111                                                struct radeon_encoder *primary)
 112 {
 113         struct drm_device *dev = mst_conn->base.dev;
 114         struct stream_attribs new_attribs[6];
 115         int i;
 116         int idx = 0;
 117         struct radeon_connector *radeon_connector;
 118         struct drm_connector *connector;
 119
 120         memset(new_attribs, 0, sizeof(new_attribs));
 121         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 122                 struct radeon_encoder *subenc;
 123                 struct radeon_encoder_mst *mst_enc;
 124
 125                 radeon_connector = to_radeon_connector(connector);
 126                 if (!radeon_connector->is_mst_connector)
 127                         continue;
 128
 129                 if (radeon_connector->mst_port != mst_conn)
 130                         continue;
 131
 132                 subenc = radeon_connector->mst_encoder;
 133                 mst_enc = subenc->enc_priv;
 134
 135                 if (!mst_enc->enc_active)
 136                         continue;
 137
 138                 new_attribs[idx].fe = mst_enc->fe;
 139                 new_attribs[idx].slots = drm_dp_mst_get_vcpi_slots(&mst_conn->mst_mgr, mst_enc->port);
 140                 idx++;
 141         }
 142
 143         for (i = 0; i < idx; i++) {
 144                 if (new_attribs[i].fe != mst_conn->cur_stream_attribs[i].fe ||
 145                     new_attribs[i].slots != mst_conn->cur_stream_attribs[i].slots) {
 146                         radeon_dp_mst_set_stream_attrib(primary, i, new_attribs[i].fe, new_attribs[i].slots);
 147                         mst_conn->cur_stream_attribs[i].fe = new_attribs[i].fe;
 148                         mst_conn->cur_stream_attribs[i].slots = new_attribs[i].slots;
 149                 }
 150         }
 151
 152         for (i = idx; i < mst_conn->enabled_attribs; i++) {
 153                 radeon_dp_mst_set_stream_attrib(primary, i, 0, 0);
 154                 mst_conn->cur_stream_attribs[i].fe = 0;
 155                 mst_conn->cur_stream_attribs[i].slots = 0;
 156         }
 157         mst_conn->enabled_attribs = idx;
 158         return 0;
 159 }
 160
 161 static int radeon_dp_mst_set_vcp_size(struct radeon_encoder *mst, s64 avg_time_slots_per_mtp)
 162 {
 163         struct drm_device *dev = mst->base.dev;
 164         struct radeon_device *rdev = dev->dev_private;
 165         struct radeon_encoder_mst *mst_enc = mst->enc_priv;
 166         uint32_t val, temp;
 167         uint32_t offset = radeon_atom_set_enc_offset(mst_enc->fe);
 168         int retries = 0;
 169         uint32_t x = drm_fixp2int(avg_time_slots_per_mtp);
 170         uint32_t y = drm_fixp2int_ceil((avg_time_slots_per_mtp - x) << 26);
 171
 172         val = NI_DP_MSE_RATE_X(x) | NI_DP_MSE_RATE_Y(y);
 173
 174         WREG32(NI_DP_MSE_RATE_CNTL + offset, val);
 175
 176         do {
 177                 temp = RREG32(NI_DP_MSE_RATE_UPDATE + offset);
 178                 udelay(10);
 179         } while ((temp & 0x1) && (retries++ < 10000));
 180
 181         if (retries >= 10000)
 182                 DRM_ERROR("timed out wait for rate cntl %d\n", mst_enc->fe);
 183         return 0;
 184 }
 185
 186 static int radeon_dp_mst_get_ddc_modes(struct drm_connector *connector)
 187 {
 188         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 189         struct radeon_connector *master = radeon_connector->mst_port;
 190         struct edid *edid;
 191         int ret = 0;
 192
 193         edid = drm_dp_mst_get_edid(connector, &master->mst_mgr, radeon_connector->port);
 194         radeon_connector->edid = edid;
 195         DRM_DEBUG_KMS("edid retrieved %p\n", edid);
 196         if (radeon_connector->edid) {
 197                 drm_mode_connector_update_edid_property(&radeon_connector->base, radeon_connector->edid);
 198                 ret = drm_add_edid_modes(&radeon_connector->base, radeon_connector->edid);
 199                 drm_edid_to_eld(&radeon_connector->base, radeon_connector->edid);
 200                 return ret;
 201         }
 202         drm_mode_connector_update_edid_property(&radeon_connector->base, NULL);
 203
 204         return ret;
 205 }
 206
 207 static int radeon_dp_mst_get_modes(struct drm_connector *connector)
 208 {
 209         return radeon_dp_mst_get_ddc_modes(connector);
 210 }
 211
 212 static enum drm_mode_status
 213 radeon_dp_mst_mode_valid(struct drm_connector *connector,
 214                         struct drm_display_mode *mode)
 215 {
 216         /* TODO - validate mode against available PBN for link */
 217         if (mode->clock < 10000)
 218                 return MODE_CLOCK_LOW;
 219
 220         if (mode->flags & DRM_MODE_FLAG_DBLCLK)
 221                 return MODE_H_ILLEGAL;
 222
 223         return MODE_OK;
 224 }
 225
 226 static struct
 227 drm_encoder *radeon_mst_best_encoder(struct drm_connector *connector)
 228 {
 229         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 230
 231         return &radeon_connector->mst_encoder->base;
 232 }
 233
 234 static const struct drm_connector_helper_funcs radeon_dp_mst_connector_helper_funcs = {
 235         .get_modes = radeon_dp_mst_get_modes,
 236         .mode_valid = radeon_dp_mst_mode_valid,
 237         .best_encoder = radeon_mst_best_encoder,
 238 };
 239
 240 static enum drm_connector_status
 241 radeon_dp_mst_detect(struct drm_connector *connector, bool force)
 242 {
 243         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 244         struct radeon_connector *master = radeon_connector->mst_port;
 245
 246         return drm_dp_mst_detect_port(connector, &master->mst_mgr, radeon_connector->port);
 247 }
 248
 249 static void
 250 radeon_dp_mst_connector_destroy(struct drm_connector *connector)
 251 {
 252         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 253         struct radeon_encoder *radeon_encoder = radeon_connector->mst_encoder;
 254
 255         drm_encoder_cleanup(&radeon_encoder->base);
 256         kfree(radeon_encoder);
 257         drm_connector_cleanup(connector);
 258         kfree(radeon_connector);
 259 }
 260
 261 static const struct drm_connector_funcs radeon_dp_mst_connector_funcs = {
 262         .dpms = drm_helper_connector_dpms,
 263         .detect = radeon_dp_mst_detect,
 264         .fill_modes = drm_helper_probe_single_connector_modes,
 265         .destroy = radeon_dp_mst_connector_destroy,
 266 };
 267
 268 static struct drm_connector *radeon_dp_add_mst_connector(struct drm_dp_mst_topology_mgr *mgr,
 269                                                          struct drm_dp_mst_port *port,
 270                                                          const char *pathprop)
 271 {
 272         struct radeon_connector *master = container_of(mgr, struct radeon_connector, mst_mgr);
 273         struct drm_device *dev = master->base.dev;
 274         struct radeon_connector *radeon_connector;
 275         struct drm_connector *connector;
 276
 277         radeon_connector = kzalloc(sizeof(*radeon_connector), GFP_KERNEL);
 278         if (!radeon_connector)
 279                 return NULL;
 280
 281         radeon_connector->is_mst_connector = true;
 282         connector = &radeon_connector->base;
 283         radeon_connector->port = port;
 284         radeon_connector->mst_port = master;
 285         DRM_DEBUG_KMS("\n");
 286
 287         drm_connector_init(dev, connector, &radeon_dp_mst_connector_funcs, DRM_MODE_CONNECTOR_DisplayPort);
 288         drm_connector_helper_add(connector, &radeon_dp_mst_connector_helper_funcs);
 289         radeon_connector->mst_encoder = radeon_dp_create_fake_mst_encoder(master);
 290
 291         drm_object_attach_property(&connector->base, dev->mode_config.path_property, 0);
 292         drm_object_attach_property(&connector->base, dev->mode_config.tile_property, 0);
 293         drm_mode_connector_set_path_property(connector, pathprop);
 294
 295         return connector;
 296 }
 297
 298 static void radeon_dp_register_mst_connector(struct drm_connector *connector)
 299 {
 300         struct drm_device *dev = connector->dev;
 301         struct radeon_device *rdev = dev->dev_private;
 302
 303         drm_modeset_lock_all(dev);
 304         radeon_fb_add_connector(rdev, connector);
 305         drm_modeset_unlock_all(dev);
 306
 307         drm_connector_register(connector);
 308 }
 309
 310 static void radeon_dp_destroy_mst_connector(struct drm_dp_mst_topology_mgr *mgr,
 311                                             struct drm_connector *connector)
 312 {
 313         struct radeon_connector *master = container_of(mgr, struct radeon_connector, mst_mgr);
 314         struct drm_device *dev = master->base.dev;
 315         struct radeon_device *rdev = dev->dev_private;
 316
 317         drm_connector_unregister(connector);
 318         /* need to nuke the connector */
 319         drm_modeset_lock_all(dev);
 320         /* dpms off */
 321         radeon_fb_remove_connector(rdev, connector);
 322
 323         drm_connector_cleanup(connector);
 324         drm_modeset_unlock_all(dev);
 325
 326         kfree(connector);
 327         DRM_DEBUG_KMS("\n");
 328 }
 329
 330 static void radeon_dp_mst_hotplug(struct drm_dp_mst_topology_mgr *mgr)
 331 {
 332         struct radeon_connector *master = container_of(mgr, struct radeon_connector, mst_mgr);
 333         struct drm_device *dev = master->base.dev;
 334
 335         drm_kms_helper_hotplug_event(dev);
 336 }
 337
 338 const struct drm_dp_mst_topology_cbs mst_cbs = {
 339         .add_connector = radeon_dp_add_mst_connector,
 340         .register_connector = radeon_dp_register_mst_connector,
 341         .destroy_connector = radeon_dp_destroy_mst_connector,
 342         .hotplug = radeon_dp_mst_hotplug,
 343 };
 344
 345 static struct
 346 radeon_connector *radeon_mst_find_connector(struct drm_encoder *encoder)
 347 {
 348         struct drm_device *dev = encoder->dev;
 349         struct drm_connector *connector;
 350
 351         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 352                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 353                 if (!connector->encoder)
 354                         continue;
 355                 if (!radeon_connector->is_mst_connector)
 356                         continue;
 357
 358                 DRM_DEBUG_KMS("checking %p vs %p\n", connector->encoder, encoder);
 359                 if (connector->encoder == encoder)
 360                         return radeon_connector;
 361         }
 362         return NULL;
 363 }
 364
 365 void radeon_dp_mst_prepare_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
 366 {
 367         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 368         struct drm_device *dev = crtc->dev;
 369         struct radeon_device *rdev = dev->dev_private;
 370         struct radeon_encoder *radeon_encoder = to_radeon_encoder(radeon_crtc->encoder);
 371         struct radeon_encoder_mst *mst_enc = radeon_encoder->enc_priv;
 372         struct radeon_connector *radeon_connector = radeon_mst_find_connector(&radeon_encoder->base);
 373         int dp_clock;
 374         struct radeon_connector_atom_dig *dig_connector = mst_enc->connector->con_priv;
 375
 376         if (radeon_connector) {
 377                 radeon_connector->pixelclock_for_modeset = mode->clock;
 378                 if (radeon_connector->base.display_info.bpc)
 379                         radeon_crtc->bpc = radeon_connector->base.display_info.bpc;
 380                 else
 381                         radeon_crtc->bpc = 8;
 382         }
 383
 384         DRM_DEBUG_KMS("dp_clock %p %d\n", dig_connector, dig_connector->dp_clock);
 385         dp_clock = dig_connector->dp_clock;
 386         radeon_crtc->ss_enabled =
 387                 radeon_atombios_get_asic_ss_info(rdev, &radeon_crtc->ss,
 388                                                  ASIC_INTERNAL_SS_ON_DP,
 389                                                  dp_clock);
 390 }
 391
 392 static void
 393 radeon_mst_encoder_dpms(struct drm_encoder *encoder, int mode)
 394 {
 395         struct drm_device *dev = encoder->dev;
 396         struct radeon_device *rdev = dev->dev_private;
 397         struct radeon_encoder *radeon_encoder, *primary;
 398         struct radeon_encoder_mst *mst_enc;
 399         struct radeon_encoder_atom_dig *dig_enc;
 400         struct radeon_connector *radeon_connector;
 401         struct drm_crtc *crtc;
 402         struct radeon_crtc *radeon_crtc;
 403         int ret, slots;
 404         s64 fixed_pbn, fixed_pbn_per_slot, avg_time_slots_per_mtp;
 405         if (!ASIC_IS_DCE5(rdev)) {
 406                 DRM_ERROR("got mst dpms on non-DCE5\n");
 407                 return;
 408         }
 409
 410         radeon_connector = radeon_mst_find_connector(encoder);
 411         if (!radeon_connector)
 412                 return;
 413
 414         radeon_encoder = to_radeon_encoder(encoder);
 415
 416         mst_enc = radeon_encoder->enc_priv;
 417
 418         primary = mst_enc->primary;
 419
 420         dig_enc = primary->enc_priv;
 421
 422         crtc = encoder->crtc;
 423         DRM_DEBUG_KMS("got connector %d\n", dig_enc->active_mst_links);
 424
 425         switch (mode) {
 426         case DRM_MODE_DPMS_ON:
 427                 dig_enc->active_mst_links++;
 428
 429                 radeon_crtc = to_radeon_crtc(crtc);
 430
 431                 if (dig_enc->active_mst_links == 1) {
 432                         mst_enc->fe = dig_enc->dig_encoder;
 433                         mst_enc->fe_from_be = true;
 434                         atombios_set_mst_encoder_crtc_source(encoder, mst_enc->fe);
 435
 436                         atombios_dig_encoder_setup(&primary->base, ATOM_ENCODER_CMD_SETUP, 0);
 437                         atombios_dig_transmitter_setup2(&primary->base, ATOM_TRANSMITTER_ACTION_ENABLE,
 438                                                         0, 0, dig_enc->dig_encoder);
 439
 440                         if (radeon_dp_needs_link_train(mst_enc->connector) ||
 441                             dig_enc->active_mst_links == 1) {
 442                                 radeon_dp_link_train(&primary->base, &mst_enc->connector->base);
 443                         }
 444
 445                 } else {
 446                         mst_enc->fe = radeon_atom_pick_dig_encoder(encoder, radeon_crtc->crtc_id);
 447                         if (mst_enc->fe == -1)
 448                                 DRM_ERROR("failed to get frontend for dig encoder\n");
 449                         mst_enc->fe_from_be = false;
 450                         atombios_set_mst_encoder_crtc_source(encoder, mst_enc->fe);
 451                 }
 452
 453                 DRM_DEBUG_KMS("dig encoder is %d %d %d\n", dig_enc->dig_encoder,
 454                               dig_enc->linkb, radeon_crtc->crtc_id);
 455
 456                 slots = drm_dp_find_vcpi_slots(&radeon_connector->mst_port->mst_mgr,
 457                                                mst_enc->pbn);
 458                 ret = drm_dp_mst_allocate_vcpi(&radeon_connector->mst_port->mst_mgr,
 459                                                radeon_connector->port,
 460                                                mst_enc->pbn, slots);
 461                 ret = drm_dp_update_payload_part1(&radeon_connector->mst_port->mst_mgr);
 462
 463                 radeon_dp_mst_set_be_cntl(primary, mst_enc,
 464                                           radeon_connector->mst_port->hpd.hpd, true);
 465
 466                 mst_enc->enc_active = true;
 467                 radeon_dp_mst_update_stream_attribs(radeon_connector->mst_port, primary);
 468
 469                 fixed_pbn = drm_int2fixp(mst_enc->pbn);
 470                 fixed_pbn_per_slot = drm_int2fixp(radeon_connector->mst_port->mst_mgr.pbn_div);
 471                 avg_time_slots_per_mtp = drm_fixp_div(fixed_pbn, fixed_pbn_per_slot);
 472                 radeon_dp_mst_set_vcp_size(radeon_encoder, avg_time_slots_per_mtp);
 473
 474                 atombios_dig_encoder_setup2(&primary->base, ATOM_ENCODER_CMD_DP_VIDEO_ON, 0,
 475                                             mst_enc->fe);
 476                 ret = drm_dp_check_act_status(&radeon_connector->mst_port->mst_mgr);
 477
 478                 ret = drm_dp_update_payload_part2(&radeon_connector->mst_port->mst_mgr);
 479
 480                 break;
 481         case DRM_MODE_DPMS_STANDBY:
 482         case DRM_MODE_DPMS_SUSPEND:
 483         case DRM_MODE_DPMS_OFF:
 484                 DRM_ERROR("DPMS OFF %d\n", dig_enc->active_mst_links);
 485
 486                 if (!mst_enc->enc_active)
 487                         return;
 488
 489                 drm_dp_mst_reset_vcpi_slots(&radeon_connector->mst_port->mst_mgr, mst_enc->port);
 490                 ret = drm_dp_update_payload_part1(&radeon_connector->mst_port->mst_mgr);
 491
 492                 drm_dp_check_act_status(&radeon_connector->mst_port->mst_mgr);
 493                 /* and this can also fail */
 494                 drm_dp_update_payload_part2(&radeon_connector->mst_port->mst_mgr);
 495
 496                 drm_dp_mst_deallocate_vcpi(&radeon_connector->mst_port->mst_mgr, mst_enc->port);
 497
 498                 mst_enc->enc_active = false;
 499                 radeon_dp_mst_update_stream_attribs(radeon_connector->mst_port, primary);
 500
 501                 radeon_dp_mst_set_be_cntl(primary, mst_enc,
 502                                           radeon_connector->mst_port->hpd.hpd, false);
 503                 atombios_dig_encoder_setup2(&primary->base, ATOM_ENCODER_CMD_DP_VIDEO_OFF, 0,
 504                                             mst_enc->fe);
 505
 506                 if (!mst_enc->fe_from_be)
 507                         radeon_atom_release_dig_encoder(rdev, mst_enc->fe);
 508
 509                 mst_enc->fe_from_be = false;
 510                 dig_enc->active_mst_links--;
 511                 if (dig_enc->active_mst_links == 0) {
 512                         /* drop link */
 513                 }
 514
 515                 break;
 516         }
 517
 518 }
 519
 520 static bool radeon_mst_mode_fixup(struct drm_encoder *encoder,
 521                                    const struct drm_display_mode *mode,
 522                                    struct drm_display_mode *adjusted_mode)
 523 {
 524         struct radeon_encoder_mst *mst_enc;
 525         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 526         struct radeon_connector_atom_dig *dig_connector;
 527         int bpp = 24;
 528
 529         mst_enc = radeon_encoder->enc_priv;
 530
 531         mst_enc->pbn = drm_dp_calc_pbn_mode(adjusted_mode->clock, bpp);
 532
 533         mst_enc->primary->active_device = mst_enc->primary->devices & mst_enc->connector->devices;
 534         DRM_DEBUG_KMS("setting active device to %08x from %08x %08x for encoder %d\n",
 535                       mst_enc->primary->active_device, mst_enc->primary->devices,
 536                       mst_enc->connector->devices, mst_enc->primary->base.encoder_type);
 537
 538
 539         drm_mode_set_crtcinfo(adjusted_mode, 0);
 540         dig_connector = mst_enc->connector->con_priv;
 541         dig_connector->dp_lane_count = drm_dp_max_lane_count(dig_connector->dpcd);
 542         dig_connector->dp_clock = drm_dp_max_link_rate(dig_connector->dpcd);
 543         DRM_DEBUG_KMS("dig clock %p %d %d\n", dig_connector,
 544                       dig_connector->dp_lane_count, dig_connector->dp_clock);
 545         return true;
 546 }
 547
 548 static void radeon_mst_encoder_prepare(struct drm_encoder *encoder)
 549 {
 550         struct radeon_connector *radeon_connector;
 551         struct radeon_encoder *radeon_encoder, *primary;
 552         struct radeon_encoder_mst *mst_enc;
 553         struct radeon_encoder_atom_dig *dig_enc;
 554
 555         radeon_connector = radeon_mst_find_connector(encoder);
 556         if (!radeon_connector) {
 557                 DRM_DEBUG_KMS("failed to find connector %p\n", encoder);
 558                 return;
 559         }
 560         radeon_encoder = to_radeon_encoder(encoder);
 561
 562         radeon_mst_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
 563
 564         mst_enc = radeon_encoder->enc_priv;
 565
 566         primary = mst_enc->primary;
 567
 568         dig_enc = primary->enc_priv;
 569
 570         mst_enc->port = radeon_connector->port;
 571
 572         if (dig_enc->dig_encoder == -1) {
 573                 dig_enc->dig_encoder = radeon_atom_pick_dig_encoder(&primary->base, -1);
 574                 primary->offset = radeon_atom_set_enc_offset(dig_enc->dig_encoder);
 575                 atombios_set_mst_encoder_crtc_source(encoder, dig_enc->dig_encoder);
 576
 577
 578         }
 579         DRM_DEBUG_KMS("%d %d\n", dig_enc->dig_encoder, primary->offset);
 580 }
 581
 582 static void
 583 radeon_mst_encoder_mode_set(struct drm_encoder *encoder,
 584                              struct drm_display_mode *mode,
 585                              struct drm_display_mode *adjusted_mode)
 586 {
 587         DRM_DEBUG_KMS("\n");
 588 }
 589
 590 static void radeon_mst_encoder_commit(struct drm_encoder *encoder)
 591 {
 592         radeon_mst_encoder_dpms(encoder, DRM_MODE_DPMS_ON);
 593         DRM_DEBUG_KMS("\n");
 594 }
 595
 596 static const struct drm_encoder_helper_funcs radeon_mst_helper_funcs = {
 597         .dpms = radeon_mst_encoder_dpms,
 598         .mode_fixup = radeon_mst_mode_fixup,
 599         .prepare = radeon_mst_encoder_prepare,
 600         .mode_set = radeon_mst_encoder_mode_set,
 601         .commit = radeon_mst_encoder_commit,
 602 };
 603
 604 static void radeon_dp_mst_encoder_destroy(struct drm_encoder *encoder)
 605 {
 606         drm_encoder_cleanup(encoder);
 607         kfree(encoder);
 608 }
 609
 610 static const struct drm_encoder_funcs radeon_dp_mst_enc_funcs = {
 611         .destroy = radeon_dp_mst_encoder_destroy,
 612 };
 613
 614 static struct radeon_encoder *
 615 radeon_dp_create_fake_mst_encoder(struct radeon_connector *connector)
 616 {
 617         struct drm_device *dev = connector->base.dev;
 618         struct radeon_device *rdev = dev->dev_private;
 619         struct radeon_encoder *radeon_encoder;
 620         struct radeon_encoder_mst *mst_enc;
 621         struct drm_encoder *encoder;
 622         const struct drm_connector_helper_funcs *connector_funcs = connector->base.helper_private;
 623         struct drm_encoder *enc_master = connector_funcs->best_encoder(&connector->base);
 624
 625         DRM_DEBUG_KMS("enc master is %p\n", enc_master);
 626         radeon_encoder = kzalloc(sizeof(*radeon_encoder), GFP_KERNEL);
 627         if (!radeon_encoder)
 628                 return NULL;
 629
 630         radeon_encoder->enc_priv = kzalloc(sizeof(*mst_enc), GFP_KERNEL);
 631         if (!radeon_encoder->enc_priv) {
 632                 kfree(radeon_encoder);
 633                 return NULL;
 634         }
 635         encoder = &radeon_encoder->base;
 636         switch (rdev->num_crtc) {
 637         case 1:
 638                 encoder->possible_crtcs = 0x1;
 639                 break;
 640         case 2:
 641         default:
 642                 encoder->possible_crtcs = 0x3;
 643                 break;
 644         case 4:
 645                 encoder->possible_crtcs = 0xf;
 646                 break;
 647         case 6:
 648                 encoder->possible_crtcs = 0x3f;
 649                 break;
 650         }
 651
 652         drm_encoder_init(dev, &radeon_encoder->base, &radeon_dp_mst_enc_funcs,
 653                          DRM_MODE_ENCODER_DPMST, NULL);
 654         drm_encoder_helper_add(encoder, &radeon_mst_helper_funcs);
 655
 656         mst_enc = radeon_encoder->enc_priv;
 657         mst_enc->connector = connector;
 658         mst_enc->primary = to_radeon_encoder(enc_master);
 659         radeon_encoder->is_mst_encoder = true;
 660         return radeon_encoder;
 661 }
 662
 663 int
 664 radeon_dp_mst_init(struct radeon_connector *radeon_connector)
 665 {
 666         struct drm_device *dev = radeon_connector->base.dev;
 667
 668         if (!radeon_connector->ddc_bus->has_aux)
 669                 return 0;
 670
 671         radeon_connector->mst_mgr.cbs = &mst_cbs;
 672         return drm_dp_mst_topology_mgr_init(&radeon_connector->mst_mgr, dev,
 673                                             &radeon_connector->ddc_bus->aux, 16, 6,
 674                                             radeon_connector->base.base.id);
 675 }
 676
 677 int
 678 radeon_dp_mst_probe(struct radeon_connector *radeon_connector)
 679 {
 680         struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv;
 681         struct drm_device *dev = radeon_connector->base.dev;
 682         struct radeon_device *rdev = dev->dev_private;
 683         int ret;
 684         u8 msg[1];
 685
 686         if (!radeon_mst)
 687                 return 0;
 688
 689         if (!ASIC_IS_DCE5(rdev))
 690                 return 0;
 691
 692         if (dig_connector->dpcd[DP_DPCD_REV] < 0x12)
 693                 return 0;
 694
 695         ret = drm_dp_dpcd_read(&radeon_connector->ddc_bus->aux, DP_MSTM_CAP, msg,
 696                                1);
 697         if (ret) {
 698                 if (msg[0] & DP_MST_CAP) {
 699                         DRM_DEBUG_KMS("Sink is MST capable\n");
 700                         dig_connector->is_mst = true;
 701                 } else {
 702                         DRM_DEBUG_KMS("Sink is not MST capable\n");
 703                         dig_connector->is_mst = false;
 704                 }
 705
 706         }
 707         drm_dp_mst_topology_mgr_set_mst(&radeon_connector->mst_mgr,
 708                                         dig_connector->is_mst);
 709         return dig_connector->is_mst;
 710 }
 711
 712 int
 713 radeon_dp_mst_check_status(struct radeon_connector *radeon_connector)
 714 {
 715         struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv;
 716         int retry;
 717
 718         if (dig_connector->is_mst) {
 719                 u8 esi[16] = { 0 };
 720                 int dret;
 721                 int ret = 0;
 722                 bool handled;
 723
 724                 dret = drm_dp_dpcd_read(&radeon_connector->ddc_bus->aux,
 725                                        DP_SINK_COUNT_ESI, esi, 8);
 726 go_again:
 727                 if (dret == 8) {
 728                         DRM_DEBUG_KMS("got esi %02x %02x %02x\n", esi[0], esi[1], esi[2]);
 729                         ret = drm_dp_mst_hpd_irq(&radeon_connector->mst_mgr, esi, &handled);
 730
 731                         if (handled) {
 732                                 for (retry = 0; retry < 3; retry++) {
 733                                         int wret;
 734                                         wret = drm_dp_dpcd_write(&radeon_connector->ddc_bus->aux,
 735                                                                  DP_SINK_COUNT_ESI + 1, &esi[1], 3);
 736                                         if (wret == 3)
 737                                                 break;
 738                                 }
 739
 740                                 dret = drm_dp_dpcd_read(&radeon_connector->ddc_bus->aux,
 741                                                         DP_SINK_COUNT_ESI, esi, 8);
 742                                 if (dret == 8) {
 743                                         DRM_DEBUG_KMS("got esi2 %02x %02x %02x\n", esi[0], esi[1], esi[2]);
 744                                         goto go_again;
 745                                 }
 746                         } else
 747                                 ret = 0;
 748
 749                         return ret;
 750                 } else {
 751                         DRM_DEBUG_KMS("failed to get ESI - device may have failed %d\n", ret);
 752                         dig_connector->is_mst = false;
 753                         drm_dp_mst_topology_mgr_set_mst(&radeon_connector->mst_mgr,
 754                                                         dig_connector->is_mst);
 755                         /* send a hotplug event */
 756                 }
 757         }
 758         return -EINVAL;
 759 }
 760
 761 #if defined(CONFIG_DEBUG_FS)
 762
 763 static int radeon_debugfs_mst_info(struct seq_file *m, void *data)
 764 {
 765         struct drm_info_node *node = (struct drm_info_node *)m->private;
 766         struct drm_device *dev = node->minor->dev;
 767         struct drm_connector *connector;
 768         struct radeon_connector *radeon_connector;
 769         struct radeon_connector_atom_dig *dig_connector;
 770         int i;
 771
 772         drm_modeset_lock_all(dev);
 773         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 774                 if (connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort)
 775                         continue;
 776
 777                 radeon_connector = to_radeon_connector(connector);
 778                 dig_connector = radeon_connector->con_priv;
 779                 if (radeon_connector->is_mst_connector)
 780                         continue;
 781                 if (!dig_connector->is_mst)
 782                         continue;
 783                 drm_dp_mst_dump_topology(m, &radeon_connector->mst_mgr);
 784
 785                 for (i = 0; i < radeon_connector->enabled_attribs; i++)
 786                         seq_printf(m, "attrib %d: %d %d\n", i,
 787                                    radeon_connector->cur_stream_attribs[i].fe,
 788                                    radeon_connector->cur_stream_attribs[i].slots);
 789         }
 790         drm_modeset_unlock_all(dev);
 791         return 0;
 792 }
 793
 794 static struct drm_info_list radeon_debugfs_mst_list[] = {
 795         {"radeon_mst_info", &radeon_debugfs_mst_info, 0, NULL},
 796 };
 797 #endif
 798
 799 int radeon_mst_debugfs_init(struct radeon_device *rdev)
 800 {
 801 #if defined(CONFIG_DEBUG_FS)
 802         return radeon_debugfs_add_files(rdev, radeon_debugfs_mst_list, 1);
 803 #endif
 804         return 0;
 805 }