drivers/gpu/drm/sun4i/sun4i_backend.c

   1 /*
   2  * Copyright (C) 2015 Free Electrons
   3  * Copyright (C) 2015 NextThing Co
   4  *
   5  * Maxime Ripard <maxime.ripard@free-electrons.com>
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 of
  10  * the License, or (at your option) any later version.
  11  */
  12
  13 #include <drm/drmP.h>
  14 #include <drm/drm_atomic_helper.h>
  15 #include <drm/drm_crtc.h>
  16 #include <drm/drm_crtc_helper.h>
  17 #include <drm/drm_fb_cma_helper.h>
  18 #include <drm/drm_gem_cma_helper.h>
  19 #include <drm/drm_plane_helper.h>
  20
  21 #include <linux/component.h>
  22 #include <linux/list.h>
  23 #include <linux/of_graph.h>
  24 #include <linux/reset.h>
  25
  26 #include "sun4i_backend.h"
  27 #include "sun4i_drv.h"
  28 #include "sun4i_layer.h"
  29 #include "sunxi_engine.h"
  30
  31 static const u32 sunxi_rgb2yuv_coef[12] = {
  32         0x00000107, 0x00000204, 0x00000064, 0x00000108,
  33         0x00003f69, 0x00003ed6, 0x000001c1, 0x00000808,
  34         0x000001c1, 0x00003e88, 0x00003fb8, 0x00000808
  35 };
  36
  37 static void sun4i_backend_apply_color_correction(struct sunxi_engine *engine)
  38 {
  39         int i;
  40
  41         DRM_DEBUG_DRIVER("Applying RGB to YUV color correction\n");
  42
  43         /* Set color correction */
  44         regmap_write(engine->regs, SUN4I_BACKEND_OCCTL_REG,
  45                      SUN4I_BACKEND_OCCTL_ENABLE);
  46
  47         for (i = 0; i < 12; i++)
  48                 regmap_write(engine->regs, SUN4I_BACKEND_OCRCOEF_REG(i),
  49                              sunxi_rgb2yuv_coef[i]);
  50 }
  51
  52 static void sun4i_backend_disable_color_correction(struct sunxi_engine *engine)
  53 {
  54         DRM_DEBUG_DRIVER("Disabling color correction\n");
  55
  56         /* Disable color correction */
  57         regmap_update_bits(engine->regs, SUN4I_BACKEND_OCCTL_REG,
  58                            SUN4I_BACKEND_OCCTL_ENABLE, 0);
  59 }
  60
  61 static void sun4i_backend_commit(struct sunxi_engine *engine)
  62 {
  63         DRM_DEBUG_DRIVER("Committing changes\n");
  64
  65         regmap_write(engine->regs, SUN4I_BACKEND_REGBUFFCTL_REG,
  66                      SUN4I_BACKEND_REGBUFFCTL_AUTOLOAD_DIS |
  67                      SUN4I_BACKEND_REGBUFFCTL_LOADCTL);
  68 }
  69
  70 void sun4i_backend_layer_enable(struct sun4i_backend *backend,
  71                                 int layer, bool enable)
  72 {
  73         u32 val;
  74
  75         DRM_DEBUG_DRIVER("%sabling layer %d\n", enable ? "En" : "Dis",
  76                          layer);
  77
  78         if (enable)
  79                 val = SUN4I_BACKEND_MODCTL_LAY_EN(layer);
  80         else
  81                 val = 0;
  82
  83         regmap_update_bits(backend->engine.regs, SUN4I_BACKEND_MODCTL_REG,
  84                            SUN4I_BACKEND_MODCTL_LAY_EN(layer), val);
  85 }
  86
  87 static int sun4i_backend_drm_format_to_layer(struct drm_plane *plane,
  88                                              u32 format, u32 *mode)
  89 {
  90         if ((plane->type == DRM_PLANE_TYPE_PRIMARY) &&
  91             (format == DRM_FORMAT_ARGB8888))
  92                 format = DRM_FORMAT_XRGB8888;
  93
  94         switch (format) {
  95         case DRM_FORMAT_ARGB8888:
  96                 *mode = SUN4I_BACKEND_LAY_FBFMT_ARGB8888;
  97                 break;
  98
  99         case DRM_FORMAT_ARGB4444:
 100                 *mode = SUN4I_BACKEND_LAY_FBFMT_ARGB4444;
 101                 break;
 102
 103         case DRM_FORMAT_ARGB1555:
 104                 *mode = SUN4I_BACKEND_LAY_FBFMT_ARGB1555;
 105                 break;
 106
 107         case DRM_FORMAT_RGBA5551:
 108                 *mode = SUN4I_BACKEND_LAY_FBFMT_RGBA5551;
 109                 break;
 110
 111         case DRM_FORMAT_RGBA4444:
 112                 *mode = SUN4I_BACKEND_LAY_FBFMT_RGBA4444;
 113                 break;
 114
 115         case DRM_FORMAT_XRGB8888:
 116                 *mode = SUN4I_BACKEND_LAY_FBFMT_XRGB8888;
 117                 break;
 118
 119         case DRM_FORMAT_RGB888:
 120                 *mode = SUN4I_BACKEND_LAY_FBFMT_RGB888;
 121                 break;
 122
 123         case DRM_FORMAT_RGB565:
 124                 *mode = SUN4I_BACKEND_LAY_FBFMT_RGB565;
 125                 break;
 126
 127         default:
 128                 return -EINVAL;
 129         }
 130
 131         return 0;
 132 }
 133
 134 int sun4i_backend_update_layer_coord(struct sun4i_backend *backend,
 135                                      int layer, struct drm_plane *plane)
 136 {
 137         struct drm_plane_state *state = plane->state;
 138         struct drm_framebuffer *fb = state->fb;
 139
 140         DRM_DEBUG_DRIVER("Updating layer %d\n", layer);
 141
 142         if (plane->type == DRM_PLANE_TYPE_PRIMARY) {
 143                 DRM_DEBUG_DRIVER("Primary layer, updating global size W: %u H: %u\n",
 144                                  state->crtc_w, state->crtc_h);
 145                 regmap_write(backend->engine.regs, SUN4I_BACKEND_DISSIZE_REG,
 146                              SUN4I_BACKEND_DISSIZE(state->crtc_w,
 147                                                    state->crtc_h));
 148         }
 149
 150         /* Set the line width */
 151         DRM_DEBUG_DRIVER("Layer line width: %d bits\n", fb->pitches[0] * 8);
 152         regmap_write(backend->engine.regs,
 153                      SUN4I_BACKEND_LAYLINEWIDTH_REG(layer),
 154                      fb->pitches[0] * 8);
 155
 156         /* Set height and width */
 157         DRM_DEBUG_DRIVER("Layer size W: %u H: %u\n",
 158                          state->crtc_w, state->crtc_h);
 159         regmap_write(backend->engine.regs, SUN4I_BACKEND_LAYSIZE_REG(layer),
 160                      SUN4I_BACKEND_LAYSIZE(state->crtc_w,
 161                                            state->crtc_h));
 162
 163         /* Set base coordinates */
 164         DRM_DEBUG_DRIVER("Layer coordinates X: %d Y: %d\n",
 165                          state->crtc_x, state->crtc_y);
 166         regmap_write(backend->engine.regs, SUN4I_BACKEND_LAYCOOR_REG(layer),
 167                      SUN4I_BACKEND_LAYCOOR(state->crtc_x,
 168                                            state->crtc_y));
 169
 170         return 0;
 171 }
 172
 173 int sun4i_backend_update_layer_formats(struct sun4i_backend *backend,
 174                                        int layer, struct drm_plane *plane)
 175 {
 176         struct drm_plane_state *state = plane->state;
 177         struct drm_framebuffer *fb = state->fb;
 178         bool interlaced = false;
 179         u32 val;
 180         int ret;
 181
 182         if (plane->state->crtc)
 183                 interlaced = plane->state->crtc->state->adjusted_mode.flags
 184                         & DRM_MODE_FLAG_INTERLACE;
 185
 186         regmap_update_bits(backend->engine.regs, SUN4I_BACKEND_MODCTL_REG,
 187                            SUN4I_BACKEND_MODCTL_ITLMOD_EN,
 188                            interlaced ? SUN4I_BACKEND_MODCTL_ITLMOD_EN : 0);
 189
 190         DRM_DEBUG_DRIVER("Switching display backend interlaced mode %s\n",
 191                          interlaced ? "on" : "off");
 192
 193         ret = sun4i_backend_drm_format_to_layer(plane, fb->format->format,
 194                                                 &val);
 195         if (ret) {
 196                 DRM_DEBUG_DRIVER("Invalid format\n");
 197                 return ret;
 198         }
 199
 200         regmap_update_bits(backend->engine.regs,
 201                            SUN4I_BACKEND_ATTCTL_REG1(layer),
 202                            SUN4I_BACKEND_ATTCTL_REG1_LAY_FBFMT, val);
 203
 204         return 0;
 205 }
 206
 207 int sun4i_backend_update_layer_buffer(struct sun4i_backend *backend,
 208                                       int layer, struct drm_plane *plane)
 209 {
 210         struct drm_plane_state *state = plane->state;
 211         struct drm_framebuffer *fb = state->fb;
 212         struct drm_gem_cma_object *gem;
 213         u32 lo_paddr, hi_paddr;
 214         dma_addr_t paddr;
 215         int bpp;
 216
 217         /* Get the physical address of the buffer in memory */
 218         gem = drm_fb_cma_get_gem_obj(fb, 0);
 219
 220         DRM_DEBUG_DRIVER("Using GEM @ %pad\n", &gem->paddr);
 221
 222         /* Compute the start of the displayed memory */
 223         bpp = fb->format->cpp[0];
 224         paddr = gem->paddr + fb->offsets[0];
 225         paddr += (state->src_x >> 16) * bpp;
 226         paddr += (state->src_y >> 16) * fb->pitches[0];
 227
 228         DRM_DEBUG_DRIVER("Setting buffer address to %pad\n", &paddr);
 229
 230         /* Write the 32 lower bits of the address (in bits) */
 231         lo_paddr = paddr << 3;
 232         DRM_DEBUG_DRIVER("Setting address lower bits to 0x%x\n", lo_paddr);
 233         regmap_write(backend->engine.regs,
 234                      SUN4I_BACKEND_LAYFB_L32ADD_REG(layer),
 235                      lo_paddr);
 236
 237         /* And the upper bits */
 238         hi_paddr = paddr >> 29;
 239         DRM_DEBUG_DRIVER("Setting address high bits to 0x%x\n", hi_paddr);
 240         regmap_update_bits(backend->engine.regs, SUN4I_BACKEND_LAYFB_H4ADD_REG,
 241                            SUN4I_BACKEND_LAYFB_H4ADD_MSK(layer),
 242                            SUN4I_BACKEND_LAYFB_H4ADD(layer, hi_paddr));
 243
 244         return 0;
 245 }
 246
 247 static int sun4i_backend_init_sat(struct device *dev) {
 248         struct sun4i_backend *backend = dev_get_drvdata(dev);
 249         int ret;
 250
 251         backend->sat_reset = devm_reset_control_get(dev, "sat");
 252         if (IS_ERR(backend->sat_reset)) {
 253                 dev_err(dev, "Couldn't get the SAT reset line\n");
 254                 return PTR_ERR(backend->sat_reset);
 255         }
 256
 257         ret = reset_control_deassert(backend->sat_reset);
 258         if (ret) {
 259                 dev_err(dev, "Couldn't deassert the SAT reset line\n");
 260                 return ret;
 261         }
 262
 263         backend->sat_clk = devm_clk_get(dev, "sat");
 264         if (IS_ERR(backend->sat_clk)) {
 265                 dev_err(dev, "Couldn't get our SAT clock\n");
 266                 ret = PTR_ERR(backend->sat_clk);
 267                 goto err_assert_reset;
 268         }
 269
 270         ret = clk_prepare_enable(backend->sat_clk);
 271         if (ret) {
 272                 dev_err(dev, "Couldn't enable the SAT clock\n");
 273                 return ret;
 274         }
 275
 276         return 0;
 277
 278 err_assert_reset:
 279         reset_control_assert(backend->sat_reset);
 280         return ret;
 281 }
 282
 283 static int sun4i_backend_free_sat(struct device *dev) {
 284         struct sun4i_backend *backend = dev_get_drvdata(dev);
 285
 286         clk_disable_unprepare(backend->sat_clk);
 287         reset_control_assert(backend->sat_reset);
 288
 289         return 0;
 290 }
 291
 292 /*
 293  * The display backend can take video output from the display frontend, or
 294  * the display enhancement unit on the A80, as input for one it its layers.
 295  * This relationship within the display pipeline is encoded in the device
 296  * tree with of_graph, and we use it here to figure out which backend, if
 297  * there are 2 or more, we are currently probing. The number would be in
 298  * the "reg" property of the upstream output port endpoint.
 299  */
 300 static int sun4i_backend_of_get_id(struct device_node *node)
 301 {
 302         struct device_node *port, *ep;
 303         int ret = -EINVAL;
 304
 305         /* input is port 0 */
 306         port = of_graph_get_port_by_id(node, 0);
 307         if (!port)
 308                 return -EINVAL;
 309
 310         /* try finding an upstream endpoint */
 311         for_each_available_child_of_node(port, ep) {
 312                 struct device_node *remote;
 313                 u32 reg;
 314
 315                 remote = of_parse_phandle(ep, "remote-endpoint", 0);
 316                 if (!remote)
 317                         continue;
 318
 319                 ret = of_property_read_u32(remote, "reg", &reg);
 320                 if (ret)
 321                         continue;
 322
 323                 ret = reg;
 324         }
 325
 326         of_node_put(port);
 327
 328         return ret;
 329 }
 330
 331 static const struct sunxi_engine_ops sun4i_backend_engine_ops = {
 332         .commit                         = sun4i_backend_commit,
 333         .layers_init                    = sun4i_layers_init,
 334         .apply_color_correction         = sun4i_backend_apply_color_correction,
 335         .disable_color_correction       = sun4i_backend_disable_color_correction,
 336 };
 337
 338 static struct regmap_config sun4i_backend_regmap_config = {
 339         .reg_bits       = 32,
 340         .val_bits       = 32,
 341         .reg_stride     = 4,
 342         .max_register   = 0x5800,
 343 };
 344
 345 static int sun4i_backend_bind(struct device *dev, struct device *master,
 346                               void *data)
 347 {
 348         struct platform_device *pdev = to_platform_device(dev);
 349         struct drm_device *drm = data;
 350         struct sun4i_drv *drv = drm->dev_private;
 351         struct sun4i_backend *backend;
 352         struct resource *res;
 353         void __iomem *regs;
 354         int i, ret;
 355
 356         backend = devm_kzalloc(dev, sizeof(*backend), GFP_KERNEL);
 357         if (!backend)
 358                 return -ENOMEM;
 359         dev_set_drvdata(dev, backend);
 360
 361         backend->engine.node = dev->of_node;
 362         backend->engine.ops = &sun4i_backend_engine_ops;
 363         backend->engine.id = sun4i_backend_of_get_id(dev->of_node);
 364         if (backend->engine.id < 0)
 365                 return backend->engine.id;
 366
 367         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 368         regs = devm_ioremap_resource(dev, res);
 369         if (IS_ERR(regs))
 370                 return PTR_ERR(regs);
 371
 372         backend->engine.regs = devm_regmap_init_mmio(dev, regs,
 373                                                      &sun4i_backend_regmap_config);
 374         if (IS_ERR(backend->engine.regs)) {
 375                 dev_err(dev, "Couldn't create the backend regmap\n");
 376                 return PTR_ERR(backend->engine.regs);
 377         }
 378
 379         backend->reset = devm_reset_control_get(dev, NULL);
 380         if (IS_ERR(backend->reset)) {
 381                 dev_err(dev, "Couldn't get our reset line\n");
 382                 return PTR_ERR(backend->reset);
 383         }
 384
 385         ret = reset_control_deassert(backend->reset);
 386         if (ret) {
 387                 dev_err(dev, "Couldn't deassert our reset line\n");
 388                 return ret;
 389         }
 390
 391         backend->bus_clk = devm_clk_get(dev, "ahb");
 392         if (IS_ERR(backend->bus_clk)) {
 393                 dev_err(dev, "Couldn't get the backend bus clock\n");
 394                 ret = PTR_ERR(backend->bus_clk);
 395                 goto err_assert_reset;
 396         }
 397         clk_prepare_enable(backend->bus_clk);
 398
 399         backend->mod_clk = devm_clk_get(dev, "mod");
 400         if (IS_ERR(backend->mod_clk)) {
 401                 dev_err(dev, "Couldn't get the backend module clock\n");
 402                 ret = PTR_ERR(backend->mod_clk);
 403                 goto err_disable_bus_clk;
 404         }
 405         clk_prepare_enable(backend->mod_clk);
 406
 407         backend->ram_clk = devm_clk_get(dev, "ram");
 408         if (IS_ERR(backend->ram_clk)) {
 409                 dev_err(dev, "Couldn't get the backend RAM clock\n");
 410                 ret = PTR_ERR(backend->ram_clk);
 411                 goto err_disable_mod_clk;
 412         }
 413         clk_prepare_enable(backend->ram_clk);
 414
 415         if (of_device_is_compatible(dev->of_node,
 416                                     "allwinner,sun8i-a33-display-backend")) {
 417                 ret = sun4i_backend_init_sat(dev);
 418                 if (ret) {
 419                         dev_err(dev, "Couldn't init SAT resources\n");
 420                         goto err_disable_ram_clk;
 421                 }
 422         }
 423
 424         list_add_tail(&backend->engine.list, &drv->engine_list);
 425
 426         /* Reset the registers */
 427         for (i = 0x800; i < 0x1000; i += 4)
 428                 regmap_write(backend->engine.regs, i, 0);
 429
 430         /* Disable registers autoloading */
 431         regmap_write(backend->engine.regs, SUN4I_BACKEND_REGBUFFCTL_REG,
 432                      SUN4I_BACKEND_REGBUFFCTL_AUTOLOAD_DIS);
 433
 434         /* Enable the backend */
 435         regmap_write(backend->engine.regs, SUN4I_BACKEND_MODCTL_REG,
 436                      SUN4I_BACKEND_MODCTL_DEBE_EN |
 437                      SUN4I_BACKEND_MODCTL_START_CTL);
 438
 439         return 0;
 440
 441 err_disable_ram_clk:
 442         clk_disable_unprepare(backend->ram_clk);
 443 err_disable_mod_clk:
 444         clk_disable_unprepare(backend->mod_clk);
 445 err_disable_bus_clk:
 446         clk_disable_unprepare(backend->bus_clk);
 447 err_assert_reset:
 448         reset_control_assert(backend->reset);
 449         return ret;
 450 }
 451
 452 static void sun4i_backend_unbind(struct device *dev, struct device *master,
 453                                  void *data)
 454 {
 455         struct sun4i_backend *backend = dev_get_drvdata(dev);
 456
 457         list_del(&backend->engine.list);
 458
 459         if (of_device_is_compatible(dev->of_node,
 460                                     "allwinner,sun8i-a33-display-backend"))
 461                 sun4i_backend_free_sat(dev);
 462
 463         clk_disable_unprepare(backend->ram_clk);
 464         clk_disable_unprepare(backend->mod_clk);
 465         clk_disable_unprepare(backend->bus_clk);
 466         reset_control_assert(backend->reset);
 467 }
 468
 469 static const struct component_ops sun4i_backend_ops = {
 470         .bind   = sun4i_backend_bind,
 471         .unbind = sun4i_backend_unbind,
 472 };
 473
 474 static int sun4i_backend_probe(struct platform_device *pdev)
 475 {
 476         return component_add(&pdev->dev, &sun4i_backend_ops);
 477 }
 478
 479 static int sun4i_backend_remove(struct platform_device *pdev)
 480 {
 481         component_del(&pdev->dev, &sun4i_backend_ops);
 482
 483         return 0;
 484 }
 485
 486 static const struct of_device_id sun4i_backend_of_table[] = {
 487         { .compatible = "allwinner,sun5i-a13-display-backend" },
 488         { .compatible = "allwinner,sun6i-a31-display-backend" },
 489         { .compatible = "allwinner,sun8i-a33-display-backend" },
 490         { }
 491 };
 492 MODULE_DEVICE_TABLE(of, sun4i_backend_of_table);
 493
 494 static struct platform_driver sun4i_backend_platform_driver = {
 495         .probe          = sun4i_backend_probe,
 496         .remove         = sun4i_backend_remove,
 497         .driver         = {
 498                 .name           = "sun4i-backend",
 499                 .of_match_table = sun4i_backend_of_table,
 500         },
 501 };
 502 module_platform_driver(sun4i_backend_platform_driver);
 503
 504 MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>");
 505 MODULE_DESCRIPTION("Allwinner A10 Display Backend Driver");
 506 MODULE_LICENSE("GPL");